include/uapi/drm/amdgpu_drm.h

   1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * Copyright 2014 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32 #ifndef __AMDGPU_DRM_H__
  33 #define __AMDGPU_DRM_H__
  34
  35 #include "drm.h"
  36
  37 #if defined(__cplusplus)
  38 extern "C" {
  39 #endif
  40
  41 #define DRM_AMDGPU_GEM_CREATE           0x00
  42 #define DRM_AMDGPU_GEM_MMAP             0x01
  43 #define DRM_AMDGPU_CTX                  0x02
  44 #define DRM_AMDGPU_BO_LIST              0x03
  45 #define DRM_AMDGPU_CS                   0x04
  46 #define DRM_AMDGPU_INFO                 0x05
  47 #define DRM_AMDGPU_GEM_METADATA         0x06
  48 #define DRM_AMDGPU_GEM_WAIT_IDLE        0x07
  49 #define DRM_AMDGPU_GEM_VA               0x08
  50 #define DRM_AMDGPU_WAIT_CS              0x09
  51 #define DRM_AMDGPU_GEM_OP               0x10
  52 #define DRM_AMDGPU_GEM_USERPTR          0x11
  53 #define DRM_AMDGPU_WAIT_FENCES          0x12
  54 #define DRM_AMDGPU_VM                   0x13
  55 #define DRM_AMDGPU_FENCE_TO_HANDLE      0x14
  56 #define DRM_AMDGPU_SCHED                0x15
  57
  58 #define DRM_IOCTL_AMDGPU_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  59 #define DRM_IOCTL_AMDGPU_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
  60 #define DRM_IOCTL_AMDGPU_CTX            DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
  61 #define DRM_IOCTL_AMDGPU_BO_LIST        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
  62 #define DRM_IOCTL_AMDGPU_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
  63 #define DRM_IOCTL_AMDGPU_INFO           DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
  64 #define DRM_IOCTL_AMDGPU_GEM_METADATA   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
  65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
  66 #define DRM_IOCTL_AMDGPU_GEM_VA         DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
  67 #define DRM_IOCTL_AMDGPU_WAIT_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
  68 #define DRM_IOCTL_AMDGPU_GEM_OP         DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
  69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
  70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
  71 #define DRM_IOCTL_AMDGPU_VM             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
  72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
  73 #define DRM_IOCTL_AMDGPU_SCHED          DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
  74
  75 #define AMDGPU_GEM_DOMAIN_CPU           0x1
  76 #define AMDGPU_GEM_DOMAIN_GTT           0x2
  77 #define AMDGPU_GEM_DOMAIN_VRAM          0x4
  78 #define AMDGPU_GEM_DOMAIN_GDS           0x8
  79 #define AMDGPU_GEM_DOMAIN_GWS           0x10
  80 #define AMDGPU_GEM_DOMAIN_OA            0x20
  81
  82 /* Flag that CPU access will be required for the case of VRAM domain */
  83 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED   (1 << 0)
  84 /* Flag that CPU access will not work, this VRAM domain is invisible */
  85 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS         (1 << 1)
  86 /* Flag that USWC attributes should be used for GTT */
  87 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC          (1 << 2)
  88 /* Flag that the memory should be in VRAM and cleared */
  89 #define AMDGPU_GEM_CREATE_VRAM_CLEARED          (1 << 3)
  90 /* Flag that create shadow bo(GTT) while allocating vram bo */
  91 #define AMDGPU_GEM_CREATE_SHADOW                (1 << 4)
  92 /* Flag that allocating the BO should use linear VRAM */
  93 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS       (1 << 5)
  94 /* Flag that BO is always valid in this VM */
  95 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID       (1 << 6)
  96 /* Flag that BO sharing will be explicitly synchronized */
  97 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC         (1 << 7)
  98
  99 struct drm_amdgpu_gem_create_in  {
 100         /** the requested memory size */
 101         __u64 bo_size;
 102         /** physical start_addr alignment in bytes for some HW requirements */
 103         __u64 alignment;
 104         /** the requested memory domains */
 105         __u64 domains;
 106         /** allocation flags */
 107         __u64 domain_flags;
 108 };
 109
 110 struct drm_amdgpu_gem_create_out  {
 111         /** returned GEM object handle */
 112         __u32 handle;
 113         __u32 _pad;
 114 };
 115
 116 union drm_amdgpu_gem_create {
 117         struct drm_amdgpu_gem_create_in         in;
 118         struct drm_amdgpu_gem_create_out        out;
 119 };
 120
 121 /** Opcode to create new residency list.  */
 122 #define AMDGPU_BO_LIST_OP_CREATE        0
 123 /** Opcode to destroy previously created residency list */
 124 #define AMDGPU_BO_LIST_OP_DESTROY       1
 125 /** Opcode to update resource information in the list */
 126 #define AMDGPU_BO_LIST_OP_UPDATE        2
 127
 128 struct drm_amdgpu_bo_list_in {
 129         /** Type of operation */
 130         __u32 operation;
 131         /** Handle of list or 0 if we want to create one */
 132         __u32 list_handle;
 133         /** Number of BOs in list  */
 134         __u32 bo_number;
 135         /** Size of each element describing BO */
 136         __u32 bo_info_size;
 137         /** Pointer to array describing BOs */
 138         __u64 bo_info_ptr;
 139 };
 140
 141 struct drm_amdgpu_bo_list_entry {
 142         /** Handle of BO */
 143         __u32 bo_handle;
 144         /** New (if specified) BO priority to be used during migration */
 145         __u32 bo_priority;
 146 };
 147
 148 struct drm_amdgpu_bo_list_out {
 149         /** Handle of resource list  */
 150         __u32 list_handle;
 151         __u32 _pad;
 152 };
 153
 154 union drm_amdgpu_bo_list {
 155         struct drm_amdgpu_bo_list_in in;
 156         struct drm_amdgpu_bo_list_out out;
 157 };
 158
 159 /* context related */
 160 #define AMDGPU_CTX_OP_ALLOC_CTX 1
 161 #define AMDGPU_CTX_OP_FREE_CTX  2
 162 #define AMDGPU_CTX_OP_QUERY_STATE       3
 163 #define AMDGPU_CTX_OP_QUERY_STATE2      4
 164
 165 /* GPU reset status */
 166 #define AMDGPU_CTX_NO_RESET             0
 167 /* this the context caused it */
 168 #define AMDGPU_CTX_GUILTY_RESET         1
 169 /* some other context caused it */
 170 #define AMDGPU_CTX_INNOCENT_RESET       2
 171 /* unknown cause */
 172 #define AMDGPU_CTX_UNKNOWN_RESET        3
 173
 174 /* indicate gpu reset occured after ctx created */
 175 #define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
 176 /* indicate vram lost occured after ctx created */
 177 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
 178 /* indicate some job from this context once cause gpu hang */
 179 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
 180
 181 /* Context priority level */
 182 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 183 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
 184 #define AMDGPU_CTX_PRIORITY_LOW         -512
 185 #define AMDGPU_CTX_PRIORITY_NORMAL      0
 186 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
 187 #define AMDGPU_CTX_PRIORITY_HIGH        512
 188 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
 189
 190 struct drm_amdgpu_ctx_in {
 191         /** AMDGPU_CTX_OP_* */
 192         __u32   op;
 193         /** For future use, no flags defined so far */
 194         __u32   flags;
 195         __u32   ctx_id;
 196         __s32   priority;
 197 };
 198
 199 union drm_amdgpu_ctx_out {
 200                 struct {
 201                         __u32   ctx_id;
 202                         __u32   _pad;
 203                 } alloc;
 204
 205                 struct {
 206                         /** For future use, no flags defined so far */
 207                         __u64   flags;
 208                         /** Number of resets caused by this context so far. */
 209                         __u32   hangs;
 210                         /** Reset status since the last call of the ioctl. */
 211                         __u32   reset_status;
 212                 } state;
 213 };
 214
 215 union drm_amdgpu_ctx {
 216         struct drm_amdgpu_ctx_in in;
 217         union drm_amdgpu_ctx_out out;
 218 };
 219
 220 /* vm ioctl */
 221 #define AMDGPU_VM_OP_RESERVE_VMID       1
 222 #define AMDGPU_VM_OP_UNRESERVE_VMID     2
 223
 224 struct drm_amdgpu_vm_in {
 225         /** AMDGPU_VM_OP_* */
 226         __u32   op;
 227         __u32   flags;
 228 };
 229
 230 struct drm_amdgpu_vm_out {
 231         /** For future use, no flags defined so far */
 232         __u64   flags;
 233 };
 234
 235 union drm_amdgpu_vm {
 236         struct drm_amdgpu_vm_in in;
 237         struct drm_amdgpu_vm_out out;
 238 };
 239
 240 /* sched ioctl */
 241 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE       1
 242
 243 struct drm_amdgpu_sched_in {
 244         /* AMDGPU_SCHED_OP_* */
 245         __u32   op;
 246         __u32   fd;
 247         __s32   priority;
 248         __u32   flags;
 249 };
 250
 251 union drm_amdgpu_sched {
 252         struct drm_amdgpu_sched_in in;
 253 };
 254
 255 /*
 256  * This is not a reliable API and you should expect it to fail for any
 257  * number of reasons and have fallback path that do not use userptr to
 258  * perform any operation.
 259  */
 260 #define AMDGPU_GEM_USERPTR_READONLY     (1 << 0)
 261 #define AMDGPU_GEM_USERPTR_ANONONLY     (1 << 1)
 262 #define AMDGPU_GEM_USERPTR_VALIDATE     (1 << 2)
 263 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 264
 265 struct drm_amdgpu_gem_userptr {
 266         __u64           addr;
 267         __u64           size;
 268         /* AMDGPU_GEM_USERPTR_* */
 269         __u32           flags;
 270         /* Resulting GEM handle */
 271         __u32           handle;
 272 };
 273
 274 /* SI-CI-VI: */
 275 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 276 #define AMDGPU_TILING_ARRAY_MODE_SHIFT                  0
 277 #define AMDGPU_TILING_ARRAY_MODE_MASK                   0xf
 278 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT                 4
 279 #define AMDGPU_TILING_PIPE_CONFIG_MASK                  0x1f
 280 #define AMDGPU_TILING_TILE_SPLIT_SHIFT                  9
 281 #define AMDGPU_TILING_TILE_SPLIT_MASK                   0x7
 282 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT             12
 283 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK              0x7
 284 #define AMDGPU_TILING_BANK_WIDTH_SHIFT                  15
 285 #define AMDGPU_TILING_BANK_WIDTH_MASK                   0x3
 286 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                 17
 287 #define AMDGPU_TILING_BANK_HEIGHT_MASK                  0x3
 288 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT           19
 289 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK            0x3
 290 #define AMDGPU_TILING_NUM_BANKS_SHIFT                   21
 291 #define AMDGPU_TILING_NUM_BANKS_MASK                    0x3
 292
 293 /* GFX9 and later: */
 294 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT                0
 295 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                 0x1f
 296
 297 /* Set/Get helpers for tiling flags. */
 298 #define AMDGPU_TILING_SET(field, value) \
 299         (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 300 #define AMDGPU_TILING_GET(value, field) \
 301         (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 302
 303 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 304 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 305
 306 /** The same structure is shared for input/output */
 307 struct drm_amdgpu_gem_metadata {
 308         /** GEM Object handle */
 309         __u32   handle;
 310         /** Do we want get or set metadata */
 311         __u32   op;
 312         struct {
 313                 /** For future use, no flags defined so far */
 314                 __u64   flags;
 315                 /** family specific tiling info */
 316                 __u64   tiling_info;
 317                 __u32   data_size_bytes;
 318                 __u32   data[64];
 319         } data;
 320 };
 321
 322 struct drm_amdgpu_gem_mmap_in {
 323         /** the GEM object handle */
 324         __u32 handle;
 325         __u32 _pad;
 326 };
 327
 328 struct drm_amdgpu_gem_mmap_out {
 329         /** mmap offset from the vma offset manager */
 330         __u64 addr_ptr;
 331 };
 332
 333 union drm_amdgpu_gem_mmap {
 334         struct drm_amdgpu_gem_mmap_in   in;
 335         struct drm_amdgpu_gem_mmap_out out;
 336 };
 337
 338 struct drm_amdgpu_gem_wait_idle_in {
 339         /** GEM object handle */
 340         __u32 handle;
 341         /** For future use, no flags defined so far */
 342         __u32 flags;
 343         /** Absolute timeout to wait */
 344         __u64 timeout;
 345 };
 346
 347 struct drm_amdgpu_gem_wait_idle_out {
 348         /** BO status:  0 - BO is idle, 1 - BO is busy */
 349         __u32 status;
 350         /** Returned current memory domain */
 351         __u32 domain;
 352 };
 353
 354 union drm_amdgpu_gem_wait_idle {
 355         struct drm_amdgpu_gem_wait_idle_in  in;
 356         struct drm_amdgpu_gem_wait_idle_out out;
 357 };
 358
 359 struct drm_amdgpu_wait_cs_in {
 360         /* Command submission handle
 361          * handle equals 0 means none to wait for
 362          * handle equals ~0ull means wait for the latest sequence number
 363          */
 364         __u64 handle;
 365         /** Absolute timeout to wait */
 366         __u64 timeout;
 367         __u32 ip_type;
 368         __u32 ip_instance;
 369         __u32 ring;
 370         __u32 ctx_id;
 371 };
 372
 373 struct drm_amdgpu_wait_cs_out {
 374         /** CS status:  0 - CS completed, 1 - CS still busy */
 375         __u64 status;
 376 };
 377
 378 union drm_amdgpu_wait_cs {
 379         struct drm_amdgpu_wait_cs_in in;
 380         struct drm_amdgpu_wait_cs_out out;
 381 };
 382
 383 struct drm_amdgpu_fence {
 384         __u32 ctx_id;
 385         __u32 ip_type;
 386         __u32 ip_instance;
 387         __u32 ring;
 388         __u64 seq_no;
 389 };
 390
 391 struct drm_amdgpu_wait_fences_in {
 392         /** This points to uint64_t * which points to fences */
 393         __u64 fences;
 394         __u32 fence_count;
 395         __u32 wait_all;
 396         __u64 timeout_ns;
 397 };
 398
 399 struct drm_amdgpu_wait_fences_out {
 400         __u32 status;
 401         __u32 first_signaled;
 402 };
 403
 404 union drm_amdgpu_wait_fences {
 405         struct drm_amdgpu_wait_fences_in in;
 406         struct drm_amdgpu_wait_fences_out out;
 407 };
 408
 409 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO       0
 410 #define AMDGPU_GEM_OP_SET_PLACEMENT             1
 411
 412 /* Sets or returns a value associated with a buffer. */
 413 struct drm_amdgpu_gem_op {
 414         /** GEM object handle */
 415         __u32   handle;
 416         /** AMDGPU_GEM_OP_* */
 417         __u32   op;
 418         /** Input or return value */
 419         __u64   value;
 420 };
 421
 422 #define AMDGPU_VA_OP_MAP                        1
 423 #define AMDGPU_VA_OP_UNMAP                      2
 424 #define AMDGPU_VA_OP_CLEAR                      3
 425 #define AMDGPU_VA_OP_REPLACE                    4
 426
 427 /* Delay the page table update till the next CS */
 428 #define AMDGPU_VM_DELAY_UPDATE          (1 << 0)
 429
 430 /* Mapping flags */
 431 /* readable mapping */
 432 #define AMDGPU_VM_PAGE_READABLE         (1 << 1)
 433 /* writable mapping */
 434 #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
 435 /* executable mapping, new for VI */
 436 #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
 437 /* partially resident texture */
 438 #define AMDGPU_VM_PAGE_PRT              (1 << 4)
 439 /* MTYPE flags use bit 5 to 8 */
 440 #define AMDGPU_VM_MTYPE_MASK            (0xf << 5)
 441 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
 442 #define AMDGPU_VM_MTYPE_DEFAULT         (0 << 5)
 443 /* Use NC MTYPE instead of default MTYPE */
 444 #define AMDGPU_VM_MTYPE_NC              (1 << 5)
 445 /* Use WC MTYPE instead of default MTYPE */
 446 #define AMDGPU_VM_MTYPE_WC              (2 << 5)
 447 /* Use CC MTYPE instead of default MTYPE */
 448 #define AMDGPU_VM_MTYPE_CC              (3 << 5)
 449 /* Use UC MTYPE instead of default MTYPE */
 450 #define AMDGPU_VM_MTYPE_UC              (4 << 5)
 451
 452 struct drm_amdgpu_gem_va {
 453         /** GEM object handle */
 454         __u32 handle;
 455         __u32 _pad;
 456         /** AMDGPU_VA_OP_* */
 457         __u32 operation;
 458         /** AMDGPU_VM_PAGE_* */
 459         __u32 flags;
 460         /** va address to assign . Must be correctly aligned.*/
 461         __u64 va_address;
 462         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
 463         __u64 offset_in_bo;
 464         /** Specify mapping size. Must be correctly aligned. */
 465         __u64 map_size;
 466 };
 467
 468 #define AMDGPU_HW_IP_GFX          0
 469 #define AMDGPU_HW_IP_COMPUTE      1
 470 #define AMDGPU_HW_IP_DMA          2
 471 #define AMDGPU_HW_IP_UVD          3
 472 #define AMDGPU_HW_IP_VCE          4
 473 #define AMDGPU_HW_IP_UVD_ENC      5
 474 #define AMDGPU_HW_IP_VCN_DEC      6
 475 #define AMDGPU_HW_IP_VCN_ENC      7
 476 #define AMDGPU_HW_IP_NUM          8
 477
 478 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 479
 480 #define AMDGPU_CHUNK_ID_IB              0x01
 481 #define AMDGPU_CHUNK_ID_FENCE           0x02
 482 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 483 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 484 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 485
 486 struct drm_amdgpu_cs_chunk {
 487         __u32           chunk_id;
 488         __u32           length_dw;
 489         __u64           chunk_data;
 490 };
 491
 492 struct drm_amdgpu_cs_in {
 493         /** Rendering context id */
 494         __u32           ctx_id;
 495         /**  Handle of resource list associated with CS */
 496         __u32           bo_list_handle;
 497         __u32           num_chunks;
 498         __u32           _pad;
 499         /** this points to __u64 * which point to cs chunks */
 500         __u64           chunks;
 501 };
 502
 503 struct drm_amdgpu_cs_out {
 504         __u64 handle;
 505 };
 506
 507 union drm_amdgpu_cs {
 508         struct drm_amdgpu_cs_in in;
 509         struct drm_amdgpu_cs_out out;
 510 };
 511
 512 /* Specify flags to be used for IB */
 513
 514 /* This IB should be submitted to CE */
 515 #define AMDGPU_IB_FLAG_CE       (1<<0)
 516
 517 /* Preamble flag, which means the IB could be dropped if no context switch */
 518 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 519
 520 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 521 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 522
 523 struct drm_amdgpu_cs_chunk_ib {
 524         __u32 _pad;
 525         /** AMDGPU_IB_FLAG_* */
 526         __u32 flags;
 527         /** Virtual address to begin IB execution */
 528         __u64 va_start;
 529         /** Size of submission */
 530         __u32 ib_bytes;
 531         /** HW IP to submit to */
 532         __u32 ip_type;
 533         /** HW IP index of the same type to submit to  */
 534         __u32 ip_instance;
 535         /** Ring index to submit to */
 536         __u32 ring;
 537 };
 538
 539 struct drm_amdgpu_cs_chunk_dep {
 540         __u32 ip_type;
 541         __u32 ip_instance;
 542         __u32 ring;
 543         __u32 ctx_id;
 544         __u64 handle;
 545 };
 546
 547 struct drm_amdgpu_cs_chunk_fence {
 548         __u32 handle;
 549         __u32 offset;
 550 };
 551
 552 struct drm_amdgpu_cs_chunk_sem {
 553         __u32 handle;
 554 };
 555
 556 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ      0
 557 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD   1
 558 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
 559
 560 union drm_amdgpu_fence_to_handle {
 561         struct {
 562                 struct drm_amdgpu_fence fence;
 563                 __u32 what;
 564                 __u32 pad;
 565         } in;
 566         struct {
 567                 __u32 handle;
 568         } out;
 569 };
 570
 571 struct drm_amdgpu_cs_chunk_data {
 572         union {
 573                 struct drm_amdgpu_cs_chunk_ib           ib_data;
 574                 struct drm_amdgpu_cs_chunk_fence        fence_data;
 575         };
 576 };
 577
 578 /**
 579  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 580  *
 581  */
 582 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 583 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 584
 585 /* indicate if acceleration can be working */
 586 #define AMDGPU_INFO_ACCEL_WORKING               0x00
 587 /* get the crtc_id from the mode object id? */
 588 #define AMDGPU_INFO_CRTC_FROM_ID                0x01
 589 /* query hw IP info */
 590 #define AMDGPU_INFO_HW_IP_INFO                  0x02
 591 /* query hw IP instance count for the specified type */
 592 #define AMDGPU_INFO_HW_IP_COUNT                 0x03
 593 /* timestamp for GL_ARB_timer_query */
 594 #define AMDGPU_INFO_TIMESTAMP                   0x05
 595 /* Query the firmware version */
 596 #define AMDGPU_INFO_FW_VERSION                  0x0e
 597         /* Subquery id: Query VCE firmware version */
 598         #define AMDGPU_INFO_FW_VCE              0x1
 599         /* Subquery id: Query UVD firmware version */
 600         #define AMDGPU_INFO_FW_UVD              0x2
 601         /* Subquery id: Query GMC firmware version */
 602         #define AMDGPU_INFO_FW_GMC              0x03
 603         /* Subquery id: Query GFX ME firmware version */
 604         #define AMDGPU_INFO_FW_GFX_ME           0x04
 605         /* Subquery id: Query GFX PFP firmware version */
 606         #define AMDGPU_INFO_FW_GFX_PFP          0x05
 607         /* Subquery id: Query GFX CE firmware version */
 608         #define AMDGPU_INFO_FW_GFX_CE           0x06
 609         /* Subquery id: Query GFX RLC firmware version */
 610         #define AMDGPU_INFO_FW_GFX_RLC          0x07
 611         /* Subquery id: Query GFX MEC firmware version */
 612         #define AMDGPU_INFO_FW_GFX_MEC          0x08
 613         /* Subquery id: Query SMC firmware version */
 614         #define AMDGPU_INFO_FW_SMC              0x0a
 615         /* Subquery id: Query SDMA firmware version */
 616         #define AMDGPU_INFO_FW_SDMA             0x0b
 617         /* Subquery id: Query PSP SOS firmware version */
 618         #define AMDGPU_INFO_FW_SOS              0x0c
 619         /* Subquery id: Query PSP ASD firmware version */
 620         #define AMDGPU_INFO_FW_ASD              0x0d
 621 /* number of bytes moved for TTM migration */
 622 #define AMDGPU_INFO_NUM_BYTES_MOVED             0x0f
 623 /* the used VRAM size */
 624 #define AMDGPU_INFO_VRAM_USAGE                  0x10
 625 /* the used GTT size */
 626 #define AMDGPU_INFO_GTT_USAGE                   0x11
 627 /* Information about GDS, etc. resource configuration */
 628 #define AMDGPU_INFO_GDS_CONFIG                  0x13
 629 /* Query information about VRAM and GTT domains */
 630 #define AMDGPU_INFO_VRAM_GTT                    0x14
 631 /* Query information about register in MMR address space*/
 632 #define AMDGPU_INFO_READ_MMR_REG                0x15
 633 /* Query information about device: rev id, family, etc. */
 634 #define AMDGPU_INFO_DEV_INFO                    0x16
 635 /* visible vram usage */
 636 #define AMDGPU_INFO_VIS_VRAM_USAGE              0x17
 637 /* number of TTM buffer evictions */
 638 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
 639 /* Query memory about VRAM and GTT domains */
 640 #define AMDGPU_INFO_MEMORY                      0x19
 641 /* Query vce clock table */
 642 #define AMDGPU_INFO_VCE_CLOCK_TABLE             0x1A
 643 /* Query vbios related information */
 644 #define AMDGPU_INFO_VBIOS                       0x1B
 645         /* Subquery id: Query vbios size */
 646         #define AMDGPU_INFO_VBIOS_SIZE          0x1
 647         /* Subquery id: Query vbios image */
 648         #define AMDGPU_INFO_VBIOS_IMAGE         0x2
 649 /* Query UVD handles */
 650 #define AMDGPU_INFO_NUM_HANDLES                 0x1C
 651 /* Query sensor related information */
 652 #define AMDGPU_INFO_SENSOR                      0x1D
 653         /* Subquery id: Query GPU shader clock */
 654         #define AMDGPU_INFO_SENSOR_GFX_SCLK             0x1
 655         /* Subquery id: Query GPU memory clock */
 656         #define AMDGPU_INFO_SENSOR_GFX_MCLK             0x2
 657         /* Subquery id: Query GPU temperature */
 658         #define AMDGPU_INFO_SENSOR_GPU_TEMP             0x3
 659         /* Subquery id: Query GPU load */
 660         #define AMDGPU_INFO_SENSOR_GPU_LOAD             0x4
 661         /* Subquery id: Query average GPU power */
 662         #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER        0x5
 663         /* Subquery id: Query northbridge voltage */
 664         #define AMDGPU_INFO_SENSOR_VDDNB                0x6
 665         /* Subquery id: Query graphics voltage */
 666         #define AMDGPU_INFO_SENSOR_VDDGFX               0x7
 667 /* Number of VRAM page faults on CPU access. */
 668 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
 669 #define AMDGPU_INFO_VRAM_LOST_COUNTER           0x1F
 670
 671 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT  0
 672 #define AMDGPU_INFO_MMR_SE_INDEX_MASK   0xff
 673 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT  8
 674 #define AMDGPU_INFO_MMR_SH_INDEX_MASK   0xff
 675
 676 struct drm_amdgpu_query_fw {
 677         /** AMDGPU_INFO_FW_* */
 678         __u32 fw_type;
 679         /**
 680          * Index of the IP if there are more IPs of
 681          * the same type.
 682          */
 683         __u32 ip_instance;
 684         /**
 685          * Index of the engine. Whether this is used depends
 686          * on the firmware type. (e.g. MEC, SDMA)
 687          */
 688         __u32 index;
 689         __u32 _pad;
 690 };
 691
 692 /* Input structure for the INFO ioctl */
 693 struct drm_amdgpu_info {
 694         /* Where the return value will be stored */
 695         __u64 return_pointer;
 696         /* The size of the return value. Just like "size" in "snprintf",
 697          * it limits how many bytes the kernel can write. */
 698         __u32 return_size;
 699         /* The query request id. */
 700         __u32 query;
 701
 702         union {
 703                 struct {
 704                         __u32 id;
 705                         __u32 _pad;
 706                 } mode_crtc;
 707
 708                 struct {
 709                         /** AMDGPU_HW_IP_* */
 710                         __u32 type;
 711                         /**
 712                          * Index of the IP if there are more IPs of the same
 713                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 714                          */
 715                         __u32 ip_instance;
 716                 } query_hw_ip;
 717
 718                 struct {
 719                         __u32 dword_offset;
 720                         /** number of registers to read */
 721                         __u32 count;
 722                         __u32 instance;
 723                         /** For future use, no flags defined so far */
 724                         __u32 flags;
 725                 } read_mmr_reg;
 726
 727                 struct drm_amdgpu_query_fw query_fw;
 728
 729                 struct {
 730                         __u32 type;
 731                         __u32 offset;
 732                 } vbios_info;
 733
 734                 struct {
 735                         __u32 type;
 736                 } sensor_info;
 737         };
 738 };
 739
 740 struct drm_amdgpu_info_gds {
 741         /** GDS GFX partition size */
 742         __u32 gds_gfx_partition_size;
 743         /** GDS compute partition size */
 744         __u32 compute_partition_size;
 745         /** total GDS memory size */
 746         __u32 gds_total_size;
 747         /** GWS size per GFX partition */
 748         __u32 gws_per_gfx_partition;
 749         /** GSW size per compute partition */
 750         __u32 gws_per_compute_partition;
 751         /** OA size per GFX partition */
 752         __u32 oa_per_gfx_partition;
 753         /** OA size per compute partition */
 754         __u32 oa_per_compute_partition;
 755         __u32 _pad;
 756 };
 757
 758 struct drm_amdgpu_info_vram_gtt {
 759         __u64 vram_size;
 760         __u64 vram_cpu_accessible_size;
 761         __u64 gtt_size;
 762 };
 763
 764 struct drm_amdgpu_heap_info {
 765         /** max. physical memory */
 766         __u64 total_heap_size;
 767
 768         /** Theoretical max. available memory in the given heap */
 769         __u64 usable_heap_size;
 770
 771         /**
 772          * Number of bytes allocated in the heap. This includes all processes
 773          * and private allocations in the kernel. It changes when new buffers
 774          * are allocated, freed, and moved. It cannot be larger than
 775          * heap_size.
 776          */
 777         __u64 heap_usage;
 778
 779         /**
 780          * Theoretical possible max. size of buffer which
 781          * could be allocated in the given heap
 782          */
 783         __u64 max_allocation;
 784 };
 785
 786 struct drm_amdgpu_memory_info {
 787         struct drm_amdgpu_heap_info vram;
 788         struct drm_amdgpu_heap_info cpu_accessible_vram;
 789         struct drm_amdgpu_heap_info gtt;
 790 };
 791
 792 struct drm_amdgpu_info_firmware {
 793         __u32 ver;
 794         __u32 feature;
 795 };
 796
 797 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 798 #define AMDGPU_VRAM_TYPE_GDDR1 1
 799 #define AMDGPU_VRAM_TYPE_DDR2  2
 800 #define AMDGPU_VRAM_TYPE_GDDR3 3
 801 #define AMDGPU_VRAM_TYPE_GDDR4 4
 802 #define AMDGPU_VRAM_TYPE_GDDR5 5
 803 #define AMDGPU_VRAM_TYPE_HBM   6
 804 #define AMDGPU_VRAM_TYPE_DDR3  7
 805
 806 struct drm_amdgpu_info_device {
 807         /** PCI Device ID */
 808         __u32 device_id;
 809         /** Internal chip revision: A0, A1, etc.) */
 810         __u32 chip_rev;
 811         __u32 external_rev;
 812         /** Revision id in PCI Config space */
 813         __u32 pci_rev;
 814         __u32 family;
 815         __u32 num_shader_engines;
 816         __u32 num_shader_arrays_per_engine;
 817         /* in KHz */
 818         __u32 gpu_counter_freq;
 819         __u64 max_engine_clock;
 820         __u64 max_memory_clock;
 821         /* cu information */
 822         __u32 cu_active_number;
 823         /* NOTE: cu_ao_mask is INVALID, DON'T use it */
 824         __u32 cu_ao_mask;
 825         __u32 cu_bitmap[4][4];
 826         /** Render backend pipe mask. One render backend is CB+DB. */
 827         __u32 enabled_rb_pipes_mask;
 828         __u32 num_rb_pipes;
 829         __u32 num_hw_gfx_contexts;
 830         __u32 _pad;
 831         __u64 ids_flags;
 832         /** Starting virtual address for UMDs. */
 833         __u64 virtual_address_offset;
 834         /** The maximum virtual address */
 835         __u64 virtual_address_max;
 836         /** Required alignment of virtual addresses. */
 837         __u32 virtual_address_alignment;
 838         /** Page table entry - fragment size */
 839         __u32 pte_fragment_size;
 840         __u32 gart_page_size;
 841         /** constant engine ram size*/
 842         __u32 ce_ram_size;
 843         /** video memory type info*/
 844         __u32 vram_type;
 845         /** video memory bit width*/
 846         __u32 vram_bit_width;
 847         /* vce harvesting instance */
 848         __u32 vce_harvest_config;
 849         /* gfx double offchip LDS buffers */
 850         __u32 gc_double_offchip_lds_buf;
 851         /* NGG Primitive Buffer */
 852         __u64 prim_buf_gpu_addr;
 853         /* NGG Position Buffer */
 854         __u64 pos_buf_gpu_addr;
 855         /* NGG Control Sideband */
 856         __u64 cntl_sb_buf_gpu_addr;
 857         /* NGG Parameter Cache */
 858         __u64 param_buf_gpu_addr;
 859         __u32 prim_buf_size;
 860         __u32 pos_buf_size;
 861         __u32 cntl_sb_buf_size;
 862         __u32 param_buf_size;
 863         /* wavefront size*/
 864         __u32 wave_front_size;
 865         /* shader visible vgprs*/
 866         __u32 num_shader_visible_vgprs;
 867         /* CU per shader array*/
 868         __u32 num_cu_per_sh;
 869         /* number of tcc blocks*/
 870         __u32 num_tcc_blocks;
 871         /* gs vgt table depth*/
 872         __u32 gs_vgt_table_depth;
 873         /* gs primitive buffer depth*/
 874         __u32 gs_prim_buffer_depth;
 875         /* max gs wavefront per vgt*/
 876         __u32 max_gs_waves_per_vgt;
 877         __u32 _pad1;
 878         /* always on cu bitmap */
 879         __u32 cu_ao_bitmap[4][4];
 880         /** Starting high virtual address for UMDs. */
 881         __u64 high_va_offset;
 882         /** The maximum high virtual address */
 883         __u64 high_va_max;
 884 };
 885
 886 struct drm_amdgpu_info_hw_ip {
 887         /** Version of h/w IP */
 888         __u32  hw_ip_version_major;
 889         __u32  hw_ip_version_minor;
 890         /** Capabilities */
 891         __u64  capabilities_flags;
 892         /** command buffer address start alignment*/
 893         __u32  ib_start_alignment;
 894         /** command buffer size alignment*/
 895         __u32  ib_size_alignment;
 896         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
 897         __u32  available_rings;
 898         __u32  _pad;
 899 };
 900
 901 struct drm_amdgpu_info_num_handles {
 902         /** Max handles as supported by firmware for UVD */
 903         __u32  uvd_max_handles;
 904         /** Handles currently in use for UVD */
 905         __u32  uvd_used_handles;
 906 };
 907
 908 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES          6
 909
 910 struct drm_amdgpu_info_vce_clock_table_entry {
 911         /** System clock */
 912         __u32 sclk;
 913         /** Memory clock */
 914         __u32 mclk;
 915         /** VCE clock */
 916         __u32 eclk;
 917         __u32 pad;
 918 };
 919
 920 struct drm_amdgpu_info_vce_clock_table {
 921         struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
 922         __u32 num_valid_entries;
 923         __u32 pad;
 924 };
 925
 926 /*
 927  * Supported GPU families
 928  */
 929 #define AMDGPU_FAMILY_UNKNOWN                   0
 930 #define AMDGPU_FAMILY_SI                        110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
 931 #define AMDGPU_FAMILY_CI                        120 /* Bonaire, Hawaii */
 932 #define AMDGPU_FAMILY_KV                        125 /* Kaveri, Kabini, Mullins */
 933 #define AMDGPU_FAMILY_VI                        130 /* Iceland, Tonga */
 934 #define AMDGPU_FAMILY_CZ                        135 /* Carrizo, Stoney */
 935 #define AMDGPU_FAMILY_AI                        141 /* Vega10 */
 936 #define AMDGPU_FAMILY_RV                        142 /* Raven */
 937
 938 #if defined(__cplusplus)
 939 }
 940 #endif
 941
 942 #endif