include/uapi/drm/amdgpu_drm.h

   1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * Copyright 2014 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32 #ifndef __AMDGPU_DRM_H__
  33 #define __AMDGPU_DRM_H__
  34
  35 #include "drm.h"
  36
  37 #if defined(__cplusplus)
  38 extern "C" {
  39 #endif
  40
  41 #define DRM_AMDGPU_GEM_CREATE           0x00
  42 #define DRM_AMDGPU_GEM_MMAP             0x01
  43 #define DRM_AMDGPU_CTX                  0x02
  44 #define DRM_AMDGPU_BO_LIST              0x03
  45 #define DRM_AMDGPU_CS                   0x04
  46 #define DRM_AMDGPU_INFO                 0x05
  47 #define DRM_AMDGPU_GEM_METADATA         0x06
  48 #define DRM_AMDGPU_GEM_WAIT_IDLE        0x07
  49 #define DRM_AMDGPU_GEM_VA               0x08
  50 #define DRM_AMDGPU_WAIT_CS              0x09
  51 #define DRM_AMDGPU_GEM_OP               0x10
  52 #define DRM_AMDGPU_GEM_USERPTR          0x11
  53 #define DRM_AMDGPU_WAIT_FENCES          0x12
  54 #define DRM_AMDGPU_VM                   0x13
  55 #define DRM_AMDGPU_FENCE_TO_HANDLE      0x14
  56 #define DRM_AMDGPU_SCHED                0x15
  57
  58 #define DRM_IOCTL_AMDGPU_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  59 #define DRM_IOCTL_AMDGPU_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
  60 #define DRM_IOCTL_AMDGPU_CTX            DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
  61 #define DRM_IOCTL_AMDGPU_BO_LIST        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
  62 #define DRM_IOCTL_AMDGPU_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
  63 #define DRM_IOCTL_AMDGPU_INFO           DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
  64 #define DRM_IOCTL_AMDGPU_GEM_METADATA   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
  65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
  66 #define DRM_IOCTL_AMDGPU_GEM_VA         DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
  67 #define DRM_IOCTL_AMDGPU_WAIT_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
  68 #define DRM_IOCTL_AMDGPU_GEM_OP         DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
  69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
  70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
  71 #define DRM_IOCTL_AMDGPU_VM             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
  72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
  73 #define DRM_IOCTL_AMDGPU_SCHED          DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
  74
  75 #define AMDGPU_GEM_DOMAIN_CPU           0x1
  76 #define AMDGPU_GEM_DOMAIN_GTT           0x2
  77 #define AMDGPU_GEM_DOMAIN_VRAM          0x4
  78 #define AMDGPU_GEM_DOMAIN_GDS           0x8
  79 #define AMDGPU_GEM_DOMAIN_GWS           0x10
  80 #define AMDGPU_GEM_DOMAIN_OA            0x20
  81 #define AMDGPU_GEM_DOMAIN_MASK          (AMDGPU_GEM_DOMAIN_CPU | \
  82                                          AMDGPU_GEM_DOMAIN_GTT | \
  83                                          AMDGPU_GEM_DOMAIN_VRAM | \
  84                                          AMDGPU_GEM_DOMAIN_GDS | \
  85                                          AMDGPU_GEM_DOMAIN_GWS | \
  86                                          AMDGPU_GEM_DOMAIN_OA)
  87
  88 /* Flag that CPU access will be required for the case of VRAM domain */
  89 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED   (1 << 0)
  90 /* Flag that CPU access will not work, this VRAM domain is invisible */
  91 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS         (1 << 1)
  92 /* Flag that USWC attributes should be used for GTT */
  93 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC          (1 << 2)
  94 /* Flag that the memory should be in VRAM and cleared */
  95 #define AMDGPU_GEM_CREATE_VRAM_CLEARED          (1 << 3)
  96 /* Flag that create shadow bo(GTT) while allocating vram bo */
  97 #define AMDGPU_GEM_CREATE_SHADOW                (1 << 4)
  98 /* Flag that allocating the BO should use linear VRAM */
  99 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS       (1 << 5)
 100 /* Flag that BO is always valid in this VM */
 101 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID       (1 << 6)
 102 /* Flag that BO sharing will be explicitly synchronized */
 103 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC         (1 << 7)
 104
 105 struct drm_amdgpu_gem_create_in  {
 106         /** the requested memory size */
 107         __u64 bo_size;
 108         /** physical start_addr alignment in bytes for some HW requirements */
 109         __u64 alignment;
 110         /** the requested memory domains */
 111         __u64 domains;
 112         /** allocation flags */
 113         __u64 domain_flags;
 114 };
 115
 116 struct drm_amdgpu_gem_create_out  {
 117         /** returned GEM object handle */
 118         __u32 handle;
 119         __u32 _pad;
 120 };
 121
 122 union drm_amdgpu_gem_create {
 123         struct drm_amdgpu_gem_create_in         in;
 124         struct drm_amdgpu_gem_create_out        out;
 125 };
 126
 127 /** Opcode to create new residency list.  */
 128 #define AMDGPU_BO_LIST_OP_CREATE        0
 129 /** Opcode to destroy previously created residency list */
 130 #define AMDGPU_BO_LIST_OP_DESTROY       1
 131 /** Opcode to update resource information in the list */
 132 #define AMDGPU_BO_LIST_OP_UPDATE        2
 133
 134 struct drm_amdgpu_bo_list_in {
 135         /** Type of operation */
 136         __u32 operation;
 137         /** Handle of list or 0 if we want to create one */
 138         __u32 list_handle;
 139         /** Number of BOs in list  */
 140         __u32 bo_number;
 141         /** Size of each element describing BO */
 142         __u32 bo_info_size;
 143         /** Pointer to array describing BOs */
 144         __u64 bo_info_ptr;
 145 };
 146
 147 struct drm_amdgpu_bo_list_entry {
 148         /** Handle of BO */
 149         __u32 bo_handle;
 150         /** New (if specified) BO priority to be used during migration */
 151         __u32 bo_priority;
 152 };
 153
 154 struct drm_amdgpu_bo_list_out {
 155         /** Handle of resource list  */
 156         __u32 list_handle;
 157         __u32 _pad;
 158 };
 159
 160 union drm_amdgpu_bo_list {
 161         struct drm_amdgpu_bo_list_in in;
 162         struct drm_amdgpu_bo_list_out out;
 163 };
 164
 165 /* context related */
 166 #define AMDGPU_CTX_OP_ALLOC_CTX 1
 167 #define AMDGPU_CTX_OP_FREE_CTX  2
 168 #define AMDGPU_CTX_OP_QUERY_STATE       3
 169 #define AMDGPU_CTX_OP_QUERY_STATE2      4
 170
 171 /* GPU reset status */
 172 #define AMDGPU_CTX_NO_RESET             0
 173 /* this the context caused it */
 174 #define AMDGPU_CTX_GUILTY_RESET         1
 175 /* some other context caused it */
 176 #define AMDGPU_CTX_INNOCENT_RESET       2
 177 /* unknown cause */
 178 #define AMDGPU_CTX_UNKNOWN_RESET        3
 179
 180 /* indicate gpu reset occured after ctx created */
 181 #define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
 182 /* indicate vram lost occured after ctx created */
 183 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
 184 /* indicate some job from this context once cause gpu hang */
 185 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
 186
 187 /* Context priority level */
 188 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 189 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
 190 #define AMDGPU_CTX_PRIORITY_LOW         -512
 191 #define AMDGPU_CTX_PRIORITY_NORMAL      0
 192 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
 193 #define AMDGPU_CTX_PRIORITY_HIGH        512
 194 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
 195
 196 struct drm_amdgpu_ctx_in {
 197         /** AMDGPU_CTX_OP_* */
 198         __u32   op;
 199         /** For future use, no flags defined so far */
 200         __u32   flags;
 201         __u32   ctx_id;
 202         __s32   priority;
 203 };
 204
 205 union drm_amdgpu_ctx_out {
 206                 struct {
 207                         __u32   ctx_id;
 208                         __u32   _pad;
 209                 } alloc;
 210
 211                 struct {
 212                         /** For future use, no flags defined so far */
 213                         __u64   flags;
 214                         /** Number of resets caused by this context so far. */
 215                         __u32   hangs;
 216                         /** Reset status since the last call of the ioctl. */
 217                         __u32   reset_status;
 218                 } state;
 219 };
 220
 221 union drm_amdgpu_ctx {
 222         struct drm_amdgpu_ctx_in in;
 223         union drm_amdgpu_ctx_out out;
 224 };
 225
 226 /* vm ioctl */
 227 #define AMDGPU_VM_OP_RESERVE_VMID       1
 228 #define AMDGPU_VM_OP_UNRESERVE_VMID     2
 229
 230 struct drm_amdgpu_vm_in {
 231         /** AMDGPU_VM_OP_* */
 232         __u32   op;
 233         __u32   flags;
 234 };
 235
 236 struct drm_amdgpu_vm_out {
 237         /** For future use, no flags defined so far */
 238         __u64   flags;
 239 };
 240
 241 union drm_amdgpu_vm {
 242         struct drm_amdgpu_vm_in in;
 243         struct drm_amdgpu_vm_out out;
 244 };
 245
 246 /* sched ioctl */
 247 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE       1
 248
 249 struct drm_amdgpu_sched_in {
 250         /* AMDGPU_SCHED_OP_* */
 251         __u32   op;
 252         __u32   fd;
 253         __s32   priority;
 254         __u32   flags;
 255 };
 256
 257 union drm_amdgpu_sched {
 258         struct drm_amdgpu_sched_in in;
 259 };
 260
 261 /*
 262  * This is not a reliable API and you should expect it to fail for any
 263  * number of reasons and have fallback path that do not use userptr to
 264  * perform any operation.
 265  */
 266 #define AMDGPU_GEM_USERPTR_READONLY     (1 << 0)
 267 #define AMDGPU_GEM_USERPTR_ANONONLY     (1 << 1)
 268 #define AMDGPU_GEM_USERPTR_VALIDATE     (1 << 2)
 269 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 270
 271 struct drm_amdgpu_gem_userptr {
 272         __u64           addr;
 273         __u64           size;
 274         /* AMDGPU_GEM_USERPTR_* */
 275         __u32           flags;
 276         /* Resulting GEM handle */
 277         __u32           handle;
 278 };
 279
 280 /* SI-CI-VI: */
 281 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 282 #define AMDGPU_TILING_ARRAY_MODE_SHIFT                  0
 283 #define AMDGPU_TILING_ARRAY_MODE_MASK                   0xf
 284 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT                 4
 285 #define AMDGPU_TILING_PIPE_CONFIG_MASK                  0x1f
 286 #define AMDGPU_TILING_TILE_SPLIT_SHIFT                  9
 287 #define AMDGPU_TILING_TILE_SPLIT_MASK                   0x7
 288 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT             12
 289 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK              0x7
 290 #define AMDGPU_TILING_BANK_WIDTH_SHIFT                  15
 291 #define AMDGPU_TILING_BANK_WIDTH_MASK                   0x3
 292 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                 17
 293 #define AMDGPU_TILING_BANK_HEIGHT_MASK                  0x3
 294 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT           19
 295 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK            0x3
 296 #define AMDGPU_TILING_NUM_BANKS_SHIFT                   21
 297 #define AMDGPU_TILING_NUM_BANKS_MASK                    0x3
 298
 299 /* GFX9 and later: */
 300 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT                0
 301 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                 0x1f
 302
 303 /* Set/Get helpers for tiling flags. */
 304 #define AMDGPU_TILING_SET(field, value) \
 305         (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 306 #define AMDGPU_TILING_GET(value, field) \
 307         (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 308
 309 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 310 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 311
 312 /** The same structure is shared for input/output */
 313 struct drm_amdgpu_gem_metadata {
 314         /** GEM Object handle */
 315         __u32   handle;
 316         /** Do we want get or set metadata */
 317         __u32   op;
 318         struct {
 319                 /** For future use, no flags defined so far */
 320                 __u64   flags;
 321                 /** family specific tiling info */
 322                 __u64   tiling_info;
 323                 __u32   data_size_bytes;
 324                 __u32   data[64];
 325         } data;
 326 };
 327
 328 struct drm_amdgpu_gem_mmap_in {
 329         /** the GEM object handle */
 330         __u32 handle;
 331         __u32 _pad;
 332 };
 333
 334 struct drm_amdgpu_gem_mmap_out {
 335         /** mmap offset from the vma offset manager */
 336         __u64 addr_ptr;
 337 };
 338
 339 union drm_amdgpu_gem_mmap {
 340         struct drm_amdgpu_gem_mmap_in   in;
 341         struct drm_amdgpu_gem_mmap_out out;
 342 };
 343
 344 struct drm_amdgpu_gem_wait_idle_in {
 345         /** GEM object handle */
 346         __u32 handle;
 347         /** For future use, no flags defined so far */
 348         __u32 flags;
 349         /** Absolute timeout to wait */
 350         __u64 timeout;
 351 };
 352
 353 struct drm_amdgpu_gem_wait_idle_out {
 354         /** BO status:  0 - BO is idle, 1 - BO is busy */
 355         __u32 status;
 356         /** Returned current memory domain */
 357         __u32 domain;
 358 };
 359
 360 union drm_amdgpu_gem_wait_idle {
 361         struct drm_amdgpu_gem_wait_idle_in  in;
 362         struct drm_amdgpu_gem_wait_idle_out out;
 363 };
 364
 365 struct drm_amdgpu_wait_cs_in {
 366         /* Command submission handle
 367          * handle equals 0 means none to wait for
 368          * handle equals ~0ull means wait for the latest sequence number
 369          */
 370         __u64 handle;
 371         /** Absolute timeout to wait */
 372         __u64 timeout;
 373         __u32 ip_type;
 374         __u32 ip_instance;
 375         __u32 ring;
 376         __u32 ctx_id;
 377 };
 378
 379 struct drm_amdgpu_wait_cs_out {
 380         /** CS status:  0 - CS completed, 1 - CS still busy */
 381         __u64 status;
 382 };
 383
 384 union drm_amdgpu_wait_cs {
 385         struct drm_amdgpu_wait_cs_in in;
 386         struct drm_amdgpu_wait_cs_out out;
 387 };
 388
 389 struct drm_amdgpu_fence {
 390         __u32 ctx_id;
 391         __u32 ip_type;
 392         __u32 ip_instance;
 393         __u32 ring;
 394         __u64 seq_no;
 395 };
 396
 397 struct drm_amdgpu_wait_fences_in {
 398         /** This points to uint64_t * which points to fences */
 399         __u64 fences;
 400         __u32 fence_count;
 401         __u32 wait_all;
 402         __u64 timeout_ns;
 403 };
 404
 405 struct drm_amdgpu_wait_fences_out {
 406         __u32 status;
 407         __u32 first_signaled;
 408 };
 409
 410 union drm_amdgpu_wait_fences {
 411         struct drm_amdgpu_wait_fences_in in;
 412         struct drm_amdgpu_wait_fences_out out;
 413 };
 414
 415 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO       0
 416 #define AMDGPU_GEM_OP_SET_PLACEMENT             1
 417
 418 /* Sets or returns a value associated with a buffer. */
 419 struct drm_amdgpu_gem_op {
 420         /** GEM object handle */
 421         __u32   handle;
 422         /** AMDGPU_GEM_OP_* */
 423         __u32   op;
 424         /** Input or return value */
 425         __u64   value;
 426 };
 427
 428 #define AMDGPU_VA_OP_MAP                        1
 429 #define AMDGPU_VA_OP_UNMAP                      2
 430 #define AMDGPU_VA_OP_CLEAR                      3
 431 #define AMDGPU_VA_OP_REPLACE                    4
 432
 433 /* Delay the page table update till the next CS */
 434 #define AMDGPU_VM_DELAY_UPDATE          (1 << 0)
 435
 436 /* Mapping flags */
 437 /* readable mapping */
 438 #define AMDGPU_VM_PAGE_READABLE         (1 << 1)
 439 /* writable mapping */
 440 #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
 441 /* executable mapping, new for VI */
 442 #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
 443 /* partially resident texture */
 444 #define AMDGPU_VM_PAGE_PRT              (1 << 4)
 445 /* MTYPE flags use bit 5 to 8 */
 446 #define AMDGPU_VM_MTYPE_MASK            (0xf << 5)
 447 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
 448 #define AMDGPU_VM_MTYPE_DEFAULT         (0 << 5)
 449 /* Use NC MTYPE instead of default MTYPE */
 450 #define AMDGPU_VM_MTYPE_NC              (1 << 5)
 451 /* Use WC MTYPE instead of default MTYPE */
 452 #define AMDGPU_VM_MTYPE_WC              (2 << 5)
 453 /* Use CC MTYPE instead of default MTYPE */
 454 #define AMDGPU_VM_MTYPE_CC              (3 << 5)
 455 /* Use UC MTYPE instead of default MTYPE */
 456 #define AMDGPU_VM_MTYPE_UC              (4 << 5)
 457
 458 struct drm_amdgpu_gem_va {
 459         /** GEM object handle */
 460         __u32 handle;
 461         __u32 _pad;
 462         /** AMDGPU_VA_OP_* */
 463         __u32 operation;
 464         /** AMDGPU_VM_PAGE_* */
 465         __u32 flags;
 466         /** va address to assign . Must be correctly aligned.*/
 467         __u64 va_address;
 468         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
 469         __u64 offset_in_bo;
 470         /** Specify mapping size. Must be correctly aligned. */
 471         __u64 map_size;
 472 };
 473
 474 #define AMDGPU_HW_IP_GFX          0
 475 #define AMDGPU_HW_IP_COMPUTE      1
 476 #define AMDGPU_HW_IP_DMA          2
 477 #define AMDGPU_HW_IP_UVD          3
 478 #define AMDGPU_HW_IP_VCE          4
 479 #define AMDGPU_HW_IP_UVD_ENC      5
 480 #define AMDGPU_HW_IP_VCN_DEC      6
 481 #define AMDGPU_HW_IP_VCN_ENC      7
 482 #define AMDGPU_HW_IP_NUM          8
 483
 484 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 485
 486 #define AMDGPU_CHUNK_ID_IB              0x01
 487 #define AMDGPU_CHUNK_ID_FENCE           0x02
 488 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 489 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 490 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 491
 492 struct drm_amdgpu_cs_chunk {
 493         __u32           chunk_id;
 494         __u32           length_dw;
 495         __u64           chunk_data;
 496 };
 497
 498 struct drm_amdgpu_cs_in {
 499         /** Rendering context id */
 500         __u32           ctx_id;
 501         /**  Handle of resource list associated with CS */
 502         __u32           bo_list_handle;
 503         __u32           num_chunks;
 504         __u32           _pad;
 505         /** this points to __u64 * which point to cs chunks */
 506         __u64           chunks;
 507 };
 508
 509 struct drm_amdgpu_cs_out {
 510         __u64 handle;
 511 };
 512
 513 union drm_amdgpu_cs {
 514         struct drm_amdgpu_cs_in in;
 515         struct drm_amdgpu_cs_out out;
 516 };
 517
 518 /* Specify flags to be used for IB */
 519
 520 /* This IB should be submitted to CE */
 521 #define AMDGPU_IB_FLAG_CE       (1<<0)
 522
 523 /* Preamble flag, which means the IB could be dropped if no context switch */
 524 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 525
 526 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 527 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 528
 529 /* The IB fence should do the L2 writeback but not invalidate any shader
 530  * caches (L2/vL1/sL1/I$). */
 531 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
 532
 533 struct drm_amdgpu_cs_chunk_ib {
 534         __u32 _pad;
 535         /** AMDGPU_IB_FLAG_* */
 536         __u32 flags;
 537         /** Virtual address to begin IB execution */
 538         __u64 va_start;
 539         /** Size of submission */
 540         __u32 ib_bytes;
 541         /** HW IP to submit to */
 542         __u32 ip_type;
 543         /** HW IP index of the same type to submit to  */
 544         __u32 ip_instance;
 545         /** Ring index to submit to */
 546         __u32 ring;
 547 };
 548
 549 struct drm_amdgpu_cs_chunk_dep {
 550         __u32 ip_type;
 551         __u32 ip_instance;
 552         __u32 ring;
 553         __u32 ctx_id;
 554         __u64 handle;
 555 };
 556
 557 struct drm_amdgpu_cs_chunk_fence {
 558         __u32 handle;
 559         __u32 offset;
 560 };
 561
 562 struct drm_amdgpu_cs_chunk_sem {
 563         __u32 handle;
 564 };
 565
 566 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ      0
 567 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD   1
 568 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
 569
 570 union drm_amdgpu_fence_to_handle {
 571         struct {
 572                 struct drm_amdgpu_fence fence;
 573                 __u32 what;
 574                 __u32 pad;
 575         } in;
 576         struct {
 577                 __u32 handle;
 578         } out;
 579 };
 580
 581 struct drm_amdgpu_cs_chunk_data {
 582         union {
 583                 struct drm_amdgpu_cs_chunk_ib           ib_data;
 584                 struct drm_amdgpu_cs_chunk_fence        fence_data;
 585         };
 586 };
 587
 588 /**
 589  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 590  *
 591  */
 592 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 593 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 594
 595 /* indicate if acceleration can be working */
 596 #define AMDGPU_INFO_ACCEL_WORKING               0x00
 597 /* get the crtc_id from the mode object id? */
 598 #define AMDGPU_INFO_CRTC_FROM_ID                0x01
 599 /* query hw IP info */
 600 #define AMDGPU_INFO_HW_IP_INFO                  0x02
 601 /* query hw IP instance count for the specified type */
 602 #define AMDGPU_INFO_HW_IP_COUNT                 0x03
 603 /* timestamp for GL_ARB_timer_query */
 604 #define AMDGPU_INFO_TIMESTAMP                   0x05
 605 /* Query the firmware version */
 606 #define AMDGPU_INFO_FW_VERSION                  0x0e
 607         /* Subquery id: Query VCE firmware version */
 608         #define AMDGPU_INFO_FW_VCE              0x1
 609         /* Subquery id: Query UVD firmware version */
 610         #define AMDGPU_INFO_FW_UVD              0x2
 611         /* Subquery id: Query GMC firmware version */
 612         #define AMDGPU_INFO_FW_GMC              0x03
 613         /* Subquery id: Query GFX ME firmware version */
 614         #define AMDGPU_INFO_FW_GFX_ME           0x04
 615         /* Subquery id: Query GFX PFP firmware version */
 616         #define AMDGPU_INFO_FW_GFX_PFP          0x05
 617         /* Subquery id: Query GFX CE firmware version */
 618         #define AMDGPU_INFO_FW_GFX_CE           0x06
 619         /* Subquery id: Query GFX RLC firmware version */
 620         #define AMDGPU_INFO_FW_GFX_RLC          0x07
 621         /* Subquery id: Query GFX MEC firmware version */
 622         #define AMDGPU_INFO_FW_GFX_MEC          0x08
 623         /* Subquery id: Query SMC firmware version */
 624         #define AMDGPU_INFO_FW_SMC              0x0a
 625         /* Subquery id: Query SDMA firmware version */
 626         #define AMDGPU_INFO_FW_SDMA             0x0b
 627         /* Subquery id: Query PSP SOS firmware version */
 628         #define AMDGPU_INFO_FW_SOS              0x0c
 629         /* Subquery id: Query PSP ASD firmware version */
 630         #define AMDGPU_INFO_FW_ASD              0x0d
 631         /* Subquery id: Query VCN firmware version */
 632         #define AMDGPU_INFO_FW_VCN              0x0e
 633 /* number of bytes moved for TTM migration */
 634 #define AMDGPU_INFO_NUM_BYTES_MOVED             0x0f
 635 /* the used VRAM size */
 636 #define AMDGPU_INFO_VRAM_USAGE                  0x10
 637 /* the used GTT size */
 638 #define AMDGPU_INFO_GTT_USAGE                   0x11
 639 /* Information about GDS, etc. resource configuration */
 640 #define AMDGPU_INFO_GDS_CONFIG                  0x13
 641 /* Query information about VRAM and GTT domains */
 642 #define AMDGPU_INFO_VRAM_GTT                    0x14
 643 /* Query information about register in MMR address space*/
 644 #define AMDGPU_INFO_READ_MMR_REG                0x15
 645 /* Query information about device: rev id, family, etc. */
 646 #define AMDGPU_INFO_DEV_INFO                    0x16
 647 /* visible vram usage */
 648 #define AMDGPU_INFO_VIS_VRAM_USAGE              0x17
 649 /* number of TTM buffer evictions */
 650 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
 651 /* Query memory about VRAM and GTT domains */
 652 #define AMDGPU_INFO_MEMORY                      0x19
 653 /* Query vce clock table */
 654 #define AMDGPU_INFO_VCE_CLOCK_TABLE             0x1A
 655 /* Query vbios related information */
 656 #define AMDGPU_INFO_VBIOS                       0x1B
 657         /* Subquery id: Query vbios size */
 658         #define AMDGPU_INFO_VBIOS_SIZE          0x1
 659         /* Subquery id: Query vbios image */
 660         #define AMDGPU_INFO_VBIOS_IMAGE         0x2
 661 /* Query UVD handles */
 662 #define AMDGPU_INFO_NUM_HANDLES                 0x1C
 663 /* Query sensor related information */
 664 #define AMDGPU_INFO_SENSOR                      0x1D
 665         /* Subquery id: Query GPU shader clock */
 666         #define AMDGPU_INFO_SENSOR_GFX_SCLK             0x1
 667         /* Subquery id: Query GPU memory clock */
 668         #define AMDGPU_INFO_SENSOR_GFX_MCLK             0x2
 669         /* Subquery id: Query GPU temperature */
 670         #define AMDGPU_INFO_SENSOR_GPU_TEMP             0x3
 671         /* Subquery id: Query GPU load */
 672         #define AMDGPU_INFO_SENSOR_GPU_LOAD             0x4
 673         /* Subquery id: Query average GPU power */
 674         #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER        0x5
 675         /* Subquery id: Query northbridge voltage */
 676         #define AMDGPU_INFO_SENSOR_VDDNB                0x6
 677         /* Subquery id: Query graphics voltage */
 678         #define AMDGPU_INFO_SENSOR_VDDGFX               0x7
 679         /* Subquery id: Query GPU stable pstate shader clock */
 680         #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK               0x8
 681         /* Subquery id: Query GPU stable pstate memory clock */
 682         #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK               0x9
 683 /* Number of VRAM page faults on CPU access. */
 684 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
 685 #define AMDGPU_INFO_VRAM_LOST_COUNTER           0x1F
 686
 687 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT  0
 688 #define AMDGPU_INFO_MMR_SE_INDEX_MASK   0xff
 689 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT  8
 690 #define AMDGPU_INFO_MMR_SH_INDEX_MASK   0xff
 691
 692 struct drm_amdgpu_query_fw {
 693         /** AMDGPU_INFO_FW_* */
 694         __u32 fw_type;
 695         /**
 696          * Index of the IP if there are more IPs of
 697          * the same type.
 698          */
 699         __u32 ip_instance;
 700         /**
 701          * Index of the engine. Whether this is used depends
 702          * on the firmware type. (e.g. MEC, SDMA)
 703          */
 704         __u32 index;
 705         __u32 _pad;
 706 };
 707
 708 /* Input structure for the INFO ioctl */
 709 struct drm_amdgpu_info {
 710         /* Where the return value will be stored */
 711         __u64 return_pointer;
 712         /* The size of the return value. Just like "size" in "snprintf",
 713          * it limits how many bytes the kernel can write. */
 714         __u32 return_size;
 715         /* The query request id. */
 716         __u32 query;
 717
 718         union {
 719                 struct {
 720                         __u32 id;
 721                         __u32 _pad;
 722                 } mode_crtc;
 723
 724                 struct {
 725                         /** AMDGPU_HW_IP_* */
 726                         __u32 type;
 727                         /**
 728                          * Index of the IP if there are more IPs of the same
 729                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 730                          */
 731                         __u32 ip_instance;
 732                 } query_hw_ip;
 733
 734                 struct {
 735                         __u32 dword_offset;
 736                         /** number of registers to read */
 737                         __u32 count;
 738                         __u32 instance;
 739                         /** For future use, no flags defined so far */
 740                         __u32 flags;
 741                 } read_mmr_reg;
 742
 743                 struct drm_amdgpu_query_fw query_fw;
 744
 745                 struct {
 746                         __u32 type;
 747                         __u32 offset;
 748                 } vbios_info;
 749
 750                 struct {
 751                         __u32 type;
 752                 } sensor_info;
 753         };
 754 };
 755
 756 struct drm_amdgpu_info_gds {
 757         /** GDS GFX partition size */
 758         __u32 gds_gfx_partition_size;
 759         /** GDS compute partition size */
 760         __u32 compute_partition_size;
 761         /** total GDS memory size */
 762         __u32 gds_total_size;
 763         /** GWS size per GFX partition */
 764         __u32 gws_per_gfx_partition;
 765         /** GSW size per compute partition */
 766         __u32 gws_per_compute_partition;
 767         /** OA size per GFX partition */
 768         __u32 oa_per_gfx_partition;
 769         /** OA size per compute partition */
 770         __u32 oa_per_compute_partition;
 771         __u32 _pad;
 772 };
 773
 774 struct drm_amdgpu_info_vram_gtt {
 775         __u64 vram_size;
 776         __u64 vram_cpu_accessible_size;
 777         __u64 gtt_size;
 778 };
 779
 780 struct drm_amdgpu_heap_info {
 781         /** max. physical memory */
 782         __u64 total_heap_size;
 783
 784         /** Theoretical max. available memory in the given heap */
 785         __u64 usable_heap_size;
 786
 787         /**
 788          * Number of bytes allocated in the heap. This includes all processes
 789          * and private allocations in the kernel. It changes when new buffers
 790          * are allocated, freed, and moved. It cannot be larger than
 791          * heap_size.
 792          */
 793         __u64 heap_usage;
 794
 795         /**
 796          * Theoretical possible max. size of buffer which
 797          * could be allocated in the given heap
 798          */
 799         __u64 max_allocation;
 800 };
 801
 802 struct drm_amdgpu_memory_info {
 803         struct drm_amdgpu_heap_info vram;
 804         struct drm_amdgpu_heap_info cpu_accessible_vram;
 805         struct drm_amdgpu_heap_info gtt;
 806 };
 807
 808 struct drm_amdgpu_info_firmware {
 809         __u32 ver;
 810         __u32 feature;
 811 };
 812
 813 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 814 #define AMDGPU_VRAM_TYPE_GDDR1 1
 815 #define AMDGPU_VRAM_TYPE_DDR2  2
 816 #define AMDGPU_VRAM_TYPE_GDDR3 3
 817 #define AMDGPU_VRAM_TYPE_GDDR4 4
 818 #define AMDGPU_VRAM_TYPE_GDDR5 5
 819 #define AMDGPU_VRAM_TYPE_HBM   6
 820 #define AMDGPU_VRAM_TYPE_DDR3  7
 821 #define AMDGPU_VRAM_TYPE_DDR4  8
 822
 823 struct drm_amdgpu_info_device {
 824         /** PCI Device ID */
 825         __u32 device_id;
 826         /** Internal chip revision: A0, A1, etc.) */
 827         __u32 chip_rev;
 828         __u32 external_rev;
 829         /** Revision id in PCI Config space */
 830         __u32 pci_rev;
 831         __u32 family;
 832         __u32 num_shader_engines;
 833         __u32 num_shader_arrays_per_engine;
 834         /* in KHz */
 835         __u32 gpu_counter_freq;
 836         __u64 max_engine_clock;
 837         __u64 max_memory_clock;
 838         /* cu information */
 839         __u32 cu_active_number;
 840         /* NOTE: cu_ao_mask is INVALID, DON'T use it */
 841         __u32 cu_ao_mask;
 842         __u32 cu_bitmap[4][4];
 843         /** Render backend pipe mask. One render backend is CB+DB. */
 844         __u32 enabled_rb_pipes_mask;
 845         __u32 num_rb_pipes;
 846         __u32 num_hw_gfx_contexts;
 847         __u32 _pad;
 848         __u64 ids_flags;
 849         /** Starting virtual address for UMDs. */
 850         __u64 virtual_address_offset;
 851         /** The maximum virtual address */
 852         __u64 virtual_address_max;
 853         /** Required alignment of virtual addresses. */
 854         __u32 virtual_address_alignment;
 855         /** Page table entry - fragment size */
 856         __u32 pte_fragment_size;
 857         __u32 gart_page_size;
 858         /** constant engine ram size*/
 859         __u32 ce_ram_size;
 860         /** video memory type info*/
 861         __u32 vram_type;
 862         /** video memory bit width*/
 863         __u32 vram_bit_width;
 864         /* vce harvesting instance */
 865         __u32 vce_harvest_config;
 866         /* gfx double offchip LDS buffers */
 867         __u32 gc_double_offchip_lds_buf;
 868         /* NGG Primitive Buffer */
 869         __u64 prim_buf_gpu_addr;
 870         /* NGG Position Buffer */
 871         __u64 pos_buf_gpu_addr;
 872         /* NGG Control Sideband */
 873         __u64 cntl_sb_buf_gpu_addr;
 874         /* NGG Parameter Cache */
 875         __u64 param_buf_gpu_addr;
 876         __u32 prim_buf_size;
 877         __u32 pos_buf_size;
 878         __u32 cntl_sb_buf_size;
 879         __u32 param_buf_size;
 880         /* wavefront size*/
 881         __u32 wave_front_size;
 882         /* shader visible vgprs*/
 883         __u32 num_shader_visible_vgprs;
 884         /* CU per shader array*/
 885         __u32 num_cu_per_sh;
 886         /* number of tcc blocks*/
 887         __u32 num_tcc_blocks;
 888         /* gs vgt table depth*/
 889         __u32 gs_vgt_table_depth;
 890         /* gs primitive buffer depth*/
 891         __u32 gs_prim_buffer_depth;
 892         /* max gs wavefront per vgt*/
 893         __u32 max_gs_waves_per_vgt;
 894         __u32 _pad1;
 895         /* always on cu bitmap */
 896         __u32 cu_ao_bitmap[4][4];
 897         /** Starting high virtual address for UMDs. */
 898         __u64 high_va_offset;
 899         /** The maximum high virtual address */
 900         __u64 high_va_max;
 901 };
 902
 903 struct drm_amdgpu_info_hw_ip {
 904         /** Version of h/w IP */
 905         __u32  hw_ip_version_major;
 906         __u32  hw_ip_version_minor;
 907         /** Capabilities */
 908         __u64  capabilities_flags;
 909         /** command buffer address start alignment*/
 910         __u32  ib_start_alignment;
 911         /** command buffer size alignment*/
 912         __u32  ib_size_alignment;
 913         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
 914         __u32  available_rings;
 915         __u32  _pad;
 916 };
 917
 918 struct drm_amdgpu_info_num_handles {
 919         /** Max handles as supported by firmware for UVD */
 920         __u32  uvd_max_handles;
 921         /** Handles currently in use for UVD */
 922         __u32  uvd_used_handles;
 923 };
 924
 925 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES          6
 926
 927 struct drm_amdgpu_info_vce_clock_table_entry {
 928         /** System clock */
 929         __u32 sclk;
 930         /** Memory clock */
 931         __u32 mclk;
 932         /** VCE clock */
 933         __u32 eclk;
 934         __u32 pad;
 935 };
 936
 937 struct drm_amdgpu_info_vce_clock_table {
 938         struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
 939         __u32 num_valid_entries;
 940         __u32 pad;
 941 };
 942
 943 /*
 944  * Supported GPU families
 945  */
 946 #define AMDGPU_FAMILY_UNKNOWN                   0
 947 #define AMDGPU_FAMILY_SI                        110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
 948 #define AMDGPU_FAMILY_CI                        120 /* Bonaire, Hawaii */
 949 #define AMDGPU_FAMILY_KV                        125 /* Kaveri, Kabini, Mullins */
 950 #define AMDGPU_FAMILY_VI                        130 /* Iceland, Tonga */
 951 #define AMDGPU_FAMILY_CZ                        135 /* Carrizo, Stoney */
 952 #define AMDGPU_FAMILY_AI                        141 /* Vega10 */
 953 #define AMDGPU_FAMILY_RV                        142 /* Raven */
 954
 955 #if defined(__cplusplus)
 956 }
 957 #endif
 958
 959 #endif