include/uapi/drm/amdgpu_drm.h

   1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * Copyright 2014 Advanced Micro Devices, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32 #ifndef __AMDGPU_DRM_H__
  33 #define __AMDGPU_DRM_H__
  34
  35 #include "drm.h"
  36
  37 #if defined(__cplusplus)
  38 extern "C" {
  39 #endif
  40
  41 #define DRM_AMDGPU_GEM_CREATE           0x00
  42 #define DRM_AMDGPU_GEM_MMAP             0x01
  43 #define DRM_AMDGPU_CTX                  0x02
  44 #define DRM_AMDGPU_BO_LIST              0x03
  45 #define DRM_AMDGPU_CS                   0x04
  46 #define DRM_AMDGPU_INFO                 0x05
  47 #define DRM_AMDGPU_GEM_METADATA         0x06
  48 #define DRM_AMDGPU_GEM_WAIT_IDLE        0x07
  49 #define DRM_AMDGPU_GEM_VA               0x08
  50 #define DRM_AMDGPU_WAIT_CS              0x09
  51 #define DRM_AMDGPU_GEM_OP               0x10
  52 #define DRM_AMDGPU_GEM_USERPTR          0x11
  53 #define DRM_AMDGPU_WAIT_FENCES          0x12
  54 #define DRM_AMDGPU_VM                   0x13
  55 #define DRM_AMDGPU_FENCE_TO_HANDLE      0x14
  56 #define DRM_AMDGPU_SCHED                0x15
  57
  58 #define DRM_IOCTL_AMDGPU_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
  59 #define DRM_IOCTL_AMDGPU_GEM_MMAP       DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
  60 #define DRM_IOCTL_AMDGPU_CTX            DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
  61 #define DRM_IOCTL_AMDGPU_BO_LIST        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
  62 #define DRM_IOCTL_AMDGPU_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
  63 #define DRM_IOCTL_AMDGPU_INFO           DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
  64 #define DRM_IOCTL_AMDGPU_GEM_METADATA   DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
  65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE  DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
  66 #define DRM_IOCTL_AMDGPU_GEM_VA         DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
  67 #define DRM_IOCTL_AMDGPU_WAIT_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
  68 #define DRM_IOCTL_AMDGPU_GEM_OP         DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
  69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
  70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
  71 #define DRM_IOCTL_AMDGPU_VM             DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
  72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
  73 #define DRM_IOCTL_AMDGPU_SCHED          DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
  74
  75 #define AMDGPU_GEM_DOMAIN_CPU           0x1
  76 #define AMDGPU_GEM_DOMAIN_GTT           0x2
  77 #define AMDGPU_GEM_DOMAIN_VRAM          0x4
  78 #define AMDGPU_GEM_DOMAIN_GDS           0x8
  79 #define AMDGPU_GEM_DOMAIN_GWS           0x10
  80 #define AMDGPU_GEM_DOMAIN_OA            0x20
  81
  82 /* Flag that CPU access will be required for the case of VRAM domain */
  83 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED   (1 << 0)
  84 /* Flag that CPU access will not work, this VRAM domain is invisible */
  85 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS         (1 << 1)
  86 /* Flag that USWC attributes should be used for GTT */
  87 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC          (1 << 2)
  88 /* Flag that the memory should be in VRAM and cleared */
  89 #define AMDGPU_GEM_CREATE_VRAM_CLEARED          (1 << 3)
  90 /* Flag that create shadow bo(GTT) while allocating vram bo */
  91 #define AMDGPU_GEM_CREATE_SHADOW                (1 << 4)
  92 /* Flag that allocating the BO should use linear VRAM */
  93 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS       (1 << 5)
  94 /* Flag that BO is always valid in this VM */
  95 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID       (1 << 6)
  96 /* Flag that BO sharing will be explicitly synchronized */
  97 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC         (1 << 7)
  98
  99 struct drm_amdgpu_gem_create_in  {
 100         /** the requested memory size */
 101         __u64 bo_size;
 102         /** physical start_addr alignment in bytes for some HW requirements */
 103         __u64 alignment;
 104         /** the requested memory domains */
 105         __u64 domains;
 106         /** allocation flags */
 107         __u64 domain_flags;
 108 };
 109
 110 struct drm_amdgpu_gem_create_out  {
 111         /** returned GEM object handle */
 112         __u32 handle;
 113         __u32 _pad;
 114 };
 115
 116 union drm_amdgpu_gem_create {
 117         struct drm_amdgpu_gem_create_in         in;
 118         struct drm_amdgpu_gem_create_out        out;
 119 };
 120
 121 /** Opcode to create new residency list.  */
 122 #define AMDGPU_BO_LIST_OP_CREATE        0
 123 /** Opcode to destroy previously created residency list */
 124 #define AMDGPU_BO_LIST_OP_DESTROY       1
 125 /** Opcode to update resource information in the list */
 126 #define AMDGPU_BO_LIST_OP_UPDATE        2
 127
 128 struct drm_amdgpu_bo_list_in {
 129         /** Type of operation */
 130         __u32 operation;
 131         /** Handle of list or 0 if we want to create one */
 132         __u32 list_handle;
 133         /** Number of BOs in list  */
 134         __u32 bo_number;
 135         /** Size of each element describing BO */
 136         __u32 bo_info_size;
 137         /** Pointer to array describing BOs */
 138         __u64 bo_info_ptr;
 139 };
 140
 141 struct drm_amdgpu_bo_list_entry {
 142         /** Handle of BO */
 143         __u32 bo_handle;
 144         /** New (if specified) BO priority to be used during migration */
 145         __u32 bo_priority;
 146 };
 147
 148 struct drm_amdgpu_bo_list_out {
 149         /** Handle of resource list  */
 150         __u32 list_handle;
 151         __u32 _pad;
 152 };
 153
 154 union drm_amdgpu_bo_list {
 155         struct drm_amdgpu_bo_list_in in;
 156         struct drm_amdgpu_bo_list_out out;
 157 };
 158
 159 /* context related */
 160 #define AMDGPU_CTX_OP_ALLOC_CTX 1
 161 #define AMDGPU_CTX_OP_FREE_CTX  2
 162 #define AMDGPU_CTX_OP_QUERY_STATE       3
 163
 164 /* GPU reset status */
 165 #define AMDGPU_CTX_NO_RESET             0
 166 /* this the context caused it */
 167 #define AMDGPU_CTX_GUILTY_RESET         1
 168 /* some other context caused it */
 169 #define AMDGPU_CTX_INNOCENT_RESET       2
 170 /* unknown cause */
 171 #define AMDGPU_CTX_UNKNOWN_RESET        3
 172
 173 /* Context priority level */
 174 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
 175 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
 176 #define AMDGPU_CTX_PRIORITY_LOW         -512
 177 #define AMDGPU_CTX_PRIORITY_NORMAL      0
 178 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
 179 #define AMDGPU_CTX_PRIORITY_HIGH        512
 180 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
 181
 182 struct drm_amdgpu_ctx_in {
 183         /** AMDGPU_CTX_OP_* */
 184         __u32   op;
 185         /** For future use, no flags defined so far */
 186         __u32   flags;
 187         __u32   ctx_id;
 188         __s32   priority;
 189 };
 190
 191 union drm_amdgpu_ctx_out {
 192                 struct {
 193                         __u32   ctx_id;
 194                         __u32   _pad;
 195                 } alloc;
 196
 197                 struct {
 198                         /** For future use, no flags defined so far */
 199                         __u64   flags;
 200                         /** Number of resets caused by this context so far. */
 201                         __u32   hangs;
 202                         /** Reset status since the last call of the ioctl. */
 203                         __u32   reset_status;
 204                 } state;
 205 };
 206
 207 union drm_amdgpu_ctx {
 208         struct drm_amdgpu_ctx_in in;
 209         union drm_amdgpu_ctx_out out;
 210 };
 211
 212 /* vm ioctl */
 213 #define AMDGPU_VM_OP_RESERVE_VMID       1
 214 #define AMDGPU_VM_OP_UNRESERVE_VMID     2
 215
 216 struct drm_amdgpu_vm_in {
 217         /** AMDGPU_VM_OP_* */
 218         __u32   op;
 219         __u32   flags;
 220 };
 221
 222 struct drm_amdgpu_vm_out {
 223         /** For future use, no flags defined so far */
 224         __u64   flags;
 225 };
 226
 227 union drm_amdgpu_vm {
 228         struct drm_amdgpu_vm_in in;
 229         struct drm_amdgpu_vm_out out;
 230 };
 231
 232 /* sched ioctl */
 233 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE       1
 234
 235 struct drm_amdgpu_sched_in {
 236         /* AMDGPU_SCHED_OP_* */
 237         __u32   op;
 238         __u32   fd;
 239         __s32   priority;
 240         __u32   flags;
 241 };
 242
 243 union drm_amdgpu_sched {
 244         struct drm_amdgpu_sched_in in;
 245 };
 246
 247 /*
 248  * This is not a reliable API and you should expect it to fail for any
 249  * number of reasons and have fallback path that do not use userptr to
 250  * perform any operation.
 251  */
 252 #define AMDGPU_GEM_USERPTR_READONLY     (1 << 0)
 253 #define AMDGPU_GEM_USERPTR_ANONONLY     (1 << 1)
 254 #define AMDGPU_GEM_USERPTR_VALIDATE     (1 << 2)
 255 #define AMDGPU_GEM_USERPTR_REGISTER     (1 << 3)
 256
 257 struct drm_amdgpu_gem_userptr {
 258         __u64           addr;
 259         __u64           size;
 260         /* AMDGPU_GEM_USERPTR_* */
 261         __u32           flags;
 262         /* Resulting GEM handle */
 263         __u32           handle;
 264 };
 265
 266 /* SI-CI-VI: */
 267 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
 268 #define AMDGPU_TILING_ARRAY_MODE_SHIFT                  0
 269 #define AMDGPU_TILING_ARRAY_MODE_MASK                   0xf
 270 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT                 4
 271 #define AMDGPU_TILING_PIPE_CONFIG_MASK                  0x1f
 272 #define AMDGPU_TILING_TILE_SPLIT_SHIFT                  9
 273 #define AMDGPU_TILING_TILE_SPLIT_MASK                   0x7
 274 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT             12
 275 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK              0x7
 276 #define AMDGPU_TILING_BANK_WIDTH_SHIFT                  15
 277 #define AMDGPU_TILING_BANK_WIDTH_MASK                   0x3
 278 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT                 17
 279 #define AMDGPU_TILING_BANK_HEIGHT_MASK                  0x3
 280 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT           19
 281 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK            0x3
 282 #define AMDGPU_TILING_NUM_BANKS_SHIFT                   21
 283 #define AMDGPU_TILING_NUM_BANKS_MASK                    0x3
 284
 285 /* GFX9 and later: */
 286 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT                0
 287 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                 0x1f
 288
 289 /* Set/Get helpers for tiling flags. */
 290 #define AMDGPU_TILING_SET(field, value) \
 291         (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
 292 #define AMDGPU_TILING_GET(value, field) \
 293         (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
 294
 295 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
 296 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
 297
 298 /** The same structure is shared for input/output */
 299 struct drm_amdgpu_gem_metadata {
 300         /** GEM Object handle */
 301         __u32   handle;
 302         /** Do we want get or set metadata */
 303         __u32   op;
 304         struct {
 305                 /** For future use, no flags defined so far */
 306                 __u64   flags;
 307                 /** family specific tiling info */
 308                 __u64   tiling_info;
 309                 __u32   data_size_bytes;
 310                 __u32   data[64];
 311         } data;
 312 };
 313
 314 struct drm_amdgpu_gem_mmap_in {
 315         /** the GEM object handle */
 316         __u32 handle;
 317         __u32 _pad;
 318 };
 319
 320 struct drm_amdgpu_gem_mmap_out {
 321         /** mmap offset from the vma offset manager */
 322         __u64 addr_ptr;
 323 };
 324
 325 union drm_amdgpu_gem_mmap {
 326         struct drm_amdgpu_gem_mmap_in   in;
 327         struct drm_amdgpu_gem_mmap_out out;
 328 };
 329
 330 struct drm_amdgpu_gem_wait_idle_in {
 331         /** GEM object handle */
 332         __u32 handle;
 333         /** For future use, no flags defined so far */
 334         __u32 flags;
 335         /** Absolute timeout to wait */
 336         __u64 timeout;
 337 };
 338
 339 struct drm_amdgpu_gem_wait_idle_out {
 340         /** BO status:  0 - BO is idle, 1 - BO is busy */
 341         __u32 status;
 342         /** Returned current memory domain */
 343         __u32 domain;
 344 };
 345
 346 union drm_amdgpu_gem_wait_idle {
 347         struct drm_amdgpu_gem_wait_idle_in  in;
 348         struct drm_amdgpu_gem_wait_idle_out out;
 349 };
 350
 351 struct drm_amdgpu_wait_cs_in {
 352         /* Command submission handle
 353          * handle equals 0 means none to wait for
 354          * handle equals ~0ull means wait for the latest sequence number
 355          */
 356         __u64 handle;
 357         /** Absolute timeout to wait */
 358         __u64 timeout;
 359         __u32 ip_type;
 360         __u32 ip_instance;
 361         __u32 ring;
 362         __u32 ctx_id;
 363 };
 364
 365 struct drm_amdgpu_wait_cs_out {
 366         /** CS status:  0 - CS completed, 1 - CS still busy */
 367         __u64 status;
 368 };
 369
 370 union drm_amdgpu_wait_cs {
 371         struct drm_amdgpu_wait_cs_in in;
 372         struct drm_amdgpu_wait_cs_out out;
 373 };
 374
 375 struct drm_amdgpu_fence {
 376         __u32 ctx_id;
 377         __u32 ip_type;
 378         __u32 ip_instance;
 379         __u32 ring;
 380         __u64 seq_no;
 381 };
 382
 383 struct drm_amdgpu_wait_fences_in {
 384         /** This points to uint64_t * which points to fences */
 385         __u64 fences;
 386         __u32 fence_count;
 387         __u32 wait_all;
 388         __u64 timeout_ns;
 389 };
 390
 391 struct drm_amdgpu_wait_fences_out {
 392         __u32 status;
 393         __u32 first_signaled;
 394 };
 395
 396 union drm_amdgpu_wait_fences {
 397         struct drm_amdgpu_wait_fences_in in;
 398         struct drm_amdgpu_wait_fences_out out;
 399 };
 400
 401 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO       0
 402 #define AMDGPU_GEM_OP_SET_PLACEMENT             1
 403
 404 /* Sets or returns a value associated with a buffer. */
 405 struct drm_amdgpu_gem_op {
 406         /** GEM object handle */
 407         __u32   handle;
 408         /** AMDGPU_GEM_OP_* */
 409         __u32   op;
 410         /** Input or return value */
 411         __u64   value;
 412 };
 413
 414 #define AMDGPU_VA_OP_MAP                        1
 415 #define AMDGPU_VA_OP_UNMAP                      2
 416 #define AMDGPU_VA_OP_CLEAR                      3
 417 #define AMDGPU_VA_OP_REPLACE                    4
 418
 419 /* Delay the page table update till the next CS */
 420 #define AMDGPU_VM_DELAY_UPDATE          (1 << 0)
 421
 422 /* Mapping flags */
 423 /* readable mapping */
 424 #define AMDGPU_VM_PAGE_READABLE         (1 << 1)
 425 /* writable mapping */
 426 #define AMDGPU_VM_PAGE_WRITEABLE        (1 << 2)
 427 /* executable mapping, new for VI */
 428 #define AMDGPU_VM_PAGE_EXECUTABLE       (1 << 3)
 429 /* partially resident texture */
 430 #define AMDGPU_VM_PAGE_PRT              (1 << 4)
 431 /* MTYPE flags use bit 5 to 8 */
 432 #define AMDGPU_VM_MTYPE_MASK            (0xf << 5)
 433 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
 434 #define AMDGPU_VM_MTYPE_DEFAULT         (0 << 5)
 435 /* Use NC MTYPE instead of default MTYPE */
 436 #define AMDGPU_VM_MTYPE_NC              (1 << 5)
 437 /* Use WC MTYPE instead of default MTYPE */
 438 #define AMDGPU_VM_MTYPE_WC              (2 << 5)
 439 /* Use CC MTYPE instead of default MTYPE */
 440 #define AMDGPU_VM_MTYPE_CC              (3 << 5)
 441 /* Use UC MTYPE instead of default MTYPE */
 442 #define AMDGPU_VM_MTYPE_UC              (4 << 5)
 443
 444 struct drm_amdgpu_gem_va {
 445         /** GEM object handle */
 446         __u32 handle;
 447         __u32 _pad;
 448         /** AMDGPU_VA_OP_* */
 449         __u32 operation;
 450         /** AMDGPU_VM_PAGE_* */
 451         __u32 flags;
 452         /** va address to assign . Must be correctly aligned.*/
 453         __u64 va_address;
 454         /** Specify offset inside of BO to assign. Must be correctly aligned.*/
 455         __u64 offset_in_bo;
 456         /** Specify mapping size. Must be correctly aligned. */
 457         __u64 map_size;
 458 };
 459
 460 #define AMDGPU_HW_IP_GFX          0
 461 #define AMDGPU_HW_IP_COMPUTE      1
 462 #define AMDGPU_HW_IP_DMA          2
 463 #define AMDGPU_HW_IP_UVD          3
 464 #define AMDGPU_HW_IP_VCE          4
 465 #define AMDGPU_HW_IP_UVD_ENC      5
 466 #define AMDGPU_HW_IP_VCN_DEC      6
 467 #define AMDGPU_HW_IP_VCN_ENC      7
 468 #define AMDGPU_HW_IP_NUM          8
 469
 470 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
 471
 472 #define AMDGPU_CHUNK_ID_IB              0x01
 473 #define AMDGPU_CHUNK_ID_FENCE           0x02
 474 #define AMDGPU_CHUNK_ID_DEPENDENCIES    0x03
 475 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 476 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 477
 478 struct drm_amdgpu_cs_chunk {
 479         __u32           chunk_id;
 480         __u32           length_dw;
 481         __u64           chunk_data;
 482 };
 483
 484 struct drm_amdgpu_cs_in {
 485         /** Rendering context id */
 486         __u32           ctx_id;
 487         /**  Handle of resource list associated with CS */
 488         __u32           bo_list_handle;
 489         __u32           num_chunks;
 490         __u32           _pad;
 491         /** this points to __u64 * which point to cs chunks */
 492         __u64           chunks;
 493 };
 494
 495 struct drm_amdgpu_cs_out {
 496         __u64 handle;
 497 };
 498
 499 union drm_amdgpu_cs {
 500         struct drm_amdgpu_cs_in in;
 501         struct drm_amdgpu_cs_out out;
 502 };
 503
 504 /* Specify flags to be used for IB */
 505
 506 /* This IB should be submitted to CE */
 507 #define AMDGPU_IB_FLAG_CE       (1<<0)
 508
 509 /* Preamble flag, which means the IB could be dropped if no context switch */
 510 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
 511
 512 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 513 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 514
 515 struct drm_amdgpu_cs_chunk_ib {
 516         __u32 _pad;
 517         /** AMDGPU_IB_FLAG_* */
 518         __u32 flags;
 519         /** Virtual address to begin IB execution */
 520         __u64 va_start;
 521         /** Size of submission */
 522         __u32 ib_bytes;
 523         /** HW IP to submit to */
 524         __u32 ip_type;
 525         /** HW IP index of the same type to submit to  */
 526         __u32 ip_instance;
 527         /** Ring index to submit to */
 528         __u32 ring;
 529 };
 530
 531 struct drm_amdgpu_cs_chunk_dep {
 532         __u32 ip_type;
 533         __u32 ip_instance;
 534         __u32 ring;
 535         __u32 ctx_id;
 536         __u64 handle;
 537 };
 538
 539 struct drm_amdgpu_cs_chunk_fence {
 540         __u32 handle;
 541         __u32 offset;
 542 };
 543
 544 struct drm_amdgpu_cs_chunk_sem {
 545         __u32 handle;
 546 };
 547
 548 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ      0
 549 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD   1
 550 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
 551
 552 union drm_amdgpu_fence_to_handle {
 553         struct {
 554                 struct drm_amdgpu_fence fence;
 555                 __u32 what;
 556                 __u32 pad;
 557         } in;
 558         struct {
 559                 __u32 handle;
 560         } out;
 561 };
 562
 563 struct drm_amdgpu_cs_chunk_data {
 564         union {
 565                 struct drm_amdgpu_cs_chunk_ib           ib_data;
 566                 struct drm_amdgpu_cs_chunk_fence        fence_data;
 567         };
 568 };
 569
 570 /**
 571  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
 572  *
 573  */
 574 #define AMDGPU_IDS_FLAGS_FUSION         0x1
 575 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
 576
 577 /* indicate if acceleration can be working */
 578 #define AMDGPU_INFO_ACCEL_WORKING               0x00
 579 /* get the crtc_id from the mode object id? */
 580 #define AMDGPU_INFO_CRTC_FROM_ID                0x01
 581 /* query hw IP info */
 582 #define AMDGPU_INFO_HW_IP_INFO                  0x02
 583 /* query hw IP instance count for the specified type */
 584 #define AMDGPU_INFO_HW_IP_COUNT                 0x03
 585 /* timestamp for GL_ARB_timer_query */
 586 #define AMDGPU_INFO_TIMESTAMP                   0x05
 587 /* Query the firmware version */
 588 #define AMDGPU_INFO_FW_VERSION                  0x0e
 589         /* Subquery id: Query VCE firmware version */
 590         #define AMDGPU_INFO_FW_VCE              0x1
 591         /* Subquery id: Query UVD firmware version */
 592         #define AMDGPU_INFO_FW_UVD              0x2
 593         /* Subquery id: Query GMC firmware version */
 594         #define AMDGPU_INFO_FW_GMC              0x03
 595         /* Subquery id: Query GFX ME firmware version */
 596         #define AMDGPU_INFO_FW_GFX_ME           0x04
 597         /* Subquery id: Query GFX PFP firmware version */
 598         #define AMDGPU_INFO_FW_GFX_PFP          0x05
 599         /* Subquery id: Query GFX CE firmware version */
 600         #define AMDGPU_INFO_FW_GFX_CE           0x06
 601         /* Subquery id: Query GFX RLC firmware version */
 602         #define AMDGPU_INFO_FW_GFX_RLC          0x07
 603         /* Subquery id: Query GFX MEC firmware version */
 604         #define AMDGPU_INFO_FW_GFX_MEC          0x08
 605         /* Subquery id: Query SMC firmware version */
 606         #define AMDGPU_INFO_FW_SMC              0x0a
 607         /* Subquery id: Query SDMA firmware version */
 608         #define AMDGPU_INFO_FW_SDMA             0x0b
 609         /* Subquery id: Query PSP SOS firmware version */
 610         #define AMDGPU_INFO_FW_SOS              0x0c
 611         /* Subquery id: Query PSP ASD firmware version */
 612         #define AMDGPU_INFO_FW_ASD              0x0d
 613 /* number of bytes moved for TTM migration */
 614 #define AMDGPU_INFO_NUM_BYTES_MOVED             0x0f
 615 /* the used VRAM size */
 616 #define AMDGPU_INFO_VRAM_USAGE                  0x10
 617 /* the used GTT size */
 618 #define AMDGPU_INFO_GTT_USAGE                   0x11
 619 /* Information about GDS, etc. resource configuration */
 620 #define AMDGPU_INFO_GDS_CONFIG                  0x13
 621 /* Query information about VRAM and GTT domains */
 622 #define AMDGPU_INFO_VRAM_GTT                    0x14
 623 /* Query information about register in MMR address space*/
 624 #define AMDGPU_INFO_READ_MMR_REG                0x15
 625 /* Query information about device: rev id, family, etc. */
 626 #define AMDGPU_INFO_DEV_INFO                    0x16
 627 /* visible vram usage */
 628 #define AMDGPU_INFO_VIS_VRAM_USAGE              0x17
 629 /* number of TTM buffer evictions */
 630 #define AMDGPU_INFO_NUM_EVICTIONS               0x18
 631 /* Query memory about VRAM and GTT domains */
 632 #define AMDGPU_INFO_MEMORY                      0x19
 633 /* Query vce clock table */
 634 #define AMDGPU_INFO_VCE_CLOCK_TABLE             0x1A
 635 /* Query vbios related information */
 636 #define AMDGPU_INFO_VBIOS                       0x1B
 637         /* Subquery id: Query vbios size */
 638         #define AMDGPU_INFO_VBIOS_SIZE          0x1
 639         /* Subquery id: Query vbios image */
 640         #define AMDGPU_INFO_VBIOS_IMAGE         0x2
 641 /* Query UVD handles */
 642 #define AMDGPU_INFO_NUM_HANDLES                 0x1C
 643 /* Query sensor related information */
 644 #define AMDGPU_INFO_SENSOR                      0x1D
 645         /* Subquery id: Query GPU shader clock */
 646         #define AMDGPU_INFO_SENSOR_GFX_SCLK             0x1
 647         /* Subquery id: Query GPU memory clock */
 648         #define AMDGPU_INFO_SENSOR_GFX_MCLK             0x2
 649         /* Subquery id: Query GPU temperature */
 650         #define AMDGPU_INFO_SENSOR_GPU_TEMP             0x3
 651         /* Subquery id: Query GPU load */
 652         #define AMDGPU_INFO_SENSOR_GPU_LOAD             0x4
 653         /* Subquery id: Query average GPU power */
 654         #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER        0x5
 655         /* Subquery id: Query northbridge voltage */
 656         #define AMDGPU_INFO_SENSOR_VDDNB                0x6
 657         /* Subquery id: Query graphics voltage */
 658         #define AMDGPU_INFO_SENSOR_VDDGFX               0x7
 659 /* Number of VRAM page faults on CPU access. */
 660 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS    0x1E
 661 #define AMDGPU_INFO_VRAM_LOST_COUNTER           0x1F
 662
 663 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT  0
 664 #define AMDGPU_INFO_MMR_SE_INDEX_MASK   0xff
 665 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT  8
 666 #define AMDGPU_INFO_MMR_SH_INDEX_MASK   0xff
 667
 668 struct drm_amdgpu_query_fw {
 669         /** AMDGPU_INFO_FW_* */
 670         __u32 fw_type;
 671         /**
 672          * Index of the IP if there are more IPs of
 673          * the same type.
 674          */
 675         __u32 ip_instance;
 676         /**
 677          * Index of the engine. Whether this is used depends
 678          * on the firmware type. (e.g. MEC, SDMA)
 679          */
 680         __u32 index;
 681         __u32 _pad;
 682 };
 683
 684 /* Input structure for the INFO ioctl */
 685 struct drm_amdgpu_info {
 686         /* Where the return value will be stored */
 687         __u64 return_pointer;
 688         /* The size of the return value. Just like "size" in "snprintf",
 689          * it limits how many bytes the kernel can write. */
 690         __u32 return_size;
 691         /* The query request id. */
 692         __u32 query;
 693
 694         union {
 695                 struct {
 696                         __u32 id;
 697                         __u32 _pad;
 698                 } mode_crtc;
 699
 700                 struct {
 701                         /** AMDGPU_HW_IP_* */
 702                         __u32 type;
 703                         /**
 704                          * Index of the IP if there are more IPs of the same
 705                          * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
 706                          */
 707                         __u32 ip_instance;
 708                 } query_hw_ip;
 709
 710                 struct {
 711                         __u32 dword_offset;
 712                         /** number of registers to read */
 713                         __u32 count;
 714                         __u32 instance;
 715                         /** For future use, no flags defined so far */
 716                         __u32 flags;
 717                 } read_mmr_reg;
 718
 719                 struct drm_amdgpu_query_fw query_fw;
 720
 721                 struct {
 722                         __u32 type;
 723                         __u32 offset;
 724                 } vbios_info;
 725
 726                 struct {
 727                         __u32 type;
 728                 } sensor_info;
 729         };
 730 };
 731
 732 struct drm_amdgpu_info_gds {
 733         /** GDS GFX partition size */
 734         __u32 gds_gfx_partition_size;
 735         /** GDS compute partition size */
 736         __u32 compute_partition_size;
 737         /** total GDS memory size */
 738         __u32 gds_total_size;
 739         /** GWS size per GFX partition */
 740         __u32 gws_per_gfx_partition;
 741         /** GSW size per compute partition */
 742         __u32 gws_per_compute_partition;
 743         /** OA size per GFX partition */
 744         __u32 oa_per_gfx_partition;
 745         /** OA size per compute partition */
 746         __u32 oa_per_compute_partition;
 747         __u32 _pad;
 748 };
 749
 750 struct drm_amdgpu_info_vram_gtt {
 751         __u64 vram_size;
 752         __u64 vram_cpu_accessible_size;
 753         __u64 gtt_size;
 754 };
 755
 756 struct drm_amdgpu_heap_info {
 757         /** max. physical memory */
 758         __u64 total_heap_size;
 759
 760         /** Theoretical max. available memory in the given heap */
 761         __u64 usable_heap_size;
 762
 763         /**
 764          * Number of bytes allocated in the heap. This includes all processes
 765          * and private allocations in the kernel. It changes when new buffers
 766          * are allocated, freed, and moved. It cannot be larger than
 767          * heap_size.
 768          */
 769         __u64 heap_usage;
 770
 771         /**
 772          * Theoretical possible max. size of buffer which
 773          * could be allocated in the given heap
 774          */
 775         __u64 max_allocation;
 776 };
 777
 778 struct drm_amdgpu_memory_info {
 779         struct drm_amdgpu_heap_info vram;
 780         struct drm_amdgpu_heap_info cpu_accessible_vram;
 781         struct drm_amdgpu_heap_info gtt;
 782 };
 783
 784 struct drm_amdgpu_info_firmware {
 785         __u32 ver;
 786         __u32 feature;
 787 };
 788
 789 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
 790 #define AMDGPU_VRAM_TYPE_GDDR1 1
 791 #define AMDGPU_VRAM_TYPE_DDR2  2
 792 #define AMDGPU_VRAM_TYPE_GDDR3 3
 793 #define AMDGPU_VRAM_TYPE_GDDR4 4
 794 #define AMDGPU_VRAM_TYPE_GDDR5 5
 795 #define AMDGPU_VRAM_TYPE_HBM   6
 796 #define AMDGPU_VRAM_TYPE_DDR3  7
 797
 798 struct drm_amdgpu_info_device {
 799         /** PCI Device ID */
 800         __u32 device_id;
 801         /** Internal chip revision: A0, A1, etc.) */
 802         __u32 chip_rev;
 803         __u32 external_rev;
 804         /** Revision id in PCI Config space */
 805         __u32 pci_rev;
 806         __u32 family;
 807         __u32 num_shader_engines;
 808         __u32 num_shader_arrays_per_engine;
 809         /* in KHz */
 810         __u32 gpu_counter_freq;
 811         __u64 max_engine_clock;
 812         __u64 max_memory_clock;
 813         /* cu information */
 814         __u32 cu_active_number;
 815         /* NOTE: cu_ao_mask is INVALID, DON'T use it */
 816         __u32 cu_ao_mask;
 817         __u32 cu_bitmap[4][4];
 818         /** Render backend pipe mask. One render backend is CB+DB. */
 819         __u32 enabled_rb_pipes_mask;
 820         __u32 num_rb_pipes;
 821         __u32 num_hw_gfx_contexts;
 822         __u32 _pad;
 823         __u64 ids_flags;
 824         /** Starting virtual address for UMDs. */
 825         __u64 virtual_address_offset;
 826         /** The maximum virtual address */
 827         __u64 virtual_address_max;
 828         /** Required alignment of virtual addresses. */
 829         __u32 virtual_address_alignment;
 830         /** Page table entry - fragment size */
 831         __u32 pte_fragment_size;
 832         __u32 gart_page_size;
 833         /** constant engine ram size*/
 834         __u32 ce_ram_size;
 835         /** video memory type info*/
 836         __u32 vram_type;
 837         /** video memory bit width*/
 838         __u32 vram_bit_width;
 839         /* vce harvesting instance */
 840         __u32 vce_harvest_config;
 841         /* gfx double offchip LDS buffers */
 842         __u32 gc_double_offchip_lds_buf;
 843         /* NGG Primitive Buffer */
 844         __u64 prim_buf_gpu_addr;
 845         /* NGG Position Buffer */
 846         __u64 pos_buf_gpu_addr;
 847         /* NGG Control Sideband */
 848         __u64 cntl_sb_buf_gpu_addr;
 849         /* NGG Parameter Cache */
 850         __u64 param_buf_gpu_addr;
 851         __u32 prim_buf_size;
 852         __u32 pos_buf_size;
 853         __u32 cntl_sb_buf_size;
 854         __u32 param_buf_size;
 855         /* wavefront size*/
 856         __u32 wave_front_size;
 857         /* shader visible vgprs*/
 858         __u32 num_shader_visible_vgprs;
 859         /* CU per shader array*/
 860         __u32 num_cu_per_sh;
 861         /* number of tcc blocks*/
 862         __u32 num_tcc_blocks;
 863         /* gs vgt table depth*/
 864         __u32 gs_vgt_table_depth;
 865         /* gs primitive buffer depth*/
 866         __u32 gs_prim_buffer_depth;
 867         /* max gs wavefront per vgt*/
 868         __u32 max_gs_waves_per_vgt;
 869         __u32 _pad1;
 870         /* always on cu bitmap */
 871         __u32 cu_ao_bitmap[4][4];
 872 };
 873
 874 struct drm_amdgpu_info_hw_ip {
 875         /** Version of h/w IP */
 876         __u32  hw_ip_version_major;
 877         __u32  hw_ip_version_minor;
 878         /** Capabilities */
 879         __u64  capabilities_flags;
 880         /** command buffer address start alignment*/
 881         __u32  ib_start_alignment;
 882         /** command buffer size alignment*/
 883         __u32  ib_size_alignment;
 884         /** Bitmask of available rings. Bit 0 means ring 0, etc. */
 885         __u32  available_rings;
 886         __u32  _pad;
 887 };
 888
 889 struct drm_amdgpu_info_num_handles {
 890         /** Max handles as supported by firmware for UVD */
 891         __u32  uvd_max_handles;
 892         /** Handles currently in use for UVD */
 893         __u32  uvd_used_handles;
 894 };
 895
 896 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES          6
 897
 898 struct drm_amdgpu_info_vce_clock_table_entry {
 899         /** System clock */
 900         __u32 sclk;
 901         /** Memory clock */
 902         __u32 mclk;
 903         /** VCE clock */
 904         __u32 eclk;
 905         __u32 pad;
 906 };
 907
 908 struct drm_amdgpu_info_vce_clock_table {
 909         struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
 910         __u32 num_valid_entries;
 911         __u32 pad;
 912 };
 913
 914 /*
 915  * Supported GPU families
 916  */
 917 #define AMDGPU_FAMILY_UNKNOWN                   0
 918 #define AMDGPU_FAMILY_SI                        110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
 919 #define AMDGPU_FAMILY_CI                        120 /* Bonaire, Hawaii */
 920 #define AMDGPU_FAMILY_KV                        125 /* Kaveri, Kabini, Mullins */
 921 #define AMDGPU_FAMILY_VI                        130 /* Iceland, Tonga */
 922 #define AMDGPU_FAMILY_CZ                        135 /* Carrizo, Stoney */
 923 #define AMDGPU_FAMILY_AI                        141 /* Vega10 */
 924 #define AMDGPU_FAMILY_RV                        142 /* Raven */
 925
 926 #if defined(__cplusplus)
 927 }
 928 #endif
 929
 930 #endif