include/uapi/drm/msm_drm.h

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #ifndef __MSM_DRM_H__
  26 #define __MSM_DRM_H__
  27
  28 #include "drm.h"
  29
  30 #if defined(__cplusplus)
  31 extern "C" {
  32 #endif
  33
  34 /* Please note that modifications to all structs defined here are
  35  * subject to backwards-compatibility constraints:
  36  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
  37  *     user/kernel compatibility
  38  *  2) Keep fields aligned to their size
  39  *  3) Because of how drm_ioctl() works, we can add new fields at
  40  *     the end of an ioctl if some care is taken: drm_ioctl() will
  41  *     zero out the new fields at the tail of the ioctl, so a zero
  42  *     value should have a backwards compatible meaning.  And for
  43  *     output params, userspace won't see the newly added output
  44  *     fields.. so that has to be somehow ok.
  45  */
  46
  47 #define MSM_PIPE_NONE        0x00
  48 #define MSM_PIPE_2D0         0x01
  49 #define MSM_PIPE_2D1         0x02
  50 #define MSM_PIPE_3D0         0x10
  51
  52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in
  53  * the upper 16 bits (which could be extended further, if needed, maybe
  54  * we extend/overload the pipe-id some day to deal with multiple rings,
  55  * but even then I don't think we need the full lower 16 bits).
  56  */
  57 #define MSM_PIPE_ID_MASK     0xffff
  58 #define MSM_PIPE_ID(x)       ((x) & MSM_PIPE_ID_MASK)
  59 #define MSM_PIPE_FLAGS(x)    ((x) & ~MSM_PIPE_ID_MASK)
  60
  61 /* timeouts are specified in clock-monotonic absolute times (to simplify
  62  * restarting interrupted ioctls).  The following struct is logically the
  63  * same as 'struct timespec' but 32/64b ABI safe.
  64  */
  65 struct drm_msm_timespec {
  66         __s64 tv_sec;          /* seconds */
  67         __s64 tv_nsec;         /* nanoseconds */
  68 };
  69
  70 #define MSM_PARAM_GPU_ID     0x01
  71 #define MSM_PARAM_GMEM_SIZE  0x02
  72 #define MSM_PARAM_CHIP_ID    0x03
  73 #define MSM_PARAM_MAX_FREQ   0x04
  74 #define MSM_PARAM_TIMESTAMP  0x05
  75 #define MSM_PARAM_GMEM_BASE  0x06
  76
  77 struct drm_msm_param {
  78         __u32 pipe;           /* in, MSM_PIPE_x */
  79         __u32 param;          /* in, MSM_PARAM_x */
  80         __u64 value;          /* out (get_param) or in (set_param) */
  81 };
  82
  83 /*
  84  * GEM buffers:
  85  */
  86
  87 #define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
  88 #define MSM_BO_GPU_READONLY  0x00000002
  89 #define MSM_BO_CACHE_MASK    0x000f0000
  90 /* cache modes */
  91 #define MSM_BO_CACHED        0x00010000
  92 #define MSM_BO_WC            0x00020000
  93 #define MSM_BO_UNCACHED      0x00040000
  94
  95 #define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
  96                               MSM_BO_GPU_READONLY | \
  97                               MSM_BO_CACHED | \
  98                               MSM_BO_WC | \
  99                               MSM_BO_UNCACHED)
 100
 101 struct drm_msm_gem_new {
 102         __u64 size;           /* in */
 103         __u32 flags;          /* in, mask of MSM_BO_x */
 104         __u32 handle;         /* out */
 105 };
 106
 107 #define MSM_INFO_IOVA   0x01
 108
 109 #define MSM_INFO_FLAGS (MSM_INFO_IOVA)
 110
 111 struct drm_msm_gem_info {
 112         __u32 handle;         /* in */
 113         __u32 flags;          /* in - combination of MSM_INFO_* flags */
 114         __u64 offset;         /* out, mmap() offset or iova */
 115 };
 116
 117 #define MSM_PREP_READ        0x01
 118 #define MSM_PREP_WRITE       0x02
 119 #define MSM_PREP_NOSYNC      0x04
 120
 121 #define MSM_PREP_FLAGS       (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
 122
 123 struct drm_msm_gem_cpu_prep {
 124         __u32 handle;         /* in */
 125         __u32 op;             /* in, mask of MSM_PREP_x */
 126         struct drm_msm_timespec timeout;   /* in */
 127 };
 128
 129 struct drm_msm_gem_cpu_fini {
 130         __u32 handle;         /* in */
 131 };
 132
 133 /*
 134  * Cmdstream Submission:
 135  */
 136
 137 /* The value written into the cmdstream is logically:
 138  *
 139  *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
 140  *
 141  * When we have GPU's w/ >32bit ptrs, it should be possible to deal
 142  * with this by emit'ing two reloc entries with appropriate shift
 143  * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
 144  *
 145  * NOTE that reloc's must be sorted by order of increasing submit_offset,
 146  * otherwise EINVAL.
 147  */
 148 struct drm_msm_gem_submit_reloc {
 149         __u32 submit_offset;  /* in, offset from submit_bo */
 150         __u32 or;             /* in, value OR'd with result */
 151         __s32 shift;          /* in, amount of left shift (can be negative) */
 152         __u32 reloc_idx;      /* in, index of reloc_bo buffer */
 153         __u64 reloc_offset;   /* in, offset from start of reloc_bo */
 154 };
 155
 156 /* submit-types:
 157  *   BUF - this cmd buffer is executed normally.
 158  *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
 159  *      processed normally, but the kernel does not setup an IB to
 160  *      this buffer in the first-level ringbuffer
 161  *   CTX_RESTORE_BUF - only executed if there has been a GPU context
 162  *      switch since the last SUBMIT ioctl
 163  */
 164 #define MSM_SUBMIT_CMD_BUF             0x0001
 165 #define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
 166 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
 167 struct drm_msm_gem_submit_cmd {
 168         __u32 type;           /* in, one of MSM_SUBMIT_CMD_x */
 169         __u32 submit_idx;     /* in, index of submit_bo cmdstream buffer */
 170         __u32 submit_offset;  /* in, offset into submit_bo */
 171         __u32 size;           /* in, cmdstream size */
 172         __u32 pad;
 173         __u32 nr_relocs;      /* in, number of submit_reloc's */
 174         __u64 relocs;         /* in, ptr to array of submit_reloc's */
 175 };
 176
 177 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
 178  * cmdstream buffer(s) themselves or reloc entries) has one (and only
 179  * one) entry in the submit->bos[] table.
 180  *
 181  * As a optimization, the current buffer (gpu virtual address) can be
 182  * passed back through the 'presumed' field.  If on a subsequent reloc,
 183  * userspace passes back a 'presumed' address that is still valid,
 184  * then patching the cmdstream for this entry is skipped.  This can
 185  * avoid kernel needing to map/access the cmdstream bo in the common
 186  * case.
 187  */
 188 #define MSM_SUBMIT_BO_READ             0x0001
 189 #define MSM_SUBMIT_BO_WRITE            0x0002
 190
 191 #define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
 192
 193 struct drm_msm_gem_submit_bo {
 194         __u32 flags;          /* in, mask of MSM_SUBMIT_BO_x */
 195         __u32 handle;         /* in, GEM handle */
 196         __u64 presumed;       /* in/out, presumed buffer address */
 197 };
 198
 199 /* Valid submit ioctl flags: */
 200 #define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
 201 #define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
 202 #define MSM_SUBMIT_FENCE_FD_OUT  0x20000000 /* enable output fence_fd */
 203 #define MSM_SUBMIT_FLAGS                ( \
 204                 MSM_SUBMIT_NO_IMPLICIT   | \
 205                 MSM_SUBMIT_FENCE_FD_IN   | \
 206                 MSM_SUBMIT_FENCE_FD_OUT  | \
 207                 0)
 208
 209 /* Each cmdstream submit consists of a table of buffers involved, and
 210  * one or more cmdstream buffers.  This allows for conditional execution
 211  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
 212  */
 213 struct drm_msm_gem_submit {
 214         __u32 flags;          /* MSM_PIPE_x | MSM_SUBMIT_x */
 215         __u32 fence;          /* out */
 216         __u32 nr_bos;         /* in, number of submit_bo's */
 217         __u32 nr_cmds;        /* in, number of submit_cmd's */
 218         __u64 bos;            /* in, ptr to array of submit_bo's */
 219         __u64 cmds;           /* in, ptr to array of submit_cmd's */
 220         __s32 fence_fd;       /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
 221 };
 222
 223 /* The normal way to synchronize with the GPU is just to CPU_PREP on
 224  * a buffer if you need to access it from the CPU (other cmdstream
 225  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
 226  * handle the required synchronization under the hood).  This ioctl
 227  * mainly just exists as a way to implement the gallium pipe_fence
 228  * APIs without requiring a dummy bo to synchronize on.
 229  */
 230 struct drm_msm_wait_fence {
 231         __u32 fence;          /* in */
 232         __u32 pad;
 233         struct drm_msm_timespec timeout;   /* in */
 234 };
 235
 236 /* madvise provides a way to tell the kernel in case a buffers contents
 237  * can be discarded under memory pressure, which is useful for userspace
 238  * bo cache where we want to optimistically hold on to buffer allocate
 239  * and potential mmap, but allow the pages to be discarded under memory
 240  * pressure.
 241  *
 242  * Typical usage would involve madvise(DONTNEED) when buffer enters BO
 243  * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
 244  * In the WILLNEED case, 'retained' indicates to userspace whether the
 245  * backing pages still exist.
 246  */
 247 #define MSM_MADV_WILLNEED 0       /* backing pages are needed, status returned in 'retained' */
 248 #define MSM_MADV_DONTNEED 1       /* backing pages not needed */
 249 #define __MSM_MADV_PURGED 2       /* internal state */
 250
 251 struct drm_msm_gem_madvise {
 252         __u32 handle;         /* in, GEM handle */
 253         __u32 madv;           /* in, MSM_MADV_x */
 254         __u32 retained;       /* out, whether backing store still exists */
 255 };
 256
 257 #define DRM_MSM_GET_PARAM              0x00
 258 /* placeholder:
 259 #define DRM_MSM_SET_PARAM              0x01
 260  */
 261 #define DRM_MSM_GEM_NEW                0x02
 262 #define DRM_MSM_GEM_INFO               0x03
 263 #define DRM_MSM_GEM_CPU_PREP           0x04
 264 #define DRM_MSM_GEM_CPU_FINI           0x05
 265 #define DRM_MSM_GEM_SUBMIT             0x06
 266 #define DRM_MSM_WAIT_FENCE             0x07
 267 #define DRM_MSM_GEM_MADVISE            0x08
 268
 269 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
 270 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
 271 #define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
 272 #define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
 273 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
 274 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
 275 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
 276 #define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
 277
 278 #if defined(__cplusplus)
 279 }
 280 #endif
 281
 282 #endif /* __MSM_DRM_H__ */