2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef KFD_IOCTL_H_INCLUDED
24 #define KFD_IOCTL_H_INCLUDED
27 #include <linux/ioctl.h>
30 * - 1.1 - initial version
31 * - 1.3 - Add SMI events support
33 #define KFD_IOCTL_MAJOR_VERSION 1
34 #define KFD_IOCTL_MINOR_VERSION 3
36 struct kfd_ioctl_get_version_args
{
37 __u32 major_version
; /* from KFD */
38 __u32 minor_version
; /* from KFD */
41 /* For kfd_ioctl_create_queue_args.queue_type. */
42 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0
43 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1
44 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2
45 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3
47 #define KFD_MAX_QUEUE_PERCENTAGE 100
48 #define KFD_MAX_QUEUE_PRIORITY 15
50 struct kfd_ioctl_create_queue_args
{
51 __u64 ring_base_address
; /* to KFD */
52 __u64 write_pointer_address
; /* from KFD */
53 __u64 read_pointer_address
; /* from KFD */
54 __u64 doorbell_offset
; /* from KFD */
56 __u32 ring_size
; /* to KFD */
57 __u32 gpu_id
; /* to KFD */
58 __u32 queue_type
; /* to KFD */
59 __u32 queue_percentage
; /* to KFD */
60 __u32 queue_priority
; /* to KFD */
61 __u32 queue_id
; /* from KFD */
63 __u64 eop_buffer_address
; /* to KFD */
64 __u64 eop_buffer_size
; /* to KFD */
65 __u64 ctx_save_restore_address
; /* to KFD */
66 __u32 ctx_save_restore_size
; /* to KFD */
67 __u32 ctl_stack_size
; /* to KFD */
70 struct kfd_ioctl_destroy_queue_args
{
71 __u32 queue_id
; /* to KFD */
75 struct kfd_ioctl_update_queue_args
{
76 __u64 ring_base_address
; /* to KFD */
78 __u32 queue_id
; /* to KFD */
79 __u32 ring_size
; /* to KFD */
80 __u32 queue_percentage
; /* to KFD */
81 __u32 queue_priority
; /* to KFD */
84 struct kfd_ioctl_set_cu_mask_args
{
85 __u32 queue_id
; /* to KFD */
86 __u32 num_cu_mask
; /* to KFD */
87 __u64 cu_mask_ptr
; /* to KFD */
90 struct kfd_ioctl_get_queue_wave_state_args
{
91 __u64 ctl_stack_address
; /* to KFD */
92 __u32 ctl_stack_used_size
; /* from KFD */
93 __u32 save_area_used_size
; /* from KFD */
94 __u32 queue_id
; /* to KFD */
98 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
99 #define KFD_IOC_CACHE_POLICY_COHERENT 0
100 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
102 struct kfd_ioctl_set_memory_policy_args
{
103 __u64 alternate_aperture_base
; /* to KFD */
104 __u64 alternate_aperture_size
; /* to KFD */
106 __u32 gpu_id
; /* to KFD */
107 __u32 default_policy
; /* to KFD */
108 __u32 alternate_policy
; /* to KFD */
113 * All counters are monotonic. They are used for profiling of compute jobs.
114 * The profiling is done by userspace.
116 * In case of GPU reset, the counter should not be affected.
119 struct kfd_ioctl_get_clock_counters_args
{
120 __u64 gpu_clock_counter
; /* from KFD */
121 __u64 cpu_clock_counter
; /* from KFD */
122 __u64 system_clock_counter
; /* from KFD */
123 __u64 system_clock_freq
; /* from KFD */
125 __u32 gpu_id
; /* to KFD */
129 struct kfd_process_device_apertures
{
130 __u64 lds_base
; /* from KFD */
131 __u64 lds_limit
; /* from KFD */
132 __u64 scratch_base
; /* from KFD */
133 __u64 scratch_limit
; /* from KFD */
134 __u64 gpuvm_base
; /* from KFD */
135 __u64 gpuvm_limit
; /* from KFD */
136 __u32 gpu_id
; /* from KFD */
141 * AMDKFD_IOC_GET_PROCESS_APERTURES is deprecated. Use
142 * AMDKFD_IOC_GET_PROCESS_APERTURES_NEW instead, which supports an
143 * unlimited number of GPUs.
145 #define NUM_OF_SUPPORTED_GPUS 7
146 struct kfd_ioctl_get_process_apertures_args
{
147 struct kfd_process_device_apertures
148 process_apertures
[NUM_OF_SUPPORTED_GPUS
];/* from KFD */
150 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
155 struct kfd_ioctl_get_process_apertures_new_args
{
156 /* User allocated. Pointer to struct kfd_process_device_apertures
157 * filled in by Kernel
159 __u64 kfd_process_device_apertures_ptr
;
160 /* to KFD - indicates amount of memory present in
161 * kfd_process_device_apertures_ptr
162 * from KFD - Number of entries filled by KFD.
168 #define MAX_ALLOWED_NUM_POINTS 100
169 #define MAX_ALLOWED_AW_BUFF_SIZE 4096
170 #define MAX_ALLOWED_WAC_BUFF_SIZE 128
172 struct kfd_ioctl_dbg_register_args
{
173 __u32 gpu_id
; /* to KFD */
177 struct kfd_ioctl_dbg_unregister_args
{
178 __u32 gpu_id
; /* to KFD */
182 struct kfd_ioctl_dbg_address_watch_args
{
183 __u64 content_ptr
; /* a pointer to the actual content */
184 __u32 gpu_id
; /* to KFD */
185 __u32 buf_size_in_bytes
; /*including gpu_id and buf_size */
188 struct kfd_ioctl_dbg_wave_control_args
{
189 __u64 content_ptr
; /* a pointer to the actual content */
190 __u32 gpu_id
; /* to KFD */
191 __u32 buf_size_in_bytes
; /*including gpu_id and buf_size */
194 /* Matching HSA_EVENTTYPE */
195 #define KFD_IOC_EVENT_SIGNAL 0
196 #define KFD_IOC_EVENT_NODECHANGE 1
197 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2
198 #define KFD_IOC_EVENT_HW_EXCEPTION 3
199 #define KFD_IOC_EVENT_SYSTEM_EVENT 4
200 #define KFD_IOC_EVENT_DEBUG_EVENT 5
201 #define KFD_IOC_EVENT_PROFILE_EVENT 6
202 #define KFD_IOC_EVENT_QUEUE_EVENT 7
203 #define KFD_IOC_EVENT_MEMORY 8
205 #define KFD_IOC_WAIT_RESULT_COMPLETE 0
206 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1
207 #define KFD_IOC_WAIT_RESULT_FAIL 2
209 #define KFD_SIGNAL_EVENT_LIMIT 4096
211 /* For kfd_event_data.hw_exception_data.reset_type. */
212 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
213 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
215 /* For kfd_event_data.hw_exception_data.reset_cause. */
216 #define KFD_HW_EXCEPTION_GPU_HANG 0
217 #define KFD_HW_EXCEPTION_ECC 1
219 /* For kfd_hsa_memory_exception_data.ErrorType */
220 #define KFD_MEM_ERR_NO_RAS 0
221 #define KFD_MEM_ERR_SRAM_ECC 1
222 #define KFD_MEM_ERR_POISON_CONSUMED 2
223 #define KFD_MEM_ERR_GPU_HANG 3
225 struct kfd_ioctl_create_event_args
{
226 __u64 event_page_offset
; /* from KFD */
227 __u32 event_trigger_data
; /* from KFD - signal events only */
228 __u32 event_type
; /* to KFD */
229 __u32 auto_reset
; /* to KFD */
230 __u32 node_id
; /* to KFD - only valid for certain
232 __u32 event_id
; /* from KFD */
233 __u32 event_slot_index
; /* from KFD */
236 struct kfd_ioctl_destroy_event_args
{
237 __u32 event_id
; /* to KFD */
241 struct kfd_ioctl_set_event_args
{
242 __u32 event_id
; /* to KFD */
246 struct kfd_ioctl_reset_event_args
{
247 __u32 event_id
; /* to KFD */
251 struct kfd_memory_exception_failure
{
252 __u32 NotPresent
; /* Page not present or supervisor privilege */
253 __u32 ReadOnly
; /* Write access to a read-only page */
254 __u32 NoExecute
; /* Execute access to a page marked NX */
255 __u32 imprecise
; /* Can't determine the exact fault address */
258 /* memory exception data */
259 struct kfd_hsa_memory_exception_data
{
260 struct kfd_memory_exception_failure failure
;
263 __u32 ErrorType
; /* 0 = no RAS error,
265 * 2 = Link_SYNFLOOD (poison),
266 * 3 = GPU hang (not attributable to a specific cause),
267 * other values reserved
271 /* hw exception data */
272 struct kfd_hsa_hw_exception_data
{
280 struct kfd_event_data
{
282 struct kfd_hsa_memory_exception_data memory_exception_data
;
283 struct kfd_hsa_hw_exception_data hw_exception_data
;
285 __u64 kfd_event_data_ext
; /* pointer to an extension structure
286 for future exception types */
287 __u32 event_id
; /* to KFD */
291 struct kfd_ioctl_wait_events_args
{
292 __u64 events_ptr
; /* pointed to struct
293 kfd_event_data array, to KFD */
294 __u32 num_events
; /* to KFD */
295 __u32 wait_for_all
; /* to KFD */
296 __u32 timeout
; /* to KFD */
297 __u32 wait_result
; /* from KFD */
300 struct kfd_ioctl_set_scratch_backing_va_args
{
301 __u64 va_addr
; /* to KFD */
302 __u32 gpu_id
; /* to KFD */
306 struct kfd_ioctl_get_tile_config_args
{
307 /* to KFD: pointer to tile array */
308 __u64 tile_config_ptr
;
309 /* to KFD: pointer to macro tile array */
310 __u64 macro_tile_config_ptr
;
311 /* to KFD: array size allocated by user mode
312 * from KFD: array size filled by kernel
314 __u32 num_tile_configs
;
315 /* to KFD: array size allocated by user mode
316 * from KFD: array size filled by kernel
318 __u32 num_macro_tile_configs
;
320 __u32 gpu_id
; /* to KFD */
321 __u32 gb_addr_config
; /* from KFD */
322 __u32 num_banks
; /* from KFD */
323 __u32 num_ranks
; /* from KFD */
324 /* struct size can be extended later if needed
325 * without breaking ABI compatibility
329 struct kfd_ioctl_set_trap_handler_args
{
330 __u64 tba_addr
; /* to KFD */
331 __u64 tma_addr
; /* to KFD */
332 __u32 gpu_id
; /* to KFD */
336 struct kfd_ioctl_acquire_vm_args
{
337 __u32 drm_fd
; /* to KFD */
338 __u32 gpu_id
; /* to KFD */
341 /* Allocation flags: memory types */
342 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
343 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
344 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
345 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
346 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
347 /* Allocation flags: attributes/access options */
348 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
349 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
350 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
351 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
352 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
353 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
355 /* Allocate memory for later SVM (shared virtual memory) mapping.
357 * @va_addr: virtual address of the memory to be allocated
358 * all later mappings on all GPUs will use this address
359 * @size: size in bytes
360 * @handle: buffer handle returned to user mode, used to refer to
361 * this allocation for mapping, unmapping and freeing
362 * @mmap_offset: for CPU-mapping the allocation by mmapping a render node
363 * for userptrs this is overloaded to specify the CPU address
364 * @gpu_id: device identifier
365 * @flags: memory type and attributes. See KFD_IOC_ALLOC_MEM_FLAGS above
367 struct kfd_ioctl_alloc_memory_of_gpu_args
{
368 __u64 va_addr
; /* to KFD */
369 __u64 size
; /* to KFD */
370 __u64 handle
; /* from KFD */
371 __u64 mmap_offset
; /* to KFD (userptr), from KFD (mmap offset) */
372 __u32 gpu_id
; /* to KFD */
376 /* Free memory allocated with kfd_ioctl_alloc_memory_of_gpu
378 * @handle: memory handle returned by alloc
380 struct kfd_ioctl_free_memory_of_gpu_args
{
381 __u64 handle
; /* to KFD */
384 /* Map memory to one or more GPUs
386 * @handle: memory handle returned by alloc
387 * @device_ids_array_ptr: array of gpu_ids (__u32 per device)
388 * @n_devices: number of devices in the array
389 * @n_success: number of devices mapped successfully
391 * @n_success returns information to the caller how many devices from
392 * the start of the array have mapped the buffer successfully. It can
393 * be passed into a subsequent retry call to skip those devices. For
394 * the first call the caller should initialize it to 0.
396 * If the ioctl completes with return code 0 (success), n_success ==
399 struct kfd_ioctl_map_memory_to_gpu_args
{
400 __u64 handle
; /* to KFD */
401 __u64 device_ids_array_ptr
; /* to KFD */
402 __u32 n_devices
; /* to KFD */
403 __u32 n_success
; /* to/from KFD */
406 /* Unmap memory from one or more GPUs
408 * same arguments as for mapping
410 struct kfd_ioctl_unmap_memory_from_gpu_args
{
411 __u64 handle
; /* to KFD */
412 __u64 device_ids_array_ptr
; /* to KFD */
413 __u32 n_devices
; /* to KFD */
414 __u32 n_success
; /* to/from KFD */
417 /* Allocate GWS for specific queue
419 * @queue_id: queue's id that GWS is allocated for
420 * @num_gws: how many GWS to allocate
421 * @first_gws: index of the first GWS allocated.
422 * only support contiguous GWS allocation
424 struct kfd_ioctl_alloc_queue_gws_args
{
425 __u32 queue_id
; /* to KFD */
426 __u32 num_gws
; /* to KFD */
427 __u32 first_gws
; /* from KFD */
431 struct kfd_ioctl_get_dmabuf_info_args
{
432 __u64 size
; /* from KFD */
433 __u64 metadata_ptr
; /* to KFD */
434 __u32 metadata_size
; /* to KFD (space allocated by user)
435 * from KFD (actual metadata size)
437 __u32 gpu_id
; /* from KFD */
438 __u32 flags
; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
439 __u32 dmabuf_fd
; /* to KFD */
442 struct kfd_ioctl_import_dmabuf_args
{
443 __u64 va_addr
; /* to KFD */
444 __u64 handle
; /* from KFD */
445 __u32 gpu_id
; /* to KFD */
446 __u32 dmabuf_fd
; /* to KFD */
450 * KFD SMI(System Management Interface) events
453 KFD_SMI_EVENT_NONE
= 0, /* not used */
454 KFD_SMI_EVENT_VMFAULT
= 1, /* event start counting at 1 */
455 KFD_SMI_EVENT_THERMAL_THROTTLE
= 2,
456 KFD_SMI_EVENT_GPU_PRE_RESET
= 3,
457 KFD_SMI_EVENT_GPU_POST_RESET
= 4,
460 #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1))
462 struct kfd_ioctl_smi_events_args
{
463 __u32 gpuid
; /* to KFD */
464 __u32 anon_fd
; /* from KFD */
467 /* Register offset inside the remapped mmio page
469 enum kfd_mmio_remap
{
470 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL
= 0,
471 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL
= 4,
474 #define AMDKFD_IOCTL_BASE 'K'
475 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
476 #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
477 #define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
478 #define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
480 #define AMDKFD_IOC_GET_VERSION \
481 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
483 #define AMDKFD_IOC_CREATE_QUEUE \
484 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
486 #define AMDKFD_IOC_DESTROY_QUEUE \
487 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
489 #define AMDKFD_IOC_SET_MEMORY_POLICY \
490 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
492 #define AMDKFD_IOC_GET_CLOCK_COUNTERS \
493 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
495 #define AMDKFD_IOC_GET_PROCESS_APERTURES \
496 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
498 #define AMDKFD_IOC_UPDATE_QUEUE \
499 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
501 #define AMDKFD_IOC_CREATE_EVENT \
502 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
504 #define AMDKFD_IOC_DESTROY_EVENT \
505 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
507 #define AMDKFD_IOC_SET_EVENT \
508 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
510 #define AMDKFD_IOC_RESET_EVENT \
511 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
513 #define AMDKFD_IOC_WAIT_EVENTS \
514 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
516 #define AMDKFD_IOC_DBG_REGISTER \
517 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
519 #define AMDKFD_IOC_DBG_UNREGISTER \
520 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
522 #define AMDKFD_IOC_DBG_ADDRESS_WATCH \
523 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
525 #define AMDKFD_IOC_DBG_WAVE_CONTROL \
526 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
528 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
529 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
531 #define AMDKFD_IOC_GET_TILE_CONFIG \
532 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
534 #define AMDKFD_IOC_SET_TRAP_HANDLER \
535 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
537 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
539 struct kfd_ioctl_get_process_apertures_new_args)
541 #define AMDKFD_IOC_ACQUIRE_VM \
542 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
544 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
545 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
547 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
548 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
550 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
551 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
553 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
554 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
556 #define AMDKFD_IOC_SET_CU_MASK \
557 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
559 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
560 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
562 #define AMDKFD_IOC_GET_DMABUF_INFO \
563 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
565 #define AMDKFD_IOC_IMPORT_DMABUF \
566 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
568 #define AMDKFD_IOC_ALLOC_QUEUE_GWS \
569 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
571 #define AMDKFD_IOC_SMI_EVENTS \
572 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args)
574 #define AMDKFD_COMMAND_START 0x01
575 #define AMDKFD_COMMAND_END 0x20