2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2013, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #ifndef _UAPI_LINUX_NVME_H
20 #define _UAPI_LINUX_NVME_H
22 #include <linux/types.h>
24 struct nvme_id_power_state
{
25 __le16 max_power
; /* centiwatts */
28 __le32 entry_lat
; /* microseconds */
29 __le32 exit_lat
; /* microseconds */
38 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
39 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
72 struct nvme_id_power_state psd
[32];
77 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
78 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
79 NVME_CTRL_ONCS_DSM
= 1 << 2,
99 struct nvme_lbaf lbaf
[16];
105 NVME_NS_FEAT_THIN
= 1 << 0,
106 NVME_LBAF_RP_BEST
= 0,
107 NVME_LBAF_RP_BETTER
= 1,
108 NVME_LBAF_RP_GOOD
= 2,
109 NVME_LBAF_RP_DEGRADED
= 3,
112 struct nvme_smart_log
{
113 __u8 critical_warning
;
119 __u8 data_units_read
[16];
120 __u8 data_units_written
[16];
122 __u8 host_writes
[16];
123 __u8 ctrl_busy_time
[16];
124 __u8 power_cycles
[16];
125 __u8 power_on_hours
[16];
126 __u8 unsafe_shutdowns
[16];
127 __u8 media_errors
[16];
128 __u8 num_err_log_entries
[16];
133 NVME_SMART_CRIT_SPARE
= 1 << 0,
134 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
135 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
136 NVME_SMART_CRIT_MEDIA
= 1 << 3,
137 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
140 struct nvme_lba_range_type
{
151 NVME_LBART_TYPE_FS
= 0x01,
152 NVME_LBART_TYPE_RAID
= 0x02,
153 NVME_LBART_TYPE_CACHE
= 0x03,
154 NVME_LBART_TYPE_SWAP
= 0x04,
156 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
157 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
163 nvme_cmd_flush
= 0x00,
164 nvme_cmd_write
= 0x01,
165 nvme_cmd_read
= 0x02,
166 nvme_cmd_write_uncor
= 0x04,
167 nvme_cmd_compare
= 0x05,
171 struct nvme_common_command
{
183 struct nvme_rw_command
{
202 NVME_RW_LR
= 1 << 15,
203 NVME_RW_FUA
= 1 << 14,
204 NVME_RW_DSM_FREQ_UNSPEC
= 0,
205 NVME_RW_DSM_FREQ_TYPICAL
= 1,
206 NVME_RW_DSM_FREQ_RARE
= 2,
207 NVME_RW_DSM_FREQ_READS
= 3,
208 NVME_RW_DSM_FREQ_WRITES
= 4,
209 NVME_RW_DSM_FREQ_RW
= 5,
210 NVME_RW_DSM_FREQ_ONCE
= 6,
211 NVME_RW_DSM_FREQ_PREFETCH
= 7,
212 NVME_RW_DSM_FREQ_TEMP
= 8,
213 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
214 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
215 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
216 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
217 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
218 NVME_RW_DSM_COMPRESSED
= 1 << 7,
221 struct nvme_dsm_cmd
{
235 NVME_DSMGMT_IDR
= 1 << 0,
236 NVME_DSMGMT_IDW
= 1 << 1,
237 NVME_DSMGMT_AD
= 1 << 2,
240 struct nvme_dsm_range
{
248 enum nvme_admin_opcode
{
249 nvme_admin_delete_sq
= 0x00,
250 nvme_admin_create_sq
= 0x01,
251 nvme_admin_get_log_page
= 0x02,
252 nvme_admin_delete_cq
= 0x04,
253 nvme_admin_create_cq
= 0x05,
254 nvme_admin_identify
= 0x06,
255 nvme_admin_abort_cmd
= 0x08,
256 nvme_admin_set_features
= 0x09,
257 nvme_admin_get_features
= 0x0a,
258 nvme_admin_async_event
= 0x0c,
259 nvme_admin_activate_fw
= 0x10,
260 nvme_admin_download_fw
= 0x11,
261 nvme_admin_format_nvm
= 0x80,
262 nvme_admin_security_send
= 0x81,
263 nvme_admin_security_recv
= 0x82,
267 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
268 NVME_CQ_IRQ_ENABLED
= (1 << 1),
269 NVME_SQ_PRIO_URGENT
= (0 << 1),
270 NVME_SQ_PRIO_HIGH
= (1 << 1),
271 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
272 NVME_SQ_PRIO_LOW
= (3 << 1),
273 NVME_FEAT_ARBITRATION
= 0x01,
274 NVME_FEAT_POWER_MGMT
= 0x02,
275 NVME_FEAT_LBA_RANGE
= 0x03,
276 NVME_FEAT_TEMP_THRESH
= 0x04,
277 NVME_FEAT_ERR_RECOVERY
= 0x05,
278 NVME_FEAT_VOLATILE_WC
= 0x06,
279 NVME_FEAT_NUM_QUEUES
= 0x07,
280 NVME_FEAT_IRQ_COALESCE
= 0x08,
281 NVME_FEAT_IRQ_CONFIG
= 0x09,
282 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
283 NVME_FEAT_ASYNC_EVENT
= 0x0b,
284 NVME_FEAT_SW_PROGRESS
= 0x0c,
285 NVME_FWACT_REPL
= (0 << 3),
286 NVME_FWACT_REPL_ACTV
= (1 << 3),
287 NVME_FWACT_ACTV
= (2 << 3),
290 struct nvme_identify
{
302 struct nvme_features
{
315 struct nvme_create_cq
{
329 struct nvme_create_sq
{
343 struct nvme_delete_queue
{
353 struct nvme_download_firmware
{
365 struct nvme_format_cmd
{
375 struct nvme_command
{
377 struct nvme_common_command common
;
378 struct nvme_rw_command rw
;
379 struct nvme_identify identify
;
380 struct nvme_features features
;
381 struct nvme_create_cq create_cq
;
382 struct nvme_create_sq create_sq
;
383 struct nvme_delete_queue delete_queue
;
384 struct nvme_download_firmware dlfw
;
385 struct nvme_format_cmd format
;
386 struct nvme_dsm_cmd dsm
;
391 NVME_SC_SUCCESS
= 0x0,
392 NVME_SC_INVALID_OPCODE
= 0x1,
393 NVME_SC_INVALID_FIELD
= 0x2,
394 NVME_SC_CMDID_CONFLICT
= 0x3,
395 NVME_SC_DATA_XFER_ERROR
= 0x4,
396 NVME_SC_POWER_LOSS
= 0x5,
397 NVME_SC_INTERNAL
= 0x6,
398 NVME_SC_ABORT_REQ
= 0x7,
399 NVME_SC_ABORT_QUEUE
= 0x8,
400 NVME_SC_FUSED_FAIL
= 0x9,
401 NVME_SC_FUSED_MISSING
= 0xa,
402 NVME_SC_INVALID_NS
= 0xb,
403 NVME_SC_CMD_SEQ_ERROR
= 0xc,
404 NVME_SC_LBA_RANGE
= 0x80,
405 NVME_SC_CAP_EXCEEDED
= 0x81,
406 NVME_SC_NS_NOT_READY
= 0x82,
407 NVME_SC_CQ_INVALID
= 0x100,
408 NVME_SC_QID_INVALID
= 0x101,
409 NVME_SC_QUEUE_SIZE
= 0x102,
410 NVME_SC_ABORT_LIMIT
= 0x103,
411 NVME_SC_ABORT_MISSING
= 0x104,
412 NVME_SC_ASYNC_LIMIT
= 0x105,
413 NVME_SC_FIRMWARE_SLOT
= 0x106,
414 NVME_SC_FIRMWARE_IMAGE
= 0x107,
415 NVME_SC_INVALID_VECTOR
= 0x108,
416 NVME_SC_INVALID_LOG_PAGE
= 0x109,
417 NVME_SC_INVALID_FORMAT
= 0x10a,
418 NVME_SC_BAD_ATTRIBUTES
= 0x180,
419 NVME_SC_WRITE_FAULT
= 0x280,
420 NVME_SC_READ_ERROR
= 0x281,
421 NVME_SC_GUARD_CHECK
= 0x282,
422 NVME_SC_APPTAG_CHECK
= 0x283,
423 NVME_SC_REFTAG_CHECK
= 0x284,
424 NVME_SC_COMPARE_FAILED
= 0x285,
425 NVME_SC_ACCESS_DENIED
= 0x286,
428 struct nvme_completion
{
429 __le32 result
; /* Used by admin commands to return data */
431 __le16 sq_head
; /* how much of this queue may be reclaimed */
432 __le16 sq_id
; /* submission queue that generated this entry */
433 __u16 command_id
; /* of the command which completed */
434 __le16 status
; /* did the command fail, and if so, why? */
437 struct nvme_user_io
{
452 struct nvme_admin_cmd
{
473 #define NVME_IOCTL_ID _IO('N', 0x40)
474 #define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
475 #define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
477 #endif /* _UAPI_LINUX_NVME_H */