2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef _UAPI_LINUX_NVME_H
16 #define _UAPI_LINUX_NVME_H
18 #include <linux/types.h>
20 struct nvme_id_power_state
{
21 __le16 max_power
; /* centiwatts */
24 __le32 entry_lat
; /* microseconds */
25 __le32 exit_lat
; /* microseconds */
34 __u8 active_work_scale
;
39 NVME_PS_FLAGS_MAX_POWER_SCALE
= 1 << 0,
40 NVME_PS_FLAGS_NON_OP_STATE
= 1 << 1,
84 struct nvme_id_power_state psd
[32];
89 NVME_CTRL_ONCS_COMPARE
= 1 << 0,
90 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE
= 1 << 1,
91 NVME_CTRL_ONCS_DSM
= 1 << 2,
92 NVME_CTRL_VWC_PRESENT
= 1 << 0,
126 struct nvme_lbaf lbaf
[16];
132 NVME_NS_FEAT_THIN
= 1 << 0,
133 NVME_NS_FLBAS_LBA_MASK
= 0xf,
134 NVME_NS_FLBAS_META_EXT
= 0x10,
135 NVME_LBAF_RP_BEST
= 0,
136 NVME_LBAF_RP_BETTER
= 1,
137 NVME_LBAF_RP_GOOD
= 2,
138 NVME_LBAF_RP_DEGRADED
= 3,
139 NVME_NS_DPC_PI_LAST
= 1 << 4,
140 NVME_NS_DPC_PI_FIRST
= 1 << 3,
141 NVME_NS_DPC_PI_TYPE3
= 1 << 2,
142 NVME_NS_DPC_PI_TYPE2
= 1 << 1,
143 NVME_NS_DPC_PI_TYPE1
= 1 << 0,
144 NVME_NS_DPS_PI_FIRST
= 1 << 3,
145 NVME_NS_DPS_PI_MASK
= 0x7,
146 NVME_NS_DPS_PI_TYPE1
= 1,
147 NVME_NS_DPS_PI_TYPE2
= 2,
148 NVME_NS_DPS_PI_TYPE3
= 3,
151 struct nvme_smart_log
{
152 __u8 critical_warning
;
158 __u8 data_units_read
[16];
159 __u8 data_units_written
[16];
161 __u8 host_writes
[16];
162 __u8 ctrl_busy_time
[16];
163 __u8 power_cycles
[16];
164 __u8 power_on_hours
[16];
165 __u8 unsafe_shutdowns
[16];
166 __u8 media_errors
[16];
167 __u8 num_err_log_entries
[16];
168 __le32 warning_temp_time
;
169 __le32 critical_comp_time
;
170 __le16 temp_sensor
[8];
175 NVME_SMART_CRIT_SPARE
= 1 << 0,
176 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
177 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
178 NVME_SMART_CRIT_MEDIA
= 1 << 3,
179 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
183 NVME_AER_NOTICE_NS_CHANGED
= 0x0002,
186 struct nvme_lba_range_type
{
197 NVME_LBART_TYPE_FS
= 0x01,
198 NVME_LBART_TYPE_RAID
= 0x02,
199 NVME_LBART_TYPE_CACHE
= 0x03,
200 NVME_LBART_TYPE_SWAP
= 0x04,
202 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
203 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
206 struct nvme_reservation_status
{
225 nvme_cmd_flush
= 0x00,
226 nvme_cmd_write
= 0x01,
227 nvme_cmd_read
= 0x02,
228 nvme_cmd_write_uncor
= 0x04,
229 nvme_cmd_compare
= 0x05,
230 nvme_cmd_write_zeroes
= 0x08,
232 nvme_cmd_resv_register
= 0x0d,
233 nvme_cmd_resv_report
= 0x0e,
234 nvme_cmd_resv_acquire
= 0x11,
235 nvme_cmd_resv_release
= 0x15,
238 struct nvme_common_command
{
250 struct nvme_rw_command
{
269 NVME_RW_LR
= 1 << 15,
270 NVME_RW_FUA
= 1 << 14,
271 NVME_RW_DSM_FREQ_UNSPEC
= 0,
272 NVME_RW_DSM_FREQ_TYPICAL
= 1,
273 NVME_RW_DSM_FREQ_RARE
= 2,
274 NVME_RW_DSM_FREQ_READS
= 3,
275 NVME_RW_DSM_FREQ_WRITES
= 4,
276 NVME_RW_DSM_FREQ_RW
= 5,
277 NVME_RW_DSM_FREQ_ONCE
= 6,
278 NVME_RW_DSM_FREQ_PREFETCH
= 7,
279 NVME_RW_DSM_FREQ_TEMP
= 8,
280 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
281 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
282 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
283 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
284 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
285 NVME_RW_DSM_COMPRESSED
= 1 << 7,
286 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
287 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
288 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
289 NVME_RW_PRINFO_PRACT
= 1 << 13,
292 struct nvme_dsm_cmd
{
306 NVME_DSMGMT_IDR
= 1 << 0,
307 NVME_DSMGMT_IDW
= 1 << 1,
308 NVME_DSMGMT_AD
= 1 << 2,
311 struct nvme_dsm_range
{
319 enum nvme_admin_opcode
{
320 nvme_admin_delete_sq
= 0x00,
321 nvme_admin_create_sq
= 0x01,
322 nvme_admin_get_log_page
= 0x02,
323 nvme_admin_delete_cq
= 0x04,
324 nvme_admin_create_cq
= 0x05,
325 nvme_admin_identify
= 0x06,
326 nvme_admin_abort_cmd
= 0x08,
327 nvme_admin_set_features
= 0x09,
328 nvme_admin_get_features
= 0x0a,
329 nvme_admin_async_event
= 0x0c,
330 nvme_admin_activate_fw
= 0x10,
331 nvme_admin_download_fw
= 0x11,
332 nvme_admin_format_nvm
= 0x80,
333 nvme_admin_security_send
= 0x81,
334 nvme_admin_security_recv
= 0x82,
338 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
339 NVME_CQ_IRQ_ENABLED
= (1 << 1),
340 NVME_SQ_PRIO_URGENT
= (0 << 1),
341 NVME_SQ_PRIO_HIGH
= (1 << 1),
342 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
343 NVME_SQ_PRIO_LOW
= (3 << 1),
344 NVME_FEAT_ARBITRATION
= 0x01,
345 NVME_FEAT_POWER_MGMT
= 0x02,
346 NVME_FEAT_LBA_RANGE
= 0x03,
347 NVME_FEAT_TEMP_THRESH
= 0x04,
348 NVME_FEAT_ERR_RECOVERY
= 0x05,
349 NVME_FEAT_VOLATILE_WC
= 0x06,
350 NVME_FEAT_NUM_QUEUES
= 0x07,
351 NVME_FEAT_IRQ_COALESCE
= 0x08,
352 NVME_FEAT_IRQ_CONFIG
= 0x09,
353 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
354 NVME_FEAT_ASYNC_EVENT
= 0x0b,
355 NVME_FEAT_AUTO_PST
= 0x0c,
356 NVME_FEAT_SW_PROGRESS
= 0x80,
357 NVME_FEAT_HOST_ID
= 0x81,
358 NVME_FEAT_RESV_MASK
= 0x82,
359 NVME_FEAT_RESV_PERSIST
= 0x83,
360 NVME_LOG_ERROR
= 0x01,
361 NVME_LOG_SMART
= 0x02,
362 NVME_LOG_FW_SLOT
= 0x03,
363 NVME_LOG_RESERVATION
= 0x80,
364 NVME_FWACT_REPL
= (0 << 3),
365 NVME_FWACT_REPL_ACTV
= (1 << 3),
366 NVME_FWACT_ACTV
= (2 << 3),
369 struct nvme_identify
{
381 struct nvme_features
{
394 struct nvme_create_cq
{
408 struct nvme_create_sq
{
422 struct nvme_delete_queue
{
432 struct nvme_abort_cmd
{
442 struct nvme_download_firmware
{
454 struct nvme_format_cmd
{
464 struct nvme_command
{
466 struct nvme_common_command common
;
467 struct nvme_rw_command rw
;
468 struct nvme_identify identify
;
469 struct nvme_features features
;
470 struct nvme_create_cq create_cq
;
471 struct nvme_create_sq create_sq
;
472 struct nvme_delete_queue delete_queue
;
473 struct nvme_download_firmware dlfw
;
474 struct nvme_format_cmd format
;
475 struct nvme_dsm_cmd dsm
;
476 struct nvme_abort_cmd abort
;
481 NVME_SC_SUCCESS
= 0x0,
482 NVME_SC_INVALID_OPCODE
= 0x1,
483 NVME_SC_INVALID_FIELD
= 0x2,
484 NVME_SC_CMDID_CONFLICT
= 0x3,
485 NVME_SC_DATA_XFER_ERROR
= 0x4,
486 NVME_SC_POWER_LOSS
= 0x5,
487 NVME_SC_INTERNAL
= 0x6,
488 NVME_SC_ABORT_REQ
= 0x7,
489 NVME_SC_ABORT_QUEUE
= 0x8,
490 NVME_SC_FUSED_FAIL
= 0x9,
491 NVME_SC_FUSED_MISSING
= 0xa,
492 NVME_SC_INVALID_NS
= 0xb,
493 NVME_SC_CMD_SEQ_ERROR
= 0xc,
494 NVME_SC_SGL_INVALID_LAST
= 0xd,
495 NVME_SC_SGL_INVALID_COUNT
= 0xe,
496 NVME_SC_SGL_INVALID_DATA
= 0xf,
497 NVME_SC_SGL_INVALID_METADATA
= 0x10,
498 NVME_SC_SGL_INVALID_TYPE
= 0x11,
499 NVME_SC_LBA_RANGE
= 0x80,
500 NVME_SC_CAP_EXCEEDED
= 0x81,
501 NVME_SC_NS_NOT_READY
= 0x82,
502 NVME_SC_RESERVATION_CONFLICT
= 0x83,
503 NVME_SC_CQ_INVALID
= 0x100,
504 NVME_SC_QID_INVALID
= 0x101,
505 NVME_SC_QUEUE_SIZE
= 0x102,
506 NVME_SC_ABORT_LIMIT
= 0x103,
507 NVME_SC_ABORT_MISSING
= 0x104,
508 NVME_SC_ASYNC_LIMIT
= 0x105,
509 NVME_SC_FIRMWARE_SLOT
= 0x106,
510 NVME_SC_FIRMWARE_IMAGE
= 0x107,
511 NVME_SC_INVALID_VECTOR
= 0x108,
512 NVME_SC_INVALID_LOG_PAGE
= 0x109,
513 NVME_SC_INVALID_FORMAT
= 0x10a,
514 NVME_SC_FIRMWARE_NEEDS_RESET
= 0x10b,
515 NVME_SC_INVALID_QUEUE
= 0x10c,
516 NVME_SC_FEATURE_NOT_SAVEABLE
= 0x10d,
517 NVME_SC_FEATURE_NOT_CHANGEABLE
= 0x10e,
518 NVME_SC_FEATURE_NOT_PER_NS
= 0x10f,
519 NVME_SC_FW_NEEDS_RESET_SUBSYS
= 0x110,
520 NVME_SC_BAD_ATTRIBUTES
= 0x180,
521 NVME_SC_INVALID_PI
= 0x181,
522 NVME_SC_READ_ONLY
= 0x182,
523 NVME_SC_WRITE_FAULT
= 0x280,
524 NVME_SC_READ_ERROR
= 0x281,
525 NVME_SC_GUARD_CHECK
= 0x282,
526 NVME_SC_APPTAG_CHECK
= 0x283,
527 NVME_SC_REFTAG_CHECK
= 0x284,
528 NVME_SC_COMPARE_FAILED
= 0x285,
529 NVME_SC_ACCESS_DENIED
= 0x286,
530 NVME_SC_DNR
= 0x4000,
533 struct nvme_completion
{
534 __le32 result
; /* Used by admin commands to return data */
536 __le16 sq_head
; /* how much of this queue may be reclaimed */
537 __le16 sq_id
; /* submission queue that generated this entry */
538 __u16 command_id
; /* of the command which completed */
539 __le16 status
; /* did the command fail, and if so, why? */
542 struct nvme_user_io
{
557 struct nvme_passthru_cmd
{
578 #define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
580 #define nvme_admin_cmd nvme_passthru_cmd
582 #define NVME_IOCTL_ID _IO('N', 0x40)
583 #define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
584 #define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
585 #define NVME_IOCTL_IO_CMD _IOWR('N', 0x43, struct nvme_passthru_cmd)
586 #define NVME_IOCTL_RESET _IO('N', 0x44)
588 #endif /* _UAPI_LINUX_NVME_H */