4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
8 * Data type definitions, declarations, prototypes.
10 * Started by: Thomas Gleixner and Ingo Molnar
12 * For licencing details see kernel-base/COPYING
14 #ifndef _UAPI_LINUX_PERF_EVENT_H
15 #define _UAPI_LINUX_PERF_EVENT_H
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19 #include <asm/byteorder.h>
22 * User-space ABI bits:
29 PERF_TYPE_HARDWARE
= 0,
30 PERF_TYPE_SOFTWARE
= 1,
31 PERF_TYPE_TRACEPOINT
= 2,
32 PERF_TYPE_HW_CACHE
= 3,
34 PERF_TYPE_BREAKPOINT
= 5,
36 PERF_TYPE_MAX
, /* non-ABI */
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
46 * Common hardware events, generalized by the kernel:
48 PERF_COUNT_HW_CPU_CYCLES
= 0,
49 PERF_COUNT_HW_INSTRUCTIONS
= 1,
50 PERF_COUNT_HW_CACHE_REFERENCES
= 2,
51 PERF_COUNT_HW_CACHE_MISSES
= 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS
= 4,
53 PERF_COUNT_HW_BRANCH_MISSES
= 5,
54 PERF_COUNT_HW_BUS_CYCLES
= 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
= 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND
= 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES
= 9,
59 PERF_COUNT_HW_MAX
, /* non-ABI */
63 * Generalized hardware cache events:
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
69 enum perf_hw_cache_id
{
70 PERF_COUNT_HW_CACHE_L1D
= 0,
71 PERF_COUNT_HW_CACHE_L1I
= 1,
72 PERF_COUNT_HW_CACHE_LL
= 2,
73 PERF_COUNT_HW_CACHE_DTLB
= 3,
74 PERF_COUNT_HW_CACHE_ITLB
= 4,
75 PERF_COUNT_HW_CACHE_BPU
= 5,
76 PERF_COUNT_HW_CACHE_NODE
= 6,
78 PERF_COUNT_HW_CACHE_MAX
, /* non-ABI */
81 enum perf_hw_cache_op_id
{
82 PERF_COUNT_HW_CACHE_OP_READ
= 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE
= 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH
= 2,
86 PERF_COUNT_HW_CACHE_OP_MAX
, /* non-ABI */
89 enum perf_hw_cache_op_result_id
{
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS
= 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS
= 1,
93 PERF_COUNT_HW_CACHE_RESULT_MAX
, /* non-ABI */
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
103 PERF_COUNT_SW_CPU_CLOCK
= 0,
104 PERF_COUNT_SW_TASK_CLOCK
= 1,
105 PERF_COUNT_SW_PAGE_FAULTS
= 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES
= 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS
= 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN
= 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ
= 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS
= 7,
111 PERF_COUNT_SW_EMULATION_FAULTS
= 8,
112 PERF_COUNT_SW_DUMMY
= 9,
114 PERF_COUNT_SW_MAX
, /* non-ABI */
118 * Bits that can be set in attr.sample_type to request information
119 * in the overflow packets.
121 enum perf_event_sample_format
{
122 PERF_SAMPLE_IP
= 1U << 0,
123 PERF_SAMPLE_TID
= 1U << 1,
124 PERF_SAMPLE_TIME
= 1U << 2,
125 PERF_SAMPLE_ADDR
= 1U << 3,
126 PERF_SAMPLE_READ
= 1U << 4,
127 PERF_SAMPLE_CALLCHAIN
= 1U << 5,
128 PERF_SAMPLE_ID
= 1U << 6,
129 PERF_SAMPLE_CPU
= 1U << 7,
130 PERF_SAMPLE_PERIOD
= 1U << 8,
131 PERF_SAMPLE_STREAM_ID
= 1U << 9,
132 PERF_SAMPLE_RAW
= 1U << 10,
133 PERF_SAMPLE_BRANCH_STACK
= 1U << 11,
134 PERF_SAMPLE_REGS_USER
= 1U << 12,
135 PERF_SAMPLE_STACK_USER
= 1U << 13,
136 PERF_SAMPLE_WEIGHT
= 1U << 14,
137 PERF_SAMPLE_DATA_SRC
= 1U << 15,
138 PERF_SAMPLE_IDENTIFIER
= 1U << 16,
139 PERF_SAMPLE_TRANSACTION
= 1U << 17,
140 PERF_SAMPLE_REGS_INTR
= 1U << 18,
142 PERF_SAMPLE_MAX
= 1U << 19, /* non-ABI */
146 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
148 * If the user does not pass priv level information via branch_sample_type,
149 * the kernel uses the event's priv level. Branch and event priv levels do
150 * not have to match. Branch priv level is checked for permissions.
152 * The branch types can be combined, however BRANCH_ANY covers all types
153 * of branches and therefore it supersedes all the other types.
155 enum perf_branch_sample_type_shift
{
156 PERF_SAMPLE_BRANCH_USER_SHIFT
= 0, /* user branches */
157 PERF_SAMPLE_BRANCH_KERNEL_SHIFT
= 1, /* kernel branches */
158 PERF_SAMPLE_BRANCH_HV_SHIFT
= 2, /* hypervisor branches */
160 PERF_SAMPLE_BRANCH_ANY_SHIFT
= 3, /* any branch types */
161 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
= 4, /* any call branch */
162 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
= 5, /* any return branch */
163 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
= 6, /* indirect calls */
164 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT
= 7, /* transaction aborts */
165 PERF_SAMPLE_BRANCH_IN_TX_SHIFT
= 8, /* in transaction */
166 PERF_SAMPLE_BRANCH_NO_TX_SHIFT
= 9, /* not in transaction */
167 PERF_SAMPLE_BRANCH_COND_SHIFT
= 10, /* conditional branches */
169 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
= 11, /* call/ret stack */
171 PERF_SAMPLE_BRANCH_MAX_SHIFT
/* non-ABI */
174 enum perf_branch_sample_type
{
175 PERF_SAMPLE_BRANCH_USER
= 1U << PERF_SAMPLE_BRANCH_USER_SHIFT
,
176 PERF_SAMPLE_BRANCH_KERNEL
= 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT
,
177 PERF_SAMPLE_BRANCH_HV
= 1U << PERF_SAMPLE_BRANCH_HV_SHIFT
,
179 PERF_SAMPLE_BRANCH_ANY
= 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT
,
180 PERF_SAMPLE_BRANCH_ANY_CALL
= 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
,
181 PERF_SAMPLE_BRANCH_ANY_RETURN
= 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
,
182 PERF_SAMPLE_BRANCH_IND_CALL
= 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
,
183 PERF_SAMPLE_BRANCH_ABORT_TX
= 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT
,
184 PERF_SAMPLE_BRANCH_IN_TX
= 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT
,
185 PERF_SAMPLE_BRANCH_NO_TX
= 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT
,
186 PERF_SAMPLE_BRANCH_COND
= 1U << PERF_SAMPLE_BRANCH_COND_SHIFT
,
188 PERF_SAMPLE_BRANCH_CALL_STACK
= 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
,
190 PERF_SAMPLE_BRANCH_MAX
= 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT
,
193 #define PERF_SAMPLE_BRANCH_PLM_ALL \
194 (PERF_SAMPLE_BRANCH_USER|\
195 PERF_SAMPLE_BRANCH_KERNEL|\
196 PERF_SAMPLE_BRANCH_HV)
199 * Values to determine ABI of the registers dump.
201 enum perf_sample_regs_abi
{
202 PERF_SAMPLE_REGS_ABI_NONE
= 0,
203 PERF_SAMPLE_REGS_ABI_32
= 1,
204 PERF_SAMPLE_REGS_ABI_64
= 2,
208 * Values for the memory transaction event qualifier, mostly for
209 * abort events. Multiple bits can be set.
212 PERF_TXN_ELISION
= (1 << 0), /* From elision */
213 PERF_TXN_TRANSACTION
= (1 << 1), /* From transaction */
214 PERF_TXN_SYNC
= (1 << 2), /* Instruction is related */
215 PERF_TXN_ASYNC
= (1 << 3), /* Instruction not related */
216 PERF_TXN_RETRY
= (1 << 4), /* Retry possible */
217 PERF_TXN_CONFLICT
= (1 << 5), /* Conflict abort */
218 PERF_TXN_CAPACITY_WRITE
= (1 << 6), /* Capacity write abort */
219 PERF_TXN_CAPACITY_READ
= (1 << 7), /* Capacity read abort */
221 PERF_TXN_MAX
= (1 << 8), /* non-ABI */
223 /* bits 32..63 are reserved for the abort code */
225 PERF_TXN_ABORT_MASK
= (0xffffffffULL
<< 32),
226 PERF_TXN_ABORT_SHIFT
= 32,
230 * The format of the data returned by read() on a perf event fd,
231 * as specified by attr.read_format:
233 * struct read_format {
235 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
236 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
237 * { u64 id; } && PERF_FORMAT_ID
238 * } && !PERF_FORMAT_GROUP
241 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
242 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
244 * { u64 id; } && PERF_FORMAT_ID
246 * } && PERF_FORMAT_GROUP
249 enum perf_event_read_format
{
250 PERF_FORMAT_TOTAL_TIME_ENABLED
= 1U << 0,
251 PERF_FORMAT_TOTAL_TIME_RUNNING
= 1U << 1,
252 PERF_FORMAT_ID
= 1U << 2,
253 PERF_FORMAT_GROUP
= 1U << 3,
255 PERF_FORMAT_MAX
= 1U << 4, /* non-ABI */
258 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
259 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
260 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
261 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
262 /* add: sample_stack_user */
263 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
266 * Hardware event_id to monitor via a performance monitoring event:
268 struct perf_event_attr
{
271 * Major type: hardware/software/tracepoint/etc.
276 * Size of the attr structure, for fwd/bwd compat.
281 * Type specific configuration information.
293 __u64 disabled
: 1, /* off by default */
294 inherit
: 1, /* children inherit it */
295 pinned
: 1, /* must always be on PMU */
296 exclusive
: 1, /* only group on PMU */
297 exclude_user
: 1, /* don't count user */
298 exclude_kernel
: 1, /* ditto kernel */
299 exclude_hv
: 1, /* ditto hypervisor */
300 exclude_idle
: 1, /* don't count when idle */
301 mmap
: 1, /* include mmap data */
302 comm
: 1, /* include comm data */
303 freq
: 1, /* use freq, not period */
304 inherit_stat
: 1, /* per task counts */
305 enable_on_exec
: 1, /* next exec enables */
306 task
: 1, /* trace fork/exit */
307 watermark
: 1, /* wakeup_watermark */
311 * 0 - SAMPLE_IP can have arbitrary skid
312 * 1 - SAMPLE_IP must have constant skid
313 * 2 - SAMPLE_IP requested to have 0 skid
314 * 3 - SAMPLE_IP must have 0 skid
316 * See also PERF_RECORD_MISC_EXACT_IP
318 precise_ip
: 2, /* skid constraint */
319 mmap_data
: 1, /* non-exec mmap data */
320 sample_id_all
: 1, /* sample_type all events */
322 exclude_host
: 1, /* don't count in host */
323 exclude_guest
: 1, /* don't count in guest */
325 exclude_callchain_kernel
: 1, /* exclude kernel callchains */
326 exclude_callchain_user
: 1, /* exclude user callchains */
327 mmap2
: 1, /* include mmap with inode data */
328 comm_exec
: 1, /* flag comm events that are due to an exec */
329 use_clockid
: 1, /* use @clockid for time fields */
333 __u32 wakeup_events
; /* wakeup every n events */
334 __u32 wakeup_watermark
; /* bytes before wakeup */
340 __u64 config1
; /* extension of config */
344 __u64 config2
; /* extension of config1 */
346 __u64 branch_sample_type
; /* enum perf_branch_sample_type */
349 * Defines set of user regs to dump on samples.
350 * See asm/perf_regs.h for details.
352 __u64 sample_regs_user
;
355 * Defines size of the user stack to dump on samples.
357 __u32 sample_stack_user
;
361 * Defines set of regs to dump for each sample
363 * - precise = 0: PMU interrupt
364 * - precise > 0: sampled instruction
366 * See asm/perf_regs.h for details.
368 __u64 sample_regs_intr
;
371 #define perf_flags(attr) (*(&(attr)->read_format + 1))
374 * Ioctls that can be done on a perf event fd:
376 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
377 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
378 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
379 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
380 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
381 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
382 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
383 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
384 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
386 enum perf_event_ioc_flags
{
387 PERF_IOC_FLAG_GROUP
= 1U << 0,
391 * Structure of the page that can be mapped via mmap
393 struct perf_event_mmap_page
{
394 __u32 version
; /* version number of this structure */
395 __u32 compat_version
; /* lowest version this is compat with */
398 * Bits needed to read the hw events in user-space.
400 * u32 seq, time_mult, time_shift, index, width;
401 * u64 count, enabled, running;
402 * u64 cyc, time_offset;
409 * enabled = pc->time_enabled;
410 * running = pc->time_running;
412 * if (pc->cap_usr_time && enabled != running) {
414 * time_offset = pc->time_offset;
415 * time_mult = pc->time_mult;
416 * time_shift = pc->time_shift;
420 * count = pc->offset;
421 * if (pc->cap_user_rdpmc && index) {
422 * width = pc->pmc_width;
423 * pmc = rdpmc(index - 1);
427 * } while (pc->lock != seq);
429 * NOTE: for obvious reason this only works on self-monitoring
432 __u32 lock
; /* seqlock for synchronization */
433 __u32 index
; /* hardware event identifier */
434 __s64 offset
; /* add to hardware event value */
435 __u64 time_enabled
; /* time event active */
436 __u64 time_running
; /* time event on cpu */
440 __u64 cap_bit0
: 1, /* Always 0, deprecated, see commit 860f085b74e9 */
441 cap_bit0_is_deprecated
: 1, /* Always 1, signals that bit 0 is zero */
443 cap_user_rdpmc
: 1, /* The RDPMC instruction can be used to read counts */
444 cap_user_time
: 1, /* The time_* fields are used */
445 cap_user_time_zero
: 1, /* The time_zero field is used */
451 * If cap_user_rdpmc this field provides the bit-width of the value
452 * read using the rdpmc() or equivalent instruction. This can be used
453 * to sign extend the result like:
455 * pmc <<= 64 - width;
456 * pmc >>= 64 - width; // signed shift right
462 * If cap_usr_time the below fields can be used to compute the time
463 * delta since time_enabled (in ns) using rdtsc or similar.
468 * quot = (cyc >> time_shift);
469 * rem = cyc & ((1 << time_shift) - 1);
470 * delta = time_offset + quot * time_mult +
471 * ((rem * time_mult) >> time_shift);
473 * Where time_offset,time_mult,time_shift and cyc are read in the
474 * seqcount loop described above. This delta can then be added to
475 * enabled and possible running (if index), improving the scaling:
481 * quot = count / running;
482 * rem = count % running;
483 * count = quot * enabled + (rem * enabled) / running;
489 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
490 * from sample timestamps.
492 * time = timestamp - time_zero;
493 * quot = time / time_mult;
494 * rem = time % time_mult;
495 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
499 * quot = cyc >> time_shift;
500 * rem = cyc & ((1 << time_shift) - 1);
501 * timestamp = time_zero + quot * time_mult +
502 * ((rem * time_mult) >> time_shift);
505 __u32 size
; /* Header size up to __reserved[] fields. */
508 * Hole for extension of the self monitor capabilities
511 __u8 __reserved
[118*8+4]; /* align to 1k. */
514 * Control data for the mmap() data buffer.
516 * User-space reading the @data_head value should issue an smp_rmb(),
517 * after reading this value.
519 * When the mapping is PROT_WRITE the @data_tail value should be
520 * written by userspace to reflect the last read data, after issueing
521 * an smp_mb() to separate the data read from the ->data_tail store.
522 * In this case the kernel will not over-write unread data.
524 * See perf_output_put_handle() for the data ordering.
526 * data_{offset,size} indicate the location and size of the perf record
527 * buffer within the mmapped area.
529 __u64 data_head
; /* head in the data section */
530 __u64 data_tail
; /* user-space written tail */
531 __u64 data_offset
; /* where the buffer starts */
532 __u64 data_size
; /* data buffer size */
535 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
536 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
537 #define PERF_RECORD_MISC_KERNEL (1 << 0)
538 #define PERF_RECORD_MISC_USER (2 << 0)
539 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
540 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
541 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
544 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
545 * different events so can reuse the same bit position.
547 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
548 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
550 * Indicates that the content of PERF_SAMPLE_IP points to
551 * the actual instruction that triggered the event. See also
552 * perf_event_attr::precise_ip.
554 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
556 * Reserve the last bit to indicate some extended misc field
558 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
560 struct perf_event_header
{
566 enum perf_event_type
{
569 * If perf_event_attr.sample_id_all is set then all event types will
570 * have the sample_type selected fields related to where/when
571 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
572 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
573 * just after the perf_event_header and the fields already present for
574 * the existing fields, i.e. at the end of the payload. That way a newer
575 * perf.data file will be supported by older perf tools, with these new
576 * optional fields being ignored.
579 * { u32 pid, tid; } && PERF_SAMPLE_TID
580 * { u64 time; } && PERF_SAMPLE_TIME
581 * { u64 id; } && PERF_SAMPLE_ID
582 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
583 * { u32 cpu, res; } && PERF_SAMPLE_CPU
584 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
585 * } && perf_event_attr::sample_id_all
587 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
588 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
589 * relative to header.size.
593 * The MMAP events record the PROT_EXEC mappings so that we can
594 * correlate userspace IPs to code. They have the following structure:
597 * struct perf_event_header header;
604 * struct sample_id sample_id;
607 PERF_RECORD_MMAP
= 1,
611 * struct perf_event_header header;
614 * struct sample_id sample_id;
617 PERF_RECORD_LOST
= 2,
621 * struct perf_event_header header;
625 * struct sample_id sample_id;
628 PERF_RECORD_COMM
= 3,
632 * struct perf_event_header header;
636 * struct sample_id sample_id;
639 PERF_RECORD_EXIT
= 4,
643 * struct perf_event_header header;
647 * struct sample_id sample_id;
650 PERF_RECORD_THROTTLE
= 5,
651 PERF_RECORD_UNTHROTTLE
= 6,
655 * struct perf_event_header header;
659 * struct sample_id sample_id;
662 PERF_RECORD_FORK
= 7,
666 * struct perf_event_header header;
669 * struct read_format values;
670 * struct sample_id sample_id;
673 PERF_RECORD_READ
= 8,
677 * struct perf_event_header header;
680 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
681 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
682 * # is fixed relative to header.
685 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
686 * { u64 ip; } && PERF_SAMPLE_IP
687 * { u32 pid, tid; } && PERF_SAMPLE_TID
688 * { u64 time; } && PERF_SAMPLE_TIME
689 * { u64 addr; } && PERF_SAMPLE_ADDR
690 * { u64 id; } && PERF_SAMPLE_ID
691 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
692 * { u32 cpu, res; } && PERF_SAMPLE_CPU
693 * { u64 period; } && PERF_SAMPLE_PERIOD
695 * { struct read_format values; } && PERF_SAMPLE_READ
698 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
701 * # The RAW record below is opaque data wrt the ABI
703 * # That is, the ABI doesn't make any promises wrt to
704 * # the stability of its content, it may vary depending
705 * # on event, hardware, kernel version and phase of
708 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
712 * char data[size];}&& PERF_SAMPLE_RAW
715 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
717 * { u64 abi; # enum perf_sample_regs_abi
718 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
722 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
724 * { u64 weight; } && PERF_SAMPLE_WEIGHT
725 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
726 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
727 * { u64 abi; # enum perf_sample_regs_abi
728 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
731 PERF_RECORD_SAMPLE
= 9,
734 * The MMAP2 records are an augmented version of MMAP, they add
735 * maj, min, ino numbers to be used to uniquely identify each mapping
738 * struct perf_event_header header;
747 * u64 ino_generation;
750 * struct sample_id sample_id;
753 PERF_RECORD_MMAP2
= 10,
755 PERF_RECORD_MAX
, /* non-ABI */
758 #define PERF_MAX_STACK_DEPTH 127
760 enum perf_callchain_context
{
761 PERF_CONTEXT_HV
= (__u64
)-32,
762 PERF_CONTEXT_KERNEL
= (__u64
)-128,
763 PERF_CONTEXT_USER
= (__u64
)-512,
765 PERF_CONTEXT_GUEST
= (__u64
)-2048,
766 PERF_CONTEXT_GUEST_KERNEL
= (__u64
)-2176,
767 PERF_CONTEXT_GUEST_USER
= (__u64
)-2560,
769 PERF_CONTEXT_MAX
= (__u64
)-4095,
772 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
773 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
774 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
775 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
777 union perf_mem_data_src
{
780 __u64 mem_op
:5, /* type of opcode */
781 mem_lvl
:14, /* memory hierarchy level */
782 mem_snoop
:5, /* snoop mode */
783 mem_lock
:2, /* lock instr */
784 mem_dtlb
:7, /* tlb access */
789 /* type of opcode (load/store/prefetch,code) */
790 #define PERF_MEM_OP_NA 0x01 /* not available */
791 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
792 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
793 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
794 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
795 #define PERF_MEM_OP_SHIFT 0
797 /* memory hierarchy (memory level, hit or miss) */
798 #define PERF_MEM_LVL_NA 0x01 /* not available */
799 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
800 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
801 #define PERF_MEM_LVL_L1 0x08 /* L1 */
802 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
803 #define PERF_MEM_LVL_L2 0x20 /* L2 */
804 #define PERF_MEM_LVL_L3 0x40 /* L3 */
805 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
806 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
807 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
808 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
809 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
810 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
811 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
812 #define PERF_MEM_LVL_SHIFT 5
815 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
816 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
817 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
818 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
819 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
820 #define PERF_MEM_SNOOP_SHIFT 19
822 /* locked instruction */
823 #define PERF_MEM_LOCK_NA 0x01 /* not available */
824 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
825 #define PERF_MEM_LOCK_SHIFT 24
828 #define PERF_MEM_TLB_NA 0x01 /* not available */
829 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
830 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
831 #define PERF_MEM_TLB_L1 0x08 /* L1 */
832 #define PERF_MEM_TLB_L2 0x10 /* L2 */
833 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
834 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
835 #define PERF_MEM_TLB_SHIFT 26
837 #define PERF_MEM_S(a, s) \
838 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
841 * single taken branch record layout:
843 * from: source instruction (may not always be a branch insn)
845 * mispred: branch target was mispredicted
846 * predicted: branch target was predicted
848 * support for mispred, predicted is optional. In case it
849 * is not supported mispred = predicted = 0.
851 * in_tx: running in a hardware transaction
852 * abort: aborting a hardware transaction
854 struct perf_branch_entry
{
857 __u64 mispred
:1, /* target mispredicted */
858 predicted
:1,/* target predicted */
859 in_tx
:1, /* in transaction */
860 abort
:1, /* transaction abort */
864 #endif /* _UAPI_LINUX_PERF_EVENT_H */