include/uapi/linux/v4l2-dv-timings.h

   1 /*
   2  * V4L2 DV timings header.
   3  *
   4  * Copyright (C) 2012  Hans Verkuil <hans.verkuil@cisco.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  */
  20
  21 #ifndef _V4L2_DV_TIMINGS_H
  22 #define _V4L2_DV_TIMINGS_H
  23
  24 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
  25 /* Sadly gcc versions older than 4.6 have a bug in how they initialize
  26    anonymous unions where they require additional curly brackets.
  27    This violates the C1x standard. This workaround adds the curly brackets
  28    if needed. */
  29 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  30         { .bt = { _width , ## args } }
  31 #else
  32 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  33         .bt = { _width , ## args }
  34 #endif
  35
  36 /* CEA-861-E timings (i.e. standard HDTV timings) */
  37
  38 #define V4L2_DV_BT_CEA_640X480P59_94 { \
  39         .type = V4L2_DV_BT_656_1120, \
  40         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  41                 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
  42                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
  43 }
  44
  45 /* Note: these are the nominal timings, for HDMI links this format is typically
  46  * double-clocked to meet the minimum pixelclock requirements.  */
  47 #define V4L2_DV_BT_CEA_720X480I59_94 { \
  48         .type = V4L2_DV_BT_656_1120, \
  49         V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
  50                 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
  51                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
  52 }
  53
  54 #define V4L2_DV_BT_CEA_720X480P59_94 { \
  55         .type = V4L2_DV_BT_656_1120, \
  56         V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
  57                 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
  58                 V4L2_DV_BT_STD_CEA861, 0) \
  59 }
  60
  61 /* Note: these are the nominal timings, for HDMI links this format is typically
  62  * double-clocked to meet the minimum pixelclock requirements.  */
  63 #define V4L2_DV_BT_CEA_720X576I50 { \
  64         .type = V4L2_DV_BT_656_1120, \
  65         V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
  66                 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
  67                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
  68 }
  69
  70 #define V4L2_DV_BT_CEA_720X576P50 { \
  71         .type = V4L2_DV_BT_656_1120, \
  72         V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
  73                 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
  74                 V4L2_DV_BT_STD_CEA861, 0) \
  75 }
  76
  77 #define V4L2_DV_BT_CEA_1280X720P24 { \
  78         .type = V4L2_DV_BT_656_1120, \
  79         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  80                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  81                 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  82                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  83                 V4L2_DV_FL_CAN_REDUCE_FPS) \
  84 }
  85
  86 #define V4L2_DV_BT_CEA_1280X720P25 { \
  87         .type = V4L2_DV_BT_656_1120, \
  88         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  89                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  90                 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
  91                 V4L2_DV_BT_STD_CEA861, 0) \
  92 }
  93
  94 #define V4L2_DV_BT_CEA_1280X720P30 { \
  95         .type = V4L2_DV_BT_656_1120, \
  96         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  97                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  98                 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  99                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 100 }
 101
 102 #define V4L2_DV_BT_CEA_1280X720P50 { \
 103         .type = V4L2_DV_BT_656_1120, \
 104         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
 105                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 106                 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
 107                 V4L2_DV_BT_STD_CEA861, 0) \
 108 }
 109
 110 #define V4L2_DV_BT_CEA_1280X720P60 { \
 111         .type = V4L2_DV_BT_656_1120, \
 112         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
 113                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 114                 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
 115                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 116 }
 117
 118 #define V4L2_DV_BT_CEA_1920X1080P24 { \
 119         .type = V4L2_DV_BT_656_1120, \
 120         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 121                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 122                 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
 123                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 124 }
 125
 126 #define V4L2_DV_BT_CEA_1920X1080P25 { \
 127         .type = V4L2_DV_BT_656_1120, \
 128         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 129                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 130                 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
 131                 V4L2_DV_BT_STD_CEA861, 0) \
 132 }
 133
 134 #define V4L2_DV_BT_CEA_1920X1080P30 { \
 135         .type = V4L2_DV_BT_656_1120, \
 136         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 137                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 138                 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
 139                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 140 }
 141
 142 #define V4L2_DV_BT_CEA_1920X1080I50 { \
 143         .type = V4L2_DV_BT_656_1120, \
 144         V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
 145                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 146                 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
 147                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
 148 }
 149
 150 #define V4L2_DV_BT_CEA_1920X1080P50 { \
 151         .type = V4L2_DV_BT_656_1120, \
 152         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 153                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 154                 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
 155                 V4L2_DV_BT_STD_CEA861, 0) \
 156 }
 157
 158 #define V4L2_DV_BT_CEA_1920X1080I60 { \
 159         .type = V4L2_DV_BT_656_1120, \
 160         V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
 161                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 162                 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
 163                 V4L2_DV_BT_STD_CEA861, \
 164                 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
 165 }
 166
 167 #define V4L2_DV_BT_CEA_1920X1080P60 { \
 168         .type = V4L2_DV_BT_656_1120, \
 169         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 170                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 171                 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
 172                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
 173                 V4L2_DV_FL_CAN_REDUCE_FPS) \
 174 }
 175
 176
 177 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
 178
 179 #define V4L2_DV_BT_DMT_640X350P85 { \
 180         .type = V4L2_DV_BT_656_1120, \
 181         V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
 182                 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
 183                 V4L2_DV_BT_STD_DMT, 0) \
 184 }
 185
 186 #define V4L2_DV_BT_DMT_640X400P85 { \
 187         .type = V4L2_DV_BT_656_1120, \
 188         V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
 189                 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
 190                 V4L2_DV_BT_STD_DMT, 0) \
 191 }
 192
 193 #define V4L2_DV_BT_DMT_720X400P85 { \
 194         .type = V4L2_DV_BT_656_1120, \
 195         V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
 196                 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
 197                 V4L2_DV_BT_STD_DMT, 0) \
 198 }
 199
 200 /* VGA resolutions */
 201 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
 202
 203 #define V4L2_DV_BT_DMT_640X480P72 { \
 204         .type = V4L2_DV_BT_656_1120, \
 205         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 206                 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
 207                 V4L2_DV_BT_STD_DMT, 0) \
 208 }
 209
 210 #define V4L2_DV_BT_DMT_640X480P75 { \
 211         .type = V4L2_DV_BT_656_1120, \
 212         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 213                 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
 214                 V4L2_DV_BT_STD_DMT, 0) \
 215 }
 216
 217 #define V4L2_DV_BT_DMT_640X480P85 { \
 218         .type = V4L2_DV_BT_656_1120, \
 219         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 220                 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
 221                 V4L2_DV_BT_STD_DMT, 0) \
 222 }
 223
 224 /* SVGA resolutions */
 225 #define V4L2_DV_BT_DMT_800X600P56 { \
 226         .type = V4L2_DV_BT_656_1120, \
 227         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 228                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 229                 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
 230                 V4L2_DV_BT_STD_DMT, 0) \
 231 }
 232
 233 #define V4L2_DV_BT_DMT_800X600P60 { \
 234         .type = V4L2_DV_BT_656_1120, \
 235         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 236                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 237                 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
 238                 V4L2_DV_BT_STD_DMT, 0) \
 239 }
 240
 241 #define V4L2_DV_BT_DMT_800X600P72 { \
 242         .type = V4L2_DV_BT_656_1120, \
 243         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 244                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 245                 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
 246                 V4L2_DV_BT_STD_DMT, 0) \
 247 }
 248
 249 #define V4L2_DV_BT_DMT_800X600P75 { \
 250         .type = V4L2_DV_BT_656_1120, \
 251         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 252                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 253                 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
 254                 V4L2_DV_BT_STD_DMT, 0) \
 255 }
 256
 257 #define V4L2_DV_BT_DMT_800X600P85 { \
 258         .type = V4L2_DV_BT_656_1120, \
 259         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 260                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 261                 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
 262                 V4L2_DV_BT_STD_DMT, 0) \
 263 }
 264
 265 #define V4L2_DV_BT_DMT_800X600P120_RB { \
 266         .type = V4L2_DV_BT_656_1120, \
 267         V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
 268                 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
 269                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 270                 V4L2_DV_FL_REDUCED_BLANKING) \
 271 }
 272
 273 #define V4L2_DV_BT_DMT_848X480P60 { \
 274         .type = V4L2_DV_BT_656_1120, \
 275         V4L2_INIT_BT_TIMINGS(848, 480, 0, \
 276                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 277                 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
 278                 V4L2_DV_BT_STD_DMT, 0) \
 279 }
 280
 281 #define V4L2_DV_BT_DMT_1024X768I43 { \
 282         .type = V4L2_DV_BT_656_1120, \
 283         V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
 284                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 285                 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
 286                 V4L2_DV_BT_STD_DMT, 0) \
 287 }
 288
 289 /* XGA resolutions */
 290 #define V4L2_DV_BT_DMT_1024X768P60 { \
 291         .type = V4L2_DV_BT_656_1120, \
 292         V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
 293                 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
 294                 V4L2_DV_BT_STD_DMT, 0) \
 295 }
 296
 297 #define V4L2_DV_BT_DMT_1024X768P70 { \
 298         .type = V4L2_DV_BT_656_1120, \
 299         V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
 300                 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
 301                 V4L2_DV_BT_STD_DMT, 0) \
 302 }
 303
 304 #define V4L2_DV_BT_DMT_1024X768P75 { \
 305         .type = V4L2_DV_BT_656_1120, \
 306         V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
 307                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 308                 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
 309                 V4L2_DV_BT_STD_DMT, 0) \
 310 }
 311
 312 #define V4L2_DV_BT_DMT_1024X768P85 { \
 313         .type = V4L2_DV_BT_656_1120, \
 314         V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
 315                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 316                 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
 317                 V4L2_DV_BT_STD_DMT, 0) \
 318 }
 319
 320 #define V4L2_DV_BT_DMT_1024X768P120_RB { \
 321         .type = V4L2_DV_BT_656_1120, \
 322         V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 323                 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
 324                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 325                 V4L2_DV_FL_REDUCED_BLANKING) \
 326 }
 327
 328 /* XGA+ resolution */
 329 #define V4L2_DV_BT_DMT_1152X864P75 { \
 330         .type = V4L2_DV_BT_656_1120, \
 331         V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
 332                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 333                 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
 334                 V4L2_DV_BT_STD_DMT, 0) \
 335 }
 336
 337 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
 338
 339 /* WXGA resolutions */
 340 #define V4L2_DV_BT_DMT_1280X768P60_RB { \
 341         .type = V4L2_DV_BT_656_1120, \
 342         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 343                 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
 344                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 345                 V4L2_DV_FL_REDUCED_BLANKING) \
 346 }
 347
 348 #define V4L2_DV_BT_DMT_1280X768P60 { \
 349         .type = V4L2_DV_BT_656_1120, \
 350         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 351                 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
 352                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 353 }
 354
 355 #define V4L2_DV_BT_DMT_1280X768P75 { \
 356         .type = V4L2_DV_BT_656_1120, \
 357         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 358                 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
 359                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 360 }
 361
 362 #define V4L2_DV_BT_DMT_1280X768P85 { \
 363         .type = V4L2_DV_BT_656_1120, \
 364         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 365                 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
 366                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 367 }
 368
 369 #define V4L2_DV_BT_DMT_1280X768P120_RB { \
 370         .type = V4L2_DV_BT_656_1120, \
 371         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 372                 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
 373                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 374                 V4L2_DV_FL_REDUCED_BLANKING) \
 375 }
 376
 377 #define V4L2_DV_BT_DMT_1280X800P60_RB { \
 378         .type = V4L2_DV_BT_656_1120, \
 379         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
 380                 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
 381                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 382                 V4L2_DV_FL_REDUCED_BLANKING) \
 383 }
 384
 385 #define V4L2_DV_BT_DMT_1280X800P60 { \
 386         .type = V4L2_DV_BT_656_1120, \
 387         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 388                 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
 389                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 390 }
 391
 392 #define V4L2_DV_BT_DMT_1280X800P75 { \
 393         .type = V4L2_DV_BT_656_1120, \
 394         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 395                 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
 396                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 397 }
 398
 399 #define V4L2_DV_BT_DMT_1280X800P85 { \
 400         .type = V4L2_DV_BT_656_1120, \
 401         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 402                 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
 403                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 404 }
 405
 406 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
 407         .type = V4L2_DV_BT_656_1120, \
 408         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
 409                 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
 410                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 411                 V4L2_DV_FL_REDUCED_BLANKING) \
 412 }
 413
 414 #define V4L2_DV_BT_DMT_1280X960P60 { \
 415         .type = V4L2_DV_BT_656_1120, \
 416         V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
 417                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 418                 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
 419                 V4L2_DV_BT_STD_DMT, 0) \
 420 }
 421
 422 #define V4L2_DV_BT_DMT_1280X960P85 { \
 423         .type = V4L2_DV_BT_656_1120, \
 424         V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
 425                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 426                 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
 427                 V4L2_DV_BT_STD_DMT, 0) \
 428 }
 429
 430 #define V4L2_DV_BT_DMT_1280X960P120_RB { \
 431         .type = V4L2_DV_BT_656_1120, \
 432         V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
 433                 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
 434                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 435                 V4L2_DV_FL_REDUCED_BLANKING) \
 436 }
 437
 438 /* SXGA resolutions */
 439 #define V4L2_DV_BT_DMT_1280X1024P60 { \
 440         .type = V4L2_DV_BT_656_1120, \
 441         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 442                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 443                 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
 444                 V4L2_DV_BT_STD_DMT, 0) \
 445 }
 446
 447 #define V4L2_DV_BT_DMT_1280X1024P75 { \
 448         .type = V4L2_DV_BT_656_1120, \
 449         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 450                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 451                 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
 452                 V4L2_DV_BT_STD_DMT, 0) \
 453 }
 454
 455 #define V4L2_DV_BT_DMT_1280X1024P85 { \
 456         .type = V4L2_DV_BT_656_1120, \
 457         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 458                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 459                 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
 460                 V4L2_DV_BT_STD_DMT, 0) \
 461 }
 462
 463 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
 464         .type = V4L2_DV_BT_656_1120, \
 465         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
 466                 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
 467                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 468                 V4L2_DV_FL_REDUCED_BLANKING) \
 469 }
 470
 471 #define V4L2_DV_BT_DMT_1360X768P60 { \
 472         .type = V4L2_DV_BT_656_1120, \
 473         V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
 474                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 475                 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
 476                 V4L2_DV_BT_STD_DMT, 0) \
 477 }
 478
 479 #define V4L2_DV_BT_DMT_1360X768P120_RB { \
 480         .type = V4L2_DV_BT_656_1120, \
 481         V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 482                 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
 483                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 484                 V4L2_DV_FL_REDUCED_BLANKING) \
 485 }
 486
 487 #define V4L2_DV_BT_DMT_1366X768P60 { \
 488         .type = V4L2_DV_BT_656_1120, \
 489         V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
 490                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 491                 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
 492                 V4L2_DV_BT_STD_DMT, 0) \
 493 }
 494
 495 #define V4L2_DV_BT_DMT_1366X768P60_RB { \
 496         .type = V4L2_DV_BT_656_1120, \
 497         V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
 498                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 499                 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
 500                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 501 }
 502
 503 /* SXGA+ resolutions */
 504 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
 505         .type = V4L2_DV_BT_656_1120, \
 506         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 507                 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
 508                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 509                 V4L2_DV_FL_REDUCED_BLANKING) \
 510 }
 511
 512 #define V4L2_DV_BT_DMT_1400X1050P60 { \
 513         .type = V4L2_DV_BT_656_1120, \
 514         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 515                 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
 516                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 517 }
 518
 519 #define V4L2_DV_BT_DMT_1400X1050P75 { \
 520         .type = V4L2_DV_BT_656_1120, \
 521         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 522                 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
 523                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 524 }
 525
 526 #define V4L2_DV_BT_DMT_1400X1050P85 { \
 527         .type = V4L2_DV_BT_656_1120, \
 528         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 529                 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
 530                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 531 }
 532
 533 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
 534         .type = V4L2_DV_BT_656_1120, \
 535         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 536                 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
 537                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 538                 V4L2_DV_FL_REDUCED_BLANKING) \
 539 }
 540
 541 /* WXGA+ resolutions */
 542 #define V4L2_DV_BT_DMT_1440X900P60_RB { \
 543         .type = V4L2_DV_BT_656_1120, \
 544         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
 545                 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
 546                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 547                 V4L2_DV_FL_REDUCED_BLANKING) \
 548 }
 549
 550 #define V4L2_DV_BT_DMT_1440X900P60 { \
 551         .type = V4L2_DV_BT_656_1120, \
 552         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 553                 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
 554                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 555 }
 556
 557 #define V4L2_DV_BT_DMT_1440X900P75 { \
 558         .type = V4L2_DV_BT_656_1120, \
 559         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 560                 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
 561                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 562 }
 563
 564 #define V4L2_DV_BT_DMT_1440X900P85 { \
 565         .type = V4L2_DV_BT_656_1120, \
 566         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 567                 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
 568                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 569 }
 570
 571 #define V4L2_DV_BT_DMT_1440X900P120_RB { \
 572         .type = V4L2_DV_BT_656_1120, \
 573         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
 574                 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
 575                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 576                 V4L2_DV_FL_REDUCED_BLANKING) \
 577 }
 578
 579 #define V4L2_DV_BT_DMT_1600X900P60_RB { \
 580         .type = V4L2_DV_BT_656_1120, \
 581         V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
 582                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 583                 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
 584                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 585 }
 586
 587 /* UXGA resolutions */
 588 #define V4L2_DV_BT_DMT_1600X1200P60 { \
 589         .type = V4L2_DV_BT_656_1120, \
 590         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 591                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 592                 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 593                 V4L2_DV_BT_STD_DMT, 0) \
 594 }
 595
 596 #define V4L2_DV_BT_DMT_1600X1200P65 { \
 597         .type = V4L2_DV_BT_656_1120, \
 598         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 599                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 600                 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 601                 V4L2_DV_BT_STD_DMT, 0) \
 602 }
 603
 604 #define V4L2_DV_BT_DMT_1600X1200P70 { \
 605         .type = V4L2_DV_BT_656_1120, \
 606         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 607                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 608                 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 609                 V4L2_DV_BT_STD_DMT, 0) \
 610 }
 611
 612 #define V4L2_DV_BT_DMT_1600X1200P75 { \
 613         .type = V4L2_DV_BT_656_1120, \
 614         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 615                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 616                 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 617                 V4L2_DV_BT_STD_DMT, 0) \
 618 }
 619
 620 #define V4L2_DV_BT_DMT_1600X1200P85 { \
 621         .type = V4L2_DV_BT_656_1120, \
 622         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 623                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 624                 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 625                 V4L2_DV_BT_STD_DMT, 0) \
 626 }
 627
 628 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
 629         .type = V4L2_DV_BT_656_1120, \
 630         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 631                 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
 632                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 633                 V4L2_DV_FL_REDUCED_BLANKING) \
 634 }
 635
 636 /* WSXGA+ resolutions */
 637 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
 638         .type = V4L2_DV_BT_656_1120, \
 639         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 640                 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
 641                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 642                 V4L2_DV_FL_REDUCED_BLANKING) \
 643 }
 644
 645 #define V4L2_DV_BT_DMT_1680X1050P60 { \
 646         .type = V4L2_DV_BT_656_1120, \
 647         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 648                 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
 649                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 650 }
 651
 652 #define V4L2_DV_BT_DMT_1680X1050P75 { \
 653         .type = V4L2_DV_BT_656_1120, \
 654         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 655                 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
 656                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 657 }
 658
 659 #define V4L2_DV_BT_DMT_1680X1050P85 { \
 660         .type = V4L2_DV_BT_656_1120, \
 661         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 662                 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
 663                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 664 }
 665
 666 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
 667         .type = V4L2_DV_BT_656_1120, \
 668         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 669                 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
 670                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 671                 V4L2_DV_FL_REDUCED_BLANKING) \
 672 }
 673
 674 #define V4L2_DV_BT_DMT_1792X1344P60 { \
 675         .type = V4L2_DV_BT_656_1120, \
 676         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
 677                 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
 678                 V4L2_DV_BT_STD_DMT, 0) \
 679 }
 680
 681 #define V4L2_DV_BT_DMT_1792X1344P75 { \
 682         .type = V4L2_DV_BT_656_1120, \
 683         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
 684                 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
 685                 V4L2_DV_BT_STD_DMT, 0) \
 686 }
 687
 688 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
 689         .type = V4L2_DV_BT_656_1120, \
 690         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
 691                 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
 692                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 693                 V4L2_DV_FL_REDUCED_BLANKING) \
 694 }
 695
 696 #define V4L2_DV_BT_DMT_1856X1392P60 { \
 697         .type = V4L2_DV_BT_656_1120, \
 698         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
 699                 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
 700                 V4L2_DV_BT_STD_DMT, 0) \
 701 }
 702
 703 #define V4L2_DV_BT_DMT_1856X1392P75 { \
 704         .type = V4L2_DV_BT_656_1120, \
 705         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
 706                 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
 707                 V4L2_DV_BT_STD_DMT, 0) \
 708 }
 709
 710 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
 711         .type = V4L2_DV_BT_656_1120, \
 712         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
 713                 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
 714                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 715                 V4L2_DV_FL_REDUCED_BLANKING) \
 716 }
 717
 718 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
 719
 720 /* WUXGA resolutions */
 721 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
 722         .type = V4L2_DV_BT_656_1120, \
 723         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 724                 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
 725                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 726                 V4L2_DV_FL_REDUCED_BLANKING) \
 727 }
 728
 729 #define V4L2_DV_BT_DMT_1920X1200P60 { \
 730         .type = V4L2_DV_BT_656_1120, \
 731         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 732                 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
 733                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 734 }
 735
 736 #define V4L2_DV_BT_DMT_1920X1200P75 { \
 737         .type = V4L2_DV_BT_656_1120, \
 738         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 739                 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
 740                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 741 }
 742
 743 #define V4L2_DV_BT_DMT_1920X1200P85 { \
 744         .type = V4L2_DV_BT_656_1120, \
 745         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 746                 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
 747                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 748 }
 749
 750 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
 751         .type = V4L2_DV_BT_656_1120, \
 752         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 753                 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
 754                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 755                 V4L2_DV_FL_REDUCED_BLANKING) \
 756 }
 757
 758 #define V4L2_DV_BT_DMT_1920X1440P60 { \
 759         .type = V4L2_DV_BT_656_1120, \
 760         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
 761                 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
 762                 V4L2_DV_BT_STD_DMT, 0) \
 763 }
 764
 765 #define V4L2_DV_BT_DMT_1920X1440P75 { \
 766         .type = V4L2_DV_BT_656_1120, \
 767         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
 768                 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
 769                 V4L2_DV_BT_STD_DMT, 0) \
 770 }
 771
 772 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
 773         .type = V4L2_DV_BT_656_1120, \
 774         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
 775                 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
 776                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 777                 V4L2_DV_FL_REDUCED_BLANKING) \
 778 }
 779
 780 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
 781         .type = V4L2_DV_BT_656_1120, \
 782         V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
 783                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 784                 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
 785                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 786 }
 787
 788 /* WQXGA resolutions */
 789 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
 790         .type = V4L2_DV_BT_656_1120, \
 791         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
 792                 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
 793                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 794                 V4L2_DV_FL_REDUCED_BLANKING) \
 795 }
 796
 797 #define V4L2_DV_BT_DMT_2560X1600P60 { \
 798         .type = V4L2_DV_BT_656_1120, \
 799         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 800                 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
 801                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 802 }
 803
 804 #define V4L2_DV_BT_DMT_2560X1600P75 { \
 805         .type = V4L2_DV_BT_656_1120, \
 806         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 807                 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
 808                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 809 }
 810
 811 #define V4L2_DV_BT_DMT_2560X1600P85 { \
 812         .type = V4L2_DV_BT_656_1120, \
 813         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 814                 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
 815                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 816 }
 817
 818 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
 819         .type = V4L2_DV_BT_656_1120, \
 820         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
 821                 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
 822                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 823                 V4L2_DV_FL_REDUCED_BLANKING) \
 824 }
 825
 826 #endif