2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
26 #define DISPC_IRQ_FRAMEDONE (1 << 0)
27 #define DISPC_IRQ_VSYNC (1 << 1)
28 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
29 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
30 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
31 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
32 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
33 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
34 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
35 #define DISPC_IRQ_OCP_ERR (1 << 9)
36 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
37 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
38 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
39 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
40 #define DISPC_IRQ_SYNC_LOST (1 << 14)
41 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
42 #define DISPC_IRQ_WAKEUP (1 << 16)
43 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
44 #define DISPC_IRQ_VSYNC2 (1 << 18)
45 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
46 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
47 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
48 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
49 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
50 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
51 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
52 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
53 #define DISPC_IRQ_VSYNC3 (1 << 28)
54 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
55 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
57 struct omap_dss_device
;
58 struct omap_overlay_manager
;
59 struct dss_lcd_mgr_config
;
60 struct snd_aes_iec958
;
61 struct snd_cea_861_aud_if
;
63 enum omap_display_type
{
64 OMAP_DISPLAY_TYPE_NONE
= 0,
65 OMAP_DISPLAY_TYPE_DPI
= 1 << 0,
66 OMAP_DISPLAY_TYPE_DBI
= 1 << 1,
67 OMAP_DISPLAY_TYPE_SDI
= 1 << 2,
68 OMAP_DISPLAY_TYPE_DSI
= 1 << 3,
69 OMAP_DISPLAY_TYPE_VENC
= 1 << 4,
70 OMAP_DISPLAY_TYPE_HDMI
= 1 << 5,
82 OMAP_DSS_CHANNEL_LCD
= 0,
83 OMAP_DSS_CHANNEL_DIGIT
= 1,
84 OMAP_DSS_CHANNEL_LCD2
= 2,
85 OMAP_DSS_CHANNEL_LCD3
= 3,
88 enum omap_color_mode
{
89 OMAP_DSS_COLOR_CLUT1
= 1 << 0, /* BITMAP 1 */
90 OMAP_DSS_COLOR_CLUT2
= 1 << 1, /* BITMAP 2 */
91 OMAP_DSS_COLOR_CLUT4
= 1 << 2, /* BITMAP 4 */
92 OMAP_DSS_COLOR_CLUT8
= 1 << 3, /* BITMAP 8 */
93 OMAP_DSS_COLOR_RGB12U
= 1 << 4, /* RGB12, 16-bit container */
94 OMAP_DSS_COLOR_ARGB16
= 1 << 5, /* ARGB16 */
95 OMAP_DSS_COLOR_RGB16
= 1 << 6, /* RGB16 */
96 OMAP_DSS_COLOR_RGB24U
= 1 << 7, /* RGB24, 32-bit container */
97 OMAP_DSS_COLOR_RGB24P
= 1 << 8, /* RGB24, 24-bit container */
98 OMAP_DSS_COLOR_YUV2
= 1 << 9, /* YUV2 4:2:2 co-sited */
99 OMAP_DSS_COLOR_UYVY
= 1 << 10, /* UYVY 4:2:2 co-sited */
100 OMAP_DSS_COLOR_ARGB32
= 1 << 11, /* ARGB32 */
101 OMAP_DSS_COLOR_RGBA32
= 1 << 12, /* RGBA32 */
102 OMAP_DSS_COLOR_RGBX32
= 1 << 13, /* RGBx32 */
103 OMAP_DSS_COLOR_NV12
= 1 << 14, /* NV12 format: YUV 4:2:0 */
104 OMAP_DSS_COLOR_RGBA16
= 1 << 15, /* RGBA16 - 4444 */
105 OMAP_DSS_COLOR_RGBX16
= 1 << 16, /* RGBx16 - 4444 */
106 OMAP_DSS_COLOR_ARGB16_1555
= 1 << 17, /* ARGB16 - 1555 */
107 OMAP_DSS_COLOR_XRGB16_1555
= 1 << 18, /* xRGB16 - 1555 */
110 enum omap_dss_load_mode
{
111 OMAP_DSS_LOAD_CLUT_AND_FRAME
= 0,
112 OMAP_DSS_LOAD_CLUT_ONLY
= 1,
113 OMAP_DSS_LOAD_FRAME_ONLY
= 2,
114 OMAP_DSS_LOAD_CLUT_ONCE_FRAME
= 3,
117 enum omap_dss_trans_key_type
{
118 OMAP_DSS_COLOR_KEY_GFX_DST
= 0,
119 OMAP_DSS_COLOR_KEY_VID_SRC
= 1,
122 enum omap_rfbi_te_mode
{
123 OMAP_DSS_RFBI_TE_MODE_1
= 1,
124 OMAP_DSS_RFBI_TE_MODE_2
= 2,
127 enum omap_dss_signal_level
{
128 OMAPDSS_SIG_ACTIVE_HIGH
= 0,
129 OMAPDSS_SIG_ACTIVE_LOW
= 1,
132 enum omap_dss_signal_edge
{
133 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES
,
134 OMAPDSS_DRIVE_SIG_RISING_EDGE
,
135 OMAPDSS_DRIVE_SIG_FALLING_EDGE
,
138 enum omap_dss_venc_type
{
139 OMAP_DSS_VENC_TYPE_COMPOSITE
,
140 OMAP_DSS_VENC_TYPE_SVIDEO
,
143 enum omap_dss_dsi_pixel_format
{
144 OMAP_DSS_DSI_FMT_RGB888
,
145 OMAP_DSS_DSI_FMT_RGB666
,
146 OMAP_DSS_DSI_FMT_RGB666_PACKED
,
147 OMAP_DSS_DSI_FMT_RGB565
,
150 enum omap_dss_dsi_mode
{
151 OMAP_DSS_DSI_CMD_MODE
= 0,
152 OMAP_DSS_DSI_VIDEO_MODE
,
155 enum omap_display_caps
{
156 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
= 1 << 0,
157 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
= 1 << 1,
160 enum omap_dss_display_state
{
161 OMAP_DSS_DISPLAY_DISABLED
= 0,
162 OMAP_DSS_DISPLAY_ACTIVE
,
165 enum omap_dss_audio_state
{
166 OMAP_DSS_AUDIO_DISABLED
= 0,
167 OMAP_DSS_AUDIO_ENABLED
,
168 OMAP_DSS_AUDIO_CONFIGURED
,
169 OMAP_DSS_AUDIO_PLAYING
,
172 enum omap_dss_rotation_type
{
173 OMAP_DSS_ROT_DMA
= 1 << 0,
174 OMAP_DSS_ROT_VRFB
= 1 << 1,
175 OMAP_DSS_ROT_TILER
= 1 << 2,
178 /* clockwise rotation angle */
179 enum omap_dss_rotation_angle
{
182 OMAP_DSS_ROT_180
= 2,
183 OMAP_DSS_ROT_270
= 3,
186 enum omap_overlay_caps
{
187 OMAP_DSS_OVL_CAP_SCALE
= 1 << 0,
188 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA
= 1 << 1,
189 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
= 1 << 2,
190 OMAP_DSS_OVL_CAP_ZORDER
= 1 << 3,
191 OMAP_DSS_OVL_CAP_POS
= 1 << 4,
192 OMAP_DSS_OVL_CAP_REPLICATION
= 1 << 5,
195 enum omap_overlay_manager_caps
{
196 OMAP_DSS_DUMMY_VALUE
, /* add a dummy value to prevent compiler error */
199 enum omap_dss_clk_source
{
200 OMAP_DSS_CLK_SRC_FCK
= 0, /* OMAP2/3: DSS1_ALWON_FCLK
202 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
, /* OMAP3: DSI1_PLL_FCLK
203 * OMAP4: PLL1_CLK1 */
204 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
, /* OMAP3: DSI2_PLL_FCLK
205 * OMAP4: PLL1_CLK2 */
206 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
, /* OMAP4: PLL2_CLK1 */
207 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
, /* OMAP4: PLL2_CLK2 */
210 enum omap_hdmi_flags
{
211 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP
= 1 << 0,
214 enum omap_dss_output_id
{
215 OMAP_DSS_OUTPUT_DPI
= 1 << 0,
216 OMAP_DSS_OUTPUT_DBI
= 1 << 1,
217 OMAP_DSS_OUTPUT_SDI
= 1 << 2,
218 OMAP_DSS_OUTPUT_DSI1
= 1 << 3,
219 OMAP_DSS_OUTPUT_DSI2
= 1 << 4,
220 OMAP_DSS_OUTPUT_VENC
= 1 << 5,
221 OMAP_DSS_OUTPUT_HDMI
= 1 << 6,
226 struct rfbi_timings
{
240 u32 tim
[5]; /* set by rfbi_convert_timings() */
245 void omap_rfbi_write_command(const void *buf
, u32 len
);
246 void omap_rfbi_read_data(void *buf
, u32 len
);
247 void omap_rfbi_write_data(const void *buf
, u32 len
);
248 void omap_rfbi_write_pixels(const void __iomem
*buf
, int scr_width
,
251 int omap_rfbi_enable_te(bool enable
, unsigned line
);
252 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode
,
253 unsigned hs_pulse_time
, unsigned vs_pulse_time
,
254 int hs_pol_inv
, int vs_pol_inv
, int extif_div
);
255 void rfbi_bus_lock(void);
256 void rfbi_bus_unlock(void);
260 enum omap_dss_dsi_trans_mode
{
261 /* Sync Pulses: both sync start and end packets sent */
262 OMAP_DSS_DSI_PULSE_MODE
,
263 /* Sync Events: only sync start packets sent */
264 OMAP_DSS_DSI_EVENT_MODE
,
265 /* Burst: only sync start packets sent, pixels are time compressed */
266 OMAP_DSS_DSI_BURST_MODE
,
269 struct omap_dss_dsi_videomode_timings
{
280 /* DSI video mode blanking data */
281 /* Unit: byte clock cycles */
287 /* Unit: line clocks */
292 /* DSI blanking modes */
294 int hsa_blanking_mode
;
295 int hbp_blanking_mode
;
296 int hfp_blanking_mode
;
298 enum omap_dss_dsi_trans_mode trans_mode
;
300 bool ddr_clk_always_on
;
304 struct omap_dss_dsi_config
{
305 enum omap_dss_dsi_mode mode
;
306 enum omap_dss_dsi_pixel_format pixel_format
;
307 const struct omap_video_timings
*timings
;
309 unsigned long hs_clk_min
, hs_clk_max
;
310 unsigned long lp_clk_min
, lp_clk_max
;
312 bool ddr_clk_always_on
;
313 enum omap_dss_dsi_trans_mode trans_mode
;
316 void dsi_bus_lock(struct omap_dss_device
*dssdev
);
317 void dsi_bus_unlock(struct omap_dss_device
*dssdev
);
318 int dsi_vc_dcs_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
320 int dsi_vc_generic_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
322 int dsi_vc_dcs_write_0(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
);
323 int dsi_vc_generic_write_0(struct omap_dss_device
*dssdev
, int channel
);
324 int dsi_vc_dcs_write_1(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
326 int dsi_vc_generic_write_1(struct omap_dss_device
*dssdev
, int channel
,
328 int dsi_vc_generic_write_2(struct omap_dss_device
*dssdev
, int channel
,
329 u8 param1
, u8 param2
);
330 int dsi_vc_dcs_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
332 int dsi_vc_generic_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
334 int dsi_vc_dcs_read(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
335 u8
*buf
, int buflen
);
336 int dsi_vc_generic_read_0(struct omap_dss_device
*dssdev
, int channel
, u8
*buf
,
338 int dsi_vc_generic_read_1(struct omap_dss_device
*dssdev
, int channel
, u8 param
,
339 u8
*buf
, int buflen
);
340 int dsi_vc_generic_read_2(struct omap_dss_device
*dssdev
, int channel
,
341 u8 param1
, u8 param2
, u8
*buf
, int buflen
);
342 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device
*dssdev
, int channel
,
344 int dsi_vc_send_null(struct omap_dss_device
*dssdev
, int channel
);
345 int dsi_vc_send_bta_sync(struct omap_dss_device
*dssdev
, int channel
);
346 int dsi_enable_video_output(struct omap_dss_device
*dssdev
, int channel
);
347 void dsi_disable_video_output(struct omap_dss_device
*dssdev
, int channel
);
349 enum omapdss_version
{
350 OMAPDSS_VER_UNKNOWN
= 0,
351 OMAPDSS_VER_OMAP24xx
,
352 OMAPDSS_VER_OMAP34xx_ES1
, /* OMAP3430 ES1.0, 2.0 */
353 OMAPDSS_VER_OMAP34xx_ES3
, /* OMAP3430 ES3.0+ */
354 OMAPDSS_VER_OMAP3630
,
356 OMAPDSS_VER_OMAP4430_ES1
, /* OMAP4430 ES1.0 */
357 OMAPDSS_VER_OMAP4430_ES2
, /* OMAP4430 ES2.0, 2.1, 2.2 */
358 OMAPDSS_VER_OMAP4
, /* All other OMAP4s */
362 /* Board specific data */
363 struct omap_dss_board_info
{
364 int (*get_context_loss_count
)(struct device
*dev
);
366 struct omap_dss_device
**devices
;
367 struct omap_dss_device
*default_device
;
368 int (*dsi_enable_pads
)(int dsi_id
, unsigned lane_mask
);
369 void (*dsi_disable_pads
)(int dsi_id
, unsigned lane_mask
);
370 int (*set_min_bus_tput
)(struct device
*dev
, unsigned long r
);
371 enum omapdss_version version
;
374 /* Init with the board info */
375 extern int omap_display_init(struct omap_dss_board_info
*board_data
);
377 extern int omap_hdmi_init(enum omap_hdmi_flags flags
);
379 struct omap_video_timings
{
386 /* Unit: pixel clocks */
387 u16 hsw
; /* Horizontal synchronization pulse width */
388 /* Unit: pixel clocks */
389 u16 hfp
; /* Horizontal front porch */
390 /* Unit: pixel clocks */
391 u16 hbp
; /* Horizontal back porch */
392 /* Unit: line clocks */
393 u16 vsw
; /* Vertical synchronization pulse width */
394 /* Unit: line clocks */
395 u16 vfp
; /* Vertical front porch */
396 /* Unit: line clocks */
397 u16 vbp
; /* Vertical back porch */
399 /* Vsync logic level */
400 enum omap_dss_signal_level vsync_level
;
401 /* Hsync logic level */
402 enum omap_dss_signal_level hsync_level
;
403 /* Interlaced or Progressive timings */
405 /* Pixel clock edge to drive LCD data */
406 enum omap_dss_signal_edge data_pclk_edge
;
407 /* Data enable logic level */
408 enum omap_dss_signal_level de_level
;
409 /* Pixel clock edges to drive HSYNC and VSYNC signals */
410 enum omap_dss_signal_edge sync_pclk_edge
;
413 #ifdef CONFIG_OMAP2_DSS_VENC
414 /* Hardcoded timings for tv modes. Venc only uses these to
415 * identify the mode, and does not actually use the configs
416 * itself. However, the configs should be something that
417 * a normal monitor can also show */
418 extern const struct omap_video_timings omap_dss_pal_timings
;
419 extern const struct omap_video_timings omap_dss_ntsc_timings
;
422 struct omap_dss_cpr_coefs
{
428 struct omap_overlay_info
{
430 u32 p_uv_addr
; /* for NV12 format */
434 enum omap_color_mode color_mode
;
436 enum omap_dss_rotation_type rotation_type
;
441 u16 out_width
; /* if 0, out_width == width */
442 u16 out_height
; /* if 0, out_height == height */
448 struct omap_overlay
{
450 struct list_head list
;
455 enum omap_color_mode supported_modes
;
456 enum omap_overlay_caps caps
;
459 struct omap_overlay_manager
*manager
;
462 * The following functions do not block:
468 * The rest of the functions may block and cannot be called from
472 int (*enable
)(struct omap_overlay
*ovl
);
473 int (*disable
)(struct omap_overlay
*ovl
);
474 bool (*is_enabled
)(struct omap_overlay
*ovl
);
476 int (*set_manager
)(struct omap_overlay
*ovl
,
477 struct omap_overlay_manager
*mgr
);
478 int (*unset_manager
)(struct omap_overlay
*ovl
);
480 int (*set_overlay_info
)(struct omap_overlay
*ovl
,
481 struct omap_overlay_info
*info
);
482 void (*get_overlay_info
)(struct omap_overlay
*ovl
,
483 struct omap_overlay_info
*info
);
485 int (*wait_for_go
)(struct omap_overlay
*ovl
);
487 struct omap_dss_device
*(*get_device
)(struct omap_overlay
*ovl
);
490 struct omap_overlay_manager_info
{
493 enum omap_dss_trans_key_type trans_key_type
;
497 bool partial_alpha_enabled
;
500 struct omap_dss_cpr_coefs cpr_coefs
;
503 struct omap_overlay_manager
{
508 enum omap_channel id
;
509 enum omap_overlay_manager_caps caps
;
510 struct list_head overlays
;
511 enum omap_display_type supported_displays
;
512 enum omap_dss_output_id supported_outputs
;
515 struct omap_dss_output
*output
;
518 * The following functions do not block:
524 * The rest of the functions may block and cannot be called from
528 int (*set_output
)(struct omap_overlay_manager
*mgr
,
529 struct omap_dss_output
*output
);
530 int (*unset_output
)(struct omap_overlay_manager
*mgr
);
532 int (*set_manager_info
)(struct omap_overlay_manager
*mgr
,
533 struct omap_overlay_manager_info
*info
);
534 void (*get_manager_info
)(struct omap_overlay_manager
*mgr
,
535 struct omap_overlay_manager_info
*info
);
537 int (*apply
)(struct omap_overlay_manager
*mgr
);
538 int (*wait_for_go
)(struct omap_overlay_manager
*mgr
);
539 int (*wait_for_vsync
)(struct omap_overlay_manager
*mgr
);
541 struct omap_dss_device
*(*get_device
)(struct omap_overlay_manager
*mgr
);
544 /* 22 pins means 1 clk lane and 10 data lanes */
545 #define OMAP_DSS_MAX_DSI_PINS 22
547 struct omap_dsi_pin_config
{
550 * pin numbers in the following order:
556 int pins
[OMAP_DSS_MAX_DSI_PINS
];
559 struct omap_dss_writeback_info
{
565 enum omap_color_mode color_mode
;
567 enum omap_dss_rotation_type rotation_type
;
572 struct omap_dss_output
{
573 struct list_head list
;
577 /* display type supported by the output */
578 enum omap_display_type type
;
580 /* DISPC channel for this output */
581 enum omap_channel dispc_channel
;
583 /* output instance */
584 enum omap_dss_output_id id
;
586 /* output's platform device pointer */
587 struct platform_device
*pdev
;
590 struct omap_overlay_manager
*manager
;
592 struct omap_dss_device
*device
;
595 struct omap_dss_device
{
598 enum omap_display_type type
;
600 /* obsolete, to be removed */
601 enum omap_channel channel
;
625 enum omap_dss_venc_type type
;
626 bool invert_polarity
;
631 struct omap_video_timings timings
;
633 enum omap_dss_dsi_pixel_format dsi_pix_fmt
;
634 enum omap_dss_dsi_mode dsi_mode
;
639 struct rfbi_timings rfbi_timings
;
644 int max_backlight_level
;
648 /* used to match device to driver */
649 const char *driver_name
;
653 struct omap_dss_driver
*driver
;
655 /* helper variable for driver suspend/resume */
656 bool activate_after_resume
;
658 enum omap_display_caps caps
;
660 struct omap_dss_output
*output
;
662 enum omap_dss_display_state state
;
664 enum omap_dss_audio_state audio_state
;
666 /* platform specific */
667 int (*platform_enable
)(struct omap_dss_device
*dssdev
);
668 void (*platform_disable
)(struct omap_dss_device
*dssdev
);
669 int (*set_backlight
)(struct omap_dss_device
*dssdev
, int level
);
670 int (*get_backlight
)(struct omap_dss_device
*dssdev
);
673 struct omap_dss_hdmi_data
680 struct omap_dss_audio
{
681 struct snd_aes_iec958
*iec
;
682 struct snd_cea_861_aud_if
*cea
;
685 struct omap_dss_driver
{
686 struct device_driver driver
;
688 int (*probe
)(struct omap_dss_device
*);
689 void (*remove
)(struct omap_dss_device
*);
691 int (*enable
)(struct omap_dss_device
*display
);
692 void (*disable
)(struct omap_dss_device
*display
);
693 int (*run_test
)(struct omap_dss_device
*display
, int test
);
695 int (*update
)(struct omap_dss_device
*dssdev
,
696 u16 x
, u16 y
, u16 w
, u16 h
);
697 int (*sync
)(struct omap_dss_device
*dssdev
);
699 int (*enable_te
)(struct omap_dss_device
*dssdev
, bool enable
);
700 int (*get_te
)(struct omap_dss_device
*dssdev
);
702 u8 (*get_rotate
)(struct omap_dss_device
*dssdev
);
703 int (*set_rotate
)(struct omap_dss_device
*dssdev
, u8 rotate
);
705 bool (*get_mirror
)(struct omap_dss_device
*dssdev
);
706 int (*set_mirror
)(struct omap_dss_device
*dssdev
, bool enable
);
708 int (*memory_read
)(struct omap_dss_device
*dssdev
,
709 void *buf
, size_t size
,
710 u16 x
, u16 y
, u16 w
, u16 h
);
712 void (*get_resolution
)(struct omap_dss_device
*dssdev
,
713 u16
*xres
, u16
*yres
);
714 void (*get_dimensions
)(struct omap_dss_device
*dssdev
,
715 u32
*width
, u32
*height
);
716 int (*get_recommended_bpp
)(struct omap_dss_device
*dssdev
);
718 int (*check_timings
)(struct omap_dss_device
*dssdev
,
719 struct omap_video_timings
*timings
);
720 void (*set_timings
)(struct omap_dss_device
*dssdev
,
721 struct omap_video_timings
*timings
);
722 void (*get_timings
)(struct omap_dss_device
*dssdev
,
723 struct omap_video_timings
*timings
);
725 int (*set_wss
)(struct omap_dss_device
*dssdev
, u32 wss
);
726 u32 (*get_wss
)(struct omap_dss_device
*dssdev
);
728 int (*read_edid
)(struct omap_dss_device
*dssdev
, u8
*buf
, int len
);
729 bool (*detect
)(struct omap_dss_device
*dssdev
);
732 * For display drivers that support audio. This encompasses
733 * HDMI and DisplayPort at the moment.
736 * Note: These functions might sleep. Do not call while
737 * holding a spinlock/readlock.
739 int (*audio_enable
)(struct omap_dss_device
*dssdev
);
740 void (*audio_disable
)(struct omap_dss_device
*dssdev
);
741 bool (*audio_supported
)(struct omap_dss_device
*dssdev
);
742 int (*audio_config
)(struct omap_dss_device
*dssdev
,
743 struct omap_dss_audio
*audio
);
744 /* Note: These functions may not sleep */
745 int (*audio_start
)(struct omap_dss_device
*dssdev
);
746 void (*audio_stop
)(struct omap_dss_device
*dssdev
);
750 enum omapdss_version
omapdss_get_version(void);
751 bool omapdss_is_initialized(void);
753 int omap_dss_register_driver(struct omap_dss_driver
*);
754 void omap_dss_unregister_driver(struct omap_dss_driver
*);
756 void omap_dss_get_device(struct omap_dss_device
*dssdev
);
757 void omap_dss_put_device(struct omap_dss_device
*dssdev
);
758 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
759 struct omap_dss_device
*omap_dss_get_next_device(struct omap_dss_device
*from
);
760 struct omap_dss_device
*omap_dss_find_device(void *data
,
761 int (*match
)(struct omap_dss_device
*dssdev
, void *data
));
762 const char *omapdss_get_default_display_name(void);
764 int omap_dss_start_device(struct omap_dss_device
*dssdev
);
765 void omap_dss_stop_device(struct omap_dss_device
*dssdev
);
767 int dss_feat_get_num_mgrs(void);
768 int dss_feat_get_num_ovls(void);
769 enum omap_display_type
dss_feat_get_supported_displays(enum omap_channel channel
);
770 enum omap_dss_output_id
dss_feat_get_supported_outputs(enum omap_channel channel
);
771 enum omap_color_mode
dss_feat_get_supported_color_modes(enum omap_plane plane
);
775 int omap_dss_get_num_overlay_managers(void);
776 struct omap_overlay_manager
*omap_dss_get_overlay_manager(int num
);
778 int omap_dss_get_num_overlays(void);
779 struct omap_overlay
*omap_dss_get_overlay(int num
);
781 struct omap_dss_output
*omap_dss_get_output(enum omap_dss_output_id id
);
782 int omapdss_output_set_device(struct omap_dss_output
*out
,
783 struct omap_dss_device
*dssdev
);
784 int omapdss_output_unset_device(struct omap_dss_output
*out
);
786 void omapdss_default_get_resolution(struct omap_dss_device
*dssdev
,
787 u16
*xres
, u16
*yres
);
788 int omapdss_default_get_recommended_bpp(struct omap_dss_device
*dssdev
);
789 void omapdss_default_get_timings(struct omap_dss_device
*dssdev
,
790 struct omap_video_timings
*timings
);
792 typedef void (*omap_dispc_isr_t
) (void *arg
, u32 mask
);
793 int omap_dispc_register_isr(omap_dispc_isr_t isr
, void *arg
, u32 mask
);
794 int omap_dispc_unregister_isr(omap_dispc_isr_t isr
, void *arg
, u32 mask
);
796 u32
dispc_read_irqstatus(void);
797 void dispc_clear_irqstatus(u32 mask
);
798 u32
dispc_read_irqenable(void);
799 void dispc_write_irqenable(u32 mask
);
801 int dispc_request_irq(irq_handler_t handler
, void *dev_id
);
802 void dispc_free_irq(void *dev_id
);
804 int dispc_runtime_get(void);
805 void dispc_runtime_put(void);
807 void dispc_mgr_enable(enum omap_channel channel
, bool enable
);
808 bool dispc_mgr_is_enabled(enum omap_channel channel
);
809 u32
dispc_mgr_get_vsync_irq(enum omap_channel channel
);
810 u32
dispc_mgr_get_framedone_irq(enum omap_channel channel
);
811 u32
dispc_mgr_get_sync_lost_irq(enum omap_channel channel
);
812 bool dispc_mgr_go_busy(enum omap_channel channel
);
813 void dispc_mgr_go(enum omap_channel channel
);
814 void dispc_mgr_set_lcd_config(enum omap_channel channel
,
815 const struct dss_lcd_mgr_config
*config
);
816 void dispc_mgr_set_timings(enum omap_channel channel
,
817 const struct omap_video_timings
*timings
);
818 void dispc_mgr_setup(enum omap_channel channel
,
819 const struct omap_overlay_manager_info
*info
);
821 int dispc_ovl_check(enum omap_plane plane
, enum omap_channel channel
,
822 const struct omap_overlay_info
*oi
,
823 const struct omap_video_timings
*timings
,
824 int *x_predecim
, int *y_predecim
);
826 int dispc_ovl_enable(enum omap_plane plane
, bool enable
);
827 bool dispc_ovl_enabled(enum omap_plane plane
);
828 void dispc_ovl_set_channel_out(enum omap_plane plane
,
829 enum omap_channel channel
);
830 int dispc_ovl_setup(enum omap_plane plane
, const struct omap_overlay_info
*oi
,
831 bool replication
, const struct omap_video_timings
*mgr_timings
,
834 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
835 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
837 void omapdss_dsi_vc_enable_hs(struct omap_dss_device
*dssdev
, int channel
,
839 int omapdss_dsi_enable_te(struct omap_dss_device
*dssdev
, bool enable
);
840 int omapdss_dsi_set_config(struct omap_dss_device
*dssdev
,
841 const struct omap_dss_dsi_config
*config
);
843 int omap_dsi_update(struct omap_dss_device
*dssdev
, int channel
,
844 void (*callback
)(int, void *), void *data
);
845 int omap_dsi_request_vc(struct omap_dss_device
*dssdev
, int *channel
);
846 int omap_dsi_set_vc_id(struct omap_dss_device
*dssdev
, int channel
, int vc_id
);
847 void omap_dsi_release_vc(struct omap_dss_device
*dssdev
, int channel
);
848 int omapdss_dsi_configure_pins(struct omap_dss_device
*dssdev
,
849 const struct omap_dsi_pin_config
*pin_cfg
);
851 int omapdss_dsi_display_enable(struct omap_dss_device
*dssdev
);
852 void omapdss_dsi_display_disable(struct omap_dss_device
*dssdev
,
853 bool disconnect_lanes
, bool enter_ulps
);
855 int omapdss_dpi_display_enable(struct omap_dss_device
*dssdev
);
856 void omapdss_dpi_display_disable(struct omap_dss_device
*dssdev
);
857 void omapdss_dpi_set_timings(struct omap_dss_device
*dssdev
,
858 struct omap_video_timings
*timings
);
859 int dpi_check_timings(struct omap_dss_device
*dssdev
,
860 struct omap_video_timings
*timings
);
861 void omapdss_dpi_set_data_lines(struct omap_dss_device
*dssdev
, int data_lines
);
863 int omapdss_sdi_display_enable(struct omap_dss_device
*dssdev
);
864 void omapdss_sdi_display_disable(struct omap_dss_device
*dssdev
);
865 void omapdss_sdi_set_timings(struct omap_dss_device
*dssdev
,
866 struct omap_video_timings
*timings
);
867 void omapdss_sdi_set_datapairs(struct omap_dss_device
*dssdev
, int datapairs
);
869 int omapdss_rfbi_display_enable(struct omap_dss_device
*dssdev
);
870 void omapdss_rfbi_display_disable(struct omap_dss_device
*dssdev
);
871 int omap_rfbi_update(struct omap_dss_device
*dssdev
, void (*callback
)(void *),
873 int omap_rfbi_configure(struct omap_dss_device
*dssdev
);
874 void omapdss_rfbi_set_size(struct omap_dss_device
*dssdev
, u16 w
, u16 h
);
875 void omapdss_rfbi_set_pixel_size(struct omap_dss_device
*dssdev
,
877 void omapdss_rfbi_set_data_lines(struct omap_dss_device
*dssdev
,
879 void omapdss_rfbi_set_interface_timings(struct omap_dss_device
*dssdev
,
880 struct rfbi_timings
*timings
);
882 int omapdss_compat_init(void);
883 void omapdss_compat_uninit(void);
886 void (*start_update
)(struct omap_overlay_manager
*mgr
);
887 int (*enable
)(struct omap_overlay_manager
*mgr
);
888 void (*disable
)(struct omap_overlay_manager
*mgr
);
889 void (*set_timings
)(struct omap_overlay_manager
*mgr
,
890 const struct omap_video_timings
*timings
);
891 void (*set_lcd_config
)(struct omap_overlay_manager
*mgr
,
892 const struct dss_lcd_mgr_config
*config
);
893 int (*register_framedone_handler
)(struct omap_overlay_manager
*mgr
,
894 void (*handler
)(void *), void *data
);
895 void (*unregister_framedone_handler
)(struct omap_overlay_manager
*mgr
,
896 void (*handler
)(void *), void *data
);
899 int dss_install_mgr_ops(const struct dss_mgr_ops
*mgr_ops
);
900 void dss_uninstall_mgr_ops(void);
902 void dss_mgr_set_timings(struct omap_overlay_manager
*mgr
,
903 const struct omap_video_timings
*timings
);
904 void dss_mgr_set_lcd_config(struct omap_overlay_manager
*mgr
,
905 const struct dss_lcd_mgr_config
*config
);
906 int dss_mgr_enable(struct omap_overlay_manager
*mgr
);
907 void dss_mgr_disable(struct omap_overlay_manager
*mgr
);
908 void dss_mgr_start_update(struct omap_overlay_manager
*mgr
);
909 int dss_mgr_register_framedone_handler(struct omap_overlay_manager
*mgr
,
910 void (*handler
)(void *), void *data
);
911 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager
*mgr
,
912 void (*handler
)(void *), void *data
);