2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/irqdomain.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/syscore_ops.h>
15 #include "internals.h"
17 static LIST_HEAD(gc_list
);
18 static DEFINE_RAW_SPINLOCK(gc_lock
);
21 * irq_gc_noop - NOOP function
24 void irq_gc_noop(struct irq_data
*d
)
29 * irq_gc_mask_disable_reg - Mask chip via disable register
32 * Chip has separate enable/disable registers instead of a single mask
35 void irq_gc_mask_disable_reg(struct irq_data
*d
)
37 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
38 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
42 irq_reg_writel(gc
, mask
, ct
->regs
.disable
);
43 *ct
->mask_cache
&= ~mask
;
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
54 void irq_gc_mask_set_bit(struct irq_data
*d
)
56 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
57 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
61 *ct
->mask_cache
|= mask
;
62 irq_reg_writel(gc
, *ct
->mask_cache
, ct
->regs
.mask
);
65 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit
);
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
74 void irq_gc_mask_clr_bit(struct irq_data
*d
)
76 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
77 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
81 *ct
->mask_cache
&= ~mask
;
82 irq_reg_writel(gc
, *ct
->mask_cache
, ct
->regs
.mask
);
85 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit
);
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
91 * Chip has separate enable/disable registers instead of a single mask
94 void irq_gc_unmask_enable_reg(struct irq_data
*d
)
96 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
97 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
101 irq_reg_writel(gc
, mask
, ct
->regs
.enable
);
102 *ct
->mask_cache
|= mask
;
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
110 void irq_gc_ack_set_bit(struct irq_data
*d
)
112 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
113 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
117 irq_reg_writel(gc
, mask
, ct
->regs
.ack
);
120 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit
);
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
126 void irq_gc_ack_clr_bit(struct irq_data
*d
)
128 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
129 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
133 irq_reg_writel(gc
, mask
, ct
->regs
.ack
);
138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
141 void irq_gc_mask_disable_reg_and_ack(struct irq_data
*d
)
143 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
144 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
148 irq_reg_writel(gc
, mask
, ct
->regs
.mask
);
149 irq_reg_writel(gc
, mask
, ct
->regs
.ack
);
154 * irq_gc_eoi - EOI interrupt
157 void irq_gc_eoi(struct irq_data
*d
)
159 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
160 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
164 irq_reg_writel(gc
, mask
, ct
->regs
.eoi
);
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
171 * @on: Indicates whether the wake bit should be set or cleared
173 * For chips where the wake from suspend functionality is not
174 * configured in a separate register and the wakeup active state is
175 * just stored in a bitmask.
177 int irq_gc_set_wake(struct irq_data
*d
, unsigned int on
)
179 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
182 if (!(mask
& gc
->wake_enabled
))
187 gc
->wake_active
|= mask
;
189 gc
->wake_active
&= ~mask
;
194 static u32
irq_readl_be(void __iomem
*addr
)
196 return ioread32be(addr
);
199 static void irq_writel_be(u32 val
, void __iomem
*addr
)
201 iowrite32be(val
, addr
);
204 void irq_init_generic_chip(struct irq_chip_generic
*gc
, const char *name
,
205 int num_ct
, unsigned int irq_base
,
206 void __iomem
*reg_base
, irq_flow_handler_t handler
)
208 raw_spin_lock_init(&gc
->lock
);
210 gc
->irq_base
= irq_base
;
211 gc
->reg_base
= reg_base
;
212 gc
->chip_types
->chip
.name
= name
;
213 gc
->chip_types
->handler
= handler
;
217 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
218 * @name: Name of the irq chip
219 * @num_ct: Number of irq_chip_type instances associated with this
220 * @irq_base: Interrupt base nr for this chip
221 * @reg_base: Register base address (virtual)
222 * @handler: Default flow handler associated with this chip
224 * Returns an initialized irq_chip_generic structure. The chip defaults
225 * to the primary (index 0) irq_chip_type and @handler
227 struct irq_chip_generic
*
228 irq_alloc_generic_chip(const char *name
, int num_ct
, unsigned int irq_base
,
229 void __iomem
*reg_base
, irq_flow_handler_t handler
)
231 struct irq_chip_generic
*gc
;
232 unsigned long sz
= sizeof(*gc
) + num_ct
* sizeof(struct irq_chip_type
);
234 gc
= kzalloc(sz
, GFP_KERNEL
);
236 irq_init_generic_chip(gc
, name
, num_ct
, irq_base
, reg_base
,
241 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip
);
244 irq_gc_init_mask_cache(struct irq_chip_generic
*gc
, enum irq_gc_flags flags
)
246 struct irq_chip_type
*ct
= gc
->chip_types
;
247 u32
*mskptr
= &gc
->mask_cache
, mskreg
= ct
->regs
.mask
;
250 for (i
= 0; i
< gc
->num_ct
; i
++) {
251 if (flags
& IRQ_GC_MASK_CACHE_PER_TYPE
) {
252 mskptr
= &ct
[i
].mask_cache_priv
;
253 mskreg
= ct
[i
].regs
.mask
;
255 ct
[i
].mask_cache
= mskptr
;
256 if (flags
& IRQ_GC_INIT_MASK_CACHE
)
257 *mskptr
= irq_reg_readl(gc
, mskreg
);
262 * __irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
263 * @d: irq domain for which to allocate chips
264 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
265 * @num_ct: Number of irq_chip_type instances associated with this
266 * @name: Name of the irq chip
267 * @handler: Default flow handler associated with these chips
268 * @clr: IRQ_* bits to clear in the mapping function
269 * @set: IRQ_* bits to set in the mapping function
270 * @gcflags: Generic chip specific setup flags
272 int __irq_alloc_domain_generic_chips(struct irq_domain
*d
, int irqs_per_chip
,
273 int num_ct
, const char *name
,
274 irq_flow_handler_t handler
,
275 unsigned int clr
, unsigned int set
,
276 enum irq_gc_flags gcflags
)
278 struct irq_domain_chip_generic
*dgc
;
279 struct irq_chip_generic
*gc
;
287 numchips
= DIV_ROUND_UP(d
->revmap_size
, irqs_per_chip
);
291 /* Allocate a pointer, generic chip and chiptypes for each chip */
292 sz
= sizeof(*dgc
) + numchips
* sizeof(gc
);
293 sz
+= numchips
* (sizeof(*gc
) + num_ct
* sizeof(struct irq_chip_type
));
295 tmp
= dgc
= kzalloc(sz
, GFP_KERNEL
);
298 dgc
->irqs_per_chip
= irqs_per_chip
;
299 dgc
->num_chips
= numchips
;
300 dgc
->irq_flags_to_set
= set
;
301 dgc
->irq_flags_to_clear
= clr
;
302 dgc
->gc_flags
= gcflags
;
305 /* Calc pointer to the first generic chip */
306 tmp
+= sizeof(*dgc
) + numchips
* sizeof(gc
);
307 for (i
= 0; i
< numchips
; i
++) {
308 /* Store the pointer to the generic chip */
309 dgc
->gc
[i
] = gc
= tmp
;
310 irq_init_generic_chip(gc
, name
, num_ct
, i
* irqs_per_chip
,
314 if (gcflags
& IRQ_GC_BE_IO
) {
315 gc
->reg_readl
= &irq_readl_be
;
316 gc
->reg_writel
= &irq_writel_be
;
319 raw_spin_lock_irqsave(&gc_lock
, flags
);
320 list_add_tail(&gc
->list
, &gc_list
);
321 raw_spin_unlock_irqrestore(&gc_lock
, flags
);
322 /* Calc pointer to the next generic chip */
323 tmp
+= sizeof(*gc
) + num_ct
* sizeof(struct irq_chip_type
);
328 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips
);
330 static struct irq_chip_generic
*
331 __irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
)
333 struct irq_domain_chip_generic
*dgc
= d
->gc
;
337 return ERR_PTR(-ENODEV
);
338 idx
= hw_irq
/ dgc
->irqs_per_chip
;
339 if (idx
>= dgc
->num_chips
)
340 return ERR_PTR(-EINVAL
);
345 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
346 * @d: irq domain pointer
347 * @hw_irq: Hardware interrupt number
349 struct irq_chip_generic
*
350 irq_get_domain_generic_chip(struct irq_domain
*d
, unsigned int hw_irq
)
352 struct irq_chip_generic
*gc
= __irq_get_domain_generic_chip(d
, hw_irq
);
354 return !IS_ERR(gc
) ? gc
: NULL
;
356 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip
);
359 * Separate lockdep class for interrupt chip which can nest irq_desc
362 static struct lock_class_key irq_nested_lock_class
;
365 * irq_map_generic_chip - Map a generic chip for an irq domain
367 int irq_map_generic_chip(struct irq_domain
*d
, unsigned int virq
,
368 irq_hw_number_t hw_irq
)
370 struct irq_data
*data
= irq_domain_get_irq_data(d
, virq
);
371 struct irq_domain_chip_generic
*dgc
= d
->gc
;
372 struct irq_chip_generic
*gc
;
373 struct irq_chip_type
*ct
;
374 struct irq_chip
*chip
;
378 gc
= __irq_get_domain_generic_chip(d
, hw_irq
);
382 idx
= hw_irq
% dgc
->irqs_per_chip
;
384 if (test_bit(idx
, &gc
->unused
))
387 if (test_bit(idx
, &gc
->installed
))
393 /* We only init the cache for the first mapping of a generic chip */
394 if (!gc
->installed
) {
395 raw_spin_lock_irqsave(&gc
->lock
, flags
);
396 irq_gc_init_mask_cache(gc
, dgc
->gc_flags
);
397 raw_spin_unlock_irqrestore(&gc
->lock
, flags
);
400 /* Mark the interrupt as installed */
401 set_bit(idx
, &gc
->installed
);
403 if (dgc
->gc_flags
& IRQ_GC_INIT_NESTED_LOCK
)
404 irq_set_lockdep_class(virq
, &irq_nested_lock_class
);
406 if (chip
->irq_calc_mask
)
407 chip
->irq_calc_mask(data
);
409 data
->mask
= 1 << idx
;
411 irq_domain_set_info(d
, virq
, hw_irq
, chip
, gc
, ct
->handler
, NULL
, NULL
);
412 irq_modify_status(virq
, dgc
->irq_flags_to_clear
, dgc
->irq_flags_to_set
);
416 static void irq_unmap_generic_chip(struct irq_domain
*d
, unsigned int virq
)
418 struct irq_data
*data
= irq_domain_get_irq_data(d
, virq
);
419 struct irq_domain_chip_generic
*dgc
= d
->gc
;
420 unsigned int hw_irq
= data
->hwirq
;
421 struct irq_chip_generic
*gc
;
424 gc
= irq_get_domain_generic_chip(d
, hw_irq
);
428 irq_idx
= hw_irq
% dgc
->irqs_per_chip
;
430 clear_bit(irq_idx
, &gc
->installed
);
431 irq_domain_set_info(d
, virq
, hw_irq
, &no_irq_chip
, NULL
, NULL
, NULL
,
436 struct irq_domain_ops irq_generic_chip_ops
= {
437 .map
= irq_map_generic_chip
,
438 .unmap
= irq_unmap_generic_chip
,
439 .xlate
= irq_domain_xlate_onetwocell
,
441 EXPORT_SYMBOL_GPL(irq_generic_chip_ops
);
444 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
445 * @gc: Generic irq chip holding all data
446 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
447 * @flags: Flags for initialization
448 * @clr: IRQ_* bits to clear
449 * @set: IRQ_* bits to set
451 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
452 * initializes all interrupts to the primary irq_chip_type and its
453 * associated handler.
455 void irq_setup_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
456 enum irq_gc_flags flags
, unsigned int clr
,
459 struct irq_chip_type
*ct
= gc
->chip_types
;
460 struct irq_chip
*chip
= &ct
->chip
;
463 raw_spin_lock(&gc_lock
);
464 list_add_tail(&gc
->list
, &gc_list
);
465 raw_spin_unlock(&gc_lock
);
467 irq_gc_init_mask_cache(gc
, flags
);
469 for (i
= gc
->irq_base
; msk
; msk
>>= 1, i
++) {
473 if (flags
& IRQ_GC_INIT_NESTED_LOCK
)
474 irq_set_lockdep_class(i
, &irq_nested_lock_class
);
476 if (!(flags
& IRQ_GC_NO_MASK
)) {
477 struct irq_data
*d
= irq_get_irq_data(i
);
479 if (chip
->irq_calc_mask
)
480 chip
->irq_calc_mask(d
);
482 d
->mask
= 1 << (i
- gc
->irq_base
);
484 irq_set_chip_and_handler(i
, chip
, ct
->handler
);
485 irq_set_chip_data(i
, gc
);
486 irq_modify_status(i
, clr
, set
);
488 gc
->irq_cnt
= i
- gc
->irq_base
;
490 EXPORT_SYMBOL_GPL(irq_setup_generic_chip
);
493 * irq_setup_alt_chip - Switch to alternative chip
494 * @d: irq_data for this interrupt
495 * @type: Flow type to be initialized
497 * Only to be called from chip->irq_set_type() callbacks.
499 int irq_setup_alt_chip(struct irq_data
*d
, unsigned int type
)
501 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
502 struct irq_chip_type
*ct
= gc
->chip_types
;
505 for (i
= 0; i
< gc
->num_ct
; i
++, ct
++) {
506 if (ct
->type
& type
) {
508 irq_data_to_desc(d
)->handle_irq
= ct
->handler
;
514 EXPORT_SYMBOL_GPL(irq_setup_alt_chip
);
517 * irq_remove_generic_chip - Remove a chip
518 * @gc: Generic irq chip holding all data
519 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
520 * @clr: IRQ_* bits to clear
521 * @set: IRQ_* bits to set
523 * Remove up to 32 interrupts starting from gc->irq_base.
525 void irq_remove_generic_chip(struct irq_chip_generic
*gc
, u32 msk
,
526 unsigned int clr
, unsigned int set
)
528 unsigned int i
= gc
->irq_base
;
530 raw_spin_lock(&gc_lock
);
532 raw_spin_unlock(&gc_lock
);
534 for (; msk
; msk
>>= 1, i
++) {
538 /* Remove handler first. That will mask the irq line */
539 irq_set_handler(i
, NULL
);
540 irq_set_chip(i
, &no_irq_chip
);
541 irq_set_chip_data(i
, NULL
);
542 irq_modify_status(i
, clr
, set
);
545 EXPORT_SYMBOL_GPL(irq_remove_generic_chip
);
547 static struct irq_data
*irq_gc_get_irq_data(struct irq_chip_generic
*gc
)
552 return irq_get_irq_data(gc
->irq_base
);
555 * We don't know which of the irqs has been actually
556 * installed. Use the first one.
561 virq
= irq_find_mapping(gc
->domain
, gc
->irq_base
+ __ffs(gc
->installed
));
562 return virq
? irq_get_irq_data(virq
) : NULL
;
566 static int irq_gc_suspend(void)
568 struct irq_chip_generic
*gc
;
570 list_for_each_entry(gc
, &gc_list
, list
) {
571 struct irq_chip_type
*ct
= gc
->chip_types
;
573 if (ct
->chip
.irq_suspend
) {
574 struct irq_data
*data
= irq_gc_get_irq_data(gc
);
577 ct
->chip
.irq_suspend(data
);
586 static void irq_gc_resume(void)
588 struct irq_chip_generic
*gc
;
590 list_for_each_entry(gc
, &gc_list
, list
) {
591 struct irq_chip_type
*ct
= gc
->chip_types
;
596 if (ct
->chip
.irq_resume
) {
597 struct irq_data
*data
= irq_gc_get_irq_data(gc
);
600 ct
->chip
.irq_resume(data
);
605 #define irq_gc_suspend NULL
606 #define irq_gc_resume NULL
609 static void irq_gc_shutdown(void)
611 struct irq_chip_generic
*gc
;
613 list_for_each_entry(gc
, &gc_list
, list
) {
614 struct irq_chip_type
*ct
= gc
->chip_types
;
616 if (ct
->chip
.irq_pm_shutdown
) {
617 struct irq_data
*data
= irq_gc_get_irq_data(gc
);
620 ct
->chip
.irq_pm_shutdown(data
);
625 static struct syscore_ops irq_gc_syscore_ops
= {
626 .suspend
= irq_gc_suspend
,
627 .resume
= irq_gc_resume
,
628 .shutdown
= irq_gc_shutdown
,
631 static int __init
irq_gc_init_ops(void)
633 register_syscore_ops(&irq_gc_syscore_ops
);
636 device_initcall(irq_gc_init_ops
);