library/stdarch/crates/core_arch/src/aarch64/prefetch.rs

   1 #[cfg(test)]
   2 use stdarch_test::assert_instr;
   3
   4 extern "unadjusted" {
   5     #[link_name = "llvm.prefetch"]
   6     fn prefetch(p: *const i8, rw: i32, loc: i32, ty: i32);
   7 }
   8
   9 /// See [`prefetch`](fn._prefetch.html).
  10 pub const _PREFETCH_READ: i32 = 0;
  11
  12 /// See [`prefetch`](fn._prefetch.html).
  13 pub const _PREFETCH_WRITE: i32 = 1;
  14
  15 /// See [`prefetch`](fn._prefetch.html).
  16 pub const _PREFETCH_LOCALITY0: i32 = 0;
  17
  18 /// See [`prefetch`](fn._prefetch.html).
  19 pub const _PREFETCH_LOCALITY1: i32 = 1;
  20
  21 /// See [`prefetch`](fn._prefetch.html).
  22 pub const _PREFETCH_LOCALITY2: i32 = 2;
  23
  24 /// See [`prefetch`](fn._prefetch.html).
  25 pub const _PREFETCH_LOCALITY3: i32 = 3;
  26
  27 /// Fetch the cache line that contains address `p` using the given `RW` and `LOCALITY`.
  28 ///
  29 /// The `RW` must be one of:
  30 ///
  31 /// * [`_PREFETCH_READ`](constant._PREFETCH_READ.html): the prefetch is preparing
  32 ///   for a read.
  33 ///
  34 /// * [`_PREFETCH_WRITE`](constant._PREFETCH_WRITE.html): the prefetch is preparing
  35 ///   for a write.
  36 ///
  37 /// The `LOCALITY` must be one of:
  38 ///
  39 /// * [`_PREFETCH_LOCALITY0`](constant._PREFETCH_LOCALITY0.html): Streaming or
  40 ///   non-temporal prefetch, for data that is used only once.
  41 ///
  42 /// * [`_PREFETCH_LOCALITY1`](constant._PREFETCH_LOCALITY1.html): Fetch into level 3 cache.
  43 ///
  44 /// * [`_PREFETCH_LOCALITY2`](constant._PREFETCH_LOCALITY2.html): Fetch into level 2 cache.
  45 ///
  46 /// * [`_PREFETCH_LOCALITY3`](constant._PREFETCH_LOCALITY3.html): Fetch into level 1 cache.
  47 ///
  48 /// The prefetch memory instructions signal to the memory system that memory accesses
  49 /// from a specified address are likely to occur in the near future. The memory system
  50 /// can respond by taking actions that are expected to speed up the memory access when
  51 /// they do occur, such as preloading the specified address into one or more caches.
  52 /// Because these signals are only hints, it is valid for a particular CPU to treat
  53 /// any or all prefetch instructions as a NOP.
  54 ///
  55 ///
  56 /// [Arm's documentation](https://developer.arm.com/documentation/den0024/a/the-a64-instruction-set/memory-access-instructions/prefetching-memory?lang=en)
  57 #[inline(always)]
  58 #[cfg_attr(test, assert_instr("prfm pldl1strm", RW = _PREFETCH_READ, LOCALITY = _PREFETCH_LOCALITY0))]
  59 #[cfg_attr(test, assert_instr("prfm pldl3keep", RW = _PREFETCH_READ, LOCALITY = _PREFETCH_LOCALITY1))]
  60 #[cfg_attr(test, assert_instr("prfm pldl2keep", RW = _PREFETCH_READ, LOCALITY = _PREFETCH_LOCALITY2))]
  61 #[cfg_attr(test, assert_instr("prfm pldl1keep", RW = _PREFETCH_READ, LOCALITY = _PREFETCH_LOCALITY3))]
  62 #[cfg_attr(test, assert_instr("prfm pstl1strm", RW = _PREFETCH_WRITE, LOCALITY = _PREFETCH_LOCALITY0))]
  63 #[cfg_attr(test, assert_instr("prfm pstl3keep", RW = _PREFETCH_WRITE, LOCALITY = _PREFETCH_LOCALITY1))]
  64 #[cfg_attr(test, assert_instr("prfm pstl2keep", RW = _PREFETCH_WRITE, LOCALITY = _PREFETCH_LOCALITY2))]
  65 #[cfg_attr(test, assert_instr("prfm pstl1keep", RW = _PREFETCH_WRITE, LOCALITY = _PREFETCH_LOCALITY3))]
  66 #[rustc_legacy_const_generics(1, 2)]
  67 // FIXME: Replace this with the standard ACLE __pld/__pldx/__pli/__plix intrinsics
  68 pub unsafe fn _prefetch<const RW: i32, const LOCALITY: i32>(p: *const i8) {
  69     // We use the `llvm.prefetch` intrinsic with `cache type` = 1 (data cache).
  70     static_assert_uimm_bits!(RW, 1);
  71     static_assert_uimm_bits!(LOCALITY, 2);
  72     prefetch(p, RW, LOCALITY, 1);
  73 }