library/stdarch/crates/core_arch/src/x86/mod.rs

   1 //! `x86` and `x86_64` intrinsics.
   2
   3 use crate::{intrinsics, marker::Sized, mem::transmute};
   4
   5 #[macro_use]
   6 mod macros;
   7
   8 types! {
   9     /// 64-bit wide integer vector type, x86-specific
  10     ///
  11     /// This type is the same as the `__m64` type defined by Intel,
  12     /// representing a 64-bit SIMD register. Usage of this type typically
  13     /// corresponds to the `mmx` target feature.
  14     ///
  15     /// Internally this type may be viewed as:
  16     ///
  17     /// * `i8x8` - eight `i8` variables packed together
  18     /// * `i16x4` - four `i16` variables packed together
  19     /// * `i32x2` - two `i32` variables packed together
  20     ///
  21     /// (as well as unsigned versions). Each intrinsic may interpret the
  22     /// internal bits differently, check the documentation of the intrinsic
  23     /// to see how it's being used.
  24     ///
  25     /// Note that this means that an instance of `__m64` typically just means
  26     /// a "bag of bits" which is left up to interpretation at the point of use.
  27     ///
  28     /// Most intrinsics using `__m64` are prefixed with `_mm_` and the
  29     /// integer types tend to correspond to suffixes like "pi8" or "pi32" (not
  30     /// to be confused with "epiXX", used for `__m128i`).
  31     ///
  32     /// # Examples
  33     ///
  34     /// ```
  35     /// # #![feature(stdsimd, mmx_target_feature)]
  36     /// #[cfg(target_arch = "x86")]
  37     /// use std::arch::x86::*;
  38     /// #[cfg(target_arch = "x86_64")]
  39     /// use std::arch::x86_64::*;
  40     ///
  41     /// # fn main() {
  42     /// # #[target_feature(enable = "mmx")]
  43     /// # unsafe fn foo() {
  44     /// let all_bytes_zero = _mm_setzero_si64();
  45     /// let all_bytes_one = _mm_set1_pi8(1);
  46     /// let two_i32 = _mm_set_pi32(1, 2);
  47     /// # }
  48     /// # if is_x86_feature_detected!("mmx") { unsafe { foo() } }
  49     /// # }
  50     /// ```
  51     pub struct __m64(i64);
  52
  53     /// 128-bit wide integer vector type, x86-specific
  54     ///
  55     /// This type is the same as the `__m128i` type defined by Intel,
  56     /// representing a 128-bit SIMD register. Usage of this type typically
  57     /// corresponds to the `sse` and up target features for x86/x86_64.
  58     ///
  59     /// Internally this type may be viewed as:
  60     ///
  61     /// * `i8x16` - sixteen `i8` variables packed together
  62     /// * `i16x8` - eight `i16` variables packed together
  63     /// * `i32x4` - four `i32` variables packed together
  64     /// * `i64x2` - two `i64` variables packed together
  65     ///
  66     /// (as well as unsigned versions). Each intrinsic may interpret the
  67     /// internal bits differently, check the documentation of the intrinsic
  68     /// to see how it's being used.
  69     ///
  70     /// Note that this means that an instance of `__m128i` typically just means
  71     /// a "bag of bits" which is left up to interpretation at the point of use.
  72     ///
  73     /// Most intrinsics using `__m128i` are prefixed with `_mm_` and the
  74     /// integer types tend to correspond to suffixes like "epi8" or "epi32".
  75     ///
  76     /// # Examples
  77     ///
  78     /// ```
  79     /// #[cfg(target_arch = "x86")]
  80     /// use std::arch::x86::*;
  81     /// #[cfg(target_arch = "x86_64")]
  82     /// use std::arch::x86_64::*;
  83     ///
  84     /// # fn main() {
  85     /// # #[target_feature(enable = "sse2")]
  86     /// # unsafe fn foo() {
  87     /// let all_bytes_zero = _mm_setzero_si128();
  88     /// let all_bytes_one = _mm_set1_epi8(1);
  89     /// let four_i32 = _mm_set_epi32(1, 2, 3, 4);
  90     /// # }
  91     /// # if is_x86_feature_detected!("sse2") { unsafe { foo() } }
  92     /// # }
  93     /// ```
  94     #[stable(feature = "simd_x86", since = "1.27.0")]
  95     pub struct __m128i(i64, i64);
  96
  97     /// 128-bit wide set of four `f32` types, x86-specific
  98     ///
  99     /// This type is the same as the `__m128` type defined by Intel,
 100     /// representing a 128-bit SIMD register which internally is consisted of
 101     /// four packed `f32` instances. Usage of this type typically corresponds
 102     /// to the `sse` and up target features for x86/x86_64.
 103     ///
 104     /// Note that unlike `__m128i`, the integer version of the 128-bit
 105     /// registers, this `__m128` type has *one* interpretation. Each instance
 106     /// of `__m128` always corresponds to `f32x4`, or four `f32` types packed
 107     /// together.
 108     ///
 109     /// Most intrinsics using `__m128` are prefixed with `_mm_` and are
 110     /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
 111     /// "pd" which is used for `__m128d`.
 112     ///
 113     /// # Examples
 114     ///
 115     /// ```
 116     /// #[cfg(target_arch = "x86")]
 117     /// use std::arch::x86::*;
 118     /// #[cfg(target_arch = "x86_64")]
 119     /// use std::arch::x86_64::*;
 120     ///
 121     /// # fn main() {
 122     /// # #[target_feature(enable = "sse")]
 123     /// # unsafe fn foo() {
 124     /// let four_zeros = _mm_setzero_ps();
 125     /// let four_ones = _mm_set1_ps(1.0);
 126     /// let four_floats = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
 127     /// # }
 128     /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
 129     /// # }
 130     /// ```
 131     #[stable(feature = "simd_x86", since = "1.27.0")]
 132     pub struct __m128(f32, f32, f32, f32);
 133
 134     /// 128-bit wide set of two `f64` types, x86-specific
 135     ///
 136     /// This type is the same as the `__m128d` type defined by Intel,
 137     /// representing a 128-bit SIMD register which internally is consisted of
 138     /// two packed `f64` instances. Usage of this type typically corresponds
 139     /// to the `sse` and up target features for x86/x86_64.
 140     ///
 141     /// Note that unlike `__m128i`, the integer version of the 128-bit
 142     /// registers, this `__m128d` type has *one* interpretation. Each instance
 143     /// of `__m128d` always corresponds to `f64x2`, or two `f64` types packed
 144     /// together.
 145     ///
 146     /// Most intrinsics using `__m128d` are prefixed with `_mm_` and are
 147     /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
 148     /// "ps" which is used for `__m128`.
 149     ///
 150     /// # Examples
 151     ///
 152     /// ```
 153     /// #[cfg(target_arch = "x86")]
 154     /// use std::arch::x86::*;
 155     /// #[cfg(target_arch = "x86_64")]
 156     /// use std::arch::x86_64::*;
 157     ///
 158     /// # fn main() {
 159     /// # #[target_feature(enable = "sse")]
 160     /// # unsafe fn foo() {
 161     /// let two_zeros = _mm_setzero_pd();
 162     /// let two_ones = _mm_set1_pd(1.0);
 163     /// let two_floats = _mm_set_pd(1.0, 2.0);
 164     /// # }
 165     /// # if is_x86_feature_detected!("sse") { unsafe { foo() } }
 166     /// # }
 167     /// ```
 168     #[stable(feature = "simd_x86", since = "1.27.0")]
 169     pub struct __m128d(f64, f64);
 170
 171     /// 256-bit wide integer vector type, x86-specific
 172     ///
 173     /// This type is the same as the `__m256i` type defined by Intel,
 174     /// representing a 256-bit SIMD register. Usage of this type typically
 175     /// corresponds to the `avx` and up target features for x86/x86_64.
 176     ///
 177     /// Internally this type may be viewed as:
 178     ///
 179     /// * `i8x32` - thirty two `i8` variables packed together
 180     /// * `i16x16` - sixteen `i16` variables packed together
 181     /// * `i32x8` - eight `i32` variables packed together
 182     /// * `i64x4` - four `i64` variables packed together
 183     ///
 184     /// (as well as unsigned versions). Each intrinsic may interpret the
 185     /// internal bits differently, check the documentation of the intrinsic
 186     /// to see how it's being used.
 187     ///
 188     /// Note that this means that an instance of `__m256i` typically just means
 189     /// a "bag of bits" which is left up to interpretation at the point of use.
 190     ///
 191     /// # Examples
 192     ///
 193     /// ```
 194     /// #[cfg(target_arch = "x86")]
 195     /// use std::arch::x86::*;
 196     /// #[cfg(target_arch = "x86_64")]
 197     /// use std::arch::x86_64::*;
 198     ///
 199     /// # fn main() {
 200     /// # #[target_feature(enable = "avx")]
 201     /// # unsafe fn foo() {
 202     /// let all_bytes_zero = _mm256_setzero_si256();
 203     /// let all_bytes_one = _mm256_set1_epi8(1);
 204     /// let eight_i32 = _mm256_set_epi32(1, 2, 3, 4, 5, 6, 7, 8);
 205     /// # }
 206     /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
 207     /// # }
 208     /// ```
 209     #[stable(feature = "simd_x86", since = "1.27.0")]
 210     pub struct __m256i(i64, i64, i64, i64);
 211
 212     /// 256-bit wide set of eight `f32` types, x86-specific
 213     ///
 214     /// This type is the same as the `__m256` type defined by Intel,
 215     /// representing a 256-bit SIMD register which internally is consisted of
 216     /// eight packed `f32` instances. Usage of this type typically corresponds
 217     /// to the `avx` and up target features for x86/x86_64.
 218     ///
 219     /// Note that unlike `__m256i`, the integer version of the 256-bit
 220     /// registers, this `__m256` type has *one* interpretation. Each instance
 221     /// of `__m256` always corresponds to `f32x8`, or eight `f32` types packed
 222     /// together.
 223     ///
 224     /// Most intrinsics using `__m256` are prefixed with `_mm256_` and are
 225     /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
 226     /// "pd" which is used for `__m256d`.
 227     ///
 228     /// # Examples
 229     ///
 230     /// ```
 231     /// #[cfg(target_arch = "x86")]
 232     /// use std::arch::x86::*;
 233     /// #[cfg(target_arch = "x86_64")]
 234     /// use std::arch::x86_64::*;
 235     ///
 236     /// # fn main() {
 237     /// # #[target_feature(enable = "avx")]
 238     /// # unsafe fn foo() {
 239     /// let eight_zeros = _mm256_setzero_ps();
 240     /// let eight_ones = _mm256_set1_ps(1.0);
 241     /// let eight_floats = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
 242     /// # }
 243     /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
 244     /// # }
 245     /// ```
 246     #[stable(feature = "simd_x86", since = "1.27.0")]
 247     pub struct __m256(f32, f32, f32, f32, f32, f32, f32, f32);
 248
 249     /// 256-bit wide set of four `f64` types, x86-specific
 250     ///
 251     /// This type is the same as the `__m256d` type defined by Intel,
 252     /// representing a 256-bit SIMD register which internally is consisted of
 253     /// four packed `f64` instances. Usage of this type typically corresponds
 254     /// to the `avx` and up target features for x86/x86_64.
 255     ///
 256     /// Note that unlike `__m256i`, the integer version of the 256-bit
 257     /// registers, this `__m256d` type has *one* interpretation. Each instance
 258     /// of `__m256d` always corresponds to `f64x4`, or four `f64` types packed
 259     /// together.
 260     ///
 261     /// Most intrinsics using `__m256d` are prefixed with `_mm256_` and are
 262     /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
 263     /// "ps" which is used for `__m256`.
 264     ///
 265     /// # Examples
 266     ///
 267     /// ```
 268     /// #[cfg(target_arch = "x86")]
 269     /// use std::arch::x86::*;
 270     /// #[cfg(target_arch = "x86_64")]
 271     /// use std::arch::x86_64::*;
 272     ///
 273     /// # fn main() {
 274     /// # #[target_feature(enable = "avx")]
 275     /// # unsafe fn foo() {
 276     /// let four_zeros = _mm256_setzero_pd();
 277     /// let four_ones = _mm256_set1_pd(1.0);
 278     /// let four_floats = _mm256_set_pd(1.0, 2.0, 3.0, 4.0);
 279     /// # }
 280     /// # if is_x86_feature_detected!("avx") { unsafe { foo() } }
 281     /// # }
 282     /// ```
 283     #[stable(feature = "simd_x86", since = "1.27.0")]
 284     pub struct __m256d(f64, f64, f64, f64);
 285
 286     /// 512-bit wide integer vector type, x86-specific
 287     ///
 288     /// This type is the same as the `__m512i` type defined by Intel,
 289     /// representing a 512-bit SIMD register. Usage of this type typically
 290     /// corresponds to the `avx512*` and up target features for x86/x86_64.
 291     ///
 292     /// Internally this type may be viewed as:
 293     ///
 294     /// * `i8x64` - sixty-four `i8` variables packed together
 295     /// * `i16x32` - thirty-two `i16` variables packed together
 296     /// * `i32x16` - sixteen `i32` variables packed together
 297     /// * `i64x8` - eight `i64` variables packed together
 298     ///
 299     /// (as well as unsigned versions). Each intrinsic may interpret the
 300     /// internal bits differently, check the documentation of the intrinsic
 301     /// to see how it's being used.
 302     ///
 303     /// Note that this means that an instance of `__m512i` typically just means
 304     /// a "bag of bits" which is left up to interpretation at the point of use.
 305     pub struct __m512i(i64, i64, i64, i64, i64, i64, i64, i64);
 306
 307     /// 512-bit wide set of sixteen `f32` types, x86-specific
 308     ///
 309     /// This type is the same as the `__m512` type defined by Intel,
 310     /// representing a 512-bit SIMD register which internally is consisted of
 311     /// eight packed `f32` instances. Usage of this type typically corresponds
 312     /// to the `avx512*` and up target features for x86/x86_64.
 313     ///
 314     /// Note that unlike `__m512i`, the integer version of the 512-bit
 315     /// registers, this `__m512` type has *one* interpretation. Each instance
 316     /// of `__m512` always corresponds to `f32x16`, or sixteen `f32` types
 317     /// packed together.
 318     ///
 319     /// Most intrinsics using `__m512` are prefixed with `_mm512_` and are
 320     /// suffixed with "ps" (or otherwise contain "ps"). Not to be confused with
 321     /// "pd" which is used for `__m512d`.
 322     pub struct __m512(
 323         f32, f32, f32, f32, f32, f32, f32, f32,
 324         f32, f32, f32, f32, f32, f32, f32, f32,
 325     );
 326
 327     /// 512-bit wide set of eight `f64` types, x86-specific
 328     ///
 329     /// This type is the same as the `__m512d` type defined by Intel,
 330     /// representing a 512-bit SIMD register which internally is consisted of
 331     /// eight packed `f64` instances. Usage of this type typically corresponds
 332     /// to the `avx` and up target features for x86/x86_64.
 333     ///
 334     /// Note that unlike `__m512i`, the integer version of the 512-bit
 335     /// registers, this `__m512d` type has *one* interpretation. Each instance
 336     /// of `__m512d` always corresponds to `f64x4`, or eight `f64` types packed
 337     /// together.
 338     ///
 339     /// Most intrinsics using `__m512d` are prefixed with `_mm512_` and are
 340     /// suffixed with "pd" (or otherwise contain "pd"). Not to be confused with
 341     /// "ps" which is used for `__m512`.
 342     pub struct __m512d(f64, f64, f64, f64, f64, f64, f64, f64);
 343 }
 344
 345 /// The `__mmask16` type used in AVX-512 intrinsics, a 16-bit integer
 346 #[allow(non_camel_case_types)]
 347 pub type __mmask16 = u16;
 348
 349 /// The `__mmask8` type used in AVX-512 intrinsics, a 8-bit integer
 350 #[allow(non_camel_case_types)]
 351 pub type __mmask8 = u8;
 352
 353 /// The `_MM_CMPINT_ENUM` type used to specify comparison operations in AVX-512 intrinsics.
 354 #[allow(non_camel_case_types)]
 355 pub type _MM_CMPINT_ENUM = i32;
 356
 357 #[cfg(test)]
 358 mod test;
 359 #[cfg(test)]
 360 pub use self::test::*;
 361
 362 #[allow(non_camel_case_types)]
 363 #[unstable(feature = "stdimd_internal", issue = "none")]
 364 pub(crate) trait m64Ext: Sized {
 365     fn as_m64(self) -> __m64;
 366
 367     #[inline]
 368     fn as_u8x8(self) -> crate::core_arch::simd::u8x8 {
 369         unsafe { transmute(self.as_m64()) }
 370     }
 371
 372     #[inline]
 373     fn as_u16x4(self) -> crate::core_arch::simd::u16x4 {
 374         unsafe { transmute(self.as_m64()) }
 375     }
 376
 377     #[inline]
 378     fn as_u32x2(self) -> crate::core_arch::simd::u32x2 {
 379         unsafe { transmute(self.as_m64()) }
 380     }
 381
 382     #[inline]
 383     fn as_i8x8(self) -> crate::core_arch::simd::i8x8 {
 384         unsafe { transmute(self.as_m64()) }
 385     }
 386
 387     #[inline]
 388     fn as_i16x4(self) -> crate::core_arch::simd::i16x4 {
 389         unsafe { transmute(self.as_m64()) }
 390     }
 391
 392     #[inline]
 393     fn as_i32x2(self) -> crate::core_arch::simd::i32x2 {
 394         unsafe { transmute(self.as_m64()) }
 395     }
 396 }
 397
 398 impl m64Ext for __m64 {
 399     #[inline]
 400     fn as_m64(self) -> Self {
 401         self
 402     }
 403 }
 404
 405 #[allow(non_camel_case_types)]
 406 #[unstable(feature = "stdimd_internal", issue = "none")]
 407 pub(crate) trait m128iExt: Sized {
 408     fn as_m128i(self) -> __m128i;
 409
 410     #[inline]
 411     fn as_u8x16(self) -> crate::core_arch::simd::u8x16 {
 412         unsafe { transmute(self.as_m128i()) }
 413     }
 414
 415     #[inline]
 416     fn as_u16x8(self) -> crate::core_arch::simd::u16x8 {
 417         unsafe { transmute(self.as_m128i()) }
 418     }
 419
 420     #[inline]
 421     fn as_u32x4(self) -> crate::core_arch::simd::u32x4 {
 422         unsafe { transmute(self.as_m128i()) }
 423     }
 424
 425     #[inline]
 426     fn as_u64x2(self) -> crate::core_arch::simd::u64x2 {
 427         unsafe { transmute(self.as_m128i()) }
 428     }
 429
 430     #[inline]
 431     fn as_i8x16(self) -> crate::core_arch::simd::i8x16 {
 432         unsafe { transmute(self.as_m128i()) }
 433     }
 434
 435     #[inline]
 436     fn as_i16x8(self) -> crate::core_arch::simd::i16x8 {
 437         unsafe { transmute(self.as_m128i()) }
 438     }
 439
 440     #[inline]
 441     fn as_i32x4(self) -> crate::core_arch::simd::i32x4 {
 442         unsafe { transmute(self.as_m128i()) }
 443     }
 444
 445     #[inline]
 446     fn as_i64x2(self) -> crate::core_arch::simd::i64x2 {
 447         unsafe { transmute(self.as_m128i()) }
 448     }
 449 }
 450
 451 impl m128iExt for __m128i {
 452     #[inline]
 453     fn as_m128i(self) -> Self {
 454         self
 455     }
 456 }
 457
 458 #[allow(non_camel_case_types)]
 459 #[unstable(feature = "stdimd_internal", issue = "none")]
 460 pub(crate) trait m256iExt: Sized {
 461     fn as_m256i(self) -> __m256i;
 462
 463     #[inline]
 464     fn as_u8x32(self) -> crate::core_arch::simd::u8x32 {
 465         unsafe { transmute(self.as_m256i()) }
 466     }
 467
 468     #[inline]
 469     fn as_u16x16(self) -> crate::core_arch::simd::u16x16 {
 470         unsafe { transmute(self.as_m256i()) }
 471     }
 472
 473     #[inline]
 474     fn as_u32x8(self) -> crate::core_arch::simd::u32x8 {
 475         unsafe { transmute(self.as_m256i()) }
 476     }
 477
 478     #[inline]
 479     fn as_u64x4(self) -> crate::core_arch::simd::u64x4 {
 480         unsafe { transmute(self.as_m256i()) }
 481     }
 482
 483     #[inline]
 484     fn as_i8x32(self) -> crate::core_arch::simd::i8x32 {
 485         unsafe { transmute(self.as_m256i()) }
 486     }
 487
 488     #[inline]
 489     fn as_i16x16(self) -> crate::core_arch::simd::i16x16 {
 490         unsafe { transmute(self.as_m256i()) }
 491     }
 492
 493     #[inline]
 494     fn as_i32x8(self) -> crate::core_arch::simd::i32x8 {
 495         unsafe { transmute(self.as_m256i()) }
 496     }
 497
 498     #[inline]
 499     fn as_i64x4(self) -> crate::core_arch::simd::i64x4 {
 500         unsafe { transmute(self.as_m256i()) }
 501     }
 502 }
 503
 504 impl m256iExt for __m256i {
 505     #[inline]
 506     fn as_m256i(self) -> Self {
 507         self
 508     }
 509 }
 510
 511 #[allow(non_camel_case_types)]
 512 #[unstable(feature = "stdimd_internal", issue = "none")]
 513 pub(crate) trait m256Ext: Sized {
 514     fn as_m256(self) -> __m256;
 515
 516     #[inline]
 517     fn as_f32x8(self) -> crate::core_arch::simd::f32x8 {
 518         unsafe { transmute(self.as_m256()) }
 519     }
 520 }
 521
 522 impl m256Ext for __m256 {
 523     #[inline]
 524     fn as_m256(self) -> Self {
 525         self
 526     }
 527 }
 528
 529 #[allow(non_camel_case_types)]
 530 #[unstable(feature = "stdimd_internal", issue = "none")]
 531 pub(crate) trait m512iExt: Sized {
 532     fn as_m512i(self) -> __m512i;
 533
 534     #[inline]
 535     fn as_u32x16(self) -> crate::core_arch::simd::u32x16 {
 536         unsafe { transmute(self.as_m512i()) }
 537     }
 538
 539     #[inline]
 540     fn as_i32x16(self) -> crate::core_arch::simd::i32x16 {
 541         unsafe { transmute(self.as_m512i()) }
 542     }
 543
 544     #[inline]
 545     fn as_u64x8(self) -> crate::core_arch::simd::u64x8 {
 546         unsafe { transmute(self.as_m512i()) }
 547     }
 548
 549     #[inline]
 550     fn as_i64x8(self) -> crate::core_arch::simd::i64x8 {
 551         unsafe { transmute(self.as_m512i()) }
 552     }
 553 }
 554
 555 impl m512iExt for __m512i {
 556     #[inline]
 557     fn as_m512i(self) -> Self {
 558         self
 559     }
 560 }
 561
 562 #[allow(non_camel_case_types)]
 563 #[unstable(feature = "stdimd_internal", issue = "none")]
 564 pub(crate) trait m512Ext: Sized {
 565     fn as_m512(self) -> __m512;
 566
 567     #[inline]
 568     fn as_f32x16(self) -> crate::core_arch::simd::f32x16 {
 569         unsafe { transmute(self.as_m512()) }
 570     }
 571 }
 572
 573 impl m512Ext for __m512 {
 574     #[inline]
 575     fn as_m512(self) -> Self {
 576         self
 577     }
 578 }
 579
 580 #[allow(non_camel_case_types)]
 581 #[unstable(feature = "stdimd_internal", issue = "none")]
 582 pub(crate) trait m512dExt: Sized {
 583     fn as_m512d(self) -> __m512d;
 584
 585     #[inline]
 586     fn as_f64x8(self) -> crate::core_arch::simd::f64x8 {
 587         unsafe { transmute(self.as_m512d()) }
 588     }
 589 }
 590
 591 impl m512dExt for __m512d {
 592     #[inline]
 593     fn as_m512d(self) -> Self {
 594         self
 595     }
 596 }
 597
 598 mod eflags;
 599 pub use self::eflags::*;
 600
 601 mod fxsr;
 602 pub use self::fxsr::*;
 603
 604 mod bswap;
 605 pub use self::bswap::*;
 606
 607 mod rdtsc;
 608 pub use self::rdtsc::*;
 609
 610 mod cpuid;
 611 pub use self::cpuid::*;
 612 mod xsave;
 613 pub use self::xsave::*;
 614
 615 mod sse;
 616 pub use self::sse::*;
 617 mod sse2;
 618 pub use self::sse2::*;
 619 mod sse3;
 620 pub use self::sse3::*;
 621 mod ssse3;
 622 pub use self::ssse3::*;
 623 mod sse41;
 624 pub use self::sse41::*;
 625 mod sse42;
 626 pub use self::sse42::*;
 627 mod avx;
 628 pub use self::avx::*;
 629 mod avx2;
 630 pub use self::avx2::*;
 631 mod fma;
 632 pub use self::fma::*;
 633
 634 mod abm;
 635 pub use self::abm::*;
 636 mod bmi1;
 637 pub use self::bmi1::*;
 638
 639 mod bmi2;
 640 pub use self::bmi2::*;
 641
 642 #[cfg(not(stdarch_intel_sde))]
 643 mod sse4a;
 644 #[cfg(not(stdarch_intel_sde))]
 645 pub use self::sse4a::*;
 646
 647 #[cfg(not(stdarch_intel_sde))]
 648 mod tbm;
 649 #[cfg(not(stdarch_intel_sde))]
 650 pub use self::tbm::*;
 651
 652 mod mmx;
 653 pub use self::mmx::*;
 654
 655 mod pclmulqdq;
 656 pub use self::pclmulqdq::*;
 657
 658 mod aes;
 659 pub use self::aes::*;
 660
 661 mod rdrand;
 662 pub use self::rdrand::*;
 663
 664 mod sha;
 665 pub use self::sha::*;
 666
 667 mod adx;
 668 pub use self::adx::*;
 669
 670 #[cfg(test)]
 671 use stdarch_test::assert_instr;
 672
 673 /// Generates the trap instruction `UD2`
 674 #[cfg_attr(test, assert_instr(ud2))]
 675 #[inline]
 676 pub unsafe fn ud2() -> ! {
 677     intrinsics::abort()
 678 }
 679
 680 mod avx512f;
 681 pub use self::avx512f::*;
 682
 683 mod avx512ifma;
 684 pub use self::avx512ifma::*;
 685
 686 mod bt;
 687 pub use self::bt::*;
 688
 689 mod rtm;
 690 pub use self::rtm::*;
 691
 692 mod f16c;
 693 pub use self::f16c::*;