linux-headers/asm-riscv/kvm.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
   4  *
   5  * Authors:
   6  *     Anup Patel <anup.patel@wdc.com>
   7  */
   8
   9 #ifndef __LINUX_KVM_RISCV_H
  10 #define __LINUX_KVM_RISCV_H
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <linux/types.h>
  15 #include <asm/ptrace.h>
  16
  17 #define __KVM_HAVE_READONLY_MEM
  18
  19 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  20
  21 #define KVM_INTERRUPT_SET       -1U
  22 #define KVM_INTERRUPT_UNSET     -2U
  23
  24 /* for KVM_GET_REGS and KVM_SET_REGS */
  25 struct kvm_regs {
  26 };
  27
  28 /* for KVM_GET_FPU and KVM_SET_FPU */
  29 struct kvm_fpu {
  30 };
  31
  32 /* KVM Debug exit structure */
  33 struct kvm_debug_exit_arch {
  34 };
  35
  36 /* for KVM_SET_GUEST_DEBUG */
  37 struct kvm_guest_debug_arch {
  38 };
  39
  40 /* definition of registers in kvm_run */
  41 struct kvm_sync_regs {
  42 };
  43
  44 /* for KVM_GET_SREGS and KVM_SET_SREGS */
  45 struct kvm_sregs {
  46 };
  47
  48 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  49 struct kvm_riscv_config {
  50         unsigned long isa;
  51         unsigned long zicbom_block_size;
  52         unsigned long mvendorid;
  53         unsigned long marchid;
  54         unsigned long mimpid;
  55 };
  56
  57 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  58 struct kvm_riscv_core {
  59         struct user_regs_struct regs;
  60         unsigned long mode;
  61 };
  62
  63 /* Possible privilege modes for kvm_riscv_core */
  64 #define KVM_RISCV_MODE_S        1
  65 #define KVM_RISCV_MODE_U        0
  66
  67 /* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  68 struct kvm_riscv_csr {
  69         unsigned long sstatus;
  70         unsigned long sie;
  71         unsigned long stvec;
  72         unsigned long sscratch;
  73         unsigned long sepc;
  74         unsigned long scause;
  75         unsigned long stval;
  76         unsigned long sip;
  77         unsigned long satp;
  78         unsigned long scounteren;
  79 };
  80
  81 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  82 struct kvm_riscv_timer {
  83         __u64 frequency;
  84         __u64 time;
  85         __u64 compare;
  86         __u64 state;
  87 };
  88
  89 /*
  90  * ISA extension IDs specific to KVM. This is not the same as the host ISA
  91  * extension IDs as that is internal to the host and should not be exposed
  92  * to the guest. This should always be contiguous to keep the mapping simple
  93  * in KVM implementation.
  94  */
  95 enum KVM_RISCV_ISA_EXT_ID {
  96         KVM_RISCV_ISA_EXT_A = 0,
  97         KVM_RISCV_ISA_EXT_C,
  98         KVM_RISCV_ISA_EXT_D,
  99         KVM_RISCV_ISA_EXT_F,
 100         KVM_RISCV_ISA_EXT_H,
 101         KVM_RISCV_ISA_EXT_I,
 102         KVM_RISCV_ISA_EXT_M,
 103         KVM_RISCV_ISA_EXT_SVPBMT,
 104         KVM_RISCV_ISA_EXT_SSTC,
 105         KVM_RISCV_ISA_EXT_SVINVAL,
 106         KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
 107         KVM_RISCV_ISA_EXT_ZICBOM,
 108         KVM_RISCV_ISA_EXT_MAX,
 109 };
 110
 111 /* Possible states for kvm_riscv_timer */
 112 #define KVM_RISCV_TIMER_STATE_OFF       0
 113 #define KVM_RISCV_TIMER_STATE_ON        1
 114
 115 #define KVM_REG_SIZE(id)                \
 116         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
 117
 118 /* If you need to interpret the index values, here is the key: */
 119 #define KVM_REG_RISCV_TYPE_MASK         0x00000000FF000000
 120 #define KVM_REG_RISCV_TYPE_SHIFT        24
 121
 122 /* Config registers are mapped as type 1 */
 123 #define KVM_REG_RISCV_CONFIG            (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
 124 #define KVM_REG_RISCV_CONFIG_REG(name)  \
 125         (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
 126
 127 /* Core registers are mapped as type 2 */
 128 #define KVM_REG_RISCV_CORE              (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
 129 #define KVM_REG_RISCV_CORE_REG(name)    \
 130                 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
 131
 132 /* Control and status registers are mapped as type 3 */
 133 #define KVM_REG_RISCV_CSR               (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
 134 #define KVM_REG_RISCV_CSR_REG(name)     \
 135                 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
 136
 137 /* Timer registers are mapped as type 4 */
 138 #define KVM_REG_RISCV_TIMER             (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
 139 #define KVM_REG_RISCV_TIMER_REG(name)   \
 140                 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
 141
 142 /* F extension registers are mapped as type 5 */
 143 #define KVM_REG_RISCV_FP_F              (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
 144 #define KVM_REG_RISCV_FP_F_REG(name)    \
 145                 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
 146
 147 /* D extension registers are mapped as type 6 */
 148 #define KVM_REG_RISCV_FP_D              (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
 149 #define KVM_REG_RISCV_FP_D_REG(name)    \
 150                 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
 151
 152 /* ISA Extension registers are mapped as type 7 */
 153 #define KVM_REG_RISCV_ISA_EXT           (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
 154
 155 #endif
 156
 157 #endif /* __LINUX_KVM_RISCV_H */