linux-headers/asm-riscv/kvm.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
   4  *
   5  * Authors:
   6  *     Anup Patel <anup.patel@wdc.com>
   7  */
   8
   9 #ifndef __LINUX_KVM_RISCV_H
  10 #define __LINUX_KVM_RISCV_H
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <linux/types.h>
  15 #include <asm/bitsperlong.h>
  16 #include <asm/ptrace.h>
  17
  18 #define __KVM_HAVE_IRQ_LINE
  19 #define __KVM_HAVE_READONLY_MEM
  20
  21 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  22
  23 #define KVM_INTERRUPT_SET       -1U
  24 #define KVM_INTERRUPT_UNSET     -2U
  25
  26 /* for KVM_GET_REGS and KVM_SET_REGS */
  27 struct kvm_regs {
  28 };
  29
  30 /* for KVM_GET_FPU and KVM_SET_FPU */
  31 struct kvm_fpu {
  32 };
  33
  34 /* KVM Debug exit structure */
  35 struct kvm_debug_exit_arch {
  36 };
  37
  38 /* for KVM_SET_GUEST_DEBUG */
  39 struct kvm_guest_debug_arch {
  40 };
  41
  42 /* definition of registers in kvm_run */
  43 struct kvm_sync_regs {
  44 };
  45
  46 /* for KVM_GET_SREGS and KVM_SET_SREGS */
  47 struct kvm_sregs {
  48 };
  49
  50 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  51 struct kvm_riscv_config {
  52         unsigned long isa;
  53         unsigned long zicbom_block_size;
  54         unsigned long mvendorid;
  55         unsigned long marchid;
  56         unsigned long mimpid;
  57         unsigned long zicboz_block_size;
  58         unsigned long satp_mode;
  59 };
  60
  61 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  62 struct kvm_riscv_core {
  63         struct user_regs_struct regs;
  64         unsigned long mode;
  65 };
  66
  67 /* Possible privilege modes for kvm_riscv_core */
  68 #define KVM_RISCV_MODE_S        1
  69 #define KVM_RISCV_MODE_U        0
  70
  71 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  72 struct kvm_riscv_csr {
  73         unsigned long sstatus;
  74         unsigned long sie;
  75         unsigned long stvec;
  76         unsigned long sscratch;
  77         unsigned long sepc;
  78         unsigned long scause;
  79         unsigned long stval;
  80         unsigned long sip;
  81         unsigned long satp;
  82         unsigned long scounteren;
  83 };
  84
  85 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  86 struct kvm_riscv_aia_csr {
  87         unsigned long siselect;
  88         unsigned long iprio1;
  89         unsigned long iprio2;
  90         unsigned long sieh;
  91         unsigned long siph;
  92         unsigned long iprio1h;
  93         unsigned long iprio2h;
  94 };
  95
  96 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  97 struct kvm_riscv_timer {
  98         __u64 frequency;
  99         __u64 time;
 100         __u64 compare;
 101         __u64 state;
 102 };
 103
 104 /*
 105  * ISA extension IDs specific to KVM. This is not the same as the host ISA
 106  * extension IDs as that is internal to the host and should not be exposed
 107  * to the guest. This should always be contiguous to keep the mapping simple
 108  * in KVM implementation.
 109  */
 110 enum KVM_RISCV_ISA_EXT_ID {
 111         KVM_RISCV_ISA_EXT_A = 0,
 112         KVM_RISCV_ISA_EXT_C,
 113         KVM_RISCV_ISA_EXT_D,
 114         KVM_RISCV_ISA_EXT_F,
 115         KVM_RISCV_ISA_EXT_H,
 116         KVM_RISCV_ISA_EXT_I,
 117         KVM_RISCV_ISA_EXT_M,
 118         KVM_RISCV_ISA_EXT_SVPBMT,
 119         KVM_RISCV_ISA_EXT_SSTC,
 120         KVM_RISCV_ISA_EXT_SVINVAL,
 121         KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
 122         KVM_RISCV_ISA_EXT_ZICBOM,
 123         KVM_RISCV_ISA_EXT_ZICBOZ,
 124         KVM_RISCV_ISA_EXT_ZBB,
 125         KVM_RISCV_ISA_EXT_SSAIA,
 126         KVM_RISCV_ISA_EXT_V,
 127         KVM_RISCV_ISA_EXT_SVNAPOT,
 128         KVM_RISCV_ISA_EXT_ZBA,
 129         KVM_RISCV_ISA_EXT_ZBS,
 130         KVM_RISCV_ISA_EXT_ZICNTR,
 131         KVM_RISCV_ISA_EXT_ZICSR,
 132         KVM_RISCV_ISA_EXT_ZIFENCEI,
 133         KVM_RISCV_ISA_EXT_ZIHPM,
 134         KVM_RISCV_ISA_EXT_MAX,
 135 };
 136
 137 /*
 138  * SBI extension IDs specific to KVM. This is not the same as the SBI
 139  * extension IDs defined by the RISC-V SBI specification.
 140  */
 141 enum KVM_RISCV_SBI_EXT_ID {
 142         KVM_RISCV_SBI_EXT_V01 = 0,
 143         KVM_RISCV_SBI_EXT_TIME,
 144         KVM_RISCV_SBI_EXT_IPI,
 145         KVM_RISCV_SBI_EXT_RFENCE,
 146         KVM_RISCV_SBI_EXT_SRST,
 147         KVM_RISCV_SBI_EXT_HSM,
 148         KVM_RISCV_SBI_EXT_PMU,
 149         KVM_RISCV_SBI_EXT_EXPERIMENTAL,
 150         KVM_RISCV_SBI_EXT_VENDOR,
 151         KVM_RISCV_SBI_EXT_MAX,
 152 };
 153
 154 /* Possible states for kvm_riscv_timer */
 155 #define KVM_RISCV_TIMER_STATE_OFF       0
 156 #define KVM_RISCV_TIMER_STATE_ON        1
 157
 158 #define KVM_REG_SIZE(id)                \
 159         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
 160
 161 /* If you need to interpret the index values, here is the key: */
 162 #define KVM_REG_RISCV_TYPE_MASK         0x00000000FF000000
 163 #define KVM_REG_RISCV_TYPE_SHIFT        24
 164 #define KVM_REG_RISCV_SUBTYPE_MASK      0x0000000000FF0000
 165 #define KVM_REG_RISCV_SUBTYPE_SHIFT     16
 166
 167 /* Config registers are mapped as type 1 */
 168 #define KVM_REG_RISCV_CONFIG            (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
 169 #define KVM_REG_RISCV_CONFIG_REG(name)  \
 170         (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
 171
 172 /* Core registers are mapped as type 2 */
 173 #define KVM_REG_RISCV_CORE              (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
 174 #define KVM_REG_RISCV_CORE_REG(name)    \
 175                 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
 176
 177 /* Control and status registers are mapped as type 3 */
 178 #define KVM_REG_RISCV_CSR               (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
 179 #define KVM_REG_RISCV_CSR_GENERAL       (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 180 #define KVM_REG_RISCV_CSR_AIA           (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 181 #define KVM_REG_RISCV_CSR_REG(name)     \
 182                 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
 183 #define KVM_REG_RISCV_CSR_AIA_REG(name) \
 184         (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
 185
 186 /* Timer registers are mapped as type 4 */
 187 #define KVM_REG_RISCV_TIMER             (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
 188 #define KVM_REG_RISCV_TIMER_REG(name)   \
 189                 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
 190
 191 /* F extension registers are mapped as type 5 */
 192 #define KVM_REG_RISCV_FP_F              (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
 193 #define KVM_REG_RISCV_FP_F_REG(name)    \
 194                 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
 195
 196 /* D extension registers are mapped as type 6 */
 197 #define KVM_REG_RISCV_FP_D              (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
 198 #define KVM_REG_RISCV_FP_D_REG(name)    \
 199                 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
 200
 201 /* ISA Extension registers are mapped as type 7 */
 202 #define KVM_REG_RISCV_ISA_EXT           (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
 203 #define KVM_REG_RISCV_ISA_SINGLE        (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 204 #define KVM_REG_RISCV_ISA_MULTI_EN      (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 205 #define KVM_REG_RISCV_ISA_MULTI_DIS     (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 206 #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id)   \
 207                 ((__ext_id) / __BITS_PER_LONG)
 208 #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id)  \
 209                 (1UL << ((__ext_id) % __BITS_PER_LONG))
 210 #define KVM_REG_RISCV_ISA_MULTI_REG_LAST        \
 211                 KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
 212
 213 /* SBI extension registers are mapped as type 8 */
 214 #define KVM_REG_RISCV_SBI_EXT           (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
 215 #define KVM_REG_RISCV_SBI_SINGLE        (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 216 #define KVM_REG_RISCV_SBI_MULTI_EN      (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 217 #define KVM_REG_RISCV_SBI_MULTI_DIS     (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
 218 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id)   \
 219                 ((__ext_id) / __BITS_PER_LONG)
 220 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id)  \
 221                 (1UL << ((__ext_id) % __BITS_PER_LONG))
 222 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST        \
 223                 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
 224
 225 /* V extension registers are mapped as type 9 */
 226 #define KVM_REG_RISCV_VECTOR            (0x09 << KVM_REG_RISCV_TYPE_SHIFT)
 227 #define KVM_REG_RISCV_VECTOR_CSR_REG(name)      \
 228                 (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
 229 #define KVM_REG_RISCV_VECTOR_REG(n)     \
 230                 ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
 231
 232 /* Device Control API: RISC-V AIA */
 233 #define KVM_DEV_RISCV_APLIC_ALIGN               0x1000
 234 #define KVM_DEV_RISCV_APLIC_SIZE                0x4000
 235 #define KVM_DEV_RISCV_APLIC_MAX_HARTS           0x4000
 236 #define KVM_DEV_RISCV_IMSIC_ALIGN               0x1000
 237 #define KVM_DEV_RISCV_IMSIC_SIZE                0x1000
 238
 239 #define KVM_DEV_RISCV_AIA_GRP_CONFIG            0
 240 #define KVM_DEV_RISCV_AIA_CONFIG_MODE           0
 241 #define KVM_DEV_RISCV_AIA_CONFIG_IDS            1
 242 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS           2
 243 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS     3
 244 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT    4
 245 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS      5
 246 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS     6
 247
 248 /*
 249  * Modes of RISC-V AIA device:
 250  * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
 251  * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
 252  * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
 253  *    available otherwise fallback to trap-n-emulation
 254  */
 255 #define KVM_DEV_RISCV_AIA_MODE_EMUL             0
 256 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL          1
 257 #define KVM_DEV_RISCV_AIA_MODE_AUTO             2
 258
 259 #define KVM_DEV_RISCV_AIA_IDS_MIN               63
 260 #define KVM_DEV_RISCV_AIA_IDS_MAX               2048
 261 #define KVM_DEV_RISCV_AIA_SRCS_MAX              1024
 262 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX        8
 263 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN       24
 264 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX       56
 265 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX         16
 266 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX        8
 267
 268 #define KVM_DEV_RISCV_AIA_GRP_ADDR              1
 269 #define KVM_DEV_RISCV_AIA_ADDR_APLIC            0
 270 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu)    (1 + (__vcpu))
 271 #define KVM_DEV_RISCV_AIA_ADDR_MAX              \
 272                 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
 273
 274 #define KVM_DEV_RISCV_AIA_GRP_CTRL              2
 275 #define KVM_DEV_RISCV_AIA_CTRL_INIT             0
 276
 277 /*
 278  * The device attribute type contains the memory mapped offset of the
 279  * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
 280  */
 281 #define KVM_DEV_RISCV_AIA_GRP_APLIC             3
 282
 283 /*
 284  * The lower 12-bits of the device attribute type contains the iselect
 285  * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
 286  * bits contains the VCPU id.
 287  */
 288 #define KVM_DEV_RISCV_AIA_GRP_IMSIC             4
 289 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS       12
 290 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK       \
 291                 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
 292 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel)  \
 293                 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
 294                  ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
 295 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr)        \
 296                 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
 297 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr)        \
 298                 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
 299
 300 /* One single KVM irqchip, ie. the AIA */
 301 #define KVM_NR_IRQCHIPS                 1
 302
 303 #endif
 304
 305 #endif /* __LINUX_KVM_RISCV_H */