linux-user/aarch64/cpu_loop.c

   1 /*
   2  *  qemu user cpu loop
   3  *
   4  *  Copyright (c) 2003-2008 Fabrice Bellard
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "qemu.h"
  23 #include "cpu_loop-common.h"
  24 #include "qemu/guest-random.h"
  25 #include "hw/semihosting/common-semi.h"
  26 #include "target/arm/syndrome.h"
  27
  28 #define get_user_code_u32(x, gaddr, env)                \
  29     ({ abi_long __r = get_user_u32((x), (gaddr));       \
  30         if (!__r && bswap_code(arm_sctlr_b(env))) {     \
  31             (x) = bswap32(x);                           \
  32         }                                               \
  33         __r;                                            \
  34     })
  35
  36 #define get_user_code_u16(x, gaddr, env)                \
  37     ({ abi_long __r = get_user_u16((x), (gaddr));       \
  38         if (!__r && bswap_code(arm_sctlr_b(env))) {     \
  39             (x) = bswap16(x);                           \
  40         }                                               \
  41         __r;                                            \
  42     })
  43
  44 #define get_user_data_u32(x, gaddr, env)                \
  45     ({ abi_long __r = get_user_u32((x), (gaddr));       \
  46         if (!__r && arm_cpu_bswap_data(env)) {          \
  47             (x) = bswap32(x);                           \
  48         }                                               \
  49         __r;                                            \
  50     })
  51
  52 #define get_user_data_u16(x, gaddr, env)                \
  53     ({ abi_long __r = get_user_u16((x), (gaddr));       \
  54         if (!__r && arm_cpu_bswap_data(env)) {          \
  55             (x) = bswap16(x);                           \
  56         }                                               \
  57         __r;                                            \
  58     })
  59
  60 #define put_user_data_u32(x, gaddr, env)                \
  61     ({ typeof(x) __x = (x);                             \
  62         if (arm_cpu_bswap_data(env)) {                  \
  63             __x = bswap32(__x);                         \
  64         }                                               \
  65         put_user_u32(__x, (gaddr));                     \
  66     })
  67
  68 #define put_user_data_u16(x, gaddr, env)                \
  69     ({ typeof(x) __x = (x);                             \
  70         if (arm_cpu_bswap_data(env)) {                  \
  71             __x = bswap16(__x);                         \
  72         }                                               \
  73         put_user_u16(__x, (gaddr));                     \
  74     })
  75
  76 /* AArch64 main loop */
  77 void cpu_loop(CPUARMState *env)
  78 {
  79     CPUState *cs = env_cpu(env);
  80     int trapnr, ec, fsc;
  81     abi_long ret;
  82     target_siginfo_t info;
  83
  84     for (;;) {
  85         cpu_exec_start(cs);
  86         trapnr = cpu_exec(cs);
  87         cpu_exec_end(cs);
  88         process_queued_cpu_work(cs);
  89
  90         switch (trapnr) {
  91         case EXCP_SWI:
  92             ret = do_syscall(env,
  93                              env->xregs[8],
  94                              env->xregs[0],
  95                              env->xregs[1],
  96                              env->xregs[2],
  97                              env->xregs[3],
  98                              env->xregs[4],
  99                              env->xregs[5],
 100                              0, 0);
 101             if (ret == -TARGET_ERESTARTSYS) {
 102                 env->pc -= 4;
 103             } else if (ret != -TARGET_QEMU_ESIGRETURN) {
 104                 env->xregs[0] = ret;
 105             }
 106             break;
 107         case EXCP_INTERRUPT:
 108             /* just indicate that signals should be handled asap */
 109             break;
 110         case EXCP_UDEF:
 111             info.si_signo = TARGET_SIGILL;
 112             info.si_errno = 0;
 113             info.si_code = TARGET_ILL_ILLOPN;
 114             info._sifields._sigfault._addr = env->pc;
 115             queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
 116             break;
 117         case EXCP_PREFETCH_ABORT:
 118         case EXCP_DATA_ABORT:
 119             info.si_signo = TARGET_SIGSEGV;
 120             info.si_errno = 0;
 121             info._sifields._sigfault._addr = env->exception.vaddress;
 122
 123             /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
 124             ec = syn_get_ec(env->exception.syndrome);
 125             assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
 126
 127             /* Both EC have the same format for FSC, or close enough. */
 128             fsc = extract32(env->exception.syndrome, 0, 6);
 129             switch (fsc) {
 130             case 0x04 ... 0x07: /* Translation fault, level {0-3} */
 131                 info.si_code = TARGET_SEGV_MAPERR;
 132                 break;
 133             case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
 134             case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
 135                 info.si_code = TARGET_SEGV_ACCERR;
 136                 break;
 137             case 0x11: /* Synchronous Tag Check Fault */
 138                 info.si_code = TARGET_SEGV_MTESERR;
 139                 break;
 140             default:
 141                 g_assert_not_reached();
 142             }
 143
 144             queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
 145             break;
 146         case EXCP_DEBUG:
 147         case EXCP_BKPT:
 148             info.si_signo = TARGET_SIGTRAP;
 149             info.si_errno = 0;
 150             info.si_code = TARGET_TRAP_BRKPT;
 151             queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
 152             break;
 153         case EXCP_SEMIHOST:
 154             env->xregs[0] = do_common_semihosting(cs);
 155             env->pc += 4;
 156             break;
 157         case EXCP_YIELD:
 158             /* nothing to do here for user-mode, just resume guest code */
 159             break;
 160         case EXCP_ATOMIC:
 161             cpu_exec_step_atomic(cs);
 162             break;
 163         default:
 164             EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
 165             abort();
 166         }
 167
 168         /* Check for MTE asynchronous faults */
 169         if (unlikely(env->cp15.tfsr_el[0])) {
 170             env->cp15.tfsr_el[0] = 0;
 171             info.si_signo = TARGET_SIGSEGV;
 172             info.si_errno = 0;
 173             info._sifields._sigfault._addr = 0;
 174             info.si_code = TARGET_SEGV_MTEAERR;
 175             queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
 176         }
 177
 178         process_pending_signals(env);
 179         /* Exception return on AArch64 always clears the exclusive monitor,
 180          * so any return to running guest code implies this.
 181          */
 182         env->exclusive_addr = -1;
 183     }
 184 }
 185
 186 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
 187 {
 188     ARMCPU *cpu = env_archcpu(env);
 189     CPUState *cs = env_cpu(env);
 190     TaskState *ts = cs->opaque;
 191     struct image_info *info = ts->info;
 192     int i;
 193
 194     if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
 195         fprintf(stderr,
 196                 "The selected ARM CPU does not support 64 bit mode\n");
 197         exit(EXIT_FAILURE);
 198     }
 199
 200     for (i = 0; i < 31; i++) {
 201         env->xregs[i] = regs->regs[i];
 202     }
 203     env->pc = regs->pc;
 204     env->xregs[31] = regs->sp;
 205 #ifdef TARGET_WORDS_BIGENDIAN
 206     env->cp15.sctlr_el[1] |= SCTLR_E0E;
 207     for (i = 1; i < 4; ++i) {
 208         env->cp15.sctlr_el[i] |= SCTLR_EE;
 209     }
 210     arm_rebuild_hflags(env);
 211 #endif
 212
 213     if (cpu_isar_feature(aa64_pauth, cpu)) {
 214         qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
 215     }
 216
 217     ts->stack_base = info->start_stack;
 218     ts->heap_base = info->brk;
 219     /* This will be filled in on the first SYS_HEAPINFO call.  */
 220     ts->heap_limit = 0;
 221 }