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git.proxmox.com Git - mirror_qemu.git/blob - linux-user/arm/cpu_loop.c
4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
23 #include "user-internals.h"
25 #include "cpu_loop-common.h"
26 #include "signal-common.h"
27 #include "semihosting/common-semi.h"
28 #include "target/arm/syndrome.h"
30 #define get_user_code_u32(x, gaddr, env) \
31 ({ abi_long __r = get_user_u32((x), (gaddr)); \
32 if (!__r && bswap_code(arm_sctlr_b(env))) { \
38 #define get_user_code_u16(x, gaddr, env) \
39 ({ abi_long __r = get_user_u16((x), (gaddr)); \
40 if (!__r && bswap_code(arm_sctlr_b(env))) { \
46 #define get_user_data_u32(x, gaddr, env) \
47 ({ abi_long __r = get_user_u32((x), (gaddr)); \
48 if (!__r && arm_cpu_bswap_data(env)) { \
54 #define get_user_data_u16(x, gaddr, env) \
55 ({ abi_long __r = get_user_u16((x), (gaddr)); \
56 if (!__r && arm_cpu_bswap_data(env)) { \
62 #define put_user_data_u32(x, gaddr, env) \
63 ({ typeof(x) __x = (x); \
64 if (arm_cpu_bswap_data(env)) { \
67 put_user_u32(__x, (gaddr)); \
70 #define put_user_data_u16(x, gaddr, env) \
71 ({ typeof(x) __x = (x); \
72 if (arm_cpu_bswap_data(env)) { \
75 put_user_u16(__x, (gaddr)); \
78 /* Commpage handling -- there is no commpage for AArch64 */
81 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
83 * r0 = pointer to oldval
84 * r1 = pointer to newval
85 * r2 = pointer to target value
88 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
89 * C set if *ptr was changed, clear if no exchange happened
91 * Note segv's in kernel helpers are a bit tricky, we can set the
92 * data address sensibly but the PC address is just the entry point.
94 static void arm_kernel_cmpxchg64_helper(CPUARMState
*env
)
96 uint64_t oldval
, newval
, val
;
99 /* Based on the 32 bit code in do_kernel_trap */
101 /* XXX: This only works between threads, not between processes.
102 It's probably possible to implement this with native host
103 operations. However things like ldrex/strex are much harder so
104 there's not much point trying. */
106 cpsr
= cpsr_read(env
);
109 if (get_user_u64(oldval
, env
->regs
[0])) {
110 env
->exception
.vaddress
= env
->regs
[0];
114 if (get_user_u64(newval
, env
->regs
[1])) {
115 env
->exception
.vaddress
= env
->regs
[1];
119 if (get_user_u64(val
, addr
)) {
120 env
->exception
.vaddress
= addr
;
127 if (put_user_u64(val
, addr
)) {
128 env
->exception
.vaddress
= addr
;
138 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
144 /* We get the PC of the entry address - which is as good as anything,
145 on a real kernel what you get depends on which mode it uses. */
146 /* XXX: check env->error_code */
147 force_sig_fault(TARGET_SIGSEGV
, TARGET_SEGV_MAPERR
,
148 env
->exception
.vaddress
);
151 /* Handle a jump to the kernel code page. */
153 do_kernel_trap(CPUARMState
*env
)
159 switch (env
->regs
[15]) {
160 case 0xffff0fa0: /* __kernel_memory_barrier */
161 /* ??? No-op. Will need to do better for SMP. */
163 case 0xffff0fc0: /* __kernel_cmpxchg */
164 /* XXX: This only works between threads, not between processes.
165 It's probably possible to implement this with native host
166 operations. However things like ldrex/strex are much harder so
167 there's not much point trying. */
169 cpsr
= cpsr_read(env
);
171 /* FIXME: This should SEGV if the access fails. */
172 if (get_user_u32(val
, addr
))
174 if (val
== env
->regs
[0]) {
176 /* FIXME: Check for segfaults. */
177 put_user_u32(val
, addr
);
184 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
187 case 0xffff0fe0: /* __kernel_get_tls */
188 env
->regs
[0] = cpu_get_tls(env
);
190 case 0xffff0f60: /* __kernel_cmpxchg64 */
191 arm_kernel_cmpxchg64_helper(env
);
197 /* Jump back to the caller. */
198 addr
= env
->regs
[14];
203 env
->regs
[15] = addr
;
208 static bool insn_is_linux_bkpt(uint32_t opcode
, bool is_thumb
)
211 * Return true if this insn is one of the three magic UDF insns
212 * which the kernel treats as breakpoint insns.
215 return (opcode
& 0x0fffffff) == 0x07f001f0;
218 * Note that we get the two halves of the 32-bit T32 insn
219 * in the opposite order to the value the kernel uses in
220 * its undef_hook struct.
222 return ((opcode
& 0xffff) == 0xde01) || (opcode
== 0xa000f7f0);
226 static bool emulate_arm_fpa11(CPUARMState
*env
, uint32_t opcode
)
228 TaskState
*ts
= env_cpu(env
)->opaque
;
229 int rc
= EmulateAll(opcode
, &ts
->fpa
, env
);
233 /* Illegal instruction */
246 /* Translate softfloat flags to FPSR flags */
247 if (rc
& float_flag_invalid
) {
250 if (rc
& float_flag_divbyzero
) {
253 if (rc
& float_flag_overflow
) {
256 if (rc
& float_flag_underflow
) {
259 if (rc
& float_flag_inexact
) {
263 /* Accumulate unenabled exceptions */
264 enabled
= ts
->fpa
.fpsr
>> 16;
265 ts
->fpa
.fpsr
|= raise
& ~enabled
;
267 if (raise
& enabled
) {
269 * The kernel's nwfpe emulator does not pass a real si_code.
270 * It merely uses send_sig(SIGFPE, current, 1), which results in
271 * __send_signal() filling out SI_KERNEL with pid and uid 0 (under
272 * the "SEND_SIG_PRIV" case). That's what our force_sig() does.
274 force_sig(TARGET_SIGFPE
);
281 void cpu_loop(CPUARMState
*env
)
283 CPUState
*cs
= env_cpu(env
);
284 int trapnr
, si_signo
, si_code
;
285 unsigned int n
, insn
;
290 trapnr
= cpu_exec(cs
);
292 process_queued_cpu_work(cs
);
301 /* we handle the FPU emulation here, as Linux */
302 /* we get the opcode */
303 /* FIXME - what to do if get_user() fails? */
304 get_user_code_u32(opcode
, env
->regs
[15], env
);
307 * The Linux kernel treats some UDF patterns specially
308 * to use as breakpoints (instead of the architectural
309 * bkpt insn). These should trigger a SIGTRAP rather
312 if (insn_is_linux_bkpt(opcode
, env
->thumb
)) {
316 if (!env
->thumb
&& emulate_arm_fpa11(env
, opcode
)) {
320 force_sig_fault(TARGET_SIGILL
, TARGET_ILL_ILLOPN
,
329 /* Thumb is always EABI style with syscall number in r7 */
333 * Equivalent of kernel CONFIG_OABI_COMPAT: read the
334 * Arm SVC insn to extract the immediate, which is the
335 * syscall number in OABI.
337 /* FIXME - what to do if get_user() fails? */
338 get_user_code_u32(insn
, env
->regs
[15] - 4, env
);
341 /* zero immediate: EABI, syscall number in r7 */
345 * This XOR matches the kernel code: an immediate
346 * in the valid range (0x900000 .. 0x9fffff) is
347 * converted into the correct EABI-style syscall
348 * number; invalid immediates end up as values
349 * > 0xfffff and are handled below as out-of-range.
351 n
^= ARM_SYSCALL_BASE
;
356 if (n
> ARM_NR_BASE
) {
358 case ARM_NR_cacheflush
:
362 cpu_set_tls(env
, env
->regs
[0]);
365 case ARM_NR_breakpoint
:
366 env
->regs
[15] -= env
->thumb
? 2 : 4;
369 env
->regs
[0] = cpu_get_tls(env
);
374 * Syscalls 0xf0000..0xf07ff (or 0x9f0000..
375 * 0x9f07ff in OABI numbering) are defined
376 * to return -ENOSYS rather than raising
377 * SIGILL. Note that we have already
378 * removed the 0x900000 prefix.
380 qemu_log_mask(LOG_UNIMP
,
381 "qemu: Unsupported ARM syscall: 0x%x\n",
383 env
->regs
[0] = -TARGET_ENOSYS
;
386 * Otherwise SIGILL. This includes any SWI with
387 * immediate not originally 0x9fxxxx, because
388 * of the earlier XOR.
389 * Like the real kernel, we report the addr of the
390 * SWI in the siginfo si_addr but leave the PC
391 * pointing at the insn after the SWI.
393 abi_ulong faultaddr
= env
->regs
[15];
394 faultaddr
-= env
->thumb
? 2 : 4;
395 force_sig_fault(TARGET_SIGILL
, TARGET_ILL_ILLTRP
,
401 ret
= do_syscall(env
,
410 if (ret
== -TARGET_ERESTARTSYS
) {
411 env
->regs
[15] -= env
->thumb
? 2 : 4;
412 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
419 env
->regs
[0] = do_common_semihosting(cs
);
420 env
->regs
[15] += env
->thumb
? 2 : 4;
423 /* just indicate that signals should be handled asap */
425 case EXCP_PREFETCH_ABORT
:
426 case EXCP_DATA_ABORT
:
427 /* For user-only we don't set TTBCR_EAE, so look at the FSR. */
428 switch (env
->exception
.fsr
& 0x1f) {
429 case 0x1: /* Alignment */
430 si_signo
= TARGET_SIGBUS
;
431 si_code
= TARGET_BUS_ADRALN
;
433 case 0x3: /* Access flag fault, level 1 */
434 case 0x6: /* Access flag fault, level 2 */
435 case 0x9: /* Domain fault, level 1 */
436 case 0xb: /* Domain fault, level 2 */
437 case 0xd: /* Permision fault, level 1 */
438 case 0xf: /* Permision fault, level 2 */
439 si_signo
= TARGET_SIGSEGV
;
440 si_code
= TARGET_SEGV_ACCERR
;
442 case 0x5: /* Translation fault, level 1 */
443 case 0x7: /* Translation fault, level 2 */
444 si_signo
= TARGET_SIGSEGV
;
445 si_code
= TARGET_SEGV_MAPERR
;
448 g_assert_not_reached();
450 force_sig_fault(si_signo
, si_code
, env
->exception
.vaddress
);
455 force_sig_fault(TARGET_SIGTRAP
, TARGET_TRAP_BRKPT
, env
->regs
[15]);
457 case EXCP_KERNEL_TRAP
:
458 if (do_kernel_trap(env
))
462 /* nothing to do here for user-mode, just resume guest code */
465 cpu_exec_step_atomic(cs
);
469 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
472 process_pending_signals(env
);
476 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
478 CPUState
*cpu
= env_cpu(env
);
479 TaskState
*ts
= cpu
->opaque
;
480 struct image_info
*info
= ts
->info
;
483 cpsr_write(env
, regs
->uregs
[16], CPSR_USER
| CPSR_EXEC
,
485 for(i
= 0; i
< 16; i
++) {
486 env
->regs
[i
] = regs
->uregs
[i
];
488 #ifdef TARGET_WORDS_BIGENDIAN
490 if (EF_ARM_EABI_VERSION(info
->elf_flags
) >= EF_ARM_EABI_VER4
491 && (info
->elf_flags
& EF_ARM_BE8
)) {
492 env
->uncached_cpsr
|= CPSR_E
;
493 env
->cp15
.sctlr_el
[1] |= SCTLR_E0E
;
495 env
->cp15
.sctlr_el
[1] |= SCTLR_B
;
497 arm_rebuild_hflags(env
);
500 ts
->stack_base
= info
->start_stack
;
501 ts
->heap_base
= info
->brk
;
502 /* This will be filled in on the first SYS_HEAPINFO call. */