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Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-upstream-pull-reque...
[mirror_qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36 #include "exec/log.h"
37 #include "trace/control.h"
38 #include "glib-compat.h"
39
40 char *exec_path;
41
42 int singlestep;
43 static const char *filename;
44 static const char *argv0;
45 static int gdbstub_port;
46 static envlist_t *envlist;
47 static const char *cpu_model;
48 unsigned long mmap_min_addr;
49 unsigned long guest_base;
50 int have_guest_base;
51
52 #define EXCP_DUMP(env, fmt, ...) \
53 do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61 } while (0)
62
63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64 /*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
71 # if defined(TARGET_MIPS) || defined(TARGET_NIOS2)
72 /*
73 * MIPS only supports 31 bits of virtual address space for user space.
74 * Nios2 also only supports 31 bits.
75 */
76 unsigned long reserved_va = 0x77000000;
77 # else
78 unsigned long reserved_va = 0xf7000000;
79 # endif
80 #else
81 unsigned long reserved_va;
82 #endif
83
84 static void usage(int exitcode);
85
86 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
87 const char *qemu_uname_release;
88
89 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
90 we allocate a bigger stack. Need a better solution, for example
91 by remapping the process stack directly at the right place */
92 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
93
94 void gemu_log(const char *fmt, ...)
95 {
96 va_list ap;
97
98 va_start(ap, fmt);
99 vfprintf(stderr, fmt, ap);
100 va_end(ap);
101 }
102
103 #if defined(TARGET_I386)
104 int cpu_get_pic_interrupt(CPUX86State *env)
105 {
106 return -1;
107 }
108 #endif
109
110 /***********************************************************/
111 /* Helper routines for implementing atomic operations. */
112
113 /* Make sure everything is in a consistent state for calling fork(). */
114 void fork_start(void)
115 {
116 cpu_list_lock();
117 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
118 mmap_fork_start();
119 }
120
121 void fork_end(int child)
122 {
123 mmap_fork_end(child);
124 if (child) {
125 CPUState *cpu, *next_cpu;
126 /* Child processes created by fork() only have a single thread.
127 Discard information about the parent threads. */
128 CPU_FOREACH_SAFE(cpu, next_cpu) {
129 if (cpu != thread_cpu) {
130 QTAILQ_REMOVE(&cpus, cpu, node);
131 }
132 }
133 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
134 qemu_init_cpu_list();
135 gdbserver_fork(thread_cpu);
136 } else {
137 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
138 cpu_list_unlock();
139 }
140 }
141
142 #ifdef TARGET_I386
143 /***********************************************************/
144 /* CPUX86 core interface */
145
146 uint64_t cpu_get_tsc(CPUX86State *env)
147 {
148 return cpu_get_host_ticks();
149 }
150
151 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
152 int flags)
153 {
154 unsigned int e1, e2;
155 uint32_t *p;
156 e1 = (addr << 16) | (limit & 0xffff);
157 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
158 e2 |= flags;
159 p = ptr;
160 p[0] = tswap32(e1);
161 p[1] = tswap32(e2);
162 }
163
164 static uint64_t *idt_table;
165 #ifdef TARGET_X86_64
166 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
167 uint64_t addr, unsigned int sel)
168 {
169 uint32_t *p, e1, e2;
170 e1 = (addr & 0xffff) | (sel << 16);
171 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
172 p = ptr;
173 p[0] = tswap32(e1);
174 p[1] = tswap32(e2);
175 p[2] = tswap32(addr >> 32);
176 p[3] = 0;
177 }
178 /* only dpl matters as we do only user space emulation */
179 static void set_idt(int n, unsigned int dpl)
180 {
181 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
182 }
183 #else
184 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
185 uint32_t addr, unsigned int sel)
186 {
187 uint32_t *p, e1, e2;
188 e1 = (addr & 0xffff) | (sel << 16);
189 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
190 p = ptr;
191 p[0] = tswap32(e1);
192 p[1] = tswap32(e2);
193 }
194
195 /* only dpl matters as we do only user space emulation */
196 static void set_idt(int n, unsigned int dpl)
197 {
198 set_gate(idt_table + n, 0, dpl, 0, 0);
199 }
200 #endif
201
202 void cpu_loop(CPUX86State *env)
203 {
204 CPUState *cs = CPU(x86_env_get_cpu(env));
205 int trapnr;
206 abi_ulong pc;
207 abi_ulong ret;
208 target_siginfo_t info;
209
210 for(;;) {
211 cpu_exec_start(cs);
212 trapnr = cpu_exec(cs);
213 cpu_exec_end(cs);
214 process_queued_cpu_work(cs);
215
216 switch(trapnr) {
217 case 0x80:
218 /* linux syscall from int $0x80 */
219 ret = do_syscall(env,
220 env->regs[R_EAX],
221 env->regs[R_EBX],
222 env->regs[R_ECX],
223 env->regs[R_EDX],
224 env->regs[R_ESI],
225 env->regs[R_EDI],
226 env->regs[R_EBP],
227 0, 0);
228 if (ret == -TARGET_ERESTARTSYS) {
229 env->eip -= 2;
230 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
231 env->regs[R_EAX] = ret;
232 }
233 break;
234 #ifndef TARGET_ABI32
235 case EXCP_SYSCALL:
236 /* linux syscall from syscall instruction */
237 ret = do_syscall(env,
238 env->regs[R_EAX],
239 env->regs[R_EDI],
240 env->regs[R_ESI],
241 env->regs[R_EDX],
242 env->regs[10],
243 env->regs[8],
244 env->regs[9],
245 0, 0);
246 if (ret == -TARGET_ERESTARTSYS) {
247 env->eip -= 2;
248 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
249 env->regs[R_EAX] = ret;
250 }
251 break;
252 #endif
253 case EXCP0B_NOSEG:
254 case EXCP0C_STACK:
255 info.si_signo = TARGET_SIGBUS;
256 info.si_errno = 0;
257 info.si_code = TARGET_SI_KERNEL;
258 info._sifields._sigfault._addr = 0;
259 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
260 break;
261 case EXCP0D_GPF:
262 /* XXX: potential problem if ABI32 */
263 #ifndef TARGET_X86_64
264 if (env->eflags & VM_MASK) {
265 handle_vm86_fault(env);
266 } else
267 #endif
268 {
269 info.si_signo = TARGET_SIGSEGV;
270 info.si_errno = 0;
271 info.si_code = TARGET_SI_KERNEL;
272 info._sifields._sigfault._addr = 0;
273 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
274 }
275 break;
276 case EXCP0E_PAGE:
277 info.si_signo = TARGET_SIGSEGV;
278 info.si_errno = 0;
279 if (!(env->error_code & 1))
280 info.si_code = TARGET_SEGV_MAPERR;
281 else
282 info.si_code = TARGET_SEGV_ACCERR;
283 info._sifields._sigfault._addr = env->cr[2];
284 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
285 break;
286 case EXCP00_DIVZ:
287 #ifndef TARGET_X86_64
288 if (env->eflags & VM_MASK) {
289 handle_vm86_trap(env, trapnr);
290 } else
291 #endif
292 {
293 /* division by zero */
294 info.si_signo = TARGET_SIGFPE;
295 info.si_errno = 0;
296 info.si_code = TARGET_FPE_INTDIV;
297 info._sifields._sigfault._addr = env->eip;
298 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
299 }
300 break;
301 case EXCP01_DB:
302 case EXCP03_INT3:
303 #ifndef TARGET_X86_64
304 if (env->eflags & VM_MASK) {
305 handle_vm86_trap(env, trapnr);
306 } else
307 #endif
308 {
309 info.si_signo = TARGET_SIGTRAP;
310 info.si_errno = 0;
311 if (trapnr == EXCP01_DB) {
312 info.si_code = TARGET_TRAP_BRKPT;
313 info._sifields._sigfault._addr = env->eip;
314 } else {
315 info.si_code = TARGET_SI_KERNEL;
316 info._sifields._sigfault._addr = 0;
317 }
318 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
319 }
320 break;
321 case EXCP04_INTO:
322 case EXCP05_BOUND:
323 #ifndef TARGET_X86_64
324 if (env->eflags & VM_MASK) {
325 handle_vm86_trap(env, trapnr);
326 } else
327 #endif
328 {
329 info.si_signo = TARGET_SIGSEGV;
330 info.si_errno = 0;
331 info.si_code = TARGET_SI_KERNEL;
332 info._sifields._sigfault._addr = 0;
333 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
334 }
335 break;
336 case EXCP06_ILLOP:
337 info.si_signo = TARGET_SIGILL;
338 info.si_errno = 0;
339 info.si_code = TARGET_ILL_ILLOPN;
340 info._sifields._sigfault._addr = env->eip;
341 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
342 break;
343 case EXCP_INTERRUPT:
344 /* just indicate that signals should be handled asap */
345 break;
346 case EXCP_DEBUG:
347 {
348 int sig;
349
350 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
351 if (sig)
352 {
353 info.si_signo = sig;
354 info.si_errno = 0;
355 info.si_code = TARGET_TRAP_BRKPT;
356 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
357 }
358 }
359 break;
360 case EXCP_ATOMIC:
361 cpu_exec_step_atomic(cs);
362 break;
363 default:
364 pc = env->segs[R_CS].base + env->eip;
365 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
366 (long)pc, trapnr);
367 abort();
368 }
369 process_pending_signals(env);
370 }
371 }
372 #endif
373
374 #ifdef TARGET_ARM
375
376 #define get_user_code_u32(x, gaddr, env) \
377 ({ abi_long __r = get_user_u32((x), (gaddr)); \
378 if (!__r && bswap_code(arm_sctlr_b(env))) { \
379 (x) = bswap32(x); \
380 } \
381 __r; \
382 })
383
384 #define get_user_code_u16(x, gaddr, env) \
385 ({ abi_long __r = get_user_u16((x), (gaddr)); \
386 if (!__r && bswap_code(arm_sctlr_b(env))) { \
387 (x) = bswap16(x); \
388 } \
389 __r; \
390 })
391
392 #define get_user_data_u32(x, gaddr, env) \
393 ({ abi_long __r = get_user_u32((x), (gaddr)); \
394 if (!__r && arm_cpu_bswap_data(env)) { \
395 (x) = bswap32(x); \
396 } \
397 __r; \
398 })
399
400 #define get_user_data_u16(x, gaddr, env) \
401 ({ abi_long __r = get_user_u16((x), (gaddr)); \
402 if (!__r && arm_cpu_bswap_data(env)) { \
403 (x) = bswap16(x); \
404 } \
405 __r; \
406 })
407
408 #define put_user_data_u32(x, gaddr, env) \
409 ({ typeof(x) __x = (x); \
410 if (arm_cpu_bswap_data(env)) { \
411 __x = bswap32(__x); \
412 } \
413 put_user_u32(__x, (gaddr)); \
414 })
415
416 #define put_user_data_u16(x, gaddr, env) \
417 ({ typeof(x) __x = (x); \
418 if (arm_cpu_bswap_data(env)) { \
419 __x = bswap16(__x); \
420 } \
421 put_user_u16(__x, (gaddr)); \
422 })
423
424 #ifdef TARGET_ABI32
425 /* Commpage handling -- there is no commpage for AArch64 */
426
427 /*
428 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
429 * Input:
430 * r0 = pointer to oldval
431 * r1 = pointer to newval
432 * r2 = pointer to target value
433 *
434 * Output:
435 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
436 * C set if *ptr was changed, clear if no exchange happened
437 *
438 * Note segv's in kernel helpers are a bit tricky, we can set the
439 * data address sensibly but the PC address is just the entry point.
440 */
441 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
442 {
443 uint64_t oldval, newval, val;
444 uint32_t addr, cpsr;
445 target_siginfo_t info;
446
447 /* Based on the 32 bit code in do_kernel_trap */
448
449 /* XXX: This only works between threads, not between processes.
450 It's probably possible to implement this with native host
451 operations. However things like ldrex/strex are much harder so
452 there's not much point trying. */
453 start_exclusive();
454 cpsr = cpsr_read(env);
455 addr = env->regs[2];
456
457 if (get_user_u64(oldval, env->regs[0])) {
458 env->exception.vaddress = env->regs[0];
459 goto segv;
460 };
461
462 if (get_user_u64(newval, env->regs[1])) {
463 env->exception.vaddress = env->regs[1];
464 goto segv;
465 };
466
467 if (get_user_u64(val, addr)) {
468 env->exception.vaddress = addr;
469 goto segv;
470 }
471
472 if (val == oldval) {
473 val = newval;
474
475 if (put_user_u64(val, addr)) {
476 env->exception.vaddress = addr;
477 goto segv;
478 };
479
480 env->regs[0] = 0;
481 cpsr |= CPSR_C;
482 } else {
483 env->regs[0] = -1;
484 cpsr &= ~CPSR_C;
485 }
486 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
487 end_exclusive();
488 return;
489
490 segv:
491 end_exclusive();
492 /* We get the PC of the entry address - which is as good as anything,
493 on a real kernel what you get depends on which mode it uses. */
494 info.si_signo = TARGET_SIGSEGV;
495 info.si_errno = 0;
496 /* XXX: check env->error_code */
497 info.si_code = TARGET_SEGV_MAPERR;
498 info._sifields._sigfault._addr = env->exception.vaddress;
499 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
500 }
501
502 /* Handle a jump to the kernel code page. */
503 static int
504 do_kernel_trap(CPUARMState *env)
505 {
506 uint32_t addr;
507 uint32_t cpsr;
508 uint32_t val;
509
510 switch (env->regs[15]) {
511 case 0xffff0fa0: /* __kernel_memory_barrier */
512 /* ??? No-op. Will need to do better for SMP. */
513 break;
514 case 0xffff0fc0: /* __kernel_cmpxchg */
515 /* XXX: This only works between threads, not between processes.
516 It's probably possible to implement this with native host
517 operations. However things like ldrex/strex are much harder so
518 there's not much point trying. */
519 start_exclusive();
520 cpsr = cpsr_read(env);
521 addr = env->regs[2];
522 /* FIXME: This should SEGV if the access fails. */
523 if (get_user_u32(val, addr))
524 val = ~env->regs[0];
525 if (val == env->regs[0]) {
526 val = env->regs[1];
527 /* FIXME: Check for segfaults. */
528 put_user_u32(val, addr);
529 env->regs[0] = 0;
530 cpsr |= CPSR_C;
531 } else {
532 env->regs[0] = -1;
533 cpsr &= ~CPSR_C;
534 }
535 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
536 end_exclusive();
537 break;
538 case 0xffff0fe0: /* __kernel_get_tls */
539 env->regs[0] = cpu_get_tls(env);
540 break;
541 case 0xffff0f60: /* __kernel_cmpxchg64 */
542 arm_kernel_cmpxchg64_helper(env);
543 break;
544
545 default:
546 return 1;
547 }
548 /* Jump back to the caller. */
549 addr = env->regs[14];
550 if (addr & 1) {
551 env->thumb = 1;
552 addr &= ~1;
553 }
554 env->regs[15] = addr;
555
556 return 0;
557 }
558
559 void cpu_loop(CPUARMState *env)
560 {
561 CPUState *cs = CPU(arm_env_get_cpu(env));
562 int trapnr;
563 unsigned int n, insn;
564 target_siginfo_t info;
565 uint32_t addr;
566 abi_ulong ret;
567
568 for(;;) {
569 cpu_exec_start(cs);
570 trapnr = cpu_exec(cs);
571 cpu_exec_end(cs);
572 process_queued_cpu_work(cs);
573
574 switch(trapnr) {
575 case EXCP_UDEF:
576 case EXCP_NOCP:
577 {
578 TaskState *ts = cs->opaque;
579 uint32_t opcode;
580 int rc;
581
582 /* we handle the FPU emulation here, as Linux */
583 /* we get the opcode */
584 /* FIXME - what to do if get_user() fails? */
585 get_user_code_u32(opcode, env->regs[15], env);
586
587 rc = EmulateAll(opcode, &ts->fpa, env);
588 if (rc == 0) { /* illegal instruction */
589 info.si_signo = TARGET_SIGILL;
590 info.si_errno = 0;
591 info.si_code = TARGET_ILL_ILLOPN;
592 info._sifields._sigfault._addr = env->regs[15];
593 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
594 } else if (rc < 0) { /* FP exception */
595 int arm_fpe=0;
596
597 /* translate softfloat flags to FPSR flags */
598 if (-rc & float_flag_invalid)
599 arm_fpe |= BIT_IOC;
600 if (-rc & float_flag_divbyzero)
601 arm_fpe |= BIT_DZC;
602 if (-rc & float_flag_overflow)
603 arm_fpe |= BIT_OFC;
604 if (-rc & float_flag_underflow)
605 arm_fpe |= BIT_UFC;
606 if (-rc & float_flag_inexact)
607 arm_fpe |= BIT_IXC;
608
609 FPSR fpsr = ts->fpa.fpsr;
610 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
611
612 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
613 info.si_signo = TARGET_SIGFPE;
614 info.si_errno = 0;
615
616 /* ordered by priority, least first */
617 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
618 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
619 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
620 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
621 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
622
623 info._sifields._sigfault._addr = env->regs[15];
624 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
625 } else {
626 env->regs[15] += 4;
627 }
628
629 /* accumulate unenabled exceptions */
630 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
631 fpsr |= BIT_IXC;
632 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
633 fpsr |= BIT_UFC;
634 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
635 fpsr |= BIT_OFC;
636 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
637 fpsr |= BIT_DZC;
638 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
639 fpsr |= BIT_IOC;
640 ts->fpa.fpsr=fpsr;
641 } else { /* everything OK */
642 /* increment PC */
643 env->regs[15] += 4;
644 }
645 }
646 break;
647 case EXCP_SWI:
648 case EXCP_BKPT:
649 {
650 env->eabi = 1;
651 /* system call */
652 if (trapnr == EXCP_BKPT) {
653 if (env->thumb) {
654 /* FIXME - what to do if get_user() fails? */
655 get_user_code_u16(insn, env->regs[15], env);
656 n = insn & 0xff;
657 env->regs[15] += 2;
658 } else {
659 /* FIXME - what to do if get_user() fails? */
660 get_user_code_u32(insn, env->regs[15], env);
661 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
662 env->regs[15] += 4;
663 }
664 } else {
665 if (env->thumb) {
666 /* FIXME - what to do if get_user() fails? */
667 get_user_code_u16(insn, env->regs[15] - 2, env);
668 n = insn & 0xff;
669 } else {
670 /* FIXME - what to do if get_user() fails? */
671 get_user_code_u32(insn, env->regs[15] - 4, env);
672 n = insn & 0xffffff;
673 }
674 }
675
676 if (n == ARM_NR_cacheflush) {
677 /* nop */
678 } else if (n == ARM_NR_semihosting
679 || n == ARM_NR_thumb_semihosting) {
680 env->regs[0] = do_arm_semihosting (env);
681 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
682 /* linux syscall */
683 if (env->thumb || n == 0) {
684 n = env->regs[7];
685 } else {
686 n -= ARM_SYSCALL_BASE;
687 env->eabi = 0;
688 }
689 if ( n > ARM_NR_BASE) {
690 switch (n) {
691 case ARM_NR_cacheflush:
692 /* nop */
693 break;
694 case ARM_NR_set_tls:
695 cpu_set_tls(env, env->regs[0]);
696 env->regs[0] = 0;
697 break;
698 case ARM_NR_breakpoint:
699 env->regs[15] -= env->thumb ? 2 : 4;
700 goto excp_debug;
701 default:
702 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
703 n);
704 env->regs[0] = -TARGET_ENOSYS;
705 break;
706 }
707 } else {
708 ret = do_syscall(env,
709 n,
710 env->regs[0],
711 env->regs[1],
712 env->regs[2],
713 env->regs[3],
714 env->regs[4],
715 env->regs[5],
716 0, 0);
717 if (ret == -TARGET_ERESTARTSYS) {
718 env->regs[15] -= env->thumb ? 2 : 4;
719 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
720 env->regs[0] = ret;
721 }
722 }
723 } else {
724 goto error;
725 }
726 }
727 break;
728 case EXCP_SEMIHOST:
729 env->regs[0] = do_arm_semihosting(env);
730 break;
731 case EXCP_INTERRUPT:
732 /* just indicate that signals should be handled asap */
733 break;
734 case EXCP_PREFETCH_ABORT:
735 case EXCP_DATA_ABORT:
736 addr = env->exception.vaddress;
737 {
738 info.si_signo = TARGET_SIGSEGV;
739 info.si_errno = 0;
740 /* XXX: check env->error_code */
741 info.si_code = TARGET_SEGV_MAPERR;
742 info._sifields._sigfault._addr = addr;
743 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
744 }
745 break;
746 case EXCP_DEBUG:
747 excp_debug:
748 {
749 int sig;
750
751 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
752 if (sig)
753 {
754 info.si_signo = sig;
755 info.si_errno = 0;
756 info.si_code = TARGET_TRAP_BRKPT;
757 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
758 }
759 }
760 break;
761 case EXCP_KERNEL_TRAP:
762 if (do_kernel_trap(env))
763 goto error;
764 break;
765 case EXCP_YIELD:
766 /* nothing to do here for user-mode, just resume guest code */
767 break;
768 case EXCP_ATOMIC:
769 cpu_exec_step_atomic(cs);
770 break;
771 default:
772 error:
773 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
774 abort();
775 }
776 process_pending_signals(env);
777 }
778 }
779
780 #else
781
782 /* AArch64 main loop */
783 void cpu_loop(CPUARMState *env)
784 {
785 CPUState *cs = CPU(arm_env_get_cpu(env));
786 int trapnr, sig;
787 abi_long ret;
788 target_siginfo_t info;
789
790 for (;;) {
791 cpu_exec_start(cs);
792 trapnr = cpu_exec(cs);
793 cpu_exec_end(cs);
794 process_queued_cpu_work(cs);
795
796 switch (trapnr) {
797 case EXCP_SWI:
798 ret = do_syscall(env,
799 env->xregs[8],
800 env->xregs[0],
801 env->xregs[1],
802 env->xregs[2],
803 env->xregs[3],
804 env->xregs[4],
805 env->xregs[5],
806 0, 0);
807 if (ret == -TARGET_ERESTARTSYS) {
808 env->pc -= 4;
809 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
810 env->xregs[0] = ret;
811 }
812 break;
813 case EXCP_INTERRUPT:
814 /* just indicate that signals should be handled asap */
815 break;
816 case EXCP_UDEF:
817 info.si_signo = TARGET_SIGILL;
818 info.si_errno = 0;
819 info.si_code = TARGET_ILL_ILLOPN;
820 info._sifields._sigfault._addr = env->pc;
821 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
822 break;
823 case EXCP_PREFETCH_ABORT:
824 case EXCP_DATA_ABORT:
825 info.si_signo = TARGET_SIGSEGV;
826 info.si_errno = 0;
827 /* XXX: check env->error_code */
828 info.si_code = TARGET_SEGV_MAPERR;
829 info._sifields._sigfault._addr = env->exception.vaddress;
830 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
831 break;
832 case EXCP_DEBUG:
833 case EXCP_BKPT:
834 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
835 if (sig) {
836 info.si_signo = sig;
837 info.si_errno = 0;
838 info.si_code = TARGET_TRAP_BRKPT;
839 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
840 }
841 break;
842 case EXCP_SEMIHOST:
843 env->xregs[0] = do_arm_semihosting(env);
844 break;
845 case EXCP_YIELD:
846 /* nothing to do here for user-mode, just resume guest code */
847 break;
848 case EXCP_ATOMIC:
849 cpu_exec_step_atomic(cs);
850 break;
851 default:
852 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
853 abort();
854 }
855 process_pending_signals(env);
856 /* Exception return on AArch64 always clears the exclusive monitor,
857 * so any return to running guest code implies this.
858 */
859 env->exclusive_addr = -1;
860 }
861 }
862 #endif /* ndef TARGET_ABI32 */
863
864 #endif
865
866 #ifdef TARGET_UNICORE32
867
868 void cpu_loop(CPUUniCore32State *env)
869 {
870 CPUState *cs = CPU(uc32_env_get_cpu(env));
871 int trapnr;
872 unsigned int n, insn;
873 target_siginfo_t info;
874
875 for (;;) {
876 cpu_exec_start(cs);
877 trapnr = cpu_exec(cs);
878 cpu_exec_end(cs);
879 process_queued_cpu_work(cs);
880
881 switch (trapnr) {
882 case UC32_EXCP_PRIV:
883 {
884 /* system call */
885 get_user_u32(insn, env->regs[31] - 4);
886 n = insn & 0xffffff;
887
888 if (n >= UC32_SYSCALL_BASE) {
889 /* linux syscall */
890 n -= UC32_SYSCALL_BASE;
891 if (n == UC32_SYSCALL_NR_set_tls) {
892 cpu_set_tls(env, env->regs[0]);
893 env->regs[0] = 0;
894 } else {
895 abi_long ret = do_syscall(env,
896 n,
897 env->regs[0],
898 env->regs[1],
899 env->regs[2],
900 env->regs[3],
901 env->regs[4],
902 env->regs[5],
903 0, 0);
904 if (ret == -TARGET_ERESTARTSYS) {
905 env->regs[31] -= 4;
906 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
907 env->regs[0] = ret;
908 }
909 }
910 } else {
911 goto error;
912 }
913 }
914 break;
915 case UC32_EXCP_DTRAP:
916 case UC32_EXCP_ITRAP:
917 info.si_signo = TARGET_SIGSEGV;
918 info.si_errno = 0;
919 /* XXX: check env->error_code */
920 info.si_code = TARGET_SEGV_MAPERR;
921 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
922 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
923 break;
924 case EXCP_INTERRUPT:
925 /* just indicate that signals should be handled asap */
926 break;
927 case EXCP_DEBUG:
928 {
929 int sig;
930
931 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
932 if (sig) {
933 info.si_signo = sig;
934 info.si_errno = 0;
935 info.si_code = TARGET_TRAP_BRKPT;
936 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
937 }
938 }
939 break;
940 case EXCP_ATOMIC:
941 cpu_exec_step_atomic(cs);
942 break;
943 default:
944 goto error;
945 }
946 process_pending_signals(env);
947 }
948
949 error:
950 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
951 abort();
952 }
953 #endif
954
955 #ifdef TARGET_SPARC
956 #define SPARC64_STACK_BIAS 2047
957
958 //#define DEBUG_WIN
959
960 /* WARNING: dealing with register windows _is_ complicated. More info
961 can be found at http://www.sics.se/~psm/sparcstack.html */
962 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
963 {
964 index = (index + cwp * 16) % (16 * env->nwindows);
965 /* wrap handling : if cwp is on the last window, then we use the
966 registers 'after' the end */
967 if (index < 8 && env->cwp == env->nwindows - 1)
968 index += 16 * env->nwindows;
969 return index;
970 }
971
972 /* save the register window 'cwp1' */
973 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
974 {
975 unsigned int i;
976 abi_ulong sp_ptr;
977
978 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
979 #ifdef TARGET_SPARC64
980 if (sp_ptr & 3)
981 sp_ptr += SPARC64_STACK_BIAS;
982 #endif
983 #if defined(DEBUG_WIN)
984 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
985 sp_ptr, cwp1);
986 #endif
987 for(i = 0; i < 16; i++) {
988 /* FIXME - what to do if put_user() fails? */
989 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
990 sp_ptr += sizeof(abi_ulong);
991 }
992 }
993
994 static void save_window(CPUSPARCState *env)
995 {
996 #ifndef TARGET_SPARC64
997 unsigned int new_wim;
998 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
999 ((1LL << env->nwindows) - 1);
1000 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1001 env->wim = new_wim;
1002 #else
1003 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1004 env->cansave++;
1005 env->canrestore--;
1006 #endif
1007 }
1008
1009 static void restore_window(CPUSPARCState *env)
1010 {
1011 #ifndef TARGET_SPARC64
1012 unsigned int new_wim;
1013 #endif
1014 unsigned int i, cwp1;
1015 abi_ulong sp_ptr;
1016
1017 #ifndef TARGET_SPARC64
1018 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1019 ((1LL << env->nwindows) - 1);
1020 #endif
1021
1022 /* restore the invalid window */
1023 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1024 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1025 #ifdef TARGET_SPARC64
1026 if (sp_ptr & 3)
1027 sp_ptr += SPARC64_STACK_BIAS;
1028 #endif
1029 #if defined(DEBUG_WIN)
1030 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1031 sp_ptr, cwp1);
1032 #endif
1033 for(i = 0; i < 16; i++) {
1034 /* FIXME - what to do if get_user() fails? */
1035 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1036 sp_ptr += sizeof(abi_ulong);
1037 }
1038 #ifdef TARGET_SPARC64
1039 env->canrestore++;
1040 if (env->cleanwin < env->nwindows - 1)
1041 env->cleanwin++;
1042 env->cansave--;
1043 #else
1044 env->wim = new_wim;
1045 #endif
1046 }
1047
1048 static void flush_windows(CPUSPARCState *env)
1049 {
1050 int offset, cwp1;
1051
1052 offset = 1;
1053 for(;;) {
1054 /* if restore would invoke restore_window(), then we can stop */
1055 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1056 #ifndef TARGET_SPARC64
1057 if (env->wim & (1 << cwp1))
1058 break;
1059 #else
1060 if (env->canrestore == 0)
1061 break;
1062 env->cansave++;
1063 env->canrestore--;
1064 #endif
1065 save_window_offset(env, cwp1);
1066 offset++;
1067 }
1068 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1069 #ifndef TARGET_SPARC64
1070 /* set wim so that restore will reload the registers */
1071 env->wim = 1 << cwp1;
1072 #endif
1073 #if defined(DEBUG_WIN)
1074 printf("flush_windows: nb=%d\n", offset - 1);
1075 #endif
1076 }
1077
1078 void cpu_loop (CPUSPARCState *env)
1079 {
1080 CPUState *cs = CPU(sparc_env_get_cpu(env));
1081 int trapnr;
1082 abi_long ret;
1083 target_siginfo_t info;
1084
1085 while (1) {
1086 cpu_exec_start(cs);
1087 trapnr = cpu_exec(cs);
1088 cpu_exec_end(cs);
1089 process_queued_cpu_work(cs);
1090
1091 /* Compute PSR before exposing state. */
1092 if (env->cc_op != CC_OP_FLAGS) {
1093 cpu_get_psr(env);
1094 }
1095
1096 switch (trapnr) {
1097 #ifndef TARGET_SPARC64
1098 case 0x88:
1099 case 0x90:
1100 #else
1101 case 0x110:
1102 case 0x16d:
1103 #endif
1104 ret = do_syscall (env, env->gregs[1],
1105 env->regwptr[0], env->regwptr[1],
1106 env->regwptr[2], env->regwptr[3],
1107 env->regwptr[4], env->regwptr[5],
1108 0, 0);
1109 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1110 break;
1111 }
1112 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1113 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1114 env->xcc |= PSR_CARRY;
1115 #else
1116 env->psr |= PSR_CARRY;
1117 #endif
1118 ret = -ret;
1119 } else {
1120 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1121 env->xcc &= ~PSR_CARRY;
1122 #else
1123 env->psr &= ~PSR_CARRY;
1124 #endif
1125 }
1126 env->regwptr[0] = ret;
1127 /* next instruction */
1128 env->pc = env->npc;
1129 env->npc = env->npc + 4;
1130 break;
1131 case 0x83: /* flush windows */
1132 #ifdef TARGET_ABI32
1133 case 0x103:
1134 #endif
1135 flush_windows(env);
1136 /* next instruction */
1137 env->pc = env->npc;
1138 env->npc = env->npc + 4;
1139 break;
1140 #ifndef TARGET_SPARC64
1141 case TT_WIN_OVF: /* window overflow */
1142 save_window(env);
1143 break;
1144 case TT_WIN_UNF: /* window underflow */
1145 restore_window(env);
1146 break;
1147 case TT_TFAULT:
1148 case TT_DFAULT:
1149 {
1150 info.si_signo = TARGET_SIGSEGV;
1151 info.si_errno = 0;
1152 /* XXX: check env->error_code */
1153 info.si_code = TARGET_SEGV_MAPERR;
1154 info._sifields._sigfault._addr = env->mmuregs[4];
1155 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1156 }
1157 break;
1158 #else
1159 case TT_SPILL: /* window overflow */
1160 save_window(env);
1161 break;
1162 case TT_FILL: /* window underflow */
1163 restore_window(env);
1164 break;
1165 case TT_TFAULT:
1166 case TT_DFAULT:
1167 {
1168 info.si_signo = TARGET_SIGSEGV;
1169 info.si_errno = 0;
1170 /* XXX: check env->error_code */
1171 info.si_code = TARGET_SEGV_MAPERR;
1172 if (trapnr == TT_DFAULT)
1173 info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
1174 else
1175 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1176 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1177 }
1178 break;
1179 #ifndef TARGET_ABI32
1180 case 0x16e:
1181 flush_windows(env);
1182 sparc64_get_context(env);
1183 break;
1184 case 0x16f:
1185 flush_windows(env);
1186 sparc64_set_context(env);
1187 break;
1188 #endif
1189 #endif
1190 case EXCP_INTERRUPT:
1191 /* just indicate that signals should be handled asap */
1192 break;
1193 case TT_ILL_INSN:
1194 {
1195 info.si_signo = TARGET_SIGILL;
1196 info.si_errno = 0;
1197 info.si_code = TARGET_ILL_ILLOPC;
1198 info._sifields._sigfault._addr = env->pc;
1199 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1200 }
1201 break;
1202 case EXCP_DEBUG:
1203 {
1204 int sig;
1205
1206 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1207 if (sig)
1208 {
1209 info.si_signo = sig;
1210 info.si_errno = 0;
1211 info.si_code = TARGET_TRAP_BRKPT;
1212 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1213 }
1214 }
1215 break;
1216 case EXCP_ATOMIC:
1217 cpu_exec_step_atomic(cs);
1218 break;
1219 default:
1220 printf ("Unhandled trap: 0x%x\n", trapnr);
1221 cpu_dump_state(cs, stderr, fprintf, 0);
1222 exit(EXIT_FAILURE);
1223 }
1224 process_pending_signals (env);
1225 }
1226 }
1227
1228 #endif
1229
1230 #ifdef TARGET_PPC
1231 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1232 {
1233 return cpu_get_host_ticks();
1234 }
1235
1236 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1237 {
1238 return cpu_ppc_get_tb(env);
1239 }
1240
1241 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1242 {
1243 return cpu_ppc_get_tb(env) >> 32;
1244 }
1245
1246 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1247 {
1248 return cpu_ppc_get_tb(env);
1249 }
1250
1251 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1252 {
1253 return cpu_ppc_get_tb(env) >> 32;
1254 }
1255
1256 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1257 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1258
1259 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1260 {
1261 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1262 }
1263
1264 /* XXX: to be fixed */
1265 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1266 {
1267 return -1;
1268 }
1269
1270 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1271 {
1272 return -1;
1273 }
1274
1275 static int do_store_exclusive(CPUPPCState *env)
1276 {
1277 target_ulong addr;
1278 target_ulong page_addr;
1279 target_ulong val, val2 __attribute__((unused)) = 0;
1280 int flags;
1281 int segv = 0;
1282
1283 addr = env->reserve_ea;
1284 page_addr = addr & TARGET_PAGE_MASK;
1285 start_exclusive();
1286 mmap_lock();
1287 flags = page_get_flags(page_addr);
1288 if ((flags & PAGE_READ) == 0) {
1289 segv = 1;
1290 } else {
1291 int reg = env->reserve_info & 0x1f;
1292 int size = env->reserve_info >> 5;
1293 int stored = 0;
1294
1295 if (addr == env->reserve_addr) {
1296 switch (size) {
1297 case 1: segv = get_user_u8(val, addr); break;
1298 case 2: segv = get_user_u16(val, addr); break;
1299 case 4: segv = get_user_u32(val, addr); break;
1300 #if defined(TARGET_PPC64)
1301 case 8: segv = get_user_u64(val, addr); break;
1302 case 16: {
1303 segv = get_user_u64(val, addr);
1304 if (!segv) {
1305 segv = get_user_u64(val2, addr + 8);
1306 }
1307 break;
1308 }
1309 #endif
1310 default: abort();
1311 }
1312 if (!segv && val == env->reserve_val) {
1313 val = env->gpr[reg];
1314 switch (size) {
1315 case 1: segv = put_user_u8(val, addr); break;
1316 case 2: segv = put_user_u16(val, addr); break;
1317 case 4: segv = put_user_u32(val, addr); break;
1318 #if defined(TARGET_PPC64)
1319 case 8: segv = put_user_u64(val, addr); break;
1320 case 16: {
1321 if (val2 == env->reserve_val2) {
1322 if (msr_le) {
1323 val2 = val;
1324 val = env->gpr[reg+1];
1325 } else {
1326 val2 = env->gpr[reg+1];
1327 }
1328 segv = put_user_u64(val, addr);
1329 if (!segv) {
1330 segv = put_user_u64(val2, addr + 8);
1331 }
1332 }
1333 break;
1334 }
1335 #endif
1336 default: abort();
1337 }
1338 if (!segv) {
1339 stored = 1;
1340 }
1341 }
1342 }
1343 env->crf[0] = (stored << 1) | xer_so;
1344 env->reserve_addr = (target_ulong)-1;
1345 }
1346 if (!segv) {
1347 env->nip += 4;
1348 }
1349 mmap_unlock();
1350 end_exclusive();
1351 return segv;
1352 }
1353
1354 void cpu_loop(CPUPPCState *env)
1355 {
1356 CPUState *cs = CPU(ppc_env_get_cpu(env));
1357 target_siginfo_t info;
1358 int trapnr;
1359 target_ulong ret;
1360
1361 for(;;) {
1362 cpu_exec_start(cs);
1363 trapnr = cpu_exec(cs);
1364 cpu_exec_end(cs);
1365 process_queued_cpu_work(cs);
1366
1367 switch(trapnr) {
1368 case POWERPC_EXCP_NONE:
1369 /* Just go on */
1370 break;
1371 case POWERPC_EXCP_CRITICAL: /* Critical input */
1372 cpu_abort(cs, "Critical interrupt while in user mode. "
1373 "Aborting\n");
1374 break;
1375 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1376 cpu_abort(cs, "Machine check exception while in user mode. "
1377 "Aborting\n");
1378 break;
1379 case POWERPC_EXCP_DSI: /* Data storage exception */
1380 /* XXX: check this. Seems bugged */
1381 switch (env->error_code & 0xFF000000) {
1382 case 0x40000000:
1383 case 0x42000000:
1384 info.si_signo = TARGET_SIGSEGV;
1385 info.si_errno = 0;
1386 info.si_code = TARGET_SEGV_MAPERR;
1387 break;
1388 case 0x04000000:
1389 info.si_signo = TARGET_SIGILL;
1390 info.si_errno = 0;
1391 info.si_code = TARGET_ILL_ILLADR;
1392 break;
1393 case 0x08000000:
1394 info.si_signo = TARGET_SIGSEGV;
1395 info.si_errno = 0;
1396 info.si_code = TARGET_SEGV_ACCERR;
1397 break;
1398 default:
1399 /* Let's send a regular segfault... */
1400 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1401 env->error_code);
1402 info.si_signo = TARGET_SIGSEGV;
1403 info.si_errno = 0;
1404 info.si_code = TARGET_SEGV_MAPERR;
1405 break;
1406 }
1407 info._sifields._sigfault._addr = env->nip;
1408 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1409 break;
1410 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1411 /* XXX: check this */
1412 switch (env->error_code & 0xFF000000) {
1413 case 0x40000000:
1414 info.si_signo = TARGET_SIGSEGV;
1415 info.si_errno = 0;
1416 info.si_code = TARGET_SEGV_MAPERR;
1417 break;
1418 case 0x10000000:
1419 case 0x08000000:
1420 info.si_signo = TARGET_SIGSEGV;
1421 info.si_errno = 0;
1422 info.si_code = TARGET_SEGV_ACCERR;
1423 break;
1424 default:
1425 /* Let's send a regular segfault... */
1426 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1427 env->error_code);
1428 info.si_signo = TARGET_SIGSEGV;
1429 info.si_errno = 0;
1430 info.si_code = TARGET_SEGV_MAPERR;
1431 break;
1432 }
1433 info._sifields._sigfault._addr = env->nip - 4;
1434 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1435 break;
1436 case POWERPC_EXCP_EXTERNAL: /* External input */
1437 cpu_abort(cs, "External interrupt while in user mode. "
1438 "Aborting\n");
1439 break;
1440 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1441 /* XXX: check this */
1442 info.si_signo = TARGET_SIGBUS;
1443 info.si_errno = 0;
1444 info.si_code = TARGET_BUS_ADRALN;
1445 info._sifields._sigfault._addr = env->nip;
1446 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1447 break;
1448 case POWERPC_EXCP_PROGRAM: /* Program exception */
1449 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1450 /* XXX: check this */
1451 switch (env->error_code & ~0xF) {
1452 case POWERPC_EXCP_FP:
1453 info.si_signo = TARGET_SIGFPE;
1454 info.si_errno = 0;
1455 switch (env->error_code & 0xF) {
1456 case POWERPC_EXCP_FP_OX:
1457 info.si_code = TARGET_FPE_FLTOVF;
1458 break;
1459 case POWERPC_EXCP_FP_UX:
1460 info.si_code = TARGET_FPE_FLTUND;
1461 break;
1462 case POWERPC_EXCP_FP_ZX:
1463 case POWERPC_EXCP_FP_VXZDZ:
1464 info.si_code = TARGET_FPE_FLTDIV;
1465 break;
1466 case POWERPC_EXCP_FP_XX:
1467 info.si_code = TARGET_FPE_FLTRES;
1468 break;
1469 case POWERPC_EXCP_FP_VXSOFT:
1470 info.si_code = TARGET_FPE_FLTINV;
1471 break;
1472 case POWERPC_EXCP_FP_VXSNAN:
1473 case POWERPC_EXCP_FP_VXISI:
1474 case POWERPC_EXCP_FP_VXIDI:
1475 case POWERPC_EXCP_FP_VXIMZ:
1476 case POWERPC_EXCP_FP_VXVC:
1477 case POWERPC_EXCP_FP_VXSQRT:
1478 case POWERPC_EXCP_FP_VXCVI:
1479 info.si_code = TARGET_FPE_FLTSUB;
1480 break;
1481 default:
1482 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1483 env->error_code);
1484 break;
1485 }
1486 break;
1487 case POWERPC_EXCP_INVAL:
1488 info.si_signo = TARGET_SIGILL;
1489 info.si_errno = 0;
1490 switch (env->error_code & 0xF) {
1491 case POWERPC_EXCP_INVAL_INVAL:
1492 info.si_code = TARGET_ILL_ILLOPC;
1493 break;
1494 case POWERPC_EXCP_INVAL_LSWX:
1495 info.si_code = TARGET_ILL_ILLOPN;
1496 break;
1497 case POWERPC_EXCP_INVAL_SPR:
1498 info.si_code = TARGET_ILL_PRVREG;
1499 break;
1500 case POWERPC_EXCP_INVAL_FP:
1501 info.si_code = TARGET_ILL_COPROC;
1502 break;
1503 default:
1504 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1505 env->error_code & 0xF);
1506 info.si_code = TARGET_ILL_ILLADR;
1507 break;
1508 }
1509 break;
1510 case POWERPC_EXCP_PRIV:
1511 info.si_signo = TARGET_SIGILL;
1512 info.si_errno = 0;
1513 switch (env->error_code & 0xF) {
1514 case POWERPC_EXCP_PRIV_OPC:
1515 info.si_code = TARGET_ILL_PRVOPC;
1516 break;
1517 case POWERPC_EXCP_PRIV_REG:
1518 info.si_code = TARGET_ILL_PRVREG;
1519 break;
1520 default:
1521 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1522 env->error_code & 0xF);
1523 info.si_code = TARGET_ILL_PRVOPC;
1524 break;
1525 }
1526 break;
1527 case POWERPC_EXCP_TRAP:
1528 cpu_abort(cs, "Tried to call a TRAP\n");
1529 break;
1530 default:
1531 /* Should not happen ! */
1532 cpu_abort(cs, "Unknown program exception (%02x)\n",
1533 env->error_code);
1534 break;
1535 }
1536 info._sifields._sigfault._addr = env->nip;
1537 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1538 break;
1539 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1540 info.si_signo = TARGET_SIGILL;
1541 info.si_errno = 0;
1542 info.si_code = TARGET_ILL_COPROC;
1543 info._sifields._sigfault._addr = env->nip;
1544 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1545 break;
1546 case POWERPC_EXCP_SYSCALL: /* System call exception */
1547 cpu_abort(cs, "Syscall exception while in user mode. "
1548 "Aborting\n");
1549 break;
1550 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1551 info.si_signo = TARGET_SIGILL;
1552 info.si_errno = 0;
1553 info.si_code = TARGET_ILL_COPROC;
1554 info._sifields._sigfault._addr = env->nip;
1555 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1556 break;
1557 case POWERPC_EXCP_DECR: /* Decrementer exception */
1558 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1559 "Aborting\n");
1560 break;
1561 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1562 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1563 "Aborting\n");
1564 break;
1565 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1566 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1567 "Aborting\n");
1568 break;
1569 case POWERPC_EXCP_DTLB: /* Data TLB error */
1570 cpu_abort(cs, "Data TLB exception while in user mode. "
1571 "Aborting\n");
1572 break;
1573 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1574 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1575 "Aborting\n");
1576 break;
1577 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1578 info.si_signo = TARGET_SIGILL;
1579 info.si_errno = 0;
1580 info.si_code = TARGET_ILL_COPROC;
1581 info._sifields._sigfault._addr = env->nip;
1582 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1583 break;
1584 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1585 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1586 break;
1587 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1588 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1589 break;
1590 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1591 cpu_abort(cs, "Performance monitor exception not handled\n");
1592 break;
1593 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1594 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1595 "Aborting\n");
1596 break;
1597 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1598 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1599 "Aborting\n");
1600 break;
1601 case POWERPC_EXCP_RESET: /* System reset exception */
1602 cpu_abort(cs, "Reset interrupt while in user mode. "
1603 "Aborting\n");
1604 break;
1605 case POWERPC_EXCP_DSEG: /* Data segment exception */
1606 cpu_abort(cs, "Data segment exception while in user mode. "
1607 "Aborting\n");
1608 break;
1609 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1610 cpu_abort(cs, "Instruction segment exception "
1611 "while in user mode. Aborting\n");
1612 break;
1613 /* PowerPC 64 with hypervisor mode support */
1614 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1615 cpu_abort(cs, "Hypervisor decrementer interrupt "
1616 "while in user mode. Aborting\n");
1617 break;
1618 case POWERPC_EXCP_TRACE: /* Trace exception */
1619 /* Nothing to do:
1620 * we use this exception to emulate step-by-step execution mode.
1621 */
1622 break;
1623 /* PowerPC 64 with hypervisor mode support */
1624 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1625 cpu_abort(cs, "Hypervisor data storage exception "
1626 "while in user mode. Aborting\n");
1627 break;
1628 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1629 cpu_abort(cs, "Hypervisor instruction storage exception "
1630 "while in user mode. Aborting\n");
1631 break;
1632 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1633 cpu_abort(cs, "Hypervisor data segment exception "
1634 "while in user mode. Aborting\n");
1635 break;
1636 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1637 cpu_abort(cs, "Hypervisor instruction segment exception "
1638 "while in user mode. Aborting\n");
1639 break;
1640 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1641 info.si_signo = TARGET_SIGILL;
1642 info.si_errno = 0;
1643 info.si_code = TARGET_ILL_COPROC;
1644 info._sifields._sigfault._addr = env->nip;
1645 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1646 break;
1647 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1648 cpu_abort(cs, "Programmable interval timer interrupt "
1649 "while in user mode. Aborting\n");
1650 break;
1651 case POWERPC_EXCP_IO: /* IO error exception */
1652 cpu_abort(cs, "IO error exception while in user mode. "
1653 "Aborting\n");
1654 break;
1655 case POWERPC_EXCP_RUNM: /* Run mode exception */
1656 cpu_abort(cs, "Run mode exception while in user mode. "
1657 "Aborting\n");
1658 break;
1659 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1660 cpu_abort(cs, "Emulation trap exception not handled\n");
1661 break;
1662 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1663 cpu_abort(cs, "Instruction fetch TLB exception "
1664 "while in user-mode. Aborting");
1665 break;
1666 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1667 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1668 "Aborting");
1669 break;
1670 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1671 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1672 "Aborting");
1673 break;
1674 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1675 cpu_abort(cs, "Floating-point assist exception not handled\n");
1676 break;
1677 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1678 cpu_abort(cs, "Instruction address breakpoint exception "
1679 "not handled\n");
1680 break;
1681 case POWERPC_EXCP_SMI: /* System management interrupt */
1682 cpu_abort(cs, "System management interrupt while in user mode. "
1683 "Aborting\n");
1684 break;
1685 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1686 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1687 "Aborting\n");
1688 break;
1689 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1690 cpu_abort(cs, "Performance monitor exception not handled\n");
1691 break;
1692 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1693 cpu_abort(cs, "Vector assist exception not handled\n");
1694 break;
1695 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1696 cpu_abort(cs, "Soft patch exception not handled\n");
1697 break;
1698 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1699 cpu_abort(cs, "Maintenance exception while in user mode. "
1700 "Aborting\n");
1701 break;
1702 case POWERPC_EXCP_STOP: /* stop translation */
1703 /* We did invalidate the instruction cache. Go on */
1704 break;
1705 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1706 /* We just stopped because of a branch. Go on */
1707 break;
1708 case POWERPC_EXCP_SYSCALL_USER:
1709 /* system call in user-mode emulation */
1710 /* WARNING:
1711 * PPC ABI uses overflow flag in cr0 to signal an error
1712 * in syscalls.
1713 */
1714 env->crf[0] &= ~0x1;
1715 env->nip += 4;
1716 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1717 env->gpr[5], env->gpr[6], env->gpr[7],
1718 env->gpr[8], 0, 0);
1719 if (ret == -TARGET_ERESTARTSYS) {
1720 env->nip -= 4;
1721 break;
1722 }
1723 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1724 /* Returning from a successful sigreturn syscall.
1725 Avoid corrupting register state. */
1726 break;
1727 }
1728 if (ret > (target_ulong)(-515)) {
1729 env->crf[0] |= 0x1;
1730 ret = -ret;
1731 }
1732 env->gpr[3] = ret;
1733 break;
1734 case POWERPC_EXCP_STCX:
1735 if (do_store_exclusive(env)) {
1736 info.si_signo = TARGET_SIGSEGV;
1737 info.si_errno = 0;
1738 info.si_code = TARGET_SEGV_MAPERR;
1739 info._sifields._sigfault._addr = env->nip;
1740 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1741 }
1742 break;
1743 case EXCP_DEBUG:
1744 {
1745 int sig;
1746
1747 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1748 if (sig) {
1749 info.si_signo = sig;
1750 info.si_errno = 0;
1751 info.si_code = TARGET_TRAP_BRKPT;
1752 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1753 }
1754 }
1755 break;
1756 case EXCP_INTERRUPT:
1757 /* just indicate that signals should be handled asap */
1758 break;
1759 case EXCP_ATOMIC:
1760 cpu_exec_step_atomic(cs);
1761 break;
1762 default:
1763 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
1764 break;
1765 }
1766 process_pending_signals(env);
1767 }
1768 }
1769 #endif
1770
1771 #ifdef TARGET_MIPS
1772
1773 # ifdef TARGET_ABI_MIPSO32
1774 # define MIPS_SYS(name, args) args,
1775 static const uint8_t mips_syscall_args[] = {
1776 MIPS_SYS(sys_syscall , 8) /* 4000 */
1777 MIPS_SYS(sys_exit , 1)
1778 MIPS_SYS(sys_fork , 0)
1779 MIPS_SYS(sys_read , 3)
1780 MIPS_SYS(sys_write , 3)
1781 MIPS_SYS(sys_open , 3) /* 4005 */
1782 MIPS_SYS(sys_close , 1)
1783 MIPS_SYS(sys_waitpid , 3)
1784 MIPS_SYS(sys_creat , 2)
1785 MIPS_SYS(sys_link , 2)
1786 MIPS_SYS(sys_unlink , 1) /* 4010 */
1787 MIPS_SYS(sys_execve , 0)
1788 MIPS_SYS(sys_chdir , 1)
1789 MIPS_SYS(sys_time , 1)
1790 MIPS_SYS(sys_mknod , 3)
1791 MIPS_SYS(sys_chmod , 2) /* 4015 */
1792 MIPS_SYS(sys_lchown , 3)
1793 MIPS_SYS(sys_ni_syscall , 0)
1794 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1795 MIPS_SYS(sys_lseek , 3)
1796 MIPS_SYS(sys_getpid , 0) /* 4020 */
1797 MIPS_SYS(sys_mount , 5)
1798 MIPS_SYS(sys_umount , 1)
1799 MIPS_SYS(sys_setuid , 1)
1800 MIPS_SYS(sys_getuid , 0)
1801 MIPS_SYS(sys_stime , 1) /* 4025 */
1802 MIPS_SYS(sys_ptrace , 4)
1803 MIPS_SYS(sys_alarm , 1)
1804 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1805 MIPS_SYS(sys_pause , 0)
1806 MIPS_SYS(sys_utime , 2) /* 4030 */
1807 MIPS_SYS(sys_ni_syscall , 0)
1808 MIPS_SYS(sys_ni_syscall , 0)
1809 MIPS_SYS(sys_access , 2)
1810 MIPS_SYS(sys_nice , 1)
1811 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1812 MIPS_SYS(sys_sync , 0)
1813 MIPS_SYS(sys_kill , 2)
1814 MIPS_SYS(sys_rename , 2)
1815 MIPS_SYS(sys_mkdir , 2)
1816 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1817 MIPS_SYS(sys_dup , 1)
1818 MIPS_SYS(sys_pipe , 0)
1819 MIPS_SYS(sys_times , 1)
1820 MIPS_SYS(sys_ni_syscall , 0)
1821 MIPS_SYS(sys_brk , 1) /* 4045 */
1822 MIPS_SYS(sys_setgid , 1)
1823 MIPS_SYS(sys_getgid , 0)
1824 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1825 MIPS_SYS(sys_geteuid , 0)
1826 MIPS_SYS(sys_getegid , 0) /* 4050 */
1827 MIPS_SYS(sys_acct , 0)
1828 MIPS_SYS(sys_umount2 , 2)
1829 MIPS_SYS(sys_ni_syscall , 0)
1830 MIPS_SYS(sys_ioctl , 3)
1831 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1832 MIPS_SYS(sys_ni_syscall , 2)
1833 MIPS_SYS(sys_setpgid , 2)
1834 MIPS_SYS(sys_ni_syscall , 0)
1835 MIPS_SYS(sys_olduname , 1)
1836 MIPS_SYS(sys_umask , 1) /* 4060 */
1837 MIPS_SYS(sys_chroot , 1)
1838 MIPS_SYS(sys_ustat , 2)
1839 MIPS_SYS(sys_dup2 , 2)
1840 MIPS_SYS(sys_getppid , 0)
1841 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1842 MIPS_SYS(sys_setsid , 0)
1843 MIPS_SYS(sys_sigaction , 3)
1844 MIPS_SYS(sys_sgetmask , 0)
1845 MIPS_SYS(sys_ssetmask , 1)
1846 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1847 MIPS_SYS(sys_setregid , 2)
1848 MIPS_SYS(sys_sigsuspend , 0)
1849 MIPS_SYS(sys_sigpending , 1)
1850 MIPS_SYS(sys_sethostname , 2)
1851 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1852 MIPS_SYS(sys_getrlimit , 2)
1853 MIPS_SYS(sys_getrusage , 2)
1854 MIPS_SYS(sys_gettimeofday, 2)
1855 MIPS_SYS(sys_settimeofday, 2)
1856 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1857 MIPS_SYS(sys_setgroups , 2)
1858 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1859 MIPS_SYS(sys_symlink , 2)
1860 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1861 MIPS_SYS(sys_readlink , 3) /* 4085 */
1862 MIPS_SYS(sys_uselib , 1)
1863 MIPS_SYS(sys_swapon , 2)
1864 MIPS_SYS(sys_reboot , 3)
1865 MIPS_SYS(old_readdir , 3)
1866 MIPS_SYS(old_mmap , 6) /* 4090 */
1867 MIPS_SYS(sys_munmap , 2)
1868 MIPS_SYS(sys_truncate , 2)
1869 MIPS_SYS(sys_ftruncate , 2)
1870 MIPS_SYS(sys_fchmod , 2)
1871 MIPS_SYS(sys_fchown , 3) /* 4095 */
1872 MIPS_SYS(sys_getpriority , 2)
1873 MIPS_SYS(sys_setpriority , 3)
1874 MIPS_SYS(sys_ni_syscall , 0)
1875 MIPS_SYS(sys_statfs , 2)
1876 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1877 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1878 MIPS_SYS(sys_socketcall , 2)
1879 MIPS_SYS(sys_syslog , 3)
1880 MIPS_SYS(sys_setitimer , 3)
1881 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1882 MIPS_SYS(sys_newstat , 2)
1883 MIPS_SYS(sys_newlstat , 2)
1884 MIPS_SYS(sys_newfstat , 2)
1885 MIPS_SYS(sys_uname , 1)
1886 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1887 MIPS_SYS(sys_vhangup , 0)
1888 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1889 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1890 MIPS_SYS(sys_wait4 , 4)
1891 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1892 MIPS_SYS(sys_sysinfo , 1)
1893 MIPS_SYS(sys_ipc , 6)
1894 MIPS_SYS(sys_fsync , 1)
1895 MIPS_SYS(sys_sigreturn , 0)
1896 MIPS_SYS(sys_clone , 6) /* 4120 */
1897 MIPS_SYS(sys_setdomainname, 2)
1898 MIPS_SYS(sys_newuname , 1)
1899 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1900 MIPS_SYS(sys_adjtimex , 1)
1901 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1902 MIPS_SYS(sys_sigprocmask , 3)
1903 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1904 MIPS_SYS(sys_init_module , 5)
1905 MIPS_SYS(sys_delete_module, 1)
1906 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1907 MIPS_SYS(sys_quotactl , 0)
1908 MIPS_SYS(sys_getpgid , 1)
1909 MIPS_SYS(sys_fchdir , 1)
1910 MIPS_SYS(sys_bdflush , 2)
1911 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1912 MIPS_SYS(sys_personality , 1)
1913 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1914 MIPS_SYS(sys_setfsuid , 1)
1915 MIPS_SYS(sys_setfsgid , 1)
1916 MIPS_SYS(sys_llseek , 5) /* 4140 */
1917 MIPS_SYS(sys_getdents , 3)
1918 MIPS_SYS(sys_select , 5)
1919 MIPS_SYS(sys_flock , 2)
1920 MIPS_SYS(sys_msync , 3)
1921 MIPS_SYS(sys_readv , 3) /* 4145 */
1922 MIPS_SYS(sys_writev , 3)
1923 MIPS_SYS(sys_cacheflush , 3)
1924 MIPS_SYS(sys_cachectl , 3)
1925 MIPS_SYS(sys_sysmips , 4)
1926 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1927 MIPS_SYS(sys_getsid , 1)
1928 MIPS_SYS(sys_fdatasync , 0)
1929 MIPS_SYS(sys_sysctl , 1)
1930 MIPS_SYS(sys_mlock , 2)
1931 MIPS_SYS(sys_munlock , 2) /* 4155 */
1932 MIPS_SYS(sys_mlockall , 1)
1933 MIPS_SYS(sys_munlockall , 0)
1934 MIPS_SYS(sys_sched_setparam, 2)
1935 MIPS_SYS(sys_sched_getparam, 2)
1936 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1937 MIPS_SYS(sys_sched_getscheduler, 1)
1938 MIPS_SYS(sys_sched_yield , 0)
1939 MIPS_SYS(sys_sched_get_priority_max, 1)
1940 MIPS_SYS(sys_sched_get_priority_min, 1)
1941 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1942 MIPS_SYS(sys_nanosleep, 2)
1943 MIPS_SYS(sys_mremap , 5)
1944 MIPS_SYS(sys_accept , 3)
1945 MIPS_SYS(sys_bind , 3)
1946 MIPS_SYS(sys_connect , 3) /* 4170 */
1947 MIPS_SYS(sys_getpeername , 3)
1948 MIPS_SYS(sys_getsockname , 3)
1949 MIPS_SYS(sys_getsockopt , 5)
1950 MIPS_SYS(sys_listen , 2)
1951 MIPS_SYS(sys_recv , 4) /* 4175 */
1952 MIPS_SYS(sys_recvfrom , 6)
1953 MIPS_SYS(sys_recvmsg , 3)
1954 MIPS_SYS(sys_send , 4)
1955 MIPS_SYS(sys_sendmsg , 3)
1956 MIPS_SYS(sys_sendto , 6) /* 4180 */
1957 MIPS_SYS(sys_setsockopt , 5)
1958 MIPS_SYS(sys_shutdown , 2)
1959 MIPS_SYS(sys_socket , 3)
1960 MIPS_SYS(sys_socketpair , 4)
1961 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1962 MIPS_SYS(sys_getresuid , 3)
1963 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1964 MIPS_SYS(sys_poll , 3)
1965 MIPS_SYS(sys_nfsservctl , 3)
1966 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1967 MIPS_SYS(sys_getresgid , 3)
1968 MIPS_SYS(sys_prctl , 5)
1969 MIPS_SYS(sys_rt_sigreturn, 0)
1970 MIPS_SYS(sys_rt_sigaction, 4)
1971 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1972 MIPS_SYS(sys_rt_sigpending, 2)
1973 MIPS_SYS(sys_rt_sigtimedwait, 4)
1974 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1975 MIPS_SYS(sys_rt_sigsuspend, 0)
1976 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1977 MIPS_SYS(sys_pwrite64 , 6)
1978 MIPS_SYS(sys_chown , 3)
1979 MIPS_SYS(sys_getcwd , 2)
1980 MIPS_SYS(sys_capget , 2)
1981 MIPS_SYS(sys_capset , 2) /* 4205 */
1982 MIPS_SYS(sys_sigaltstack , 2)
1983 MIPS_SYS(sys_sendfile , 4)
1984 MIPS_SYS(sys_ni_syscall , 0)
1985 MIPS_SYS(sys_ni_syscall , 0)
1986 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1987 MIPS_SYS(sys_truncate64 , 4)
1988 MIPS_SYS(sys_ftruncate64 , 4)
1989 MIPS_SYS(sys_stat64 , 2)
1990 MIPS_SYS(sys_lstat64 , 2)
1991 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1992 MIPS_SYS(sys_pivot_root , 2)
1993 MIPS_SYS(sys_mincore , 3)
1994 MIPS_SYS(sys_madvise , 3)
1995 MIPS_SYS(sys_getdents64 , 3)
1996 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1997 MIPS_SYS(sys_ni_syscall , 0)
1998 MIPS_SYS(sys_gettid , 0)
1999 MIPS_SYS(sys_readahead , 5)
2000 MIPS_SYS(sys_setxattr , 5)
2001 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2002 MIPS_SYS(sys_fsetxattr , 5)
2003 MIPS_SYS(sys_getxattr , 4)
2004 MIPS_SYS(sys_lgetxattr , 4)
2005 MIPS_SYS(sys_fgetxattr , 4)
2006 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2007 MIPS_SYS(sys_llistxattr , 3)
2008 MIPS_SYS(sys_flistxattr , 3)
2009 MIPS_SYS(sys_removexattr , 2)
2010 MIPS_SYS(sys_lremovexattr, 2)
2011 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2012 MIPS_SYS(sys_tkill , 2)
2013 MIPS_SYS(sys_sendfile64 , 5)
2014 MIPS_SYS(sys_futex , 6)
2015 MIPS_SYS(sys_sched_setaffinity, 3)
2016 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2017 MIPS_SYS(sys_io_setup , 2)
2018 MIPS_SYS(sys_io_destroy , 1)
2019 MIPS_SYS(sys_io_getevents, 5)
2020 MIPS_SYS(sys_io_submit , 3)
2021 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2022 MIPS_SYS(sys_exit_group , 1)
2023 MIPS_SYS(sys_lookup_dcookie, 3)
2024 MIPS_SYS(sys_epoll_create, 1)
2025 MIPS_SYS(sys_epoll_ctl , 4)
2026 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2027 MIPS_SYS(sys_remap_file_pages, 5)
2028 MIPS_SYS(sys_set_tid_address, 1)
2029 MIPS_SYS(sys_restart_syscall, 0)
2030 MIPS_SYS(sys_fadvise64_64, 7)
2031 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2032 MIPS_SYS(sys_fstatfs64 , 2)
2033 MIPS_SYS(sys_timer_create, 3)
2034 MIPS_SYS(sys_timer_settime, 4)
2035 MIPS_SYS(sys_timer_gettime, 2)
2036 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2037 MIPS_SYS(sys_timer_delete, 1)
2038 MIPS_SYS(sys_clock_settime, 2)
2039 MIPS_SYS(sys_clock_gettime, 2)
2040 MIPS_SYS(sys_clock_getres, 2)
2041 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2042 MIPS_SYS(sys_tgkill , 3)
2043 MIPS_SYS(sys_utimes , 2)
2044 MIPS_SYS(sys_mbind , 4)
2045 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2046 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2047 MIPS_SYS(sys_mq_open , 4)
2048 MIPS_SYS(sys_mq_unlink , 1)
2049 MIPS_SYS(sys_mq_timedsend, 5)
2050 MIPS_SYS(sys_mq_timedreceive, 5)
2051 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2052 MIPS_SYS(sys_mq_getsetattr, 3)
2053 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2054 MIPS_SYS(sys_waitid , 4)
2055 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2056 MIPS_SYS(sys_add_key , 5)
2057 MIPS_SYS(sys_request_key, 4)
2058 MIPS_SYS(sys_keyctl , 5)
2059 MIPS_SYS(sys_set_thread_area, 1)
2060 MIPS_SYS(sys_inotify_init, 0)
2061 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2062 MIPS_SYS(sys_inotify_rm_watch, 2)
2063 MIPS_SYS(sys_migrate_pages, 4)
2064 MIPS_SYS(sys_openat, 4)
2065 MIPS_SYS(sys_mkdirat, 3)
2066 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2067 MIPS_SYS(sys_fchownat, 5)
2068 MIPS_SYS(sys_futimesat, 3)
2069 MIPS_SYS(sys_fstatat64, 4)
2070 MIPS_SYS(sys_unlinkat, 3)
2071 MIPS_SYS(sys_renameat, 4) /* 4295 */
2072 MIPS_SYS(sys_linkat, 5)
2073 MIPS_SYS(sys_symlinkat, 3)
2074 MIPS_SYS(sys_readlinkat, 4)
2075 MIPS_SYS(sys_fchmodat, 3)
2076 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2077 MIPS_SYS(sys_pselect6, 6)
2078 MIPS_SYS(sys_ppoll, 5)
2079 MIPS_SYS(sys_unshare, 1)
2080 MIPS_SYS(sys_splice, 6)
2081 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2082 MIPS_SYS(sys_tee, 4)
2083 MIPS_SYS(sys_vmsplice, 4)
2084 MIPS_SYS(sys_move_pages, 6)
2085 MIPS_SYS(sys_set_robust_list, 2)
2086 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2087 MIPS_SYS(sys_kexec_load, 4)
2088 MIPS_SYS(sys_getcpu, 3)
2089 MIPS_SYS(sys_epoll_pwait, 6)
2090 MIPS_SYS(sys_ioprio_set, 3)
2091 MIPS_SYS(sys_ioprio_get, 2)
2092 MIPS_SYS(sys_utimensat, 4)
2093 MIPS_SYS(sys_signalfd, 3)
2094 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2095 MIPS_SYS(sys_eventfd, 1)
2096 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2097 MIPS_SYS(sys_timerfd_create, 2)
2098 MIPS_SYS(sys_timerfd_gettime, 2)
2099 MIPS_SYS(sys_timerfd_settime, 4)
2100 MIPS_SYS(sys_signalfd4, 4)
2101 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2102 MIPS_SYS(sys_epoll_create1, 1)
2103 MIPS_SYS(sys_dup3, 3)
2104 MIPS_SYS(sys_pipe2, 2)
2105 MIPS_SYS(sys_inotify_init1, 1)
2106 MIPS_SYS(sys_preadv, 5) /* 4330 */
2107 MIPS_SYS(sys_pwritev, 5)
2108 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2109 MIPS_SYS(sys_perf_event_open, 5)
2110 MIPS_SYS(sys_accept4, 4)
2111 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2112 MIPS_SYS(sys_fanotify_init, 2)
2113 MIPS_SYS(sys_fanotify_mark, 6)
2114 MIPS_SYS(sys_prlimit64, 4)
2115 MIPS_SYS(sys_name_to_handle_at, 5)
2116 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2117 MIPS_SYS(sys_clock_adjtime, 2)
2118 MIPS_SYS(sys_syncfs, 1)
2119 MIPS_SYS(sys_sendmmsg, 4)
2120 MIPS_SYS(sys_setns, 2)
2121 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2122 MIPS_SYS(sys_process_vm_writev, 6)
2123 MIPS_SYS(sys_kcmp, 5)
2124 MIPS_SYS(sys_finit_module, 3)
2125 MIPS_SYS(sys_sched_setattr, 2)
2126 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2127 MIPS_SYS(sys_renameat2, 5)
2128 MIPS_SYS(sys_seccomp, 3)
2129 MIPS_SYS(sys_getrandom, 3)
2130 MIPS_SYS(sys_memfd_create, 2)
2131 MIPS_SYS(sys_bpf, 3) /* 355 */
2132 MIPS_SYS(sys_execveat, 5)
2133 MIPS_SYS(sys_userfaultfd, 1)
2134 MIPS_SYS(sys_membarrier, 2)
2135 MIPS_SYS(sys_mlock2, 3)
2136 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2137 MIPS_SYS(sys_preadv2, 6)
2138 MIPS_SYS(sys_pwritev2, 6)
2139 };
2140 # undef MIPS_SYS
2141 # endif /* O32 */
2142
2143 static int do_store_exclusive(CPUMIPSState *env)
2144 {
2145 target_ulong addr;
2146 target_ulong page_addr;
2147 target_ulong val;
2148 int flags;
2149 int segv = 0;
2150 int reg;
2151 int d;
2152
2153 addr = env->lladdr;
2154 page_addr = addr & TARGET_PAGE_MASK;
2155 start_exclusive();
2156 mmap_lock();
2157 flags = page_get_flags(page_addr);
2158 if ((flags & PAGE_READ) == 0) {
2159 segv = 1;
2160 } else {
2161 reg = env->llreg & 0x1f;
2162 d = (env->llreg & 0x20) != 0;
2163 if (d) {
2164 segv = get_user_s64(val, addr);
2165 } else {
2166 segv = get_user_s32(val, addr);
2167 }
2168 if (!segv) {
2169 if (val != env->llval) {
2170 env->active_tc.gpr[reg] = 0;
2171 } else {
2172 if (d) {
2173 segv = put_user_u64(env->llnewval, addr);
2174 } else {
2175 segv = put_user_u32(env->llnewval, addr);
2176 }
2177 if (!segv) {
2178 env->active_tc.gpr[reg] = 1;
2179 }
2180 }
2181 }
2182 }
2183 env->lladdr = -1;
2184 if (!segv) {
2185 env->active_tc.PC += 4;
2186 }
2187 mmap_unlock();
2188 end_exclusive();
2189 return segv;
2190 }
2191
2192 /* Break codes */
2193 enum {
2194 BRK_OVERFLOW = 6,
2195 BRK_DIVZERO = 7
2196 };
2197
2198 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2199 unsigned int code)
2200 {
2201 int ret = -1;
2202
2203 switch (code) {
2204 case BRK_OVERFLOW:
2205 case BRK_DIVZERO:
2206 info->si_signo = TARGET_SIGFPE;
2207 info->si_errno = 0;
2208 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2209 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2210 ret = 0;
2211 break;
2212 default:
2213 info->si_signo = TARGET_SIGTRAP;
2214 info->si_errno = 0;
2215 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2216 ret = 0;
2217 break;
2218 }
2219
2220 return ret;
2221 }
2222
2223 void cpu_loop(CPUMIPSState *env)
2224 {
2225 CPUState *cs = CPU(mips_env_get_cpu(env));
2226 target_siginfo_t info;
2227 int trapnr;
2228 abi_long ret;
2229 # ifdef TARGET_ABI_MIPSO32
2230 unsigned int syscall_num;
2231 # endif
2232
2233 for(;;) {
2234 cpu_exec_start(cs);
2235 trapnr = cpu_exec(cs);
2236 cpu_exec_end(cs);
2237 process_queued_cpu_work(cs);
2238
2239 switch(trapnr) {
2240 case EXCP_SYSCALL:
2241 env->active_tc.PC += 4;
2242 # ifdef TARGET_ABI_MIPSO32
2243 syscall_num = env->active_tc.gpr[2] - 4000;
2244 if (syscall_num >= sizeof(mips_syscall_args)) {
2245 ret = -TARGET_ENOSYS;
2246 } else {
2247 int nb_args;
2248 abi_ulong sp_reg;
2249 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2250
2251 nb_args = mips_syscall_args[syscall_num];
2252 sp_reg = env->active_tc.gpr[29];
2253 switch (nb_args) {
2254 /* these arguments are taken from the stack */
2255 case 8:
2256 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2257 goto done_syscall;
2258 }
2259 case 7:
2260 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2261 goto done_syscall;
2262 }
2263 case 6:
2264 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2265 goto done_syscall;
2266 }
2267 case 5:
2268 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2269 goto done_syscall;
2270 }
2271 default:
2272 break;
2273 }
2274 ret = do_syscall(env, env->active_tc.gpr[2],
2275 env->active_tc.gpr[4],
2276 env->active_tc.gpr[5],
2277 env->active_tc.gpr[6],
2278 env->active_tc.gpr[7],
2279 arg5, arg6, arg7, arg8);
2280 }
2281 done_syscall:
2282 # else
2283 ret = do_syscall(env, env->active_tc.gpr[2],
2284 env->active_tc.gpr[4], env->active_tc.gpr[5],
2285 env->active_tc.gpr[6], env->active_tc.gpr[7],
2286 env->active_tc.gpr[8], env->active_tc.gpr[9],
2287 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2288 # endif /* O32 */
2289 if (ret == -TARGET_ERESTARTSYS) {
2290 env->active_tc.PC -= 4;
2291 break;
2292 }
2293 if (ret == -TARGET_QEMU_ESIGRETURN) {
2294 /* Returning from a successful sigreturn syscall.
2295 Avoid clobbering register state. */
2296 break;
2297 }
2298 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2299 env->active_tc.gpr[7] = 1; /* error flag */
2300 ret = -ret;
2301 } else {
2302 env->active_tc.gpr[7] = 0; /* error flag */
2303 }
2304 env->active_tc.gpr[2] = ret;
2305 break;
2306 case EXCP_TLBL:
2307 case EXCP_TLBS:
2308 case EXCP_AdEL:
2309 case EXCP_AdES:
2310 info.si_signo = TARGET_SIGSEGV;
2311 info.si_errno = 0;
2312 /* XXX: check env->error_code */
2313 info.si_code = TARGET_SEGV_MAPERR;
2314 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2316 break;
2317 case EXCP_CpU:
2318 case EXCP_RI:
2319 info.si_signo = TARGET_SIGILL;
2320 info.si_errno = 0;
2321 info.si_code = 0;
2322 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2323 break;
2324 case EXCP_INTERRUPT:
2325 /* just indicate that signals should be handled asap */
2326 break;
2327 case EXCP_DEBUG:
2328 {
2329 int sig;
2330
2331 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2332 if (sig)
2333 {
2334 info.si_signo = sig;
2335 info.si_errno = 0;
2336 info.si_code = TARGET_TRAP_BRKPT;
2337 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2338 }
2339 }
2340 break;
2341 case EXCP_SC:
2342 if (do_store_exclusive(env)) {
2343 info.si_signo = TARGET_SIGSEGV;
2344 info.si_errno = 0;
2345 info.si_code = TARGET_SEGV_MAPERR;
2346 info._sifields._sigfault._addr = env->active_tc.PC;
2347 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2348 }
2349 break;
2350 case EXCP_DSPDIS:
2351 info.si_signo = TARGET_SIGILL;
2352 info.si_errno = 0;
2353 info.si_code = TARGET_ILL_ILLOPC;
2354 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2355 break;
2356 /* The code below was inspired by the MIPS Linux kernel trap
2357 * handling code in arch/mips/kernel/traps.c.
2358 */
2359 case EXCP_BREAK:
2360 {
2361 abi_ulong trap_instr;
2362 unsigned int code;
2363
2364 if (env->hflags & MIPS_HFLAG_M16) {
2365 if (env->insn_flags & ASE_MICROMIPS) {
2366 /* microMIPS mode */
2367 ret = get_user_u16(trap_instr, env->active_tc.PC);
2368 if (ret != 0) {
2369 goto error;
2370 }
2371
2372 if ((trap_instr >> 10) == 0x11) {
2373 /* 16-bit instruction */
2374 code = trap_instr & 0xf;
2375 } else {
2376 /* 32-bit instruction */
2377 abi_ulong instr_lo;
2378
2379 ret = get_user_u16(instr_lo,
2380 env->active_tc.PC + 2);
2381 if (ret != 0) {
2382 goto error;
2383 }
2384 trap_instr = (trap_instr << 16) | instr_lo;
2385 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2386 /* Unfortunately, microMIPS also suffers from
2387 the old assembler bug... */
2388 if (code >= (1 << 10)) {
2389 code >>= 10;
2390 }
2391 }
2392 } else {
2393 /* MIPS16e mode */
2394 ret = get_user_u16(trap_instr, env->active_tc.PC);
2395 if (ret != 0) {
2396 goto error;
2397 }
2398 code = (trap_instr >> 6) & 0x3f;
2399 }
2400 } else {
2401 ret = get_user_u32(trap_instr, env->active_tc.PC);
2402 if (ret != 0) {
2403 goto error;
2404 }
2405
2406 /* As described in the original Linux kernel code, the
2407 * below checks on 'code' are to work around an old
2408 * assembly bug.
2409 */
2410 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2411 if (code >= (1 << 10)) {
2412 code >>= 10;
2413 }
2414 }
2415
2416 if (do_break(env, &info, code) != 0) {
2417 goto error;
2418 }
2419 }
2420 break;
2421 case EXCP_TRAP:
2422 {
2423 abi_ulong trap_instr;
2424 unsigned int code = 0;
2425
2426 if (env->hflags & MIPS_HFLAG_M16) {
2427 /* microMIPS mode */
2428 abi_ulong instr[2];
2429
2430 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2431 get_user_u16(instr[1], env->active_tc.PC + 2);
2432
2433 trap_instr = (instr[0] << 16) | instr[1];
2434 } else {
2435 ret = get_user_u32(trap_instr, env->active_tc.PC);
2436 }
2437
2438 if (ret != 0) {
2439 goto error;
2440 }
2441
2442 /* The immediate versions don't provide a code. */
2443 if (!(trap_instr & 0xFC000000)) {
2444 if (env->hflags & MIPS_HFLAG_M16) {
2445 /* microMIPS mode */
2446 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2447 } else {
2448 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2449 }
2450 }
2451
2452 if (do_break(env, &info, code) != 0) {
2453 goto error;
2454 }
2455 }
2456 break;
2457 case EXCP_ATOMIC:
2458 cpu_exec_step_atomic(cs);
2459 break;
2460 default:
2461 error:
2462 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2463 abort();
2464 }
2465 process_pending_signals(env);
2466 }
2467 }
2468 #endif
2469
2470 #ifdef TARGET_NIOS2
2471
2472 void cpu_loop(CPUNios2State *env)
2473 {
2474 CPUState *cs = ENV_GET_CPU(env);
2475 Nios2CPU *cpu = NIOS2_CPU(cs);
2476 target_siginfo_t info;
2477 int trapnr, gdbsig, ret;
2478
2479 for (;;) {
2480 cpu_exec_start(cs);
2481 trapnr = cpu_exec(cs);
2482 cpu_exec_end(cs);
2483 gdbsig = 0;
2484
2485 switch (trapnr) {
2486 case EXCP_INTERRUPT:
2487 /* just indicate that signals should be handled asap */
2488 break;
2489 case EXCP_TRAP:
2490 if (env->regs[R_AT] == 0) {
2491 abi_long ret;
2492 qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
2493
2494 ret = do_syscall(env, env->regs[2],
2495 env->regs[4], env->regs[5], env->regs[6],
2496 env->regs[7], env->regs[8], env->regs[9],
2497 0, 0);
2498
2499 if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */
2500 ret = 0;
2501 }
2502
2503 env->regs[2] = abs(ret);
2504 /* Return value is 0..4096 */
2505 env->regs[7] = (ret > 0xfffffffffffff000ULL);
2506 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2507 env->regs[CR_STATUS] &= ~0x3;
2508 env->regs[R_EA] = env->regs[R_PC] + 4;
2509 env->regs[R_PC] += 4;
2510 break;
2511 } else {
2512 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2513
2514 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2515 env->regs[CR_STATUS] &= ~0x3;
2516 env->regs[R_EA] = env->regs[R_PC] + 4;
2517 env->regs[R_PC] = cpu->exception_addr;
2518
2519 gdbsig = TARGET_SIGTRAP;
2520 break;
2521 }
2522 case 0xaa:
2523 switch (env->regs[R_PC]) {
2524 /*case 0x1000:*/ /* TODO:__kuser_helper_version */
2525 case 0x1004: /* __kuser_cmpxchg */
2526 start_exclusive();
2527 if (env->regs[4] & 0x3) {
2528 goto kuser_fail;
2529 }
2530 ret = get_user_u32(env->regs[2], env->regs[4]);
2531 if (ret) {
2532 end_exclusive();
2533 goto kuser_fail;
2534 }
2535 env->regs[2] -= env->regs[5];
2536 if (env->regs[2] == 0) {
2537 put_user_u32(env->regs[6], env->regs[4]);
2538 }
2539 end_exclusive();
2540 env->regs[R_PC] = env->regs[R_RA];
2541 break;
2542 /*case 0x1040:*/ /* TODO:__kuser_sigtramp */
2543 default:
2544 ;
2545 kuser_fail:
2546 info.si_signo = TARGET_SIGSEGV;
2547 info.si_errno = 0;
2548 /* TODO: check env->error_code */
2549 info.si_code = TARGET_SEGV_MAPERR;
2550 info._sifields._sigfault._addr = env->regs[R_PC];
2551 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2552 }
2553 break;
2554 default:
2555 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2556 trapnr);
2557 gdbsig = TARGET_SIGILL;
2558 break;
2559 }
2560 if (gdbsig) {
2561 gdb_handlesig(cs, gdbsig);
2562 if (gdbsig != TARGET_SIGTRAP) {
2563 exit(EXIT_FAILURE);
2564 }
2565 }
2566
2567 process_pending_signals(env);
2568 }
2569 }
2570
2571 #endif /* TARGET_NIOS2 */
2572
2573 #ifdef TARGET_OPENRISC
2574
2575 void cpu_loop(CPUOpenRISCState *env)
2576 {
2577 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2578 int trapnr;
2579 abi_long ret;
2580 target_siginfo_t info;
2581
2582 for (;;) {
2583 cpu_exec_start(cs);
2584 trapnr = cpu_exec(cs);
2585 cpu_exec_end(cs);
2586 process_queued_cpu_work(cs);
2587
2588 switch (trapnr) {
2589 case EXCP_SYSCALL:
2590 env->pc += 4; /* 0xc00; */
2591 ret = do_syscall(env,
2592 env->gpr[11], /* return value */
2593 env->gpr[3], /* r3 - r7 are params */
2594 env->gpr[4],
2595 env->gpr[5],
2596 env->gpr[6],
2597 env->gpr[7],
2598 env->gpr[8], 0, 0);
2599 if (ret == -TARGET_ERESTARTSYS) {
2600 env->pc -= 4;
2601 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2602 env->gpr[11] = ret;
2603 }
2604 break;
2605 case EXCP_DPF:
2606 case EXCP_IPF:
2607 case EXCP_RANGE:
2608 info.si_signo = TARGET_SIGSEGV;
2609 info.si_errno = 0;
2610 info.si_code = TARGET_SEGV_MAPERR;
2611 info._sifields._sigfault._addr = env->pc;
2612 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2613 break;
2614 case EXCP_ALIGN:
2615 info.si_signo = TARGET_SIGBUS;
2616 info.si_errno = 0;
2617 info.si_code = TARGET_BUS_ADRALN;
2618 info._sifields._sigfault._addr = env->pc;
2619 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2620 break;
2621 case EXCP_ILLEGAL:
2622 info.si_signo = TARGET_SIGILL;
2623 info.si_errno = 0;
2624 info.si_code = TARGET_ILL_ILLOPC;
2625 info._sifields._sigfault._addr = env->pc;
2626 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2627 break;
2628 case EXCP_FPE:
2629 info.si_signo = TARGET_SIGFPE;
2630 info.si_errno = 0;
2631 info.si_code = 0;
2632 info._sifields._sigfault._addr = env->pc;
2633 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2634 break;
2635 case EXCP_INTERRUPT:
2636 /* We processed the pending cpu work above. */
2637 break;
2638 case EXCP_DEBUG:
2639 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
2640 if (trapnr) {
2641 info.si_signo = trapnr;
2642 info.si_errno = 0;
2643 info.si_code = TARGET_TRAP_BRKPT;
2644 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2645 }
2646 break;
2647 case EXCP_ATOMIC:
2648 cpu_exec_step_atomic(cs);
2649 break;
2650 default:
2651 g_assert_not_reached();
2652 }
2653 process_pending_signals(env);
2654 }
2655 }
2656
2657 #endif /* TARGET_OPENRISC */
2658
2659 #ifdef TARGET_SH4
2660 void cpu_loop(CPUSH4State *env)
2661 {
2662 CPUState *cs = CPU(sh_env_get_cpu(env));
2663 int trapnr, ret;
2664 target_siginfo_t info;
2665
2666 while (1) {
2667 cpu_exec_start(cs);
2668 trapnr = cpu_exec(cs);
2669 cpu_exec_end(cs);
2670 process_queued_cpu_work(cs);
2671
2672 switch (trapnr) {
2673 case 0x160:
2674 env->pc += 2;
2675 ret = do_syscall(env,
2676 env->gregs[3],
2677 env->gregs[4],
2678 env->gregs[5],
2679 env->gregs[6],
2680 env->gregs[7],
2681 env->gregs[0],
2682 env->gregs[1],
2683 0, 0);
2684 if (ret == -TARGET_ERESTARTSYS) {
2685 env->pc -= 2;
2686 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2687 env->gregs[0] = ret;
2688 }
2689 break;
2690 case EXCP_INTERRUPT:
2691 /* just indicate that signals should be handled asap */
2692 break;
2693 case EXCP_DEBUG:
2694 {
2695 int sig;
2696
2697 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2698 if (sig)
2699 {
2700 info.si_signo = sig;
2701 info.si_errno = 0;
2702 info.si_code = TARGET_TRAP_BRKPT;
2703 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2704 }
2705 }
2706 break;
2707 case 0xa0:
2708 case 0xc0:
2709 info.si_signo = TARGET_SIGSEGV;
2710 info.si_errno = 0;
2711 info.si_code = TARGET_SEGV_MAPERR;
2712 info._sifields._sigfault._addr = env->tea;
2713 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2714 break;
2715
2716 case EXCP_ATOMIC:
2717 cpu_exec_step_atomic(cs);
2718 break;
2719 default:
2720 printf ("Unhandled trap: 0x%x\n", trapnr);
2721 cpu_dump_state(cs, stderr, fprintf, 0);
2722 exit(EXIT_FAILURE);
2723 }
2724 process_pending_signals (env);
2725 }
2726 }
2727 #endif
2728
2729 #ifdef TARGET_CRIS
2730 void cpu_loop(CPUCRISState *env)
2731 {
2732 CPUState *cs = CPU(cris_env_get_cpu(env));
2733 int trapnr, ret;
2734 target_siginfo_t info;
2735
2736 while (1) {
2737 cpu_exec_start(cs);
2738 trapnr = cpu_exec(cs);
2739 cpu_exec_end(cs);
2740 process_queued_cpu_work(cs);
2741
2742 switch (trapnr) {
2743 case 0xaa:
2744 {
2745 info.si_signo = TARGET_SIGSEGV;
2746 info.si_errno = 0;
2747 /* XXX: check env->error_code */
2748 info.si_code = TARGET_SEGV_MAPERR;
2749 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2750 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2751 }
2752 break;
2753 case EXCP_INTERRUPT:
2754 /* just indicate that signals should be handled asap */
2755 break;
2756 case EXCP_BREAK:
2757 ret = do_syscall(env,
2758 env->regs[9],
2759 env->regs[10],
2760 env->regs[11],
2761 env->regs[12],
2762 env->regs[13],
2763 env->pregs[7],
2764 env->pregs[11],
2765 0, 0);
2766 if (ret == -TARGET_ERESTARTSYS) {
2767 env->pc -= 2;
2768 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2769 env->regs[10] = ret;
2770 }
2771 break;
2772 case EXCP_DEBUG:
2773 {
2774 int sig;
2775
2776 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2777 if (sig)
2778 {
2779 info.si_signo = sig;
2780 info.si_errno = 0;
2781 info.si_code = TARGET_TRAP_BRKPT;
2782 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2783 }
2784 }
2785 break;
2786 case EXCP_ATOMIC:
2787 cpu_exec_step_atomic(cs);
2788 break;
2789 default:
2790 printf ("Unhandled trap: 0x%x\n", trapnr);
2791 cpu_dump_state(cs, stderr, fprintf, 0);
2792 exit(EXIT_FAILURE);
2793 }
2794 process_pending_signals (env);
2795 }
2796 }
2797 #endif
2798
2799 #ifdef TARGET_MICROBLAZE
2800 void cpu_loop(CPUMBState *env)
2801 {
2802 CPUState *cs = CPU(mb_env_get_cpu(env));
2803 int trapnr, ret;
2804 target_siginfo_t info;
2805
2806 while (1) {
2807 cpu_exec_start(cs);
2808 trapnr = cpu_exec(cs);
2809 cpu_exec_end(cs);
2810 process_queued_cpu_work(cs);
2811
2812 switch (trapnr) {
2813 case 0xaa:
2814 {
2815 info.si_signo = TARGET_SIGSEGV;
2816 info.si_errno = 0;
2817 /* XXX: check env->error_code */
2818 info.si_code = TARGET_SEGV_MAPERR;
2819 info._sifields._sigfault._addr = 0;
2820 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2821 }
2822 break;
2823 case EXCP_INTERRUPT:
2824 /* just indicate that signals should be handled asap */
2825 break;
2826 case EXCP_BREAK:
2827 /* Return address is 4 bytes after the call. */
2828 env->regs[14] += 4;
2829 env->sregs[SR_PC] = env->regs[14];
2830 ret = do_syscall(env,
2831 env->regs[12],
2832 env->regs[5],
2833 env->regs[6],
2834 env->regs[7],
2835 env->regs[8],
2836 env->regs[9],
2837 env->regs[10],
2838 0, 0);
2839 if (ret == -TARGET_ERESTARTSYS) {
2840 /* Wind back to before the syscall. */
2841 env->sregs[SR_PC] -= 4;
2842 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2843 env->regs[3] = ret;
2844 }
2845 /* All syscall exits result in guest r14 being equal to the
2846 * PC we return to, because the kernel syscall exit "rtbd" does
2847 * this. (This is true even for sigreturn(); note that r14 is
2848 * not a userspace-usable register, as the kernel may clobber it
2849 * at any point.)
2850 */
2851 env->regs[14] = env->sregs[SR_PC];
2852 break;
2853 case EXCP_HW_EXCP:
2854 env->regs[17] = env->sregs[SR_PC] + 4;
2855 if (env->iflags & D_FLAG) {
2856 env->sregs[SR_ESR] |= 1 << 12;
2857 env->sregs[SR_PC] -= 4;
2858 /* FIXME: if branch was immed, replay the imm as well. */
2859 }
2860
2861 env->iflags &= ~(IMM_FLAG | D_FLAG);
2862
2863 switch (env->sregs[SR_ESR] & 31) {
2864 case ESR_EC_DIVZERO:
2865 info.si_signo = TARGET_SIGFPE;
2866 info.si_errno = 0;
2867 info.si_code = TARGET_FPE_FLTDIV;
2868 info._sifields._sigfault._addr = 0;
2869 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2870 break;
2871 case ESR_EC_FPU:
2872 info.si_signo = TARGET_SIGFPE;
2873 info.si_errno = 0;
2874 if (env->sregs[SR_FSR] & FSR_IO) {
2875 info.si_code = TARGET_FPE_FLTINV;
2876 }
2877 if (env->sregs[SR_FSR] & FSR_DZ) {
2878 info.si_code = TARGET_FPE_FLTDIV;
2879 }
2880 info._sifields._sigfault._addr = 0;
2881 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2882 break;
2883 default:
2884 printf ("Unhandled hw-exception: 0x%x\n",
2885 env->sregs[SR_ESR] & ESR_EC_MASK);
2886 cpu_dump_state(cs, stderr, fprintf, 0);
2887 exit(EXIT_FAILURE);
2888 break;
2889 }
2890 break;
2891 case EXCP_DEBUG:
2892 {
2893 int sig;
2894
2895 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2896 if (sig)
2897 {
2898 info.si_signo = sig;
2899 info.si_errno = 0;
2900 info.si_code = TARGET_TRAP_BRKPT;
2901 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2902 }
2903 }
2904 break;
2905 case EXCP_ATOMIC:
2906 cpu_exec_step_atomic(cs);
2907 break;
2908 default:
2909 printf ("Unhandled trap: 0x%x\n", trapnr);
2910 cpu_dump_state(cs, stderr, fprintf, 0);
2911 exit(EXIT_FAILURE);
2912 }
2913 process_pending_signals (env);
2914 }
2915 }
2916 #endif
2917
2918 #ifdef TARGET_M68K
2919
2920 void cpu_loop(CPUM68KState *env)
2921 {
2922 CPUState *cs = CPU(m68k_env_get_cpu(env));
2923 int trapnr;
2924 unsigned int n;
2925 target_siginfo_t info;
2926 TaskState *ts = cs->opaque;
2927
2928 for(;;) {
2929 cpu_exec_start(cs);
2930 trapnr = cpu_exec(cs);
2931 cpu_exec_end(cs);
2932 process_queued_cpu_work(cs);
2933
2934 switch(trapnr) {
2935 case EXCP_ILLEGAL:
2936 {
2937 if (ts->sim_syscalls) {
2938 uint16_t nr;
2939 get_user_u16(nr, env->pc + 2);
2940 env->pc += 4;
2941 do_m68k_simcall(env, nr);
2942 } else {
2943 goto do_sigill;
2944 }
2945 }
2946 break;
2947 case EXCP_HALT_INSN:
2948 /* Semihosing syscall. */
2949 env->pc += 4;
2950 do_m68k_semihosting(env, env->dregs[0]);
2951 break;
2952 case EXCP_LINEA:
2953 case EXCP_LINEF:
2954 case EXCP_UNSUPPORTED:
2955 do_sigill:
2956 info.si_signo = TARGET_SIGILL;
2957 info.si_errno = 0;
2958 info.si_code = TARGET_ILL_ILLOPN;
2959 info._sifields._sigfault._addr = env->pc;
2960 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2961 break;
2962 case EXCP_DIV0:
2963 info.si_signo = TARGET_SIGFPE;
2964 info.si_errno = 0;
2965 info.si_code = TARGET_FPE_INTDIV;
2966 info._sifields._sigfault._addr = env->pc;
2967 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2968 break;
2969 case EXCP_TRAP0:
2970 {
2971 abi_long ret;
2972 ts->sim_syscalls = 0;
2973 n = env->dregs[0];
2974 env->pc += 2;
2975 ret = do_syscall(env,
2976 n,
2977 env->dregs[1],
2978 env->dregs[2],
2979 env->dregs[3],
2980 env->dregs[4],
2981 env->dregs[5],
2982 env->aregs[0],
2983 0, 0);
2984 if (ret == -TARGET_ERESTARTSYS) {
2985 env->pc -= 2;
2986 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2987 env->dregs[0] = ret;
2988 }
2989 }
2990 break;
2991 case EXCP_INTERRUPT:
2992 /* just indicate that signals should be handled asap */
2993 break;
2994 case EXCP_ACCESS:
2995 {
2996 info.si_signo = TARGET_SIGSEGV;
2997 info.si_errno = 0;
2998 /* XXX: check env->error_code */
2999 info.si_code = TARGET_SEGV_MAPERR;
3000 info._sifields._sigfault._addr = env->mmu.ar;
3001 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3002 }
3003 break;
3004 case EXCP_DEBUG:
3005 {
3006 int sig;
3007
3008 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3009 if (sig)
3010 {
3011 info.si_signo = sig;
3012 info.si_errno = 0;
3013 info.si_code = TARGET_TRAP_BRKPT;
3014 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3015 }
3016 }
3017 break;
3018 case EXCP_ATOMIC:
3019 cpu_exec_step_atomic(cs);
3020 break;
3021 default:
3022 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3023 abort();
3024 }
3025 process_pending_signals(env);
3026 }
3027 }
3028 #endif /* TARGET_M68K */
3029
3030 #ifdef TARGET_ALPHA
3031 void cpu_loop(CPUAlphaState *env)
3032 {
3033 CPUState *cs = CPU(alpha_env_get_cpu(env));
3034 int trapnr;
3035 target_siginfo_t info;
3036 abi_long sysret;
3037
3038 while (1) {
3039 cpu_exec_start(cs);
3040 trapnr = cpu_exec(cs);
3041 cpu_exec_end(cs);
3042 process_queued_cpu_work(cs);
3043
3044 /* All of the traps imply a transition through PALcode, which
3045 implies an REI instruction has been executed. Which means
3046 that the intr_flag should be cleared. */
3047 env->intr_flag = 0;
3048
3049 switch (trapnr) {
3050 case EXCP_RESET:
3051 fprintf(stderr, "Reset requested. Exit\n");
3052 exit(EXIT_FAILURE);
3053 break;
3054 case EXCP_MCHK:
3055 fprintf(stderr, "Machine check exception. Exit\n");
3056 exit(EXIT_FAILURE);
3057 break;
3058 case EXCP_SMP_INTERRUPT:
3059 case EXCP_CLK_INTERRUPT:
3060 case EXCP_DEV_INTERRUPT:
3061 fprintf(stderr, "External interrupt. Exit\n");
3062 exit(EXIT_FAILURE);
3063 break;
3064 case EXCP_MMFAULT:
3065 env->lock_addr = -1;
3066 info.si_signo = TARGET_SIGSEGV;
3067 info.si_errno = 0;
3068 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3069 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3070 info._sifields._sigfault._addr = env->trap_arg0;
3071 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3072 break;
3073 case EXCP_UNALIGN:
3074 env->lock_addr = -1;
3075 info.si_signo = TARGET_SIGBUS;
3076 info.si_errno = 0;
3077 info.si_code = TARGET_BUS_ADRALN;
3078 info._sifields._sigfault._addr = env->trap_arg0;
3079 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3080 break;
3081 case EXCP_OPCDEC:
3082 do_sigill:
3083 env->lock_addr = -1;
3084 info.si_signo = TARGET_SIGILL;
3085 info.si_errno = 0;
3086 info.si_code = TARGET_ILL_ILLOPC;
3087 info._sifields._sigfault._addr = env->pc;
3088 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3089 break;
3090 case EXCP_ARITH:
3091 env->lock_addr = -1;
3092 info.si_signo = TARGET_SIGFPE;
3093 info.si_errno = 0;
3094 info.si_code = TARGET_FPE_FLTINV;
3095 info._sifields._sigfault._addr = env->pc;
3096 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3097 break;
3098 case EXCP_FEN:
3099 /* No-op. Linux simply re-enables the FPU. */
3100 break;
3101 case EXCP_CALL_PAL:
3102 env->lock_addr = -1;
3103 switch (env->error_code) {
3104 case 0x80:
3105 /* BPT */
3106 info.si_signo = TARGET_SIGTRAP;
3107 info.si_errno = 0;
3108 info.si_code = TARGET_TRAP_BRKPT;
3109 info._sifields._sigfault._addr = env->pc;
3110 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3111 break;
3112 case 0x81:
3113 /* BUGCHK */
3114 info.si_signo = TARGET_SIGTRAP;
3115 info.si_errno = 0;
3116 info.si_code = 0;
3117 info._sifields._sigfault._addr = env->pc;
3118 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3119 break;
3120 case 0x83:
3121 /* CALLSYS */
3122 trapnr = env->ir[IR_V0];
3123 sysret = do_syscall(env, trapnr,
3124 env->ir[IR_A0], env->ir[IR_A1],
3125 env->ir[IR_A2], env->ir[IR_A3],
3126 env->ir[IR_A4], env->ir[IR_A5],
3127 0, 0);
3128 if (sysret == -TARGET_ERESTARTSYS) {
3129 env->pc -= 4;
3130 break;
3131 }
3132 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3133 break;
3134 }
3135 /* Syscall writes 0 to V0 to bypass error check, similar
3136 to how this is handled internal to Linux kernel.
3137 (Ab)use trapnr temporarily as boolean indicating error. */
3138 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3139 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3140 env->ir[IR_A3] = trapnr;
3141 break;
3142 case 0x86:
3143 /* IMB */
3144 /* ??? We can probably elide the code using page_unprotect
3145 that is checking for self-modifying code. Instead we
3146 could simply call tb_flush here. Until we work out the
3147 changes required to turn off the extra write protection,
3148 this can be a no-op. */
3149 break;
3150 case 0x9E:
3151 /* RDUNIQUE */
3152 /* Handled in the translator for usermode. */
3153 abort();
3154 case 0x9F:
3155 /* WRUNIQUE */
3156 /* Handled in the translator for usermode. */
3157 abort();
3158 case 0xAA:
3159 /* GENTRAP */
3160 info.si_signo = TARGET_SIGFPE;
3161 switch (env->ir[IR_A0]) {
3162 case TARGET_GEN_INTOVF:
3163 info.si_code = TARGET_FPE_INTOVF;
3164 break;
3165 case TARGET_GEN_INTDIV:
3166 info.si_code = TARGET_FPE_INTDIV;
3167 break;
3168 case TARGET_GEN_FLTOVF:
3169 info.si_code = TARGET_FPE_FLTOVF;
3170 break;
3171 case TARGET_GEN_FLTUND:
3172 info.si_code = TARGET_FPE_FLTUND;
3173 break;
3174 case TARGET_GEN_FLTINV:
3175 info.si_code = TARGET_FPE_FLTINV;
3176 break;
3177 case TARGET_GEN_FLTINE:
3178 info.si_code = TARGET_FPE_FLTRES;
3179 break;
3180 case TARGET_GEN_ROPRAND:
3181 info.si_code = 0;
3182 break;
3183 default:
3184 info.si_signo = TARGET_SIGTRAP;
3185 info.si_code = 0;
3186 break;
3187 }
3188 info.si_errno = 0;
3189 info._sifields._sigfault._addr = env->pc;
3190 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3191 break;
3192 default:
3193 goto do_sigill;
3194 }
3195 break;
3196 case EXCP_DEBUG:
3197 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3198 if (info.si_signo) {
3199 env->lock_addr = -1;
3200 info.si_errno = 0;
3201 info.si_code = TARGET_TRAP_BRKPT;
3202 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3203 }
3204 break;
3205 case EXCP_INTERRUPT:
3206 /* Just indicate that signals should be handled asap. */
3207 break;
3208 case EXCP_ATOMIC:
3209 cpu_exec_step_atomic(cs);
3210 break;
3211 default:
3212 printf ("Unhandled trap: 0x%x\n", trapnr);
3213 cpu_dump_state(cs, stderr, fprintf, 0);
3214 exit(EXIT_FAILURE);
3215 }
3216 process_pending_signals (env);
3217 }
3218 }
3219 #endif /* TARGET_ALPHA */
3220
3221 #ifdef TARGET_S390X
3222 void cpu_loop(CPUS390XState *env)
3223 {
3224 CPUState *cs = CPU(s390_env_get_cpu(env));
3225 int trapnr, n, sig;
3226 target_siginfo_t info;
3227 target_ulong addr;
3228 abi_long ret;
3229
3230 while (1) {
3231 cpu_exec_start(cs);
3232 trapnr = cpu_exec(cs);
3233 cpu_exec_end(cs);
3234 process_queued_cpu_work(cs);
3235
3236 switch (trapnr) {
3237 case EXCP_INTERRUPT:
3238 /* Just indicate that signals should be handled asap. */
3239 break;
3240
3241 case EXCP_SVC:
3242 n = env->int_svc_code;
3243 if (!n) {
3244 /* syscalls > 255 */
3245 n = env->regs[1];
3246 }
3247 env->psw.addr += env->int_svc_ilen;
3248 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3249 env->regs[4], env->regs[5],
3250 env->regs[6], env->regs[7], 0, 0);
3251 if (ret == -TARGET_ERESTARTSYS) {
3252 env->psw.addr -= env->int_svc_ilen;
3253 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3254 env->regs[2] = ret;
3255 }
3256 break;
3257
3258 case EXCP_DEBUG:
3259 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3260 if (sig) {
3261 n = TARGET_TRAP_BRKPT;
3262 goto do_signal_pc;
3263 }
3264 break;
3265 case EXCP_PGM:
3266 n = env->int_pgm_code;
3267 switch (n) {
3268 case PGM_OPERATION:
3269 case PGM_PRIVILEGED:
3270 sig = TARGET_SIGILL;
3271 n = TARGET_ILL_ILLOPC;
3272 goto do_signal_pc;
3273 case PGM_PROTECTION:
3274 case PGM_ADDRESSING:
3275 sig = TARGET_SIGSEGV;
3276 /* XXX: check env->error_code */
3277 n = TARGET_SEGV_MAPERR;
3278 addr = env->__excp_addr;
3279 goto do_signal;
3280 case PGM_EXECUTE:
3281 case PGM_SPECIFICATION:
3282 case PGM_SPECIAL_OP:
3283 case PGM_OPERAND:
3284 do_sigill_opn:
3285 sig = TARGET_SIGILL;
3286 n = TARGET_ILL_ILLOPN;
3287 goto do_signal_pc;
3288
3289 case PGM_FIXPT_OVERFLOW:
3290 sig = TARGET_SIGFPE;
3291 n = TARGET_FPE_INTOVF;
3292 goto do_signal_pc;
3293 case PGM_FIXPT_DIVIDE:
3294 sig = TARGET_SIGFPE;
3295 n = TARGET_FPE_INTDIV;
3296 goto do_signal_pc;
3297
3298 case PGM_DATA:
3299 n = (env->fpc >> 8) & 0xff;
3300 if (n == 0xff) {
3301 /* compare-and-trap */
3302 goto do_sigill_opn;
3303 } else {
3304 /* An IEEE exception, simulated or otherwise. */
3305 if (n & 0x80) {
3306 n = TARGET_FPE_FLTINV;
3307 } else if (n & 0x40) {
3308 n = TARGET_FPE_FLTDIV;
3309 } else if (n & 0x20) {
3310 n = TARGET_FPE_FLTOVF;
3311 } else if (n & 0x10) {
3312 n = TARGET_FPE_FLTUND;
3313 } else if (n & 0x08) {
3314 n = TARGET_FPE_FLTRES;
3315 } else {
3316 /* ??? Quantum exception; BFP, DFP error. */
3317 goto do_sigill_opn;
3318 }
3319 sig = TARGET_SIGFPE;
3320 goto do_signal_pc;
3321 }
3322
3323 default:
3324 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3325 cpu_dump_state(cs, stderr, fprintf, 0);
3326 exit(EXIT_FAILURE);
3327 }
3328 break;
3329
3330 do_signal_pc:
3331 addr = env->psw.addr;
3332 do_signal:
3333 info.si_signo = sig;
3334 info.si_errno = 0;
3335 info.si_code = n;
3336 info._sifields._sigfault._addr = addr;
3337 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3338 break;
3339
3340 case EXCP_ATOMIC:
3341 cpu_exec_step_atomic(cs);
3342 break;
3343 default:
3344 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3345 cpu_dump_state(cs, stderr, fprintf, 0);
3346 exit(EXIT_FAILURE);
3347 }
3348 process_pending_signals (env);
3349 }
3350 }
3351
3352 #endif /* TARGET_S390X */
3353
3354 #ifdef TARGET_TILEGX
3355
3356 static void gen_sigill_reg(CPUTLGState *env)
3357 {
3358 target_siginfo_t info;
3359
3360 info.si_signo = TARGET_SIGILL;
3361 info.si_errno = 0;
3362 info.si_code = TARGET_ILL_PRVREG;
3363 info._sifields._sigfault._addr = env->pc;
3364 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3365 }
3366
3367 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3368 {
3369 target_siginfo_t info;
3370
3371 info.si_signo = signo;
3372 info.si_errno = 0;
3373 info._sifields._sigfault._addr = env->pc;
3374
3375 if (signo == TARGET_SIGSEGV) {
3376 /* The passed in sigcode is a dummy; check for a page mapping
3377 and pass either MAPERR or ACCERR. */
3378 target_ulong addr = env->excaddr;
3379 info._sifields._sigfault._addr = addr;
3380 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3381 sigcode = TARGET_SEGV_MAPERR;
3382 } else {
3383 sigcode = TARGET_SEGV_ACCERR;
3384 }
3385 }
3386 info.si_code = sigcode;
3387
3388 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3389 }
3390
3391 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3392 {
3393 env->excaddr = addr;
3394 do_signal(env, TARGET_SIGSEGV, 0);
3395 }
3396
3397 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3398 {
3399 if (unlikely(reg >= TILEGX_R_COUNT)) {
3400 switch (reg) {
3401 case TILEGX_R_SN:
3402 case TILEGX_R_ZERO:
3403 return;
3404 case TILEGX_R_IDN0:
3405 case TILEGX_R_IDN1:
3406 case TILEGX_R_UDN0:
3407 case TILEGX_R_UDN1:
3408 case TILEGX_R_UDN2:
3409 case TILEGX_R_UDN3:
3410 gen_sigill_reg(env);
3411 return;
3412 default:
3413 g_assert_not_reached();
3414 }
3415 }
3416 env->regs[reg] = val;
3417 }
3418
3419 /*
3420 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3421 * memory at the address held in the first source register. If the values are
3422 * not equal, then no memory operation is performed. If the values are equal,
3423 * the 8-byte quantity from the second source register is written into memory
3424 * at the address held in the first source register. In either case, the result
3425 * of the instruction is the value read from memory. The compare and write to
3426 * memory are atomic and thus can be used for synchronization purposes. This
3427 * instruction only operates for addresses aligned to a 8-byte boundary.
3428 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3429 *
3430 * Functional Description (64-bit)
3431 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3432 * rf[Dest] = memVal;
3433 * if (memVal == SPR[CmpValueSPR])
3434 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3435 *
3436 * Functional Description (32-bit)
3437 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3438 * rf[Dest] = memVal;
3439 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3440 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3441 *
3442 *
3443 * This function also processes exch and exch4 which need not process SPR.
3444 */
3445 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3446 {
3447 target_ulong addr;
3448 target_long val, sprval;
3449
3450 start_exclusive();
3451
3452 addr = env->atomic_srca;
3453 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3454 goto sigsegv_maperr;
3455 }
3456
3457 if (cmp) {
3458 if (quad) {
3459 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3460 } else {
3461 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3462 }
3463 }
3464
3465 if (!cmp || val == sprval) {
3466 target_long valb = env->atomic_srcb;
3467 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3468 goto sigsegv_maperr;
3469 }
3470 }
3471
3472 set_regval(env, env->atomic_dstr, val);
3473 end_exclusive();
3474 return;
3475
3476 sigsegv_maperr:
3477 end_exclusive();
3478 gen_sigsegv_maperr(env, addr);
3479 }
3480
3481 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3482 {
3483 int8_t write = 1;
3484 target_ulong addr;
3485 target_long val, valb;
3486
3487 start_exclusive();
3488
3489 addr = env->atomic_srca;
3490 valb = env->atomic_srcb;
3491 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3492 goto sigsegv_maperr;
3493 }
3494
3495 switch (trapnr) {
3496 case TILEGX_EXCP_OPCODE_FETCHADD:
3497 case TILEGX_EXCP_OPCODE_FETCHADD4:
3498 valb += val;
3499 break;
3500 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3501 valb += val;
3502 if (valb < 0) {
3503 write = 0;
3504 }
3505 break;
3506 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3507 valb += val;
3508 if ((int32_t)valb < 0) {
3509 write = 0;
3510 }
3511 break;
3512 case TILEGX_EXCP_OPCODE_FETCHAND:
3513 case TILEGX_EXCP_OPCODE_FETCHAND4:
3514 valb &= val;
3515 break;
3516 case TILEGX_EXCP_OPCODE_FETCHOR:
3517 case TILEGX_EXCP_OPCODE_FETCHOR4:
3518 valb |= val;
3519 break;
3520 default:
3521 g_assert_not_reached();
3522 }
3523
3524 if (write) {
3525 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3526 goto sigsegv_maperr;
3527 }
3528 }
3529
3530 set_regval(env, env->atomic_dstr, val);
3531 end_exclusive();
3532 return;
3533
3534 sigsegv_maperr:
3535 end_exclusive();
3536 gen_sigsegv_maperr(env, addr);
3537 }
3538
3539 void cpu_loop(CPUTLGState *env)
3540 {
3541 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3542 int trapnr;
3543
3544 while (1) {
3545 cpu_exec_start(cs);
3546 trapnr = cpu_exec(cs);
3547 cpu_exec_end(cs);
3548 process_queued_cpu_work(cs);
3549
3550 switch (trapnr) {
3551 case TILEGX_EXCP_SYSCALL:
3552 {
3553 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3554 env->regs[0], env->regs[1],
3555 env->regs[2], env->regs[3],
3556 env->regs[4], env->regs[5],
3557 env->regs[6], env->regs[7]);
3558 if (ret == -TARGET_ERESTARTSYS) {
3559 env->pc -= 8;
3560 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3561 env->regs[TILEGX_R_RE] = ret;
3562 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3563 }
3564 break;
3565 }
3566 case TILEGX_EXCP_OPCODE_EXCH:
3567 do_exch(env, true, false);
3568 break;
3569 case TILEGX_EXCP_OPCODE_EXCH4:
3570 do_exch(env, false, false);
3571 break;
3572 case TILEGX_EXCP_OPCODE_CMPEXCH:
3573 do_exch(env, true, true);
3574 break;
3575 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3576 do_exch(env, false, true);
3577 break;
3578 case TILEGX_EXCP_OPCODE_FETCHADD:
3579 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3580 case TILEGX_EXCP_OPCODE_FETCHAND:
3581 case TILEGX_EXCP_OPCODE_FETCHOR:
3582 do_fetch(env, trapnr, true);
3583 break;
3584 case TILEGX_EXCP_OPCODE_FETCHADD4:
3585 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3586 case TILEGX_EXCP_OPCODE_FETCHAND4:
3587 case TILEGX_EXCP_OPCODE_FETCHOR4:
3588 do_fetch(env, trapnr, false);
3589 break;
3590 case TILEGX_EXCP_SIGNAL:
3591 do_signal(env, env->signo, env->sigcode);
3592 break;
3593 case TILEGX_EXCP_REG_IDN_ACCESS:
3594 case TILEGX_EXCP_REG_UDN_ACCESS:
3595 gen_sigill_reg(env);
3596 break;
3597 case EXCP_ATOMIC:
3598 cpu_exec_step_atomic(cs);
3599 break;
3600 default:
3601 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3602 g_assert_not_reached();
3603 }
3604 process_pending_signals(env);
3605 }
3606 }
3607
3608 #endif
3609
3610 #ifdef TARGET_HPPA
3611
3612 static abi_ulong hppa_lws(CPUHPPAState *env)
3613 {
3614 uint32_t which = env->gr[20];
3615 abi_ulong addr = env->gr[26];
3616 abi_ulong old = env->gr[25];
3617 abi_ulong new = env->gr[24];
3618 abi_ulong size, ret;
3619
3620 switch (which) {
3621 default:
3622 return -TARGET_ENOSYS;
3623
3624 case 0: /* elf32 atomic 32bit cmpxchg */
3625 if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) {
3626 return -TARGET_EFAULT;
3627 }
3628 old = tswap32(old);
3629 new = tswap32(new);
3630 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3631 ret = tswap32(ret);
3632 break;
3633
3634 case 2: /* elf32 atomic "new" cmpxchg */
3635 size = env->gr[23];
3636 if (size >= 4) {
3637 return -TARGET_ENOSYS;
3638 }
3639 if (((addr | old | new) & ((1 << size) - 1))
3640 || !access_ok(VERIFY_WRITE, addr, 1 << size)
3641 || !access_ok(VERIFY_READ, old, 1 << size)
3642 || !access_ok(VERIFY_READ, new, 1 << size)) {
3643 return -TARGET_EFAULT;
3644 }
3645 /* Note that below we use host-endian loads so that the cmpxchg
3646 can be host-endian as well. */
3647 switch (size) {
3648 case 0:
3649 old = *(uint8_t *)g2h(old);
3650 new = *(uint8_t *)g2h(new);
3651 ret = atomic_cmpxchg((uint8_t *)g2h(addr), old, new);
3652 ret = ret != old;
3653 break;
3654 case 1:
3655 old = *(uint16_t *)g2h(old);
3656 new = *(uint16_t *)g2h(new);
3657 ret = atomic_cmpxchg((uint16_t *)g2h(addr), old, new);
3658 ret = ret != old;
3659 break;
3660 case 2:
3661 old = *(uint32_t *)g2h(old);
3662 new = *(uint32_t *)g2h(new);
3663 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3664 ret = ret != old;
3665 break;
3666 case 3:
3667 {
3668 uint64_t o64, n64, r64;
3669 o64 = *(uint64_t *)g2h(old);
3670 n64 = *(uint64_t *)g2h(new);
3671 #ifdef CONFIG_ATOMIC64
3672 r64 = atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64, n64);
3673 ret = r64 != o64;
3674 #else
3675 start_exclusive();
3676 r64 = *(uint64_t *)g2h(addr);
3677 ret = 1;
3678 if (r64 == o64) {
3679 *(uint64_t *)g2h(addr) = n64;
3680 ret = 0;
3681 }
3682 end_exclusive();
3683 #endif
3684 }
3685 break;
3686 }
3687 break;
3688 }
3689
3690 env->gr[28] = ret;
3691 return 0;
3692 }
3693
3694 void cpu_loop(CPUHPPAState *env)
3695 {
3696 CPUState *cs = CPU(hppa_env_get_cpu(env));
3697 target_siginfo_t info;
3698 abi_ulong ret;
3699 int trapnr;
3700
3701 while (1) {
3702 cpu_exec_start(cs);
3703 trapnr = cpu_exec(cs);
3704 cpu_exec_end(cs);
3705 process_queued_cpu_work(cs);
3706
3707 switch (trapnr) {
3708 case EXCP_SYSCALL:
3709 ret = do_syscall(env, env->gr[20],
3710 env->gr[26], env->gr[25],
3711 env->gr[24], env->gr[23],
3712 env->gr[22], env->gr[21], 0, 0);
3713 switch (ret) {
3714 default:
3715 env->gr[28] = ret;
3716 /* We arrived here by faking the gateway page. Return. */
3717 env->iaoq_f = env->gr[31];
3718 env->iaoq_b = env->gr[31] + 4;
3719 break;
3720 case -TARGET_ERESTARTSYS:
3721 case -TARGET_QEMU_ESIGRETURN:
3722 break;
3723 }
3724 break;
3725 case EXCP_SYSCALL_LWS:
3726 env->gr[21] = hppa_lws(env);
3727 /* We arrived here by faking the gateway page. Return. */
3728 env->iaoq_f = env->gr[31];
3729 env->iaoq_b = env->gr[31] + 4;
3730 break;
3731 case EXCP_SIGSEGV:
3732 info.si_signo = TARGET_SIGSEGV;
3733 info.si_errno = 0;
3734 info.si_code = TARGET_SEGV_ACCERR;
3735 info._sifields._sigfault._addr = env->ior;
3736 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3737 break;
3738 case EXCP_SIGILL:
3739 info.si_signo = TARGET_SIGILL;
3740 info.si_errno = 0;
3741 info.si_code = TARGET_ILL_ILLOPN;
3742 info._sifields._sigfault._addr = env->iaoq_f;
3743 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3744 break;
3745 case EXCP_SIGFPE:
3746 info.si_signo = TARGET_SIGFPE;
3747 info.si_errno = 0;
3748 info.si_code = 0;
3749 info._sifields._sigfault._addr = env->iaoq_f;
3750 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3751 break;
3752 case EXCP_DEBUG:
3753 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
3754 if (trapnr) {
3755 info.si_signo = trapnr;
3756 info.si_errno = 0;
3757 info.si_code = TARGET_TRAP_BRKPT;
3758 queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
3759 }
3760 break;
3761 case EXCP_INTERRUPT:
3762 /* just indicate that signals should be handled asap */
3763 break;
3764 default:
3765 g_assert_not_reached();
3766 }
3767 process_pending_signals(env);
3768 }
3769 }
3770
3771 #endif /* TARGET_HPPA */
3772
3773 THREAD CPUState *thread_cpu;
3774
3775 bool qemu_cpu_is_self(CPUState *cpu)
3776 {
3777 return thread_cpu == cpu;
3778 }
3779
3780 void qemu_cpu_kick(CPUState *cpu)
3781 {
3782 cpu_exit(cpu);
3783 }
3784
3785 void task_settid(TaskState *ts)
3786 {
3787 if (ts->ts_tid == 0) {
3788 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3789 }
3790 }
3791
3792 void stop_all_tasks(void)
3793 {
3794 /*
3795 * We trust that when using NPTL, start_exclusive()
3796 * handles thread stopping correctly.
3797 */
3798 start_exclusive();
3799 }
3800
3801 /* Assumes contents are already zeroed. */
3802 void init_task_state(TaskState *ts)
3803 {
3804 ts->used = 1;
3805 }
3806
3807 CPUArchState *cpu_copy(CPUArchState *env)
3808 {
3809 CPUState *cpu = ENV_GET_CPU(env);
3810 CPUState *new_cpu = cpu_init(cpu_model);
3811 CPUArchState *new_env = new_cpu->env_ptr;
3812 CPUBreakpoint *bp;
3813 CPUWatchpoint *wp;
3814
3815 /* Reset non arch specific state */
3816 cpu_reset(new_cpu);
3817
3818 memcpy(new_env, env, sizeof(CPUArchState));
3819
3820 /* Clone all break/watchpoints.
3821 Note: Once we support ptrace with hw-debug register access, make sure
3822 BP_CPU break/watchpoints are handled correctly on clone. */
3823 QTAILQ_INIT(&new_cpu->breakpoints);
3824 QTAILQ_INIT(&new_cpu->watchpoints);
3825 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3826 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3827 }
3828 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3829 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3830 }
3831
3832 return new_env;
3833 }
3834
3835 static void handle_arg_help(const char *arg)
3836 {
3837 usage(EXIT_SUCCESS);
3838 }
3839
3840 static void handle_arg_log(const char *arg)
3841 {
3842 int mask;
3843
3844 mask = qemu_str_to_log_mask(arg);
3845 if (!mask) {
3846 qemu_print_log_usage(stdout);
3847 exit(EXIT_FAILURE);
3848 }
3849 qemu_log_needs_buffers();
3850 qemu_set_log(mask);
3851 }
3852
3853 static void handle_arg_log_filename(const char *arg)
3854 {
3855 qemu_set_log_filename(arg, &error_fatal);
3856 }
3857
3858 static void handle_arg_set_env(const char *arg)
3859 {
3860 char *r, *p, *token;
3861 r = p = strdup(arg);
3862 while ((token = strsep(&p, ",")) != NULL) {
3863 if (envlist_setenv(envlist, token) != 0) {
3864 usage(EXIT_FAILURE);
3865 }
3866 }
3867 free(r);
3868 }
3869
3870 static void handle_arg_unset_env(const char *arg)
3871 {
3872 char *r, *p, *token;
3873 r = p = strdup(arg);
3874 while ((token = strsep(&p, ",")) != NULL) {
3875 if (envlist_unsetenv(envlist, token) != 0) {
3876 usage(EXIT_FAILURE);
3877 }
3878 }
3879 free(r);
3880 }
3881
3882 static void handle_arg_argv0(const char *arg)
3883 {
3884 argv0 = strdup(arg);
3885 }
3886
3887 static void handle_arg_stack_size(const char *arg)
3888 {
3889 char *p;
3890 guest_stack_size = strtoul(arg, &p, 0);
3891 if (guest_stack_size == 0) {
3892 usage(EXIT_FAILURE);
3893 }
3894
3895 if (*p == 'M') {
3896 guest_stack_size *= 1024 * 1024;
3897 } else if (*p == 'k' || *p == 'K') {
3898 guest_stack_size *= 1024;
3899 }
3900 }
3901
3902 static void handle_arg_ld_prefix(const char *arg)
3903 {
3904 interp_prefix = strdup(arg);
3905 }
3906
3907 static void handle_arg_pagesize(const char *arg)
3908 {
3909 qemu_host_page_size = atoi(arg);
3910 if (qemu_host_page_size == 0 ||
3911 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3912 fprintf(stderr, "page size must be a power of two\n");
3913 exit(EXIT_FAILURE);
3914 }
3915 }
3916
3917 static void handle_arg_randseed(const char *arg)
3918 {
3919 unsigned long long seed;
3920
3921 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3922 fprintf(stderr, "Invalid seed number: %s\n", arg);
3923 exit(EXIT_FAILURE);
3924 }
3925 srand(seed);
3926 }
3927
3928 static void handle_arg_gdb(const char *arg)
3929 {
3930 gdbstub_port = atoi(arg);
3931 }
3932
3933 static void handle_arg_uname(const char *arg)
3934 {
3935 qemu_uname_release = strdup(arg);
3936 }
3937
3938 static void handle_arg_cpu(const char *arg)
3939 {
3940 cpu_model = strdup(arg);
3941 if (cpu_model == NULL || is_help_option(cpu_model)) {
3942 /* XXX: implement xxx_cpu_list for targets that still miss it */
3943 #if defined(cpu_list)
3944 cpu_list(stdout, &fprintf);
3945 #endif
3946 exit(EXIT_FAILURE);
3947 }
3948 }
3949
3950 static void handle_arg_guest_base(const char *arg)
3951 {
3952 guest_base = strtol(arg, NULL, 0);
3953 have_guest_base = 1;
3954 }
3955
3956 static void handle_arg_reserved_va(const char *arg)
3957 {
3958 char *p;
3959 int shift = 0;
3960 reserved_va = strtoul(arg, &p, 0);
3961 switch (*p) {
3962 case 'k':
3963 case 'K':
3964 shift = 10;
3965 break;
3966 case 'M':
3967 shift = 20;
3968 break;
3969 case 'G':
3970 shift = 30;
3971 break;
3972 }
3973 if (shift) {
3974 unsigned long unshifted = reserved_va;
3975 p++;
3976 reserved_va <<= shift;
3977 if (((reserved_va >> shift) != unshifted)
3978 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3979 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3980 #endif
3981 ) {
3982 fprintf(stderr, "Reserved virtual address too big\n");
3983 exit(EXIT_FAILURE);
3984 }
3985 }
3986 if (*p) {
3987 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3988 exit(EXIT_FAILURE);
3989 }
3990 }
3991
3992 static void handle_arg_singlestep(const char *arg)
3993 {
3994 singlestep = 1;
3995 }
3996
3997 static void handle_arg_strace(const char *arg)
3998 {
3999 do_strace = 1;
4000 }
4001
4002 static void handle_arg_version(const char *arg)
4003 {
4004 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
4005 "\n" QEMU_COPYRIGHT "\n");
4006 exit(EXIT_SUCCESS);
4007 }
4008
4009 static char *trace_file;
4010 static void handle_arg_trace(const char *arg)
4011 {
4012 g_free(trace_file);
4013 trace_file = trace_opt_parse(arg);
4014 }
4015
4016 struct qemu_argument {
4017 const char *argv;
4018 const char *env;
4019 bool has_arg;
4020 void (*handle_opt)(const char *arg);
4021 const char *example;
4022 const char *help;
4023 };
4024
4025 static const struct qemu_argument arg_table[] = {
4026 {"h", "", false, handle_arg_help,
4027 "", "print this help"},
4028 {"help", "", false, handle_arg_help,
4029 "", ""},
4030 {"g", "QEMU_GDB", true, handle_arg_gdb,
4031 "port", "wait gdb connection to 'port'"},
4032 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4033 "path", "set the elf interpreter prefix to 'path'"},
4034 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4035 "size", "set the stack size to 'size' bytes"},
4036 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4037 "model", "select CPU (-cpu help for list)"},
4038 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4039 "var=value", "sets targets environment variable (see below)"},
4040 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4041 "var", "unsets targets environment variable (see below)"},
4042 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4043 "argv0", "forces target process argv[0] to be 'argv0'"},
4044 {"r", "QEMU_UNAME", true, handle_arg_uname,
4045 "uname", "set qemu uname release string to 'uname'"},
4046 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4047 "address", "set guest_base address to 'address'"},
4048 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4049 "size", "reserve 'size' bytes for guest virtual address space"},
4050 {"d", "QEMU_LOG", true, handle_arg_log,
4051 "item[,...]", "enable logging of specified items "
4052 "(use '-d help' for a list of items)"},
4053 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4054 "logfile", "write logs to 'logfile' (default stderr)"},
4055 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4056 "pagesize", "set the host page size to 'pagesize'"},
4057 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4058 "", "run in singlestep mode"},
4059 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4060 "", "log system calls"},
4061 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4062 "", "Seed for pseudo-random number generator"},
4063 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4064 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4065 {"version", "QEMU_VERSION", false, handle_arg_version,
4066 "", "display version information and exit"},
4067 {NULL, NULL, false, NULL, NULL, NULL}
4068 };
4069
4070 static void usage(int exitcode)
4071 {
4072 const struct qemu_argument *arginfo;
4073 int maxarglen;
4074 int maxenvlen;
4075
4076 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4077 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4078 "\n"
4079 "Options and associated environment variables:\n"
4080 "\n");
4081
4082 /* Calculate column widths. We must always have at least enough space
4083 * for the column header.
4084 */
4085 maxarglen = strlen("Argument");
4086 maxenvlen = strlen("Env-variable");
4087
4088 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4089 int arglen = strlen(arginfo->argv);
4090 if (arginfo->has_arg) {
4091 arglen += strlen(arginfo->example) + 1;
4092 }
4093 if (strlen(arginfo->env) > maxenvlen) {
4094 maxenvlen = strlen(arginfo->env);
4095 }
4096 if (arglen > maxarglen) {
4097 maxarglen = arglen;
4098 }
4099 }
4100
4101 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4102 maxenvlen, "Env-variable");
4103
4104 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4105 if (arginfo->has_arg) {
4106 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4107 (int)(maxarglen - strlen(arginfo->argv) - 1),
4108 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4109 } else {
4110 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4111 maxenvlen, arginfo->env,
4112 arginfo->help);
4113 }
4114 }
4115
4116 printf("\n"
4117 "Defaults:\n"
4118 "QEMU_LD_PREFIX = %s\n"
4119 "QEMU_STACK_SIZE = %ld byte\n",
4120 interp_prefix,
4121 guest_stack_size);
4122
4123 printf("\n"
4124 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4125 "QEMU_UNSET_ENV environment variables to set and unset\n"
4126 "environment variables for the target process.\n"
4127 "It is possible to provide several variables by separating them\n"
4128 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4129 "provide the -E and -U options multiple times.\n"
4130 "The following lines are equivalent:\n"
4131 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4132 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4133 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4134 "Note that if you provide several changes to a single variable\n"
4135 "the last change will stay in effect.\n");
4136
4137 exit(exitcode);
4138 }
4139
4140 static int parse_args(int argc, char **argv)
4141 {
4142 const char *r;
4143 int optind;
4144 const struct qemu_argument *arginfo;
4145
4146 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4147 if (arginfo->env == NULL) {
4148 continue;
4149 }
4150
4151 r = getenv(arginfo->env);
4152 if (r != NULL) {
4153 arginfo->handle_opt(r);
4154 }
4155 }
4156
4157 optind = 1;
4158 for (;;) {
4159 if (optind >= argc) {
4160 break;
4161 }
4162 r = argv[optind];
4163 if (r[0] != '-') {
4164 break;
4165 }
4166 optind++;
4167 r++;
4168 if (!strcmp(r, "-")) {
4169 break;
4170 }
4171 /* Treat --foo the same as -foo. */
4172 if (r[0] == '-') {
4173 r++;
4174 }
4175
4176 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4177 if (!strcmp(r, arginfo->argv)) {
4178 if (arginfo->has_arg) {
4179 if (optind >= argc) {
4180 (void) fprintf(stderr,
4181 "qemu: missing argument for option '%s'\n", r);
4182 exit(EXIT_FAILURE);
4183 }
4184 arginfo->handle_opt(argv[optind]);
4185 optind++;
4186 } else {
4187 arginfo->handle_opt(NULL);
4188 }
4189 break;
4190 }
4191 }
4192
4193 /* no option matched the current argv */
4194 if (arginfo->handle_opt == NULL) {
4195 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4196 exit(EXIT_FAILURE);
4197 }
4198 }
4199
4200 if (optind >= argc) {
4201 (void) fprintf(stderr, "qemu: no user program specified\n");
4202 exit(EXIT_FAILURE);
4203 }
4204
4205 filename = argv[optind];
4206 exec_path = argv[optind];
4207
4208 return optind;
4209 }
4210
4211 int main(int argc, char **argv, char **envp)
4212 {
4213 struct target_pt_regs regs1, *regs = &regs1;
4214 struct image_info info1, *info = &info1;
4215 struct linux_binprm bprm;
4216 TaskState *ts;
4217 CPUArchState *env;
4218 CPUState *cpu;
4219 int optind;
4220 char **target_environ, **wrk;
4221 char **target_argv;
4222 int target_argc;
4223 int i;
4224 int ret;
4225 int execfd;
4226
4227 module_call_init(MODULE_INIT_TRACE);
4228 qemu_init_cpu_list();
4229 module_call_init(MODULE_INIT_QOM);
4230
4231 if ((envlist = envlist_create()) == NULL) {
4232 (void) fprintf(stderr, "Unable to allocate envlist\n");
4233 exit(EXIT_FAILURE);
4234 }
4235
4236 /* add current environment into the list */
4237 for (wrk = environ; *wrk != NULL; wrk++) {
4238 (void) envlist_setenv(envlist, *wrk);
4239 }
4240
4241 /* Read the stack limit from the kernel. If it's "unlimited",
4242 then we can do little else besides use the default. */
4243 {
4244 struct rlimit lim;
4245 if (getrlimit(RLIMIT_STACK, &lim) == 0
4246 && lim.rlim_cur != RLIM_INFINITY
4247 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4248 guest_stack_size = lim.rlim_cur;
4249 }
4250 }
4251
4252 cpu_model = NULL;
4253
4254 srand(time(NULL));
4255
4256 qemu_add_opts(&qemu_trace_opts);
4257
4258 optind = parse_args(argc, argv);
4259
4260 if (!trace_init_backends()) {
4261 exit(1);
4262 }
4263 trace_init_file(trace_file);
4264
4265 /* Zero out regs */
4266 memset(regs, 0, sizeof(struct target_pt_regs));
4267
4268 /* Zero out image_info */
4269 memset(info, 0, sizeof(struct image_info));
4270
4271 memset(&bprm, 0, sizeof (bprm));
4272
4273 /* Scan interp_prefix dir for replacement files. */
4274 init_paths(interp_prefix);
4275
4276 init_qemu_uname_release();
4277
4278 if (cpu_model == NULL) {
4279 #if defined(TARGET_I386)
4280 #ifdef TARGET_X86_64
4281 cpu_model = "qemu64";
4282 #else
4283 cpu_model = "qemu32";
4284 #endif
4285 #elif defined(TARGET_ARM)
4286 cpu_model = "any";
4287 #elif defined(TARGET_UNICORE32)
4288 cpu_model = "any";
4289 #elif defined(TARGET_M68K)
4290 cpu_model = "any";
4291 #elif defined(TARGET_SPARC)
4292 #ifdef TARGET_SPARC64
4293 cpu_model = "TI UltraSparc II";
4294 #else
4295 cpu_model = "Fujitsu MB86904";
4296 #endif
4297 #elif defined(TARGET_MIPS)
4298 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4299 cpu_model = "5KEf";
4300 #else
4301 cpu_model = "24Kf";
4302 #endif
4303 #elif defined TARGET_OPENRISC
4304 cpu_model = "or1200";
4305 #elif defined(TARGET_PPC)
4306 # ifdef TARGET_PPC64
4307 cpu_model = "POWER8";
4308 # else
4309 cpu_model = "750";
4310 # endif
4311 #elif defined TARGET_SH4
4312 cpu_model = TYPE_SH7785_CPU;
4313 #elif defined TARGET_S390X
4314 cpu_model = "qemu";
4315 #else
4316 cpu_model = "any";
4317 #endif
4318 }
4319 tcg_exec_init(0);
4320 /* NOTE: we need to init the CPU at this stage to get
4321 qemu_host_page_size */
4322 cpu = cpu_init(cpu_model);
4323 if (!cpu) {
4324 fprintf(stderr, "Unable to find CPU definition\n");
4325 exit(EXIT_FAILURE);
4326 }
4327 env = cpu->env_ptr;
4328 cpu_reset(cpu);
4329
4330 thread_cpu = cpu;
4331
4332 if (getenv("QEMU_STRACE")) {
4333 do_strace = 1;
4334 }
4335
4336 if (getenv("QEMU_RAND_SEED")) {
4337 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4338 }
4339
4340 target_environ = envlist_to_environ(envlist, NULL);
4341 envlist_free(envlist);
4342
4343 /*
4344 * Now that page sizes are configured in cpu_init() we can do
4345 * proper page alignment for guest_base.
4346 */
4347 guest_base = HOST_PAGE_ALIGN(guest_base);
4348
4349 if (reserved_va || have_guest_base) {
4350 guest_base = init_guest_space(guest_base, reserved_va, 0,
4351 have_guest_base);
4352 if (guest_base == (unsigned long)-1) {
4353 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4354 "space for use as guest address space (check your virtual "
4355 "memory ulimit setting or reserve less using -R option)\n",
4356 reserved_va);
4357 exit(EXIT_FAILURE);
4358 }
4359
4360 if (reserved_va) {
4361 mmap_next_start = reserved_va;
4362 }
4363 }
4364
4365 /*
4366 * Read in mmap_min_addr kernel parameter. This value is used
4367 * When loading the ELF image to determine whether guest_base
4368 * is needed. It is also used in mmap_find_vma.
4369 */
4370 {
4371 FILE *fp;
4372
4373 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4374 unsigned long tmp;
4375 if (fscanf(fp, "%lu", &tmp) == 1) {
4376 mmap_min_addr = tmp;
4377 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4378 }
4379 fclose(fp);
4380 }
4381 }
4382
4383 /*
4384 * Prepare copy of argv vector for target.
4385 */
4386 target_argc = argc - optind;
4387 target_argv = calloc(target_argc + 1, sizeof (char *));
4388 if (target_argv == NULL) {
4389 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4390 exit(EXIT_FAILURE);
4391 }
4392
4393 /*
4394 * If argv0 is specified (using '-0' switch) we replace
4395 * argv[0] pointer with the given one.
4396 */
4397 i = 0;
4398 if (argv0 != NULL) {
4399 target_argv[i++] = strdup(argv0);
4400 }
4401 for (; i < target_argc; i++) {
4402 target_argv[i] = strdup(argv[optind + i]);
4403 }
4404 target_argv[target_argc] = NULL;
4405
4406 ts = g_new0(TaskState, 1);
4407 init_task_state(ts);
4408 /* build Task State */
4409 ts->info = info;
4410 ts->bprm = &bprm;
4411 cpu->opaque = ts;
4412 task_settid(ts);
4413
4414 execfd = qemu_getauxval(AT_EXECFD);
4415 if (execfd == 0) {
4416 execfd = open(filename, O_RDONLY);
4417 if (execfd < 0) {
4418 printf("Error while loading %s: %s\n", filename, strerror(errno));
4419 _exit(EXIT_FAILURE);
4420 }
4421 }
4422
4423 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4424 info, &bprm);
4425 if (ret != 0) {
4426 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4427 _exit(EXIT_FAILURE);
4428 }
4429
4430 for (wrk = target_environ; *wrk; wrk++) {
4431 free(*wrk);
4432 }
4433
4434 free(target_environ);
4435
4436 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4437 qemu_log("guest_base 0x%lx\n", guest_base);
4438 log_page_dump();
4439
4440 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4441 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4442 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", info->start_code);
4443 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", info->start_data);
4444 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4445 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", info->start_stack);
4446 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4447 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4448 qemu_log("argv_start 0x" TARGET_ABI_FMT_lx "\n", info->arg_start);
4449 qemu_log("env_start 0x" TARGET_ABI_FMT_lx "\n",
4450 info->arg_end + (abi_ulong)sizeof(abi_ulong));
4451 qemu_log("auxv_start 0x" TARGET_ABI_FMT_lx "\n", info->saved_auxv);
4452 }
4453
4454 target_set_brk(info->brk);
4455 syscall_init();
4456 signal_init();
4457
4458 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4459 generating the prologue until now so that the prologue can take
4460 the real value of GUEST_BASE into account. */
4461 tcg_prologue_init(&tcg_ctx);
4462
4463 #if defined(TARGET_I386)
4464 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4465 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4466 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4467 env->cr[4] |= CR4_OSFXSR_MASK;
4468 env->hflags |= HF_OSFXSR_MASK;
4469 }
4470 #ifndef TARGET_ABI32
4471 /* enable 64 bit mode if possible */
4472 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4473 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4474 exit(EXIT_FAILURE);
4475 }
4476 env->cr[4] |= CR4_PAE_MASK;
4477 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4478 env->hflags |= HF_LMA_MASK;
4479 #endif
4480
4481 /* flags setup : we activate the IRQs by default as in user mode */
4482 env->eflags |= IF_MASK;
4483
4484 /* linux register setup */
4485 #ifndef TARGET_ABI32
4486 env->regs[R_EAX] = regs->rax;
4487 env->regs[R_EBX] = regs->rbx;
4488 env->regs[R_ECX] = regs->rcx;
4489 env->regs[R_EDX] = regs->rdx;
4490 env->regs[R_ESI] = regs->rsi;
4491 env->regs[R_EDI] = regs->rdi;
4492 env->regs[R_EBP] = regs->rbp;
4493 env->regs[R_ESP] = regs->rsp;
4494 env->eip = regs->rip;
4495 #else
4496 env->regs[R_EAX] = regs->eax;
4497 env->regs[R_EBX] = regs->ebx;
4498 env->regs[R_ECX] = regs->ecx;
4499 env->regs[R_EDX] = regs->edx;
4500 env->regs[R_ESI] = regs->esi;
4501 env->regs[R_EDI] = regs->edi;
4502 env->regs[R_EBP] = regs->ebp;
4503 env->regs[R_ESP] = regs->esp;
4504 env->eip = regs->eip;
4505 #endif
4506
4507 /* linux interrupt setup */
4508 #ifndef TARGET_ABI32
4509 env->idt.limit = 511;
4510 #else
4511 env->idt.limit = 255;
4512 #endif
4513 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4514 PROT_READ|PROT_WRITE,
4515 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4516 idt_table = g2h(env->idt.base);
4517 set_idt(0, 0);
4518 set_idt(1, 0);
4519 set_idt(2, 0);
4520 set_idt(3, 3);
4521 set_idt(4, 3);
4522 set_idt(5, 0);
4523 set_idt(6, 0);
4524 set_idt(7, 0);
4525 set_idt(8, 0);
4526 set_idt(9, 0);
4527 set_idt(10, 0);
4528 set_idt(11, 0);
4529 set_idt(12, 0);
4530 set_idt(13, 0);
4531 set_idt(14, 0);
4532 set_idt(15, 0);
4533 set_idt(16, 0);
4534 set_idt(17, 0);
4535 set_idt(18, 0);
4536 set_idt(19, 0);
4537 set_idt(0x80, 3);
4538
4539 /* linux segment setup */
4540 {
4541 uint64_t *gdt_table;
4542 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4543 PROT_READ|PROT_WRITE,
4544 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4545 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4546 gdt_table = g2h(env->gdt.base);
4547 #ifdef TARGET_ABI32
4548 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4549 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4550 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4551 #else
4552 /* 64 bit code segment */
4553 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4554 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4555 DESC_L_MASK |
4556 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4557 #endif
4558 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4559 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4560 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4561 }
4562 cpu_x86_load_seg(env, R_CS, __USER_CS);
4563 cpu_x86_load_seg(env, R_SS, __USER_DS);
4564 #ifdef TARGET_ABI32
4565 cpu_x86_load_seg(env, R_DS, __USER_DS);
4566 cpu_x86_load_seg(env, R_ES, __USER_DS);
4567 cpu_x86_load_seg(env, R_FS, __USER_DS);
4568 cpu_x86_load_seg(env, R_GS, __USER_DS);
4569 /* This hack makes Wine work... */
4570 env->segs[R_FS].selector = 0;
4571 #else
4572 cpu_x86_load_seg(env, R_DS, 0);
4573 cpu_x86_load_seg(env, R_ES, 0);
4574 cpu_x86_load_seg(env, R_FS, 0);
4575 cpu_x86_load_seg(env, R_GS, 0);
4576 #endif
4577 #elif defined(TARGET_AARCH64)
4578 {
4579 int i;
4580
4581 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4582 fprintf(stderr,
4583 "The selected ARM CPU does not support 64 bit mode\n");
4584 exit(EXIT_FAILURE);
4585 }
4586
4587 for (i = 0; i < 31; i++) {
4588 env->xregs[i] = regs->regs[i];
4589 }
4590 env->pc = regs->pc;
4591 env->xregs[31] = regs->sp;
4592 }
4593 #elif defined(TARGET_ARM)
4594 {
4595 int i;
4596 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4597 CPSRWriteByInstr);
4598 for(i = 0; i < 16; i++) {
4599 env->regs[i] = regs->uregs[i];
4600 }
4601 #ifdef TARGET_WORDS_BIGENDIAN
4602 /* Enable BE8. */
4603 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4604 && (info->elf_flags & EF_ARM_BE8)) {
4605 env->uncached_cpsr |= CPSR_E;
4606 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4607 } else {
4608 env->cp15.sctlr_el[1] |= SCTLR_B;
4609 }
4610 #endif
4611 }
4612 #elif defined(TARGET_UNICORE32)
4613 {
4614 int i;
4615 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4616 for (i = 0; i < 32; i++) {
4617 env->regs[i] = regs->uregs[i];
4618 }
4619 }
4620 #elif defined(TARGET_SPARC)
4621 {
4622 int i;
4623 env->pc = regs->pc;
4624 env->npc = regs->npc;
4625 env->y = regs->y;
4626 for(i = 0; i < 8; i++)
4627 env->gregs[i] = regs->u_regs[i];
4628 for(i = 0; i < 8; i++)
4629 env->regwptr[i] = regs->u_regs[i + 8];
4630 }
4631 #elif defined(TARGET_PPC)
4632 {
4633 int i;
4634
4635 #if defined(TARGET_PPC64)
4636 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4637 #if defined(TARGET_ABI32)
4638 env->msr &= ~((target_ulong)1 << flag);
4639 #else
4640 env->msr |= (target_ulong)1 << flag;
4641 #endif
4642 #endif
4643 env->nip = regs->nip;
4644 for(i = 0; i < 32; i++) {
4645 env->gpr[i] = regs->gpr[i];
4646 }
4647 }
4648 #elif defined(TARGET_M68K)
4649 {
4650 env->pc = regs->pc;
4651 env->dregs[0] = regs->d0;
4652 env->dregs[1] = regs->d1;
4653 env->dregs[2] = regs->d2;
4654 env->dregs[3] = regs->d3;
4655 env->dregs[4] = regs->d4;
4656 env->dregs[5] = regs->d5;
4657 env->dregs[6] = regs->d6;
4658 env->dregs[7] = regs->d7;
4659 env->aregs[0] = regs->a0;
4660 env->aregs[1] = regs->a1;
4661 env->aregs[2] = regs->a2;
4662 env->aregs[3] = regs->a3;
4663 env->aregs[4] = regs->a4;
4664 env->aregs[5] = regs->a5;
4665 env->aregs[6] = regs->a6;
4666 env->aregs[7] = regs->usp;
4667 env->sr = regs->sr;
4668 ts->sim_syscalls = 1;
4669 }
4670 #elif defined(TARGET_MICROBLAZE)
4671 {
4672 env->regs[0] = regs->r0;
4673 env->regs[1] = regs->r1;
4674 env->regs[2] = regs->r2;
4675 env->regs[3] = regs->r3;
4676 env->regs[4] = regs->r4;
4677 env->regs[5] = regs->r5;
4678 env->regs[6] = regs->r6;
4679 env->regs[7] = regs->r7;
4680 env->regs[8] = regs->r8;
4681 env->regs[9] = regs->r9;
4682 env->regs[10] = regs->r10;
4683 env->regs[11] = regs->r11;
4684 env->regs[12] = regs->r12;
4685 env->regs[13] = regs->r13;
4686 env->regs[14] = regs->r14;
4687 env->regs[15] = regs->r15;
4688 env->regs[16] = regs->r16;
4689 env->regs[17] = regs->r17;
4690 env->regs[18] = regs->r18;
4691 env->regs[19] = regs->r19;
4692 env->regs[20] = regs->r20;
4693 env->regs[21] = regs->r21;
4694 env->regs[22] = regs->r22;
4695 env->regs[23] = regs->r23;
4696 env->regs[24] = regs->r24;
4697 env->regs[25] = regs->r25;
4698 env->regs[26] = regs->r26;
4699 env->regs[27] = regs->r27;
4700 env->regs[28] = regs->r28;
4701 env->regs[29] = regs->r29;
4702 env->regs[30] = regs->r30;
4703 env->regs[31] = regs->r31;
4704 env->sregs[SR_PC] = regs->pc;
4705 }
4706 #elif defined(TARGET_MIPS)
4707 {
4708 int i;
4709
4710 for(i = 0; i < 32; i++) {
4711 env->active_tc.gpr[i] = regs->regs[i];
4712 }
4713 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4714 if (regs->cp0_epc & 1) {
4715 env->hflags |= MIPS_HFLAG_M16;
4716 }
4717 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4718 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4719 if ((env->active_fpu.fcr31_rw_bitmask &
4720 (1 << FCR31_NAN2008)) == 0) {
4721 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4722 exit(1);
4723 }
4724 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4725 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4726 } else {
4727 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4728 }
4729 restore_snan_bit_mode(env);
4730 }
4731 }
4732 #elif defined(TARGET_NIOS2)
4733 {
4734 env->regs[0] = 0;
4735 env->regs[1] = regs->r1;
4736 env->regs[2] = regs->r2;
4737 env->regs[3] = regs->r3;
4738 env->regs[4] = regs->r4;
4739 env->regs[5] = regs->r5;
4740 env->regs[6] = regs->r6;
4741 env->regs[7] = regs->r7;
4742 env->regs[8] = regs->r8;
4743 env->regs[9] = regs->r9;
4744 env->regs[10] = regs->r10;
4745 env->regs[11] = regs->r11;
4746 env->regs[12] = regs->r12;
4747 env->regs[13] = regs->r13;
4748 env->regs[14] = regs->r14;
4749 env->regs[15] = regs->r15;
4750 /* TODO: unsigned long orig_r2; */
4751 env->regs[R_RA] = regs->ra;
4752 env->regs[R_FP] = regs->fp;
4753 env->regs[R_SP] = regs->sp;
4754 env->regs[R_GP] = regs->gp;
4755 env->regs[CR_ESTATUS] = regs->estatus;
4756 env->regs[R_EA] = regs->ea;
4757 /* TODO: unsigned long orig_r7; */
4758
4759 /* Emulate eret when starting thread. */
4760 env->regs[R_PC] = regs->ea;
4761 }
4762 #elif defined(TARGET_OPENRISC)
4763 {
4764 int i;
4765
4766 for (i = 0; i < 32; i++) {
4767 env->gpr[i] = regs->gpr[i];
4768 }
4769 env->pc = regs->pc;
4770 cpu_set_sr(env, regs->sr);
4771 }
4772 #elif defined(TARGET_SH4)
4773 {
4774 int i;
4775
4776 for(i = 0; i < 16; i++) {
4777 env->gregs[i] = regs->regs[i];
4778 }
4779 env->pc = regs->pc;
4780 }
4781 #elif defined(TARGET_ALPHA)
4782 {
4783 int i;
4784
4785 for(i = 0; i < 28; i++) {
4786 env->ir[i] = ((abi_ulong *)regs)[i];
4787 }
4788 env->ir[IR_SP] = regs->usp;
4789 env->pc = regs->pc;
4790 }
4791 #elif defined(TARGET_CRIS)
4792 {
4793 env->regs[0] = regs->r0;
4794 env->regs[1] = regs->r1;
4795 env->regs[2] = regs->r2;
4796 env->regs[3] = regs->r3;
4797 env->regs[4] = regs->r4;
4798 env->regs[5] = regs->r5;
4799 env->regs[6] = regs->r6;
4800 env->regs[7] = regs->r7;
4801 env->regs[8] = regs->r8;
4802 env->regs[9] = regs->r9;
4803 env->regs[10] = regs->r10;
4804 env->regs[11] = regs->r11;
4805 env->regs[12] = regs->r12;
4806 env->regs[13] = regs->r13;
4807 env->regs[14] = info->start_stack;
4808 env->regs[15] = regs->acr;
4809 env->pc = regs->erp;
4810 }
4811 #elif defined(TARGET_S390X)
4812 {
4813 int i;
4814 for (i = 0; i < 16; i++) {
4815 env->regs[i] = regs->gprs[i];
4816 }
4817 env->psw.mask = regs->psw.mask;
4818 env->psw.addr = regs->psw.addr;
4819 }
4820 #elif defined(TARGET_TILEGX)
4821 {
4822 int i;
4823 for (i = 0; i < TILEGX_R_COUNT; i++) {
4824 env->regs[i] = regs->regs[i];
4825 }
4826 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4827 env->spregs[i] = 0;
4828 }
4829 env->pc = regs->pc;
4830 }
4831 #elif defined(TARGET_HPPA)
4832 {
4833 int i;
4834 for (i = 1; i < 32; i++) {
4835 env->gr[i] = regs->gr[i];
4836 }
4837 env->iaoq_f = regs->iaoq[0];
4838 env->iaoq_b = regs->iaoq[1];
4839 }
4840 #else
4841 #error unsupported target CPU
4842 #endif
4843
4844 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4845 ts->stack_base = info->start_stack;
4846 ts->heap_base = info->brk;
4847 /* This will be filled in on the first SYS_HEAPINFO call. */
4848 ts->heap_limit = 0;
4849 #endif
4850
4851 if (gdbstub_port) {
4852 if (gdbserver_start(gdbstub_port) < 0) {
4853 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4854 gdbstub_port);
4855 exit(EXIT_FAILURE);
4856 }
4857 gdb_handlesig(cpu, 0);
4858 }
4859 cpu_loop(env);
4860 /* never exits */
4861 return 0;
4862 }
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