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target-i386: Replace cpuid_*features fields with a feature word array
[mirror_qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "qemu/cache-utils.h"
32 #include "cpu.h"
33 #include "tcg.h"
34 #include "qemu/timer.h"
35 #include "qemu/envlist.h"
36 #include "elf.h"
37
38 char *exec_path;
39
40 int singlestep;
41 const char *filename;
42 const char *argv0;
43 int gdbstub_port;
44 envlist_t *envlist;
45 const char *cpu_model;
46 unsigned long mmap_min_addr;
47 #if defined(CONFIG_USE_GUEST_BASE)
48 unsigned long guest_base;
49 int have_guest_base;
50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51 /*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
58 # ifdef TARGET_MIPS
59 /* MIPS only supports 31 bits of virtual address space for user space */
60 unsigned long reserved_va = 0x77000000;
61 # else
62 unsigned long reserved_va = 0xf7000000;
63 # endif
64 #else
65 unsigned long reserved_va;
66 #endif
67 #endif
68
69 static void usage(void);
70
71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
73
74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
77 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
78
79 void gemu_log(const char *fmt, ...)
80 {
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86 }
87
88 #if defined(TARGET_I386)
89 int cpu_get_pic_interrupt(CPUX86State *env)
90 {
91 return -1;
92 }
93 #endif
94
95 #if defined(CONFIG_USE_NPTL)
96 /***********************************************************/
97 /* Helper routines for implementing atomic operations. */
98
99 /* To implement exclusive operations we force all cpus to syncronise.
100 We don't require a full sync, only that no cpus are executing guest code.
101 The alternative is to map target atomic ops onto host equivalents,
102 which requires quite a lot of per host/target work. */
103 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
104 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
105 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
106 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
107 static int pending_cpus;
108
109 /* Make sure everything is in a consistent state for calling fork(). */
110 void fork_start(void)
111 {
112 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
113 pthread_mutex_lock(&exclusive_lock);
114 mmap_fork_start();
115 }
116
117 void fork_end(int child)
118 {
119 mmap_fork_end(child);
120 if (child) {
121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
123 first_cpu = thread_env;
124 thread_env->next_cpu = NULL;
125 pending_cpus = 0;
126 pthread_mutex_init(&exclusive_lock, NULL);
127 pthread_mutex_init(&cpu_list_mutex, NULL);
128 pthread_cond_init(&exclusive_cond, NULL);
129 pthread_cond_init(&exclusive_resume, NULL);
130 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
131 gdbserver_fork(thread_env);
132 } else {
133 pthread_mutex_unlock(&exclusive_lock);
134 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
135 }
136 }
137
138 /* Wait for pending exclusive operations to complete. The exclusive lock
139 must be held. */
140 static inline void exclusive_idle(void)
141 {
142 while (pending_cpus) {
143 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
144 }
145 }
146
147 /* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149 static inline void start_exclusive(void)
150 {
151 CPUArchState *other;
152 CPUState *other_cpu;
153
154 pthread_mutex_lock(&exclusive_lock);
155 exclusive_idle();
156
157 pending_cpus = 1;
158 /* Make all other cpus stop executing. */
159 for (other = first_cpu; other; other = other->next_cpu) {
160 other_cpu = ENV_GET_CPU(other);
161 if (other_cpu->running) {
162 pending_cpus++;
163 cpu_exit(other);
164 }
165 }
166 if (pending_cpus > 1) {
167 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
168 }
169 }
170
171 /* Finish an exclusive operation. */
172 static inline void end_exclusive(void)
173 {
174 pending_cpus = 0;
175 pthread_cond_broadcast(&exclusive_resume);
176 pthread_mutex_unlock(&exclusive_lock);
177 }
178
179 /* Wait for exclusive ops to finish, and begin cpu execution. */
180 static inline void cpu_exec_start(CPUState *cpu)
181 {
182 pthread_mutex_lock(&exclusive_lock);
183 exclusive_idle();
184 cpu->running = true;
185 pthread_mutex_unlock(&exclusive_lock);
186 }
187
188 /* Mark cpu as not executing, and release pending exclusive ops. */
189 static inline void cpu_exec_end(CPUState *cpu)
190 {
191 pthread_mutex_lock(&exclusive_lock);
192 cpu->running = false;
193 if (pending_cpus > 1) {
194 pending_cpus--;
195 if (pending_cpus == 1) {
196 pthread_cond_signal(&exclusive_cond);
197 }
198 }
199 exclusive_idle();
200 pthread_mutex_unlock(&exclusive_lock);
201 }
202
203 void cpu_list_lock(void)
204 {
205 pthread_mutex_lock(&cpu_list_mutex);
206 }
207
208 void cpu_list_unlock(void)
209 {
210 pthread_mutex_unlock(&cpu_list_mutex);
211 }
212 #else /* if !CONFIG_USE_NPTL */
213 /* These are no-ops because we are not threadsafe. */
214 static inline void cpu_exec_start(CPUState *cpu)
215 {
216 }
217
218 static inline void cpu_exec_end(CPUState *cpu)
219 {
220 }
221
222 static inline void start_exclusive(void)
223 {
224 }
225
226 static inline void end_exclusive(void)
227 {
228 }
229
230 void fork_start(void)
231 {
232 }
233
234 void fork_end(int child)
235 {
236 if (child) {
237 gdbserver_fork(thread_env);
238 }
239 }
240
241 void cpu_list_lock(void)
242 {
243 }
244
245 void cpu_list_unlock(void)
246 {
247 }
248 #endif
249
250
251 #ifdef TARGET_I386
252 /***********************************************************/
253 /* CPUX86 core interface */
254
255 void cpu_smm_update(CPUX86State *env)
256 {
257 }
258
259 uint64_t cpu_get_tsc(CPUX86State *env)
260 {
261 return cpu_get_real_ticks();
262 }
263
264 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
265 int flags)
266 {
267 unsigned int e1, e2;
268 uint32_t *p;
269 e1 = (addr << 16) | (limit & 0xffff);
270 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
271 e2 |= flags;
272 p = ptr;
273 p[0] = tswap32(e1);
274 p[1] = tswap32(e2);
275 }
276
277 static uint64_t *idt_table;
278 #ifdef TARGET_X86_64
279 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
280 uint64_t addr, unsigned int sel)
281 {
282 uint32_t *p, e1, e2;
283 e1 = (addr & 0xffff) | (sel << 16);
284 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
285 p = ptr;
286 p[0] = tswap32(e1);
287 p[1] = tswap32(e2);
288 p[2] = tswap32(addr >> 32);
289 p[3] = 0;
290 }
291 /* only dpl matters as we do only user space emulation */
292 static void set_idt(int n, unsigned int dpl)
293 {
294 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
295 }
296 #else
297 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
298 uint32_t addr, unsigned int sel)
299 {
300 uint32_t *p, e1, e2;
301 e1 = (addr & 0xffff) | (sel << 16);
302 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
303 p = ptr;
304 p[0] = tswap32(e1);
305 p[1] = tswap32(e2);
306 }
307
308 /* only dpl matters as we do only user space emulation */
309 static void set_idt(int n, unsigned int dpl)
310 {
311 set_gate(idt_table + n, 0, dpl, 0, 0);
312 }
313 #endif
314
315 void cpu_loop(CPUX86State *env)
316 {
317 int trapnr;
318 abi_ulong pc;
319 target_siginfo_t info;
320
321 for(;;) {
322 trapnr = cpu_x86_exec(env);
323 switch(trapnr) {
324 case 0x80:
325 /* linux syscall from int $0x80 */
326 env->regs[R_EAX] = do_syscall(env,
327 env->regs[R_EAX],
328 env->regs[R_EBX],
329 env->regs[R_ECX],
330 env->regs[R_EDX],
331 env->regs[R_ESI],
332 env->regs[R_EDI],
333 env->regs[R_EBP],
334 0, 0);
335 break;
336 #ifndef TARGET_ABI32
337 case EXCP_SYSCALL:
338 /* linux syscall from syscall instruction */
339 env->regs[R_EAX] = do_syscall(env,
340 env->regs[R_EAX],
341 env->regs[R_EDI],
342 env->regs[R_ESI],
343 env->regs[R_EDX],
344 env->regs[10],
345 env->regs[8],
346 env->regs[9],
347 0, 0);
348 env->eip = env->exception_next_eip;
349 break;
350 #endif
351 case EXCP0B_NOSEG:
352 case EXCP0C_STACK:
353 info.si_signo = SIGBUS;
354 info.si_errno = 0;
355 info.si_code = TARGET_SI_KERNEL;
356 info._sifields._sigfault._addr = 0;
357 queue_signal(env, info.si_signo, &info);
358 break;
359 case EXCP0D_GPF:
360 /* XXX: potential problem if ABI32 */
361 #ifndef TARGET_X86_64
362 if (env->eflags & VM_MASK) {
363 handle_vm86_fault(env);
364 } else
365 #endif
366 {
367 info.si_signo = SIGSEGV;
368 info.si_errno = 0;
369 info.si_code = TARGET_SI_KERNEL;
370 info._sifields._sigfault._addr = 0;
371 queue_signal(env, info.si_signo, &info);
372 }
373 break;
374 case EXCP0E_PAGE:
375 info.si_signo = SIGSEGV;
376 info.si_errno = 0;
377 if (!(env->error_code & 1))
378 info.si_code = TARGET_SEGV_MAPERR;
379 else
380 info.si_code = TARGET_SEGV_ACCERR;
381 info._sifields._sigfault._addr = env->cr[2];
382 queue_signal(env, info.si_signo, &info);
383 break;
384 case EXCP00_DIVZ:
385 #ifndef TARGET_X86_64
386 if (env->eflags & VM_MASK) {
387 handle_vm86_trap(env, trapnr);
388 } else
389 #endif
390 {
391 /* division by zero */
392 info.si_signo = SIGFPE;
393 info.si_errno = 0;
394 info.si_code = TARGET_FPE_INTDIV;
395 info._sifields._sigfault._addr = env->eip;
396 queue_signal(env, info.si_signo, &info);
397 }
398 break;
399 case EXCP01_DB:
400 case EXCP03_INT3:
401 #ifndef TARGET_X86_64
402 if (env->eflags & VM_MASK) {
403 handle_vm86_trap(env, trapnr);
404 } else
405 #endif
406 {
407 info.si_signo = SIGTRAP;
408 info.si_errno = 0;
409 if (trapnr == EXCP01_DB) {
410 info.si_code = TARGET_TRAP_BRKPT;
411 info._sifields._sigfault._addr = env->eip;
412 } else {
413 info.si_code = TARGET_SI_KERNEL;
414 info._sifields._sigfault._addr = 0;
415 }
416 queue_signal(env, info.si_signo, &info);
417 }
418 break;
419 case EXCP04_INTO:
420 case EXCP05_BOUND:
421 #ifndef TARGET_X86_64
422 if (env->eflags & VM_MASK) {
423 handle_vm86_trap(env, trapnr);
424 } else
425 #endif
426 {
427 info.si_signo = SIGSEGV;
428 info.si_errno = 0;
429 info.si_code = TARGET_SI_KERNEL;
430 info._sifields._sigfault._addr = 0;
431 queue_signal(env, info.si_signo, &info);
432 }
433 break;
434 case EXCP06_ILLOP:
435 info.si_signo = SIGILL;
436 info.si_errno = 0;
437 info.si_code = TARGET_ILL_ILLOPN;
438 info._sifields._sigfault._addr = env->eip;
439 queue_signal(env, info.si_signo, &info);
440 break;
441 case EXCP_INTERRUPT:
442 /* just indicate that signals should be handled asap */
443 break;
444 case EXCP_DEBUG:
445 {
446 int sig;
447
448 sig = gdb_handlesig (env, TARGET_SIGTRAP);
449 if (sig)
450 {
451 info.si_signo = sig;
452 info.si_errno = 0;
453 info.si_code = TARGET_TRAP_BRKPT;
454 queue_signal(env, info.si_signo, &info);
455 }
456 }
457 break;
458 default:
459 pc = env->segs[R_CS].base + env->eip;
460 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
461 (long)pc, trapnr);
462 abort();
463 }
464 process_pending_signals(env);
465 }
466 }
467 #endif
468
469 #ifdef TARGET_ARM
470
471 #define get_user_code_u32(x, gaddr, doswap) \
472 ({ abi_long __r = get_user_u32((x), (gaddr)); \
473 if (!__r && (doswap)) { \
474 (x) = bswap32(x); \
475 } \
476 __r; \
477 })
478
479 #define get_user_code_u16(x, gaddr, doswap) \
480 ({ abi_long __r = get_user_u16((x), (gaddr)); \
481 if (!__r && (doswap)) { \
482 (x) = bswap16(x); \
483 } \
484 __r; \
485 })
486
487 /*
488 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
489 * Input:
490 * r0 = pointer to oldval
491 * r1 = pointer to newval
492 * r2 = pointer to target value
493 *
494 * Output:
495 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
496 * C set if *ptr was changed, clear if no exchange happened
497 *
498 * Note segv's in kernel helpers are a bit tricky, we can set the
499 * data address sensibly but the PC address is just the entry point.
500 */
501 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
502 {
503 uint64_t oldval, newval, val;
504 uint32_t addr, cpsr;
505 target_siginfo_t info;
506
507 /* Based on the 32 bit code in do_kernel_trap */
508
509 /* XXX: This only works between threads, not between processes.
510 It's probably possible to implement this with native host
511 operations. However things like ldrex/strex are much harder so
512 there's not much point trying. */
513 start_exclusive();
514 cpsr = cpsr_read(env);
515 addr = env->regs[2];
516
517 if (get_user_u64(oldval, env->regs[0])) {
518 env->cp15.c6_data = env->regs[0];
519 goto segv;
520 };
521
522 if (get_user_u64(newval, env->regs[1])) {
523 env->cp15.c6_data = env->regs[1];
524 goto segv;
525 };
526
527 if (get_user_u64(val, addr)) {
528 env->cp15.c6_data = addr;
529 goto segv;
530 }
531
532 if (val == oldval) {
533 val = newval;
534
535 if (put_user_u64(val, addr)) {
536 env->cp15.c6_data = addr;
537 goto segv;
538 };
539
540 env->regs[0] = 0;
541 cpsr |= CPSR_C;
542 } else {
543 env->regs[0] = -1;
544 cpsr &= ~CPSR_C;
545 }
546 cpsr_write(env, cpsr, CPSR_C);
547 end_exclusive();
548 return;
549
550 segv:
551 end_exclusive();
552 /* We get the PC of the entry address - which is as good as anything,
553 on a real kernel what you get depends on which mode it uses. */
554 info.si_signo = SIGSEGV;
555 info.si_errno = 0;
556 /* XXX: check env->error_code */
557 info.si_code = TARGET_SEGV_MAPERR;
558 info._sifields._sigfault._addr = env->cp15.c6_data;
559 queue_signal(env, info.si_signo, &info);
560
561 end_exclusive();
562 }
563
564 /* Handle a jump to the kernel code page. */
565 static int
566 do_kernel_trap(CPUARMState *env)
567 {
568 uint32_t addr;
569 uint32_t cpsr;
570 uint32_t val;
571
572 switch (env->regs[15]) {
573 case 0xffff0fa0: /* __kernel_memory_barrier */
574 /* ??? No-op. Will need to do better for SMP. */
575 break;
576 case 0xffff0fc0: /* __kernel_cmpxchg */
577 /* XXX: This only works between threads, not between processes.
578 It's probably possible to implement this with native host
579 operations. However things like ldrex/strex are much harder so
580 there's not much point trying. */
581 start_exclusive();
582 cpsr = cpsr_read(env);
583 addr = env->regs[2];
584 /* FIXME: This should SEGV if the access fails. */
585 if (get_user_u32(val, addr))
586 val = ~env->regs[0];
587 if (val == env->regs[0]) {
588 val = env->regs[1];
589 /* FIXME: Check for segfaults. */
590 put_user_u32(val, addr);
591 env->regs[0] = 0;
592 cpsr |= CPSR_C;
593 } else {
594 env->regs[0] = -1;
595 cpsr &= ~CPSR_C;
596 }
597 cpsr_write(env, cpsr, CPSR_C);
598 end_exclusive();
599 break;
600 case 0xffff0fe0: /* __kernel_get_tls */
601 env->regs[0] = env->cp15.c13_tls2;
602 break;
603 case 0xffff0f60: /* __kernel_cmpxchg64 */
604 arm_kernel_cmpxchg64_helper(env);
605 break;
606
607 default:
608 return 1;
609 }
610 /* Jump back to the caller. */
611 addr = env->regs[14];
612 if (addr & 1) {
613 env->thumb = 1;
614 addr &= ~1;
615 }
616 env->regs[15] = addr;
617
618 return 0;
619 }
620
621 static int do_strex(CPUARMState *env)
622 {
623 uint32_t val;
624 int size;
625 int rc = 1;
626 int segv = 0;
627 uint32_t addr;
628 start_exclusive();
629 addr = env->exclusive_addr;
630 if (addr != env->exclusive_test) {
631 goto fail;
632 }
633 size = env->exclusive_info & 0xf;
634 switch (size) {
635 case 0:
636 segv = get_user_u8(val, addr);
637 break;
638 case 1:
639 segv = get_user_u16(val, addr);
640 break;
641 case 2:
642 case 3:
643 segv = get_user_u32(val, addr);
644 break;
645 default:
646 abort();
647 }
648 if (segv) {
649 env->cp15.c6_data = addr;
650 goto done;
651 }
652 if (val != env->exclusive_val) {
653 goto fail;
654 }
655 if (size == 3) {
656 segv = get_user_u32(val, addr + 4);
657 if (segv) {
658 env->cp15.c6_data = addr + 4;
659 goto done;
660 }
661 if (val != env->exclusive_high) {
662 goto fail;
663 }
664 }
665 val = env->regs[(env->exclusive_info >> 8) & 0xf];
666 switch (size) {
667 case 0:
668 segv = put_user_u8(val, addr);
669 break;
670 case 1:
671 segv = put_user_u16(val, addr);
672 break;
673 case 2:
674 case 3:
675 segv = put_user_u32(val, addr);
676 break;
677 }
678 if (segv) {
679 env->cp15.c6_data = addr;
680 goto done;
681 }
682 if (size == 3) {
683 val = env->regs[(env->exclusive_info >> 12) & 0xf];
684 segv = put_user_u32(val, addr + 4);
685 if (segv) {
686 env->cp15.c6_data = addr + 4;
687 goto done;
688 }
689 }
690 rc = 0;
691 fail:
692 env->regs[15] += 4;
693 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
694 done:
695 end_exclusive();
696 return segv;
697 }
698
699 void cpu_loop(CPUARMState *env)
700 {
701 CPUState *cs = CPU(arm_env_get_cpu(env));
702 int trapnr;
703 unsigned int n, insn;
704 target_siginfo_t info;
705 uint32_t addr;
706
707 for(;;) {
708 cpu_exec_start(cs);
709 trapnr = cpu_arm_exec(env);
710 cpu_exec_end(cs);
711 switch(trapnr) {
712 case EXCP_UDEF:
713 {
714 TaskState *ts = env->opaque;
715 uint32_t opcode;
716 int rc;
717
718 /* we handle the FPU emulation here, as Linux */
719 /* we get the opcode */
720 /* FIXME - what to do if get_user() fails? */
721 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
722
723 rc = EmulateAll(opcode, &ts->fpa, env);
724 if (rc == 0) { /* illegal instruction */
725 info.si_signo = SIGILL;
726 info.si_errno = 0;
727 info.si_code = TARGET_ILL_ILLOPN;
728 info._sifields._sigfault._addr = env->regs[15];
729 queue_signal(env, info.si_signo, &info);
730 } else if (rc < 0) { /* FP exception */
731 int arm_fpe=0;
732
733 /* translate softfloat flags to FPSR flags */
734 if (-rc & float_flag_invalid)
735 arm_fpe |= BIT_IOC;
736 if (-rc & float_flag_divbyzero)
737 arm_fpe |= BIT_DZC;
738 if (-rc & float_flag_overflow)
739 arm_fpe |= BIT_OFC;
740 if (-rc & float_flag_underflow)
741 arm_fpe |= BIT_UFC;
742 if (-rc & float_flag_inexact)
743 arm_fpe |= BIT_IXC;
744
745 FPSR fpsr = ts->fpa.fpsr;
746 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
747
748 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
749 info.si_signo = SIGFPE;
750 info.si_errno = 0;
751
752 /* ordered by priority, least first */
753 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
754 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
755 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
756 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
757 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
758
759 info._sifields._sigfault._addr = env->regs[15];
760 queue_signal(env, info.si_signo, &info);
761 } else {
762 env->regs[15] += 4;
763 }
764
765 /* accumulate unenabled exceptions */
766 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
767 fpsr |= BIT_IXC;
768 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
769 fpsr |= BIT_UFC;
770 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
771 fpsr |= BIT_OFC;
772 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
773 fpsr |= BIT_DZC;
774 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
775 fpsr |= BIT_IOC;
776 ts->fpa.fpsr=fpsr;
777 } else { /* everything OK */
778 /* increment PC */
779 env->regs[15] += 4;
780 }
781 }
782 break;
783 case EXCP_SWI:
784 case EXCP_BKPT:
785 {
786 env->eabi = 1;
787 /* system call */
788 if (trapnr == EXCP_BKPT) {
789 if (env->thumb) {
790 /* FIXME - what to do if get_user() fails? */
791 get_user_code_u16(insn, env->regs[15], env->bswap_code);
792 n = insn & 0xff;
793 env->regs[15] += 2;
794 } else {
795 /* FIXME - what to do if get_user() fails? */
796 get_user_code_u32(insn, env->regs[15], env->bswap_code);
797 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
798 env->regs[15] += 4;
799 }
800 } else {
801 if (env->thumb) {
802 /* FIXME - what to do if get_user() fails? */
803 get_user_code_u16(insn, env->regs[15] - 2,
804 env->bswap_code);
805 n = insn & 0xff;
806 } else {
807 /* FIXME - what to do if get_user() fails? */
808 get_user_code_u32(insn, env->regs[15] - 4,
809 env->bswap_code);
810 n = insn & 0xffffff;
811 }
812 }
813
814 if (n == ARM_NR_cacheflush) {
815 /* nop */
816 } else if (n == ARM_NR_semihosting
817 || n == ARM_NR_thumb_semihosting) {
818 env->regs[0] = do_arm_semihosting (env);
819 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
820 /* linux syscall */
821 if (env->thumb || n == 0) {
822 n = env->regs[7];
823 } else {
824 n -= ARM_SYSCALL_BASE;
825 env->eabi = 0;
826 }
827 if ( n > ARM_NR_BASE) {
828 switch (n) {
829 case ARM_NR_cacheflush:
830 /* nop */
831 break;
832 case ARM_NR_set_tls:
833 cpu_set_tls(env, env->regs[0]);
834 env->regs[0] = 0;
835 break;
836 default:
837 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
838 n);
839 env->regs[0] = -TARGET_ENOSYS;
840 break;
841 }
842 } else {
843 env->regs[0] = do_syscall(env,
844 n,
845 env->regs[0],
846 env->regs[1],
847 env->regs[2],
848 env->regs[3],
849 env->regs[4],
850 env->regs[5],
851 0, 0);
852 }
853 } else {
854 goto error;
855 }
856 }
857 break;
858 case EXCP_INTERRUPT:
859 /* just indicate that signals should be handled asap */
860 break;
861 case EXCP_PREFETCH_ABORT:
862 addr = env->cp15.c6_insn;
863 goto do_segv;
864 case EXCP_DATA_ABORT:
865 addr = env->cp15.c6_data;
866 do_segv:
867 {
868 info.si_signo = SIGSEGV;
869 info.si_errno = 0;
870 /* XXX: check env->error_code */
871 info.si_code = TARGET_SEGV_MAPERR;
872 info._sifields._sigfault._addr = addr;
873 queue_signal(env, info.si_signo, &info);
874 }
875 break;
876 case EXCP_DEBUG:
877 {
878 int sig;
879
880 sig = gdb_handlesig (env, TARGET_SIGTRAP);
881 if (sig)
882 {
883 info.si_signo = sig;
884 info.si_errno = 0;
885 info.si_code = TARGET_TRAP_BRKPT;
886 queue_signal(env, info.si_signo, &info);
887 }
888 }
889 break;
890 case EXCP_KERNEL_TRAP:
891 if (do_kernel_trap(env))
892 goto error;
893 break;
894 case EXCP_STREX:
895 if (do_strex(env)) {
896 addr = env->cp15.c6_data;
897 goto do_segv;
898 }
899 break;
900 default:
901 error:
902 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
903 trapnr);
904 cpu_dump_state(env, stderr, fprintf, 0);
905 abort();
906 }
907 process_pending_signals(env);
908 }
909 }
910
911 #endif
912
913 #ifdef TARGET_UNICORE32
914
915 void cpu_loop(CPUUniCore32State *env)
916 {
917 CPUState *cs = CPU(uc32_env_get_cpu(env));
918 int trapnr;
919 unsigned int n, insn;
920 target_siginfo_t info;
921
922 for (;;) {
923 cpu_exec_start(cs);
924 trapnr = uc32_cpu_exec(env);
925 cpu_exec_end(cs);
926 switch (trapnr) {
927 case UC32_EXCP_PRIV:
928 {
929 /* system call */
930 get_user_u32(insn, env->regs[31] - 4);
931 n = insn & 0xffffff;
932
933 if (n >= UC32_SYSCALL_BASE) {
934 /* linux syscall */
935 n -= UC32_SYSCALL_BASE;
936 if (n == UC32_SYSCALL_NR_set_tls) {
937 cpu_set_tls(env, env->regs[0]);
938 env->regs[0] = 0;
939 } else {
940 env->regs[0] = do_syscall(env,
941 n,
942 env->regs[0],
943 env->regs[1],
944 env->regs[2],
945 env->regs[3],
946 env->regs[4],
947 env->regs[5],
948 0, 0);
949 }
950 } else {
951 goto error;
952 }
953 }
954 break;
955 case UC32_EXCP_DTRAP:
956 case UC32_EXCP_ITRAP:
957 info.si_signo = SIGSEGV;
958 info.si_errno = 0;
959 /* XXX: check env->error_code */
960 info.si_code = TARGET_SEGV_MAPERR;
961 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
962 queue_signal(env, info.si_signo, &info);
963 break;
964 case EXCP_INTERRUPT:
965 /* just indicate that signals should be handled asap */
966 break;
967 case EXCP_DEBUG:
968 {
969 int sig;
970
971 sig = gdb_handlesig(env, TARGET_SIGTRAP);
972 if (sig) {
973 info.si_signo = sig;
974 info.si_errno = 0;
975 info.si_code = TARGET_TRAP_BRKPT;
976 queue_signal(env, info.si_signo, &info);
977 }
978 }
979 break;
980 default:
981 goto error;
982 }
983 process_pending_signals(env);
984 }
985
986 error:
987 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
988 cpu_dump_state(env, stderr, fprintf, 0);
989 abort();
990 }
991 #endif
992
993 #ifdef TARGET_SPARC
994 #define SPARC64_STACK_BIAS 2047
995
996 //#define DEBUG_WIN
997
998 /* WARNING: dealing with register windows _is_ complicated. More info
999 can be found at http://www.sics.se/~psm/sparcstack.html */
1000 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1001 {
1002 index = (index + cwp * 16) % (16 * env->nwindows);
1003 /* wrap handling : if cwp is on the last window, then we use the
1004 registers 'after' the end */
1005 if (index < 8 && env->cwp == env->nwindows - 1)
1006 index += 16 * env->nwindows;
1007 return index;
1008 }
1009
1010 /* save the register window 'cwp1' */
1011 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1012 {
1013 unsigned int i;
1014 abi_ulong sp_ptr;
1015
1016 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1017 #ifdef TARGET_SPARC64
1018 if (sp_ptr & 3)
1019 sp_ptr += SPARC64_STACK_BIAS;
1020 #endif
1021 #if defined(DEBUG_WIN)
1022 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1023 sp_ptr, cwp1);
1024 #endif
1025 for(i = 0; i < 16; i++) {
1026 /* FIXME - what to do if put_user() fails? */
1027 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1028 sp_ptr += sizeof(abi_ulong);
1029 }
1030 }
1031
1032 static void save_window(CPUSPARCState *env)
1033 {
1034 #ifndef TARGET_SPARC64
1035 unsigned int new_wim;
1036 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1037 ((1LL << env->nwindows) - 1);
1038 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1039 env->wim = new_wim;
1040 #else
1041 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1042 env->cansave++;
1043 env->canrestore--;
1044 #endif
1045 }
1046
1047 static void restore_window(CPUSPARCState *env)
1048 {
1049 #ifndef TARGET_SPARC64
1050 unsigned int new_wim;
1051 #endif
1052 unsigned int i, cwp1;
1053 abi_ulong sp_ptr;
1054
1055 #ifndef TARGET_SPARC64
1056 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1057 ((1LL << env->nwindows) - 1);
1058 #endif
1059
1060 /* restore the invalid window */
1061 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1062 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1063 #ifdef TARGET_SPARC64
1064 if (sp_ptr & 3)
1065 sp_ptr += SPARC64_STACK_BIAS;
1066 #endif
1067 #if defined(DEBUG_WIN)
1068 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1069 sp_ptr, cwp1);
1070 #endif
1071 for(i = 0; i < 16; i++) {
1072 /* FIXME - what to do if get_user() fails? */
1073 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1074 sp_ptr += sizeof(abi_ulong);
1075 }
1076 #ifdef TARGET_SPARC64
1077 env->canrestore++;
1078 if (env->cleanwin < env->nwindows - 1)
1079 env->cleanwin++;
1080 env->cansave--;
1081 #else
1082 env->wim = new_wim;
1083 #endif
1084 }
1085
1086 static void flush_windows(CPUSPARCState *env)
1087 {
1088 int offset, cwp1;
1089
1090 offset = 1;
1091 for(;;) {
1092 /* if restore would invoke restore_window(), then we can stop */
1093 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1094 #ifndef TARGET_SPARC64
1095 if (env->wim & (1 << cwp1))
1096 break;
1097 #else
1098 if (env->canrestore == 0)
1099 break;
1100 env->cansave++;
1101 env->canrestore--;
1102 #endif
1103 save_window_offset(env, cwp1);
1104 offset++;
1105 }
1106 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1107 #ifndef TARGET_SPARC64
1108 /* set wim so that restore will reload the registers */
1109 env->wim = 1 << cwp1;
1110 #endif
1111 #if defined(DEBUG_WIN)
1112 printf("flush_windows: nb=%d\n", offset - 1);
1113 #endif
1114 }
1115
1116 void cpu_loop (CPUSPARCState *env)
1117 {
1118 int trapnr;
1119 abi_long ret;
1120 target_siginfo_t info;
1121
1122 while (1) {
1123 trapnr = cpu_sparc_exec (env);
1124
1125 /* Compute PSR before exposing state. */
1126 if (env->cc_op != CC_OP_FLAGS) {
1127 cpu_get_psr(env);
1128 }
1129
1130 switch (trapnr) {
1131 #ifndef TARGET_SPARC64
1132 case 0x88:
1133 case 0x90:
1134 #else
1135 case 0x110:
1136 case 0x16d:
1137 #endif
1138 ret = do_syscall (env, env->gregs[1],
1139 env->regwptr[0], env->regwptr[1],
1140 env->regwptr[2], env->regwptr[3],
1141 env->regwptr[4], env->regwptr[5],
1142 0, 0);
1143 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1144 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1145 env->xcc |= PSR_CARRY;
1146 #else
1147 env->psr |= PSR_CARRY;
1148 #endif
1149 ret = -ret;
1150 } else {
1151 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1152 env->xcc &= ~PSR_CARRY;
1153 #else
1154 env->psr &= ~PSR_CARRY;
1155 #endif
1156 }
1157 env->regwptr[0] = ret;
1158 /* next instruction */
1159 env->pc = env->npc;
1160 env->npc = env->npc + 4;
1161 break;
1162 case 0x83: /* flush windows */
1163 #ifdef TARGET_ABI32
1164 case 0x103:
1165 #endif
1166 flush_windows(env);
1167 /* next instruction */
1168 env->pc = env->npc;
1169 env->npc = env->npc + 4;
1170 break;
1171 #ifndef TARGET_SPARC64
1172 case TT_WIN_OVF: /* window overflow */
1173 save_window(env);
1174 break;
1175 case TT_WIN_UNF: /* window underflow */
1176 restore_window(env);
1177 break;
1178 case TT_TFAULT:
1179 case TT_DFAULT:
1180 {
1181 info.si_signo = TARGET_SIGSEGV;
1182 info.si_errno = 0;
1183 /* XXX: check env->error_code */
1184 info.si_code = TARGET_SEGV_MAPERR;
1185 info._sifields._sigfault._addr = env->mmuregs[4];
1186 queue_signal(env, info.si_signo, &info);
1187 }
1188 break;
1189 #else
1190 case TT_SPILL: /* window overflow */
1191 save_window(env);
1192 break;
1193 case TT_FILL: /* window underflow */
1194 restore_window(env);
1195 break;
1196 case TT_TFAULT:
1197 case TT_DFAULT:
1198 {
1199 info.si_signo = TARGET_SIGSEGV;
1200 info.si_errno = 0;
1201 /* XXX: check env->error_code */
1202 info.si_code = TARGET_SEGV_MAPERR;
1203 if (trapnr == TT_DFAULT)
1204 info._sifields._sigfault._addr = env->dmmuregs[4];
1205 else
1206 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1207 queue_signal(env, info.si_signo, &info);
1208 }
1209 break;
1210 #ifndef TARGET_ABI32
1211 case 0x16e:
1212 flush_windows(env);
1213 sparc64_get_context(env);
1214 break;
1215 case 0x16f:
1216 flush_windows(env);
1217 sparc64_set_context(env);
1218 break;
1219 #endif
1220 #endif
1221 case EXCP_INTERRUPT:
1222 /* just indicate that signals should be handled asap */
1223 break;
1224 case TT_ILL_INSN:
1225 {
1226 info.si_signo = TARGET_SIGILL;
1227 info.si_errno = 0;
1228 info.si_code = TARGET_ILL_ILLOPC;
1229 info._sifields._sigfault._addr = env->pc;
1230 queue_signal(env, info.si_signo, &info);
1231 }
1232 break;
1233 case EXCP_DEBUG:
1234 {
1235 int sig;
1236
1237 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1238 if (sig)
1239 {
1240 info.si_signo = sig;
1241 info.si_errno = 0;
1242 info.si_code = TARGET_TRAP_BRKPT;
1243 queue_signal(env, info.si_signo, &info);
1244 }
1245 }
1246 break;
1247 default:
1248 printf ("Unhandled trap: 0x%x\n", trapnr);
1249 cpu_dump_state(env, stderr, fprintf, 0);
1250 exit (1);
1251 }
1252 process_pending_signals (env);
1253 }
1254 }
1255
1256 #endif
1257
1258 #ifdef TARGET_PPC
1259 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1260 {
1261 /* TO FIX */
1262 return 0;
1263 }
1264
1265 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1266 {
1267 return cpu_ppc_get_tb(env);
1268 }
1269
1270 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1271 {
1272 return cpu_ppc_get_tb(env) >> 32;
1273 }
1274
1275 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1276 {
1277 return cpu_ppc_get_tb(env);
1278 }
1279
1280 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1281 {
1282 return cpu_ppc_get_tb(env) >> 32;
1283 }
1284
1285 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1286 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1287
1288 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1289 {
1290 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1291 }
1292
1293 /* XXX: to be fixed */
1294 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1295 {
1296 return -1;
1297 }
1298
1299 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1300 {
1301 return -1;
1302 }
1303
1304 #define EXCP_DUMP(env, fmt, ...) \
1305 do { \
1306 fprintf(stderr, fmt , ## __VA_ARGS__); \
1307 cpu_dump_state(env, stderr, fprintf, 0); \
1308 qemu_log(fmt, ## __VA_ARGS__); \
1309 if (qemu_log_enabled()) { \
1310 log_cpu_state(env, 0); \
1311 } \
1312 } while (0)
1313
1314 static int do_store_exclusive(CPUPPCState *env)
1315 {
1316 target_ulong addr;
1317 target_ulong page_addr;
1318 target_ulong val;
1319 int flags;
1320 int segv = 0;
1321
1322 addr = env->reserve_ea;
1323 page_addr = addr & TARGET_PAGE_MASK;
1324 start_exclusive();
1325 mmap_lock();
1326 flags = page_get_flags(page_addr);
1327 if ((flags & PAGE_READ) == 0) {
1328 segv = 1;
1329 } else {
1330 int reg = env->reserve_info & 0x1f;
1331 int size = (env->reserve_info >> 5) & 0xf;
1332 int stored = 0;
1333
1334 if (addr == env->reserve_addr) {
1335 switch (size) {
1336 case 1: segv = get_user_u8(val, addr); break;
1337 case 2: segv = get_user_u16(val, addr); break;
1338 case 4: segv = get_user_u32(val, addr); break;
1339 #if defined(TARGET_PPC64)
1340 case 8: segv = get_user_u64(val, addr); break;
1341 #endif
1342 default: abort();
1343 }
1344 if (!segv && val == env->reserve_val) {
1345 val = env->gpr[reg];
1346 switch (size) {
1347 case 1: segv = put_user_u8(val, addr); break;
1348 case 2: segv = put_user_u16(val, addr); break;
1349 case 4: segv = put_user_u32(val, addr); break;
1350 #if defined(TARGET_PPC64)
1351 case 8: segv = put_user_u64(val, addr); break;
1352 #endif
1353 default: abort();
1354 }
1355 if (!segv) {
1356 stored = 1;
1357 }
1358 }
1359 }
1360 env->crf[0] = (stored << 1) | xer_so;
1361 env->reserve_addr = (target_ulong)-1;
1362 }
1363 if (!segv) {
1364 env->nip += 4;
1365 }
1366 mmap_unlock();
1367 end_exclusive();
1368 return segv;
1369 }
1370
1371 void cpu_loop(CPUPPCState *env)
1372 {
1373 CPUState *cs = CPU(ppc_env_get_cpu(env));
1374 target_siginfo_t info;
1375 int trapnr;
1376 target_ulong ret;
1377
1378 for(;;) {
1379 cpu_exec_start(cs);
1380 trapnr = cpu_ppc_exec(env);
1381 cpu_exec_end(cs);
1382 switch(trapnr) {
1383 case POWERPC_EXCP_NONE:
1384 /* Just go on */
1385 break;
1386 case POWERPC_EXCP_CRITICAL: /* Critical input */
1387 cpu_abort(env, "Critical interrupt while in user mode. "
1388 "Aborting\n");
1389 break;
1390 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1391 cpu_abort(env, "Machine check exception while in user mode. "
1392 "Aborting\n");
1393 break;
1394 case POWERPC_EXCP_DSI: /* Data storage exception */
1395 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1396 env->spr[SPR_DAR]);
1397 /* XXX: check this. Seems bugged */
1398 switch (env->error_code & 0xFF000000) {
1399 case 0x40000000:
1400 info.si_signo = TARGET_SIGSEGV;
1401 info.si_errno = 0;
1402 info.si_code = TARGET_SEGV_MAPERR;
1403 break;
1404 case 0x04000000:
1405 info.si_signo = TARGET_SIGILL;
1406 info.si_errno = 0;
1407 info.si_code = TARGET_ILL_ILLADR;
1408 break;
1409 case 0x08000000:
1410 info.si_signo = TARGET_SIGSEGV;
1411 info.si_errno = 0;
1412 info.si_code = TARGET_SEGV_ACCERR;
1413 break;
1414 default:
1415 /* Let's send a regular segfault... */
1416 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1417 env->error_code);
1418 info.si_signo = TARGET_SIGSEGV;
1419 info.si_errno = 0;
1420 info.si_code = TARGET_SEGV_MAPERR;
1421 break;
1422 }
1423 info._sifields._sigfault._addr = env->nip;
1424 queue_signal(env, info.si_signo, &info);
1425 break;
1426 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1427 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1428 "\n", env->spr[SPR_SRR0]);
1429 /* XXX: check this */
1430 switch (env->error_code & 0xFF000000) {
1431 case 0x40000000:
1432 info.si_signo = TARGET_SIGSEGV;
1433 info.si_errno = 0;
1434 info.si_code = TARGET_SEGV_MAPERR;
1435 break;
1436 case 0x10000000:
1437 case 0x08000000:
1438 info.si_signo = TARGET_SIGSEGV;
1439 info.si_errno = 0;
1440 info.si_code = TARGET_SEGV_ACCERR;
1441 break;
1442 default:
1443 /* Let's send a regular segfault... */
1444 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1445 env->error_code);
1446 info.si_signo = TARGET_SIGSEGV;
1447 info.si_errno = 0;
1448 info.si_code = TARGET_SEGV_MAPERR;
1449 break;
1450 }
1451 info._sifields._sigfault._addr = env->nip - 4;
1452 queue_signal(env, info.si_signo, &info);
1453 break;
1454 case POWERPC_EXCP_EXTERNAL: /* External input */
1455 cpu_abort(env, "External interrupt while in user mode. "
1456 "Aborting\n");
1457 break;
1458 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1459 EXCP_DUMP(env, "Unaligned memory access\n");
1460 /* XXX: check this */
1461 info.si_signo = TARGET_SIGBUS;
1462 info.si_errno = 0;
1463 info.si_code = TARGET_BUS_ADRALN;
1464 info._sifields._sigfault._addr = env->nip - 4;
1465 queue_signal(env, info.si_signo, &info);
1466 break;
1467 case POWERPC_EXCP_PROGRAM: /* Program exception */
1468 /* XXX: check this */
1469 switch (env->error_code & ~0xF) {
1470 case POWERPC_EXCP_FP:
1471 EXCP_DUMP(env, "Floating point program exception\n");
1472 info.si_signo = TARGET_SIGFPE;
1473 info.si_errno = 0;
1474 switch (env->error_code & 0xF) {
1475 case POWERPC_EXCP_FP_OX:
1476 info.si_code = TARGET_FPE_FLTOVF;
1477 break;
1478 case POWERPC_EXCP_FP_UX:
1479 info.si_code = TARGET_FPE_FLTUND;
1480 break;
1481 case POWERPC_EXCP_FP_ZX:
1482 case POWERPC_EXCP_FP_VXZDZ:
1483 info.si_code = TARGET_FPE_FLTDIV;
1484 break;
1485 case POWERPC_EXCP_FP_XX:
1486 info.si_code = TARGET_FPE_FLTRES;
1487 break;
1488 case POWERPC_EXCP_FP_VXSOFT:
1489 info.si_code = TARGET_FPE_FLTINV;
1490 break;
1491 case POWERPC_EXCP_FP_VXSNAN:
1492 case POWERPC_EXCP_FP_VXISI:
1493 case POWERPC_EXCP_FP_VXIDI:
1494 case POWERPC_EXCP_FP_VXIMZ:
1495 case POWERPC_EXCP_FP_VXVC:
1496 case POWERPC_EXCP_FP_VXSQRT:
1497 case POWERPC_EXCP_FP_VXCVI:
1498 info.si_code = TARGET_FPE_FLTSUB;
1499 break;
1500 default:
1501 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1502 env->error_code);
1503 break;
1504 }
1505 break;
1506 case POWERPC_EXCP_INVAL:
1507 EXCP_DUMP(env, "Invalid instruction\n");
1508 info.si_signo = TARGET_SIGILL;
1509 info.si_errno = 0;
1510 switch (env->error_code & 0xF) {
1511 case POWERPC_EXCP_INVAL_INVAL:
1512 info.si_code = TARGET_ILL_ILLOPC;
1513 break;
1514 case POWERPC_EXCP_INVAL_LSWX:
1515 info.si_code = TARGET_ILL_ILLOPN;
1516 break;
1517 case POWERPC_EXCP_INVAL_SPR:
1518 info.si_code = TARGET_ILL_PRVREG;
1519 break;
1520 case POWERPC_EXCP_INVAL_FP:
1521 info.si_code = TARGET_ILL_COPROC;
1522 break;
1523 default:
1524 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1525 env->error_code & 0xF);
1526 info.si_code = TARGET_ILL_ILLADR;
1527 break;
1528 }
1529 break;
1530 case POWERPC_EXCP_PRIV:
1531 EXCP_DUMP(env, "Privilege violation\n");
1532 info.si_signo = TARGET_SIGILL;
1533 info.si_errno = 0;
1534 switch (env->error_code & 0xF) {
1535 case POWERPC_EXCP_PRIV_OPC:
1536 info.si_code = TARGET_ILL_PRVOPC;
1537 break;
1538 case POWERPC_EXCP_PRIV_REG:
1539 info.si_code = TARGET_ILL_PRVREG;
1540 break;
1541 default:
1542 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1543 env->error_code & 0xF);
1544 info.si_code = TARGET_ILL_PRVOPC;
1545 break;
1546 }
1547 break;
1548 case POWERPC_EXCP_TRAP:
1549 cpu_abort(env, "Tried to call a TRAP\n");
1550 break;
1551 default:
1552 /* Should not happen ! */
1553 cpu_abort(env, "Unknown program exception (%02x)\n",
1554 env->error_code);
1555 break;
1556 }
1557 info._sifields._sigfault._addr = env->nip - 4;
1558 queue_signal(env, info.si_signo, &info);
1559 break;
1560 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1561 EXCP_DUMP(env, "No floating point allowed\n");
1562 info.si_signo = TARGET_SIGILL;
1563 info.si_errno = 0;
1564 info.si_code = TARGET_ILL_COPROC;
1565 info._sifields._sigfault._addr = env->nip - 4;
1566 queue_signal(env, info.si_signo, &info);
1567 break;
1568 case POWERPC_EXCP_SYSCALL: /* System call exception */
1569 cpu_abort(env, "Syscall exception while in user mode. "
1570 "Aborting\n");
1571 break;
1572 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1573 EXCP_DUMP(env, "No APU instruction allowed\n");
1574 info.si_signo = TARGET_SIGILL;
1575 info.si_errno = 0;
1576 info.si_code = TARGET_ILL_COPROC;
1577 info._sifields._sigfault._addr = env->nip - 4;
1578 queue_signal(env, info.si_signo, &info);
1579 break;
1580 case POWERPC_EXCP_DECR: /* Decrementer exception */
1581 cpu_abort(env, "Decrementer interrupt while in user mode. "
1582 "Aborting\n");
1583 break;
1584 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1585 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1586 "Aborting\n");
1587 break;
1588 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1589 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1590 "Aborting\n");
1591 break;
1592 case POWERPC_EXCP_DTLB: /* Data TLB error */
1593 cpu_abort(env, "Data TLB exception while in user mode. "
1594 "Aborting\n");
1595 break;
1596 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1597 cpu_abort(env, "Instruction TLB exception while in user mode. "
1598 "Aborting\n");
1599 break;
1600 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1601 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1602 info.si_signo = TARGET_SIGILL;
1603 info.si_errno = 0;
1604 info.si_code = TARGET_ILL_COPROC;
1605 info._sifields._sigfault._addr = env->nip - 4;
1606 queue_signal(env, info.si_signo, &info);
1607 break;
1608 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1609 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1610 break;
1611 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1612 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1613 break;
1614 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1615 cpu_abort(env, "Performance monitor exception not handled\n");
1616 break;
1617 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1618 cpu_abort(env, "Doorbell interrupt while in user mode. "
1619 "Aborting\n");
1620 break;
1621 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1622 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1623 "Aborting\n");
1624 break;
1625 case POWERPC_EXCP_RESET: /* System reset exception */
1626 cpu_abort(env, "Reset interrupt while in user mode. "
1627 "Aborting\n");
1628 break;
1629 case POWERPC_EXCP_DSEG: /* Data segment exception */
1630 cpu_abort(env, "Data segment exception while in user mode. "
1631 "Aborting\n");
1632 break;
1633 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1634 cpu_abort(env, "Instruction segment exception "
1635 "while in user mode. Aborting\n");
1636 break;
1637 /* PowerPC 64 with hypervisor mode support */
1638 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1639 cpu_abort(env, "Hypervisor decrementer interrupt "
1640 "while in user mode. Aborting\n");
1641 break;
1642 case POWERPC_EXCP_TRACE: /* Trace exception */
1643 /* Nothing to do:
1644 * we use this exception to emulate step-by-step execution mode.
1645 */
1646 break;
1647 /* PowerPC 64 with hypervisor mode support */
1648 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1649 cpu_abort(env, "Hypervisor data storage exception "
1650 "while in user mode. Aborting\n");
1651 break;
1652 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1653 cpu_abort(env, "Hypervisor instruction storage exception "
1654 "while in user mode. Aborting\n");
1655 break;
1656 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1657 cpu_abort(env, "Hypervisor data segment exception "
1658 "while in user mode. Aborting\n");
1659 break;
1660 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1661 cpu_abort(env, "Hypervisor instruction segment exception "
1662 "while in user mode. Aborting\n");
1663 break;
1664 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1665 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1666 info.si_signo = TARGET_SIGILL;
1667 info.si_errno = 0;
1668 info.si_code = TARGET_ILL_COPROC;
1669 info._sifields._sigfault._addr = env->nip - 4;
1670 queue_signal(env, info.si_signo, &info);
1671 break;
1672 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1673 cpu_abort(env, "Programmable interval timer interrupt "
1674 "while in user mode. Aborting\n");
1675 break;
1676 case POWERPC_EXCP_IO: /* IO error exception */
1677 cpu_abort(env, "IO error exception while in user mode. "
1678 "Aborting\n");
1679 break;
1680 case POWERPC_EXCP_RUNM: /* Run mode exception */
1681 cpu_abort(env, "Run mode exception while in user mode. "
1682 "Aborting\n");
1683 break;
1684 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1685 cpu_abort(env, "Emulation trap exception not handled\n");
1686 break;
1687 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1688 cpu_abort(env, "Instruction fetch TLB exception "
1689 "while in user-mode. Aborting");
1690 break;
1691 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1692 cpu_abort(env, "Data load TLB exception while in user-mode. "
1693 "Aborting");
1694 break;
1695 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1696 cpu_abort(env, "Data store TLB exception while in user-mode. "
1697 "Aborting");
1698 break;
1699 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1700 cpu_abort(env, "Floating-point assist exception not handled\n");
1701 break;
1702 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1703 cpu_abort(env, "Instruction address breakpoint exception "
1704 "not handled\n");
1705 break;
1706 case POWERPC_EXCP_SMI: /* System management interrupt */
1707 cpu_abort(env, "System management interrupt while in user mode. "
1708 "Aborting\n");
1709 break;
1710 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1711 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1712 "Aborting\n");
1713 break;
1714 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1715 cpu_abort(env, "Performance monitor exception not handled\n");
1716 break;
1717 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1718 cpu_abort(env, "Vector assist exception not handled\n");
1719 break;
1720 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1721 cpu_abort(env, "Soft patch exception not handled\n");
1722 break;
1723 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1724 cpu_abort(env, "Maintenance exception while in user mode. "
1725 "Aborting\n");
1726 break;
1727 case POWERPC_EXCP_STOP: /* stop translation */
1728 /* We did invalidate the instruction cache. Go on */
1729 break;
1730 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1731 /* We just stopped because of a branch. Go on */
1732 break;
1733 case POWERPC_EXCP_SYSCALL_USER:
1734 /* system call in user-mode emulation */
1735 /* WARNING:
1736 * PPC ABI uses overflow flag in cr0 to signal an error
1737 * in syscalls.
1738 */
1739 env->crf[0] &= ~0x1;
1740 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1741 env->gpr[5], env->gpr[6], env->gpr[7],
1742 env->gpr[8], 0, 0);
1743 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1744 /* Returning from a successful sigreturn syscall.
1745 Avoid corrupting register state. */
1746 break;
1747 }
1748 if (ret > (target_ulong)(-515)) {
1749 env->crf[0] |= 0x1;
1750 ret = -ret;
1751 }
1752 env->gpr[3] = ret;
1753 break;
1754 case POWERPC_EXCP_STCX:
1755 if (do_store_exclusive(env)) {
1756 info.si_signo = TARGET_SIGSEGV;
1757 info.si_errno = 0;
1758 info.si_code = TARGET_SEGV_MAPERR;
1759 info._sifields._sigfault._addr = env->nip;
1760 queue_signal(env, info.si_signo, &info);
1761 }
1762 break;
1763 case EXCP_DEBUG:
1764 {
1765 int sig;
1766
1767 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1768 if (sig) {
1769 info.si_signo = sig;
1770 info.si_errno = 0;
1771 info.si_code = TARGET_TRAP_BRKPT;
1772 queue_signal(env, info.si_signo, &info);
1773 }
1774 }
1775 break;
1776 case EXCP_INTERRUPT:
1777 /* just indicate that signals should be handled asap */
1778 break;
1779 default:
1780 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1781 break;
1782 }
1783 process_pending_signals(env);
1784 }
1785 }
1786 #endif
1787
1788 #ifdef TARGET_MIPS
1789
1790 # ifdef TARGET_ABI_MIPSO32
1791 # define MIPS_SYS(name, args) args,
1792 static const uint8_t mips_syscall_args[] = {
1793 MIPS_SYS(sys_syscall , 8) /* 4000 */
1794 MIPS_SYS(sys_exit , 1)
1795 MIPS_SYS(sys_fork , 0)
1796 MIPS_SYS(sys_read , 3)
1797 MIPS_SYS(sys_write , 3)
1798 MIPS_SYS(sys_open , 3) /* 4005 */
1799 MIPS_SYS(sys_close , 1)
1800 MIPS_SYS(sys_waitpid , 3)
1801 MIPS_SYS(sys_creat , 2)
1802 MIPS_SYS(sys_link , 2)
1803 MIPS_SYS(sys_unlink , 1) /* 4010 */
1804 MIPS_SYS(sys_execve , 0)
1805 MIPS_SYS(sys_chdir , 1)
1806 MIPS_SYS(sys_time , 1)
1807 MIPS_SYS(sys_mknod , 3)
1808 MIPS_SYS(sys_chmod , 2) /* 4015 */
1809 MIPS_SYS(sys_lchown , 3)
1810 MIPS_SYS(sys_ni_syscall , 0)
1811 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1812 MIPS_SYS(sys_lseek , 3)
1813 MIPS_SYS(sys_getpid , 0) /* 4020 */
1814 MIPS_SYS(sys_mount , 5)
1815 MIPS_SYS(sys_oldumount , 1)
1816 MIPS_SYS(sys_setuid , 1)
1817 MIPS_SYS(sys_getuid , 0)
1818 MIPS_SYS(sys_stime , 1) /* 4025 */
1819 MIPS_SYS(sys_ptrace , 4)
1820 MIPS_SYS(sys_alarm , 1)
1821 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1822 MIPS_SYS(sys_pause , 0)
1823 MIPS_SYS(sys_utime , 2) /* 4030 */
1824 MIPS_SYS(sys_ni_syscall , 0)
1825 MIPS_SYS(sys_ni_syscall , 0)
1826 MIPS_SYS(sys_access , 2)
1827 MIPS_SYS(sys_nice , 1)
1828 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1829 MIPS_SYS(sys_sync , 0)
1830 MIPS_SYS(sys_kill , 2)
1831 MIPS_SYS(sys_rename , 2)
1832 MIPS_SYS(sys_mkdir , 2)
1833 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1834 MIPS_SYS(sys_dup , 1)
1835 MIPS_SYS(sys_pipe , 0)
1836 MIPS_SYS(sys_times , 1)
1837 MIPS_SYS(sys_ni_syscall , 0)
1838 MIPS_SYS(sys_brk , 1) /* 4045 */
1839 MIPS_SYS(sys_setgid , 1)
1840 MIPS_SYS(sys_getgid , 0)
1841 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1842 MIPS_SYS(sys_geteuid , 0)
1843 MIPS_SYS(sys_getegid , 0) /* 4050 */
1844 MIPS_SYS(sys_acct , 0)
1845 MIPS_SYS(sys_umount , 2)
1846 MIPS_SYS(sys_ni_syscall , 0)
1847 MIPS_SYS(sys_ioctl , 3)
1848 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1849 MIPS_SYS(sys_ni_syscall , 2)
1850 MIPS_SYS(sys_setpgid , 2)
1851 MIPS_SYS(sys_ni_syscall , 0)
1852 MIPS_SYS(sys_olduname , 1)
1853 MIPS_SYS(sys_umask , 1) /* 4060 */
1854 MIPS_SYS(sys_chroot , 1)
1855 MIPS_SYS(sys_ustat , 2)
1856 MIPS_SYS(sys_dup2 , 2)
1857 MIPS_SYS(sys_getppid , 0)
1858 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1859 MIPS_SYS(sys_setsid , 0)
1860 MIPS_SYS(sys_sigaction , 3)
1861 MIPS_SYS(sys_sgetmask , 0)
1862 MIPS_SYS(sys_ssetmask , 1)
1863 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1864 MIPS_SYS(sys_setregid , 2)
1865 MIPS_SYS(sys_sigsuspend , 0)
1866 MIPS_SYS(sys_sigpending , 1)
1867 MIPS_SYS(sys_sethostname , 2)
1868 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1869 MIPS_SYS(sys_getrlimit , 2)
1870 MIPS_SYS(sys_getrusage , 2)
1871 MIPS_SYS(sys_gettimeofday, 2)
1872 MIPS_SYS(sys_settimeofday, 2)
1873 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1874 MIPS_SYS(sys_setgroups , 2)
1875 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1876 MIPS_SYS(sys_symlink , 2)
1877 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1878 MIPS_SYS(sys_readlink , 3) /* 4085 */
1879 MIPS_SYS(sys_uselib , 1)
1880 MIPS_SYS(sys_swapon , 2)
1881 MIPS_SYS(sys_reboot , 3)
1882 MIPS_SYS(old_readdir , 3)
1883 MIPS_SYS(old_mmap , 6) /* 4090 */
1884 MIPS_SYS(sys_munmap , 2)
1885 MIPS_SYS(sys_truncate , 2)
1886 MIPS_SYS(sys_ftruncate , 2)
1887 MIPS_SYS(sys_fchmod , 2)
1888 MIPS_SYS(sys_fchown , 3) /* 4095 */
1889 MIPS_SYS(sys_getpriority , 2)
1890 MIPS_SYS(sys_setpriority , 3)
1891 MIPS_SYS(sys_ni_syscall , 0)
1892 MIPS_SYS(sys_statfs , 2)
1893 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1894 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1895 MIPS_SYS(sys_socketcall , 2)
1896 MIPS_SYS(sys_syslog , 3)
1897 MIPS_SYS(sys_setitimer , 3)
1898 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1899 MIPS_SYS(sys_newstat , 2)
1900 MIPS_SYS(sys_newlstat , 2)
1901 MIPS_SYS(sys_newfstat , 2)
1902 MIPS_SYS(sys_uname , 1)
1903 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1904 MIPS_SYS(sys_vhangup , 0)
1905 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1906 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1907 MIPS_SYS(sys_wait4 , 4)
1908 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1909 MIPS_SYS(sys_sysinfo , 1)
1910 MIPS_SYS(sys_ipc , 6)
1911 MIPS_SYS(sys_fsync , 1)
1912 MIPS_SYS(sys_sigreturn , 0)
1913 MIPS_SYS(sys_clone , 6) /* 4120 */
1914 MIPS_SYS(sys_setdomainname, 2)
1915 MIPS_SYS(sys_newuname , 1)
1916 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1917 MIPS_SYS(sys_adjtimex , 1)
1918 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1919 MIPS_SYS(sys_sigprocmask , 3)
1920 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1921 MIPS_SYS(sys_init_module , 5)
1922 MIPS_SYS(sys_delete_module, 1)
1923 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1924 MIPS_SYS(sys_quotactl , 0)
1925 MIPS_SYS(sys_getpgid , 1)
1926 MIPS_SYS(sys_fchdir , 1)
1927 MIPS_SYS(sys_bdflush , 2)
1928 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1929 MIPS_SYS(sys_personality , 1)
1930 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1931 MIPS_SYS(sys_setfsuid , 1)
1932 MIPS_SYS(sys_setfsgid , 1)
1933 MIPS_SYS(sys_llseek , 5) /* 4140 */
1934 MIPS_SYS(sys_getdents , 3)
1935 MIPS_SYS(sys_select , 5)
1936 MIPS_SYS(sys_flock , 2)
1937 MIPS_SYS(sys_msync , 3)
1938 MIPS_SYS(sys_readv , 3) /* 4145 */
1939 MIPS_SYS(sys_writev , 3)
1940 MIPS_SYS(sys_cacheflush , 3)
1941 MIPS_SYS(sys_cachectl , 3)
1942 MIPS_SYS(sys_sysmips , 4)
1943 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1944 MIPS_SYS(sys_getsid , 1)
1945 MIPS_SYS(sys_fdatasync , 0)
1946 MIPS_SYS(sys_sysctl , 1)
1947 MIPS_SYS(sys_mlock , 2)
1948 MIPS_SYS(sys_munlock , 2) /* 4155 */
1949 MIPS_SYS(sys_mlockall , 1)
1950 MIPS_SYS(sys_munlockall , 0)
1951 MIPS_SYS(sys_sched_setparam, 2)
1952 MIPS_SYS(sys_sched_getparam, 2)
1953 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1954 MIPS_SYS(sys_sched_getscheduler, 1)
1955 MIPS_SYS(sys_sched_yield , 0)
1956 MIPS_SYS(sys_sched_get_priority_max, 1)
1957 MIPS_SYS(sys_sched_get_priority_min, 1)
1958 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1959 MIPS_SYS(sys_nanosleep, 2)
1960 MIPS_SYS(sys_mremap , 4)
1961 MIPS_SYS(sys_accept , 3)
1962 MIPS_SYS(sys_bind , 3)
1963 MIPS_SYS(sys_connect , 3) /* 4170 */
1964 MIPS_SYS(sys_getpeername , 3)
1965 MIPS_SYS(sys_getsockname , 3)
1966 MIPS_SYS(sys_getsockopt , 5)
1967 MIPS_SYS(sys_listen , 2)
1968 MIPS_SYS(sys_recv , 4) /* 4175 */
1969 MIPS_SYS(sys_recvfrom , 6)
1970 MIPS_SYS(sys_recvmsg , 3)
1971 MIPS_SYS(sys_send , 4)
1972 MIPS_SYS(sys_sendmsg , 3)
1973 MIPS_SYS(sys_sendto , 6) /* 4180 */
1974 MIPS_SYS(sys_setsockopt , 5)
1975 MIPS_SYS(sys_shutdown , 2)
1976 MIPS_SYS(sys_socket , 3)
1977 MIPS_SYS(sys_socketpair , 4)
1978 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1979 MIPS_SYS(sys_getresuid , 3)
1980 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1981 MIPS_SYS(sys_poll , 3)
1982 MIPS_SYS(sys_nfsservctl , 3)
1983 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1984 MIPS_SYS(sys_getresgid , 3)
1985 MIPS_SYS(sys_prctl , 5)
1986 MIPS_SYS(sys_rt_sigreturn, 0)
1987 MIPS_SYS(sys_rt_sigaction, 4)
1988 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1989 MIPS_SYS(sys_rt_sigpending, 2)
1990 MIPS_SYS(sys_rt_sigtimedwait, 4)
1991 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1992 MIPS_SYS(sys_rt_sigsuspend, 0)
1993 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1994 MIPS_SYS(sys_pwrite64 , 6)
1995 MIPS_SYS(sys_chown , 3)
1996 MIPS_SYS(sys_getcwd , 2)
1997 MIPS_SYS(sys_capget , 2)
1998 MIPS_SYS(sys_capset , 2) /* 4205 */
1999 MIPS_SYS(sys_sigaltstack , 2)
2000 MIPS_SYS(sys_sendfile , 4)
2001 MIPS_SYS(sys_ni_syscall , 0)
2002 MIPS_SYS(sys_ni_syscall , 0)
2003 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2004 MIPS_SYS(sys_truncate64 , 4)
2005 MIPS_SYS(sys_ftruncate64 , 4)
2006 MIPS_SYS(sys_stat64 , 2)
2007 MIPS_SYS(sys_lstat64 , 2)
2008 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2009 MIPS_SYS(sys_pivot_root , 2)
2010 MIPS_SYS(sys_mincore , 3)
2011 MIPS_SYS(sys_madvise , 3)
2012 MIPS_SYS(sys_getdents64 , 3)
2013 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2014 MIPS_SYS(sys_ni_syscall , 0)
2015 MIPS_SYS(sys_gettid , 0)
2016 MIPS_SYS(sys_readahead , 5)
2017 MIPS_SYS(sys_setxattr , 5)
2018 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2019 MIPS_SYS(sys_fsetxattr , 5)
2020 MIPS_SYS(sys_getxattr , 4)
2021 MIPS_SYS(sys_lgetxattr , 4)
2022 MIPS_SYS(sys_fgetxattr , 4)
2023 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2024 MIPS_SYS(sys_llistxattr , 3)
2025 MIPS_SYS(sys_flistxattr , 3)
2026 MIPS_SYS(sys_removexattr , 2)
2027 MIPS_SYS(sys_lremovexattr, 2)
2028 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2029 MIPS_SYS(sys_tkill , 2)
2030 MIPS_SYS(sys_sendfile64 , 5)
2031 MIPS_SYS(sys_futex , 2)
2032 MIPS_SYS(sys_sched_setaffinity, 3)
2033 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2034 MIPS_SYS(sys_io_setup , 2)
2035 MIPS_SYS(sys_io_destroy , 1)
2036 MIPS_SYS(sys_io_getevents, 5)
2037 MIPS_SYS(sys_io_submit , 3)
2038 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2039 MIPS_SYS(sys_exit_group , 1)
2040 MIPS_SYS(sys_lookup_dcookie, 3)
2041 MIPS_SYS(sys_epoll_create, 1)
2042 MIPS_SYS(sys_epoll_ctl , 4)
2043 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2044 MIPS_SYS(sys_remap_file_pages, 5)
2045 MIPS_SYS(sys_set_tid_address, 1)
2046 MIPS_SYS(sys_restart_syscall, 0)
2047 MIPS_SYS(sys_fadvise64_64, 7)
2048 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2049 MIPS_SYS(sys_fstatfs64 , 2)
2050 MIPS_SYS(sys_timer_create, 3)
2051 MIPS_SYS(sys_timer_settime, 4)
2052 MIPS_SYS(sys_timer_gettime, 2)
2053 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2054 MIPS_SYS(sys_timer_delete, 1)
2055 MIPS_SYS(sys_clock_settime, 2)
2056 MIPS_SYS(sys_clock_gettime, 2)
2057 MIPS_SYS(sys_clock_getres, 2)
2058 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2059 MIPS_SYS(sys_tgkill , 3)
2060 MIPS_SYS(sys_utimes , 2)
2061 MIPS_SYS(sys_mbind , 4)
2062 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2063 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2064 MIPS_SYS(sys_mq_open , 4)
2065 MIPS_SYS(sys_mq_unlink , 1)
2066 MIPS_SYS(sys_mq_timedsend, 5)
2067 MIPS_SYS(sys_mq_timedreceive, 5)
2068 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2069 MIPS_SYS(sys_mq_getsetattr, 3)
2070 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2071 MIPS_SYS(sys_waitid , 4)
2072 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2073 MIPS_SYS(sys_add_key , 5)
2074 MIPS_SYS(sys_request_key, 4)
2075 MIPS_SYS(sys_keyctl , 5)
2076 MIPS_SYS(sys_set_thread_area, 1)
2077 MIPS_SYS(sys_inotify_init, 0)
2078 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2079 MIPS_SYS(sys_inotify_rm_watch, 2)
2080 MIPS_SYS(sys_migrate_pages, 4)
2081 MIPS_SYS(sys_openat, 4)
2082 MIPS_SYS(sys_mkdirat, 3)
2083 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2084 MIPS_SYS(sys_fchownat, 5)
2085 MIPS_SYS(sys_futimesat, 3)
2086 MIPS_SYS(sys_fstatat64, 4)
2087 MIPS_SYS(sys_unlinkat, 3)
2088 MIPS_SYS(sys_renameat, 4) /* 4295 */
2089 MIPS_SYS(sys_linkat, 5)
2090 MIPS_SYS(sys_symlinkat, 3)
2091 MIPS_SYS(sys_readlinkat, 4)
2092 MIPS_SYS(sys_fchmodat, 3)
2093 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2094 MIPS_SYS(sys_pselect6, 6)
2095 MIPS_SYS(sys_ppoll, 5)
2096 MIPS_SYS(sys_unshare, 1)
2097 MIPS_SYS(sys_splice, 4)
2098 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2099 MIPS_SYS(sys_tee, 4)
2100 MIPS_SYS(sys_vmsplice, 4)
2101 MIPS_SYS(sys_move_pages, 6)
2102 MIPS_SYS(sys_set_robust_list, 2)
2103 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2104 MIPS_SYS(sys_kexec_load, 4)
2105 MIPS_SYS(sys_getcpu, 3)
2106 MIPS_SYS(sys_epoll_pwait, 6)
2107 MIPS_SYS(sys_ioprio_set, 3)
2108 MIPS_SYS(sys_ioprio_get, 2)
2109 MIPS_SYS(sys_utimensat, 4)
2110 MIPS_SYS(sys_signalfd, 3)
2111 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2112 MIPS_SYS(sys_eventfd, 1)
2113 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2114 MIPS_SYS(sys_timerfd_create, 2)
2115 MIPS_SYS(sys_timerfd_gettime, 2)
2116 MIPS_SYS(sys_timerfd_settime, 4)
2117 MIPS_SYS(sys_signalfd4, 4)
2118 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2119 MIPS_SYS(sys_epoll_create1, 1)
2120 MIPS_SYS(sys_dup3, 3)
2121 MIPS_SYS(sys_pipe2, 2)
2122 MIPS_SYS(sys_inotify_init1, 1)
2123 MIPS_SYS(sys_preadv, 6) /* 4330 */
2124 MIPS_SYS(sys_pwritev, 6)
2125 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2126 MIPS_SYS(sys_perf_event_open, 5)
2127 MIPS_SYS(sys_accept4, 4)
2128 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2129 MIPS_SYS(sys_fanotify_init, 2)
2130 MIPS_SYS(sys_fanotify_mark, 6)
2131 MIPS_SYS(sys_prlimit64, 4)
2132 MIPS_SYS(sys_name_to_handle_at, 5)
2133 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2134 MIPS_SYS(sys_clock_adjtime, 2)
2135 MIPS_SYS(sys_syncfs, 1)
2136 };
2137 # undef MIPS_SYS
2138 # endif /* O32 */
2139
2140 static int do_store_exclusive(CPUMIPSState *env)
2141 {
2142 target_ulong addr;
2143 target_ulong page_addr;
2144 target_ulong val;
2145 int flags;
2146 int segv = 0;
2147 int reg;
2148 int d;
2149
2150 addr = env->lladdr;
2151 page_addr = addr & TARGET_PAGE_MASK;
2152 start_exclusive();
2153 mmap_lock();
2154 flags = page_get_flags(page_addr);
2155 if ((flags & PAGE_READ) == 0) {
2156 segv = 1;
2157 } else {
2158 reg = env->llreg & 0x1f;
2159 d = (env->llreg & 0x20) != 0;
2160 if (d) {
2161 segv = get_user_s64(val, addr);
2162 } else {
2163 segv = get_user_s32(val, addr);
2164 }
2165 if (!segv) {
2166 if (val != env->llval) {
2167 env->active_tc.gpr[reg] = 0;
2168 } else {
2169 if (d) {
2170 segv = put_user_u64(env->llnewval, addr);
2171 } else {
2172 segv = put_user_u32(env->llnewval, addr);
2173 }
2174 if (!segv) {
2175 env->active_tc.gpr[reg] = 1;
2176 }
2177 }
2178 }
2179 }
2180 env->lladdr = -1;
2181 if (!segv) {
2182 env->active_tc.PC += 4;
2183 }
2184 mmap_unlock();
2185 end_exclusive();
2186 return segv;
2187 }
2188
2189 /* Break codes */
2190 enum {
2191 BRK_OVERFLOW = 6,
2192 BRK_DIVZERO = 7
2193 };
2194
2195 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2196 unsigned int code)
2197 {
2198 int ret = -1;
2199
2200 switch (code) {
2201 case BRK_OVERFLOW:
2202 case BRK_DIVZERO:
2203 info->si_signo = TARGET_SIGFPE;
2204 info->si_errno = 0;
2205 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2206 queue_signal(env, info->si_signo, &*info);
2207 ret = 0;
2208 break;
2209 default:
2210 break;
2211 }
2212
2213 return ret;
2214 }
2215
2216 void cpu_loop(CPUMIPSState *env)
2217 {
2218 CPUState *cs = CPU(mips_env_get_cpu(env));
2219 target_siginfo_t info;
2220 int trapnr;
2221 abi_long ret;
2222 # ifdef TARGET_ABI_MIPSO32
2223 unsigned int syscall_num;
2224 # endif
2225
2226 for(;;) {
2227 cpu_exec_start(cs);
2228 trapnr = cpu_mips_exec(env);
2229 cpu_exec_end(cs);
2230 switch(trapnr) {
2231 case EXCP_SYSCALL:
2232 env->active_tc.PC += 4;
2233 # ifdef TARGET_ABI_MIPSO32
2234 syscall_num = env->active_tc.gpr[2] - 4000;
2235 if (syscall_num >= sizeof(mips_syscall_args)) {
2236 ret = -TARGET_ENOSYS;
2237 } else {
2238 int nb_args;
2239 abi_ulong sp_reg;
2240 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2241
2242 nb_args = mips_syscall_args[syscall_num];
2243 sp_reg = env->active_tc.gpr[29];
2244 switch (nb_args) {
2245 /* these arguments are taken from the stack */
2246 case 8:
2247 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2248 goto done_syscall;
2249 }
2250 case 7:
2251 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2252 goto done_syscall;
2253 }
2254 case 6:
2255 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2256 goto done_syscall;
2257 }
2258 case 5:
2259 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2260 goto done_syscall;
2261 }
2262 default:
2263 break;
2264 }
2265 ret = do_syscall(env, env->active_tc.gpr[2],
2266 env->active_tc.gpr[4],
2267 env->active_tc.gpr[5],
2268 env->active_tc.gpr[6],
2269 env->active_tc.gpr[7],
2270 arg5, arg6, arg7, arg8);
2271 }
2272 done_syscall:
2273 # else
2274 ret = do_syscall(env, env->active_tc.gpr[2],
2275 env->active_tc.gpr[4], env->active_tc.gpr[5],
2276 env->active_tc.gpr[6], env->active_tc.gpr[7],
2277 env->active_tc.gpr[8], env->active_tc.gpr[9],
2278 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2279 # endif /* O32 */
2280 if (ret == -TARGET_QEMU_ESIGRETURN) {
2281 /* Returning from a successful sigreturn syscall.
2282 Avoid clobbering register state. */
2283 break;
2284 }
2285 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2286 env->active_tc.gpr[7] = 1; /* error flag */
2287 ret = -ret;
2288 } else {
2289 env->active_tc.gpr[7] = 0; /* error flag */
2290 }
2291 env->active_tc.gpr[2] = ret;
2292 break;
2293 case EXCP_TLBL:
2294 case EXCP_TLBS:
2295 case EXCP_AdEL:
2296 case EXCP_AdES:
2297 info.si_signo = TARGET_SIGSEGV;
2298 info.si_errno = 0;
2299 /* XXX: check env->error_code */
2300 info.si_code = TARGET_SEGV_MAPERR;
2301 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2302 queue_signal(env, info.si_signo, &info);
2303 break;
2304 case EXCP_CpU:
2305 case EXCP_RI:
2306 info.si_signo = TARGET_SIGILL;
2307 info.si_errno = 0;
2308 info.si_code = 0;
2309 queue_signal(env, info.si_signo, &info);
2310 break;
2311 case EXCP_INTERRUPT:
2312 /* just indicate that signals should be handled asap */
2313 break;
2314 case EXCP_DEBUG:
2315 {
2316 int sig;
2317
2318 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2319 if (sig)
2320 {
2321 info.si_signo = sig;
2322 info.si_errno = 0;
2323 info.si_code = TARGET_TRAP_BRKPT;
2324 queue_signal(env, info.si_signo, &info);
2325 }
2326 }
2327 break;
2328 case EXCP_SC:
2329 if (do_store_exclusive(env)) {
2330 info.si_signo = TARGET_SIGSEGV;
2331 info.si_errno = 0;
2332 info.si_code = TARGET_SEGV_MAPERR;
2333 info._sifields._sigfault._addr = env->active_tc.PC;
2334 queue_signal(env, info.si_signo, &info);
2335 }
2336 break;
2337 case EXCP_DSPDIS:
2338 info.si_signo = TARGET_SIGILL;
2339 info.si_errno = 0;
2340 info.si_code = TARGET_ILL_ILLOPC;
2341 queue_signal(env, info.si_signo, &info);
2342 break;
2343 /* The code below was inspired by the MIPS Linux kernel trap
2344 * handling code in arch/mips/kernel/traps.c.
2345 */
2346 case EXCP_BREAK:
2347 {
2348 abi_ulong trap_instr;
2349 unsigned int code;
2350
2351 ret = get_user_ual(trap_instr, env->active_tc.PC);
2352 if (ret != 0) {
2353 goto error;
2354 }
2355
2356 /* As described in the original Linux kernel code, the
2357 * below checks on 'code' are to work around an old
2358 * assembly bug.
2359 */
2360 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2361 if (code >= (1 << 10)) {
2362 code >>= 10;
2363 }
2364
2365 if (do_break(env, &info, code) != 0) {
2366 goto error;
2367 }
2368 }
2369 break;
2370 case EXCP_TRAP:
2371 {
2372 abi_ulong trap_instr;
2373 unsigned int code = 0;
2374
2375 ret = get_user_ual(trap_instr, env->active_tc.PC);
2376 if (ret != 0) {
2377 goto error;
2378 }
2379
2380 /* The immediate versions don't provide a code. */
2381 if (!(trap_instr & 0xFC000000)) {
2382 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2383 }
2384
2385 if (do_break(env, &info, code) != 0) {
2386 goto error;
2387 }
2388 }
2389 break;
2390 default:
2391 error:
2392 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2393 trapnr);
2394 cpu_dump_state(env, stderr, fprintf, 0);
2395 abort();
2396 }
2397 process_pending_signals(env);
2398 }
2399 }
2400 #endif
2401
2402 #ifdef TARGET_OPENRISC
2403
2404 void cpu_loop(CPUOpenRISCState *env)
2405 {
2406 int trapnr, gdbsig;
2407
2408 for (;;) {
2409 trapnr = cpu_exec(env);
2410 gdbsig = 0;
2411
2412 switch (trapnr) {
2413 case EXCP_RESET:
2414 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2415 exit(1);
2416 break;
2417 case EXCP_BUSERR:
2418 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2419 gdbsig = SIGBUS;
2420 break;
2421 case EXCP_DPF:
2422 case EXCP_IPF:
2423 cpu_dump_state(env, stderr, fprintf, 0);
2424 gdbsig = TARGET_SIGSEGV;
2425 break;
2426 case EXCP_TICK:
2427 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2428 break;
2429 case EXCP_ALIGN:
2430 qemu_log("\nAlignment pc is %#x\n", env->pc);
2431 gdbsig = SIGBUS;
2432 break;
2433 case EXCP_ILLEGAL:
2434 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2435 gdbsig = SIGILL;
2436 break;
2437 case EXCP_INT:
2438 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2439 break;
2440 case EXCP_DTLBMISS:
2441 case EXCP_ITLBMISS:
2442 qemu_log("\nTLB miss\n");
2443 break;
2444 case EXCP_RANGE:
2445 qemu_log("\nRange\n");
2446 gdbsig = SIGSEGV;
2447 break;
2448 case EXCP_SYSCALL:
2449 env->pc += 4; /* 0xc00; */
2450 env->gpr[11] = do_syscall(env,
2451 env->gpr[11], /* return value */
2452 env->gpr[3], /* r3 - r7 are params */
2453 env->gpr[4],
2454 env->gpr[5],
2455 env->gpr[6],
2456 env->gpr[7],
2457 env->gpr[8], 0, 0);
2458 break;
2459 case EXCP_FPE:
2460 qemu_log("\nFloating point error\n");
2461 break;
2462 case EXCP_TRAP:
2463 qemu_log("\nTrap\n");
2464 gdbsig = SIGTRAP;
2465 break;
2466 case EXCP_NR:
2467 qemu_log("\nNR\n");
2468 break;
2469 default:
2470 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2471 trapnr);
2472 cpu_dump_state(env, stderr, fprintf, 0);
2473 gdbsig = TARGET_SIGILL;
2474 break;
2475 }
2476 if (gdbsig) {
2477 gdb_handlesig(env, gdbsig);
2478 if (gdbsig != TARGET_SIGTRAP) {
2479 exit(1);
2480 }
2481 }
2482
2483 process_pending_signals(env);
2484 }
2485 }
2486
2487 #endif /* TARGET_OPENRISC */
2488
2489 #ifdef TARGET_SH4
2490 void cpu_loop(CPUSH4State *env)
2491 {
2492 int trapnr, ret;
2493 target_siginfo_t info;
2494
2495 while (1) {
2496 trapnr = cpu_sh4_exec (env);
2497
2498 switch (trapnr) {
2499 case 0x160:
2500 env->pc += 2;
2501 ret = do_syscall(env,
2502 env->gregs[3],
2503 env->gregs[4],
2504 env->gregs[5],
2505 env->gregs[6],
2506 env->gregs[7],
2507 env->gregs[0],
2508 env->gregs[1],
2509 0, 0);
2510 env->gregs[0] = ret;
2511 break;
2512 case EXCP_INTERRUPT:
2513 /* just indicate that signals should be handled asap */
2514 break;
2515 case EXCP_DEBUG:
2516 {
2517 int sig;
2518
2519 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2520 if (sig)
2521 {
2522 info.si_signo = sig;
2523 info.si_errno = 0;
2524 info.si_code = TARGET_TRAP_BRKPT;
2525 queue_signal(env, info.si_signo, &info);
2526 }
2527 }
2528 break;
2529 case 0xa0:
2530 case 0xc0:
2531 info.si_signo = SIGSEGV;
2532 info.si_errno = 0;
2533 info.si_code = TARGET_SEGV_MAPERR;
2534 info._sifields._sigfault._addr = env->tea;
2535 queue_signal(env, info.si_signo, &info);
2536 break;
2537
2538 default:
2539 printf ("Unhandled trap: 0x%x\n", trapnr);
2540 cpu_dump_state(env, stderr, fprintf, 0);
2541 exit (1);
2542 }
2543 process_pending_signals (env);
2544 }
2545 }
2546 #endif
2547
2548 #ifdef TARGET_CRIS
2549 void cpu_loop(CPUCRISState *env)
2550 {
2551 int trapnr, ret;
2552 target_siginfo_t info;
2553
2554 while (1) {
2555 trapnr = cpu_cris_exec (env);
2556 switch (trapnr) {
2557 case 0xaa:
2558 {
2559 info.si_signo = SIGSEGV;
2560 info.si_errno = 0;
2561 /* XXX: check env->error_code */
2562 info.si_code = TARGET_SEGV_MAPERR;
2563 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2564 queue_signal(env, info.si_signo, &info);
2565 }
2566 break;
2567 case EXCP_INTERRUPT:
2568 /* just indicate that signals should be handled asap */
2569 break;
2570 case EXCP_BREAK:
2571 ret = do_syscall(env,
2572 env->regs[9],
2573 env->regs[10],
2574 env->regs[11],
2575 env->regs[12],
2576 env->regs[13],
2577 env->pregs[7],
2578 env->pregs[11],
2579 0, 0);
2580 env->regs[10] = ret;
2581 break;
2582 case EXCP_DEBUG:
2583 {
2584 int sig;
2585
2586 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2587 if (sig)
2588 {
2589 info.si_signo = sig;
2590 info.si_errno = 0;
2591 info.si_code = TARGET_TRAP_BRKPT;
2592 queue_signal(env, info.si_signo, &info);
2593 }
2594 }
2595 break;
2596 default:
2597 printf ("Unhandled trap: 0x%x\n", trapnr);
2598 cpu_dump_state(env, stderr, fprintf, 0);
2599 exit (1);
2600 }
2601 process_pending_signals (env);
2602 }
2603 }
2604 #endif
2605
2606 #ifdef TARGET_MICROBLAZE
2607 void cpu_loop(CPUMBState *env)
2608 {
2609 int trapnr, ret;
2610 target_siginfo_t info;
2611
2612 while (1) {
2613 trapnr = cpu_mb_exec (env);
2614 switch (trapnr) {
2615 case 0xaa:
2616 {
2617 info.si_signo = SIGSEGV;
2618 info.si_errno = 0;
2619 /* XXX: check env->error_code */
2620 info.si_code = TARGET_SEGV_MAPERR;
2621 info._sifields._sigfault._addr = 0;
2622 queue_signal(env, info.si_signo, &info);
2623 }
2624 break;
2625 case EXCP_INTERRUPT:
2626 /* just indicate that signals should be handled asap */
2627 break;
2628 case EXCP_BREAK:
2629 /* Return address is 4 bytes after the call. */
2630 env->regs[14] += 4;
2631 env->sregs[SR_PC] = env->regs[14];
2632 ret = do_syscall(env,
2633 env->regs[12],
2634 env->regs[5],
2635 env->regs[6],
2636 env->regs[7],
2637 env->regs[8],
2638 env->regs[9],
2639 env->regs[10],
2640 0, 0);
2641 env->regs[3] = ret;
2642 break;
2643 case EXCP_HW_EXCP:
2644 env->regs[17] = env->sregs[SR_PC] + 4;
2645 if (env->iflags & D_FLAG) {
2646 env->sregs[SR_ESR] |= 1 << 12;
2647 env->sregs[SR_PC] -= 4;
2648 /* FIXME: if branch was immed, replay the imm as well. */
2649 }
2650
2651 env->iflags &= ~(IMM_FLAG | D_FLAG);
2652
2653 switch (env->sregs[SR_ESR] & 31) {
2654 case ESR_EC_DIVZERO:
2655 info.si_signo = SIGFPE;
2656 info.si_errno = 0;
2657 info.si_code = TARGET_FPE_FLTDIV;
2658 info._sifields._sigfault._addr = 0;
2659 queue_signal(env, info.si_signo, &info);
2660 break;
2661 case ESR_EC_FPU:
2662 info.si_signo = SIGFPE;
2663 info.si_errno = 0;
2664 if (env->sregs[SR_FSR] & FSR_IO) {
2665 info.si_code = TARGET_FPE_FLTINV;
2666 }
2667 if (env->sregs[SR_FSR] & FSR_DZ) {
2668 info.si_code = TARGET_FPE_FLTDIV;
2669 }
2670 info._sifields._sigfault._addr = 0;
2671 queue_signal(env, info.si_signo, &info);
2672 break;
2673 default:
2674 printf ("Unhandled hw-exception: 0x%x\n",
2675 env->sregs[SR_ESR] & ESR_EC_MASK);
2676 cpu_dump_state(env, stderr, fprintf, 0);
2677 exit (1);
2678 break;
2679 }
2680 break;
2681 case EXCP_DEBUG:
2682 {
2683 int sig;
2684
2685 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2686 if (sig)
2687 {
2688 info.si_signo = sig;
2689 info.si_errno = 0;
2690 info.si_code = TARGET_TRAP_BRKPT;
2691 queue_signal(env, info.si_signo, &info);
2692 }
2693 }
2694 break;
2695 default:
2696 printf ("Unhandled trap: 0x%x\n", trapnr);
2697 cpu_dump_state(env, stderr, fprintf, 0);
2698 exit (1);
2699 }
2700 process_pending_signals (env);
2701 }
2702 }
2703 #endif
2704
2705 #ifdef TARGET_M68K
2706
2707 void cpu_loop(CPUM68KState *env)
2708 {
2709 int trapnr;
2710 unsigned int n;
2711 target_siginfo_t info;
2712 TaskState *ts = env->opaque;
2713
2714 for(;;) {
2715 trapnr = cpu_m68k_exec(env);
2716 switch(trapnr) {
2717 case EXCP_ILLEGAL:
2718 {
2719 if (ts->sim_syscalls) {
2720 uint16_t nr;
2721 nr = lduw(env->pc + 2);
2722 env->pc += 4;
2723 do_m68k_simcall(env, nr);
2724 } else {
2725 goto do_sigill;
2726 }
2727 }
2728 break;
2729 case EXCP_HALT_INSN:
2730 /* Semihosing syscall. */
2731 env->pc += 4;
2732 do_m68k_semihosting(env, env->dregs[0]);
2733 break;
2734 case EXCP_LINEA:
2735 case EXCP_LINEF:
2736 case EXCP_UNSUPPORTED:
2737 do_sigill:
2738 info.si_signo = SIGILL;
2739 info.si_errno = 0;
2740 info.si_code = TARGET_ILL_ILLOPN;
2741 info._sifields._sigfault._addr = env->pc;
2742 queue_signal(env, info.si_signo, &info);
2743 break;
2744 case EXCP_TRAP0:
2745 {
2746 ts->sim_syscalls = 0;
2747 n = env->dregs[0];
2748 env->pc += 2;
2749 env->dregs[0] = do_syscall(env,
2750 n,
2751 env->dregs[1],
2752 env->dregs[2],
2753 env->dregs[3],
2754 env->dregs[4],
2755 env->dregs[5],
2756 env->aregs[0],
2757 0, 0);
2758 }
2759 break;
2760 case EXCP_INTERRUPT:
2761 /* just indicate that signals should be handled asap */
2762 break;
2763 case EXCP_ACCESS:
2764 {
2765 info.si_signo = SIGSEGV;
2766 info.si_errno = 0;
2767 /* XXX: check env->error_code */
2768 info.si_code = TARGET_SEGV_MAPERR;
2769 info._sifields._sigfault._addr = env->mmu.ar;
2770 queue_signal(env, info.si_signo, &info);
2771 }
2772 break;
2773 case EXCP_DEBUG:
2774 {
2775 int sig;
2776
2777 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2778 if (sig)
2779 {
2780 info.si_signo = sig;
2781 info.si_errno = 0;
2782 info.si_code = TARGET_TRAP_BRKPT;
2783 queue_signal(env, info.si_signo, &info);
2784 }
2785 }
2786 break;
2787 default:
2788 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2789 trapnr);
2790 cpu_dump_state(env, stderr, fprintf, 0);
2791 abort();
2792 }
2793 process_pending_signals(env);
2794 }
2795 }
2796 #endif /* TARGET_M68K */
2797
2798 #ifdef TARGET_ALPHA
2799 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2800 {
2801 target_ulong addr, val, tmp;
2802 target_siginfo_t info;
2803 int ret = 0;
2804
2805 addr = env->lock_addr;
2806 tmp = env->lock_st_addr;
2807 env->lock_addr = -1;
2808 env->lock_st_addr = 0;
2809
2810 start_exclusive();
2811 mmap_lock();
2812
2813 if (addr == tmp) {
2814 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2815 goto do_sigsegv;
2816 }
2817
2818 if (val == env->lock_value) {
2819 tmp = env->ir[reg];
2820 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2821 goto do_sigsegv;
2822 }
2823 ret = 1;
2824 }
2825 }
2826 env->ir[reg] = ret;
2827 env->pc += 4;
2828
2829 mmap_unlock();
2830 end_exclusive();
2831 return;
2832
2833 do_sigsegv:
2834 mmap_unlock();
2835 end_exclusive();
2836
2837 info.si_signo = TARGET_SIGSEGV;
2838 info.si_errno = 0;
2839 info.si_code = TARGET_SEGV_MAPERR;
2840 info._sifields._sigfault._addr = addr;
2841 queue_signal(env, TARGET_SIGSEGV, &info);
2842 }
2843
2844 void cpu_loop(CPUAlphaState *env)
2845 {
2846 int trapnr;
2847 target_siginfo_t info;
2848 abi_long sysret;
2849
2850 while (1) {
2851 trapnr = cpu_alpha_exec (env);
2852
2853 /* All of the traps imply a transition through PALcode, which
2854 implies an REI instruction has been executed. Which means
2855 that the intr_flag should be cleared. */
2856 env->intr_flag = 0;
2857
2858 switch (trapnr) {
2859 case EXCP_RESET:
2860 fprintf(stderr, "Reset requested. Exit\n");
2861 exit(1);
2862 break;
2863 case EXCP_MCHK:
2864 fprintf(stderr, "Machine check exception. Exit\n");
2865 exit(1);
2866 break;
2867 case EXCP_SMP_INTERRUPT:
2868 case EXCP_CLK_INTERRUPT:
2869 case EXCP_DEV_INTERRUPT:
2870 fprintf(stderr, "External interrupt. Exit\n");
2871 exit(1);
2872 break;
2873 case EXCP_MMFAULT:
2874 env->lock_addr = -1;
2875 info.si_signo = TARGET_SIGSEGV;
2876 info.si_errno = 0;
2877 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
2878 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
2879 info._sifields._sigfault._addr = env->trap_arg0;
2880 queue_signal(env, info.si_signo, &info);
2881 break;
2882 case EXCP_UNALIGN:
2883 env->lock_addr = -1;
2884 info.si_signo = TARGET_SIGBUS;
2885 info.si_errno = 0;
2886 info.si_code = TARGET_BUS_ADRALN;
2887 info._sifields._sigfault._addr = env->trap_arg0;
2888 queue_signal(env, info.si_signo, &info);
2889 break;
2890 case EXCP_OPCDEC:
2891 do_sigill:
2892 env->lock_addr = -1;
2893 info.si_signo = TARGET_SIGILL;
2894 info.si_errno = 0;
2895 info.si_code = TARGET_ILL_ILLOPC;
2896 info._sifields._sigfault._addr = env->pc;
2897 queue_signal(env, info.si_signo, &info);
2898 break;
2899 case EXCP_ARITH:
2900 env->lock_addr = -1;
2901 info.si_signo = TARGET_SIGFPE;
2902 info.si_errno = 0;
2903 info.si_code = TARGET_FPE_FLTINV;
2904 info._sifields._sigfault._addr = env->pc;
2905 queue_signal(env, info.si_signo, &info);
2906 break;
2907 case EXCP_FEN:
2908 /* No-op. Linux simply re-enables the FPU. */
2909 break;
2910 case EXCP_CALL_PAL:
2911 env->lock_addr = -1;
2912 switch (env->error_code) {
2913 case 0x80:
2914 /* BPT */
2915 info.si_signo = TARGET_SIGTRAP;
2916 info.si_errno = 0;
2917 info.si_code = TARGET_TRAP_BRKPT;
2918 info._sifields._sigfault._addr = env->pc;
2919 queue_signal(env, info.si_signo, &info);
2920 break;
2921 case 0x81:
2922 /* BUGCHK */
2923 info.si_signo = TARGET_SIGTRAP;
2924 info.si_errno = 0;
2925 info.si_code = 0;
2926 info._sifields._sigfault._addr = env->pc;
2927 queue_signal(env, info.si_signo, &info);
2928 break;
2929 case 0x83:
2930 /* CALLSYS */
2931 trapnr = env->ir[IR_V0];
2932 sysret = do_syscall(env, trapnr,
2933 env->ir[IR_A0], env->ir[IR_A1],
2934 env->ir[IR_A2], env->ir[IR_A3],
2935 env->ir[IR_A4], env->ir[IR_A5],
2936 0, 0);
2937 if (trapnr == TARGET_NR_sigreturn
2938 || trapnr == TARGET_NR_rt_sigreturn) {
2939 break;
2940 }
2941 /* Syscall writes 0 to V0 to bypass error check, similar
2942 to how this is handled internal to Linux kernel.
2943 (Ab)use trapnr temporarily as boolean indicating error. */
2944 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2945 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2946 env->ir[IR_A3] = trapnr;
2947 break;
2948 case 0x86:
2949 /* IMB */
2950 /* ??? We can probably elide the code using page_unprotect
2951 that is checking for self-modifying code. Instead we
2952 could simply call tb_flush here. Until we work out the
2953 changes required to turn off the extra write protection,
2954 this can be a no-op. */
2955 break;
2956 case 0x9E:
2957 /* RDUNIQUE */
2958 /* Handled in the translator for usermode. */
2959 abort();
2960 case 0x9F:
2961 /* WRUNIQUE */
2962 /* Handled in the translator for usermode. */
2963 abort();
2964 case 0xAA:
2965 /* GENTRAP */
2966 info.si_signo = TARGET_SIGFPE;
2967 switch (env->ir[IR_A0]) {
2968 case TARGET_GEN_INTOVF:
2969 info.si_code = TARGET_FPE_INTOVF;
2970 break;
2971 case TARGET_GEN_INTDIV:
2972 info.si_code = TARGET_FPE_INTDIV;
2973 break;
2974 case TARGET_GEN_FLTOVF:
2975 info.si_code = TARGET_FPE_FLTOVF;
2976 break;
2977 case TARGET_GEN_FLTUND:
2978 info.si_code = TARGET_FPE_FLTUND;
2979 break;
2980 case TARGET_GEN_FLTINV:
2981 info.si_code = TARGET_FPE_FLTINV;
2982 break;
2983 case TARGET_GEN_FLTINE:
2984 info.si_code = TARGET_FPE_FLTRES;
2985 break;
2986 case TARGET_GEN_ROPRAND:
2987 info.si_code = 0;
2988 break;
2989 default:
2990 info.si_signo = TARGET_SIGTRAP;
2991 info.si_code = 0;
2992 break;
2993 }
2994 info.si_errno = 0;
2995 info._sifields._sigfault._addr = env->pc;
2996 queue_signal(env, info.si_signo, &info);
2997 break;
2998 default:
2999 goto do_sigill;
3000 }
3001 break;
3002 case EXCP_DEBUG:
3003 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
3004 if (info.si_signo) {
3005 env->lock_addr = -1;
3006 info.si_errno = 0;
3007 info.si_code = TARGET_TRAP_BRKPT;
3008 queue_signal(env, info.si_signo, &info);
3009 }
3010 break;
3011 case EXCP_STL_C:
3012 case EXCP_STQ_C:
3013 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3014 break;
3015 case EXCP_INTERRUPT:
3016 /* Just indicate that signals should be handled asap. */
3017 break;
3018 default:
3019 printf ("Unhandled trap: 0x%x\n", trapnr);
3020 cpu_dump_state(env, stderr, fprintf, 0);
3021 exit (1);
3022 }
3023 process_pending_signals (env);
3024 }
3025 }
3026 #endif /* TARGET_ALPHA */
3027
3028 #ifdef TARGET_S390X
3029 void cpu_loop(CPUS390XState *env)
3030 {
3031 int trapnr, n, sig;
3032 target_siginfo_t info;
3033 target_ulong addr;
3034
3035 while (1) {
3036 trapnr = cpu_s390x_exec(env);
3037 switch (trapnr) {
3038 case EXCP_INTERRUPT:
3039 /* Just indicate that signals should be handled asap. */
3040 break;
3041
3042 case EXCP_SVC:
3043 n = env->int_svc_code;
3044 if (!n) {
3045 /* syscalls > 255 */
3046 n = env->regs[1];
3047 }
3048 env->psw.addr += env->int_svc_ilen;
3049 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3050 env->regs[4], env->regs[5],
3051 env->regs[6], env->regs[7], 0, 0);
3052 break;
3053
3054 case EXCP_DEBUG:
3055 sig = gdb_handlesig(env, TARGET_SIGTRAP);
3056 if (sig) {
3057 n = TARGET_TRAP_BRKPT;
3058 goto do_signal_pc;
3059 }
3060 break;
3061 case EXCP_PGM:
3062 n = env->int_pgm_code;
3063 switch (n) {
3064 case PGM_OPERATION:
3065 case PGM_PRIVILEGED:
3066 sig = SIGILL;
3067 n = TARGET_ILL_ILLOPC;
3068 goto do_signal_pc;
3069 case PGM_PROTECTION:
3070 case PGM_ADDRESSING:
3071 sig = SIGSEGV;
3072 /* XXX: check env->error_code */
3073 n = TARGET_SEGV_MAPERR;
3074 addr = env->__excp_addr;
3075 goto do_signal;
3076 case PGM_EXECUTE:
3077 case PGM_SPECIFICATION:
3078 case PGM_SPECIAL_OP:
3079 case PGM_OPERAND:
3080 do_sigill_opn:
3081 sig = SIGILL;
3082 n = TARGET_ILL_ILLOPN;
3083 goto do_signal_pc;
3084
3085 case PGM_FIXPT_OVERFLOW:
3086 sig = SIGFPE;
3087 n = TARGET_FPE_INTOVF;
3088 goto do_signal_pc;
3089 case PGM_FIXPT_DIVIDE:
3090 sig = SIGFPE;
3091 n = TARGET_FPE_INTDIV;
3092 goto do_signal_pc;
3093
3094 case PGM_DATA:
3095 n = (env->fpc >> 8) & 0xff;
3096 if (n == 0xff) {
3097 /* compare-and-trap */
3098 goto do_sigill_opn;
3099 } else {
3100 /* An IEEE exception, simulated or otherwise. */
3101 if (n & 0x80) {
3102 n = TARGET_FPE_FLTINV;
3103 } else if (n & 0x40) {
3104 n = TARGET_FPE_FLTDIV;
3105 } else if (n & 0x20) {
3106 n = TARGET_FPE_FLTOVF;
3107 } else if (n & 0x10) {
3108 n = TARGET_FPE_FLTUND;
3109 } else if (n & 0x08) {
3110 n = TARGET_FPE_FLTRES;
3111 } else {
3112 /* ??? Quantum exception; BFP, DFP error. */
3113 goto do_sigill_opn;
3114 }
3115 sig = SIGFPE;
3116 goto do_signal_pc;
3117 }
3118
3119 default:
3120 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3121 cpu_dump_state(env, stderr, fprintf, 0);
3122 exit(1);
3123 }
3124 break;
3125
3126 do_signal_pc:
3127 addr = env->psw.addr;
3128 do_signal:
3129 info.si_signo = sig;
3130 info.si_errno = 0;
3131 info.si_code = n;
3132 info._sifields._sigfault._addr = addr;
3133 queue_signal(env, info.si_signo, &info);
3134 break;
3135
3136 default:
3137 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3138 cpu_dump_state(env, stderr, fprintf, 0);
3139 exit(1);
3140 }
3141 process_pending_signals (env);
3142 }
3143 }
3144
3145 #endif /* TARGET_S390X */
3146
3147 THREAD CPUArchState *thread_env;
3148
3149 void task_settid(TaskState *ts)
3150 {
3151 if (ts->ts_tid == 0) {
3152 #ifdef CONFIG_USE_NPTL
3153 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3154 #else
3155 /* when no threads are used, tid becomes pid */
3156 ts->ts_tid = getpid();
3157 #endif
3158 }
3159 }
3160
3161 void stop_all_tasks(void)
3162 {
3163 /*
3164 * We trust that when using NPTL, start_exclusive()
3165 * handles thread stopping correctly.
3166 */
3167 start_exclusive();
3168 }
3169
3170 /* Assumes contents are already zeroed. */
3171 void init_task_state(TaskState *ts)
3172 {
3173 int i;
3174
3175 ts->used = 1;
3176 ts->first_free = ts->sigqueue_table;
3177 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3178 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3179 }
3180 ts->sigqueue_table[i].next = NULL;
3181 }
3182
3183 static void handle_arg_help(const char *arg)
3184 {
3185 usage();
3186 }
3187
3188 static void handle_arg_log(const char *arg)
3189 {
3190 int mask;
3191
3192 mask = qemu_str_to_log_mask(arg);
3193 if (!mask) {
3194 qemu_print_log_usage(stdout);
3195 exit(1);
3196 }
3197 qemu_set_log(mask);
3198 }
3199
3200 static void handle_arg_log_filename(const char *arg)
3201 {
3202 qemu_set_log_filename(arg);
3203 }
3204
3205 static void handle_arg_set_env(const char *arg)
3206 {
3207 char *r, *p, *token;
3208 r = p = strdup(arg);
3209 while ((token = strsep(&p, ",")) != NULL) {
3210 if (envlist_setenv(envlist, token) != 0) {
3211 usage();
3212 }
3213 }
3214 free(r);
3215 }
3216
3217 static void handle_arg_unset_env(const char *arg)
3218 {
3219 char *r, *p, *token;
3220 r = p = strdup(arg);
3221 while ((token = strsep(&p, ",")) != NULL) {
3222 if (envlist_unsetenv(envlist, token) != 0) {
3223 usage();
3224 }
3225 }
3226 free(r);
3227 }
3228
3229 static void handle_arg_argv0(const char *arg)
3230 {
3231 argv0 = strdup(arg);
3232 }
3233
3234 static void handle_arg_stack_size(const char *arg)
3235 {
3236 char *p;
3237 guest_stack_size = strtoul(arg, &p, 0);
3238 if (guest_stack_size == 0) {
3239 usage();
3240 }
3241
3242 if (*p == 'M') {
3243 guest_stack_size *= 1024 * 1024;
3244 } else if (*p == 'k' || *p == 'K') {
3245 guest_stack_size *= 1024;
3246 }
3247 }
3248
3249 static void handle_arg_ld_prefix(const char *arg)
3250 {
3251 interp_prefix = strdup(arg);
3252 }
3253
3254 static void handle_arg_pagesize(const char *arg)
3255 {
3256 qemu_host_page_size = atoi(arg);
3257 if (qemu_host_page_size == 0 ||
3258 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3259 fprintf(stderr, "page size must be a power of two\n");
3260 exit(1);
3261 }
3262 }
3263
3264 static void handle_arg_gdb(const char *arg)
3265 {
3266 gdbstub_port = atoi(arg);
3267 }
3268
3269 static void handle_arg_uname(const char *arg)
3270 {
3271 qemu_uname_release = strdup(arg);
3272 }
3273
3274 static void handle_arg_cpu(const char *arg)
3275 {
3276 cpu_model = strdup(arg);
3277 if (cpu_model == NULL || is_help_option(cpu_model)) {
3278 /* XXX: implement xxx_cpu_list for targets that still miss it */
3279 #if defined(cpu_list)
3280 cpu_list(stdout, &fprintf);
3281 #endif
3282 exit(1);
3283 }
3284 }
3285
3286 #if defined(CONFIG_USE_GUEST_BASE)
3287 static void handle_arg_guest_base(const char *arg)
3288 {
3289 guest_base = strtol(arg, NULL, 0);
3290 have_guest_base = 1;
3291 }
3292
3293 static void handle_arg_reserved_va(const char *arg)
3294 {
3295 char *p;
3296 int shift = 0;
3297 reserved_va = strtoul(arg, &p, 0);
3298 switch (*p) {
3299 case 'k':
3300 case 'K':
3301 shift = 10;
3302 break;
3303 case 'M':
3304 shift = 20;
3305 break;
3306 case 'G':
3307 shift = 30;
3308 break;
3309 }
3310 if (shift) {
3311 unsigned long unshifted = reserved_va;
3312 p++;
3313 reserved_va <<= shift;
3314 if (((reserved_va >> shift) != unshifted)
3315 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3316 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3317 #endif
3318 ) {
3319 fprintf(stderr, "Reserved virtual address too big\n");
3320 exit(1);
3321 }
3322 }
3323 if (*p) {
3324 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3325 exit(1);
3326 }
3327 }
3328 #endif
3329
3330 static void handle_arg_singlestep(const char *arg)
3331 {
3332 singlestep = 1;
3333 }
3334
3335 static void handle_arg_strace(const char *arg)
3336 {
3337 do_strace = 1;
3338 }
3339
3340 static void handle_arg_version(const char *arg)
3341 {
3342 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION
3343 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3344 exit(0);
3345 }
3346
3347 struct qemu_argument {
3348 const char *argv;
3349 const char *env;
3350 bool has_arg;
3351 void (*handle_opt)(const char *arg);
3352 const char *example;
3353 const char *help;
3354 };
3355
3356 static const struct qemu_argument arg_table[] = {
3357 {"h", "", false, handle_arg_help,
3358 "", "print this help"},
3359 {"g", "QEMU_GDB", true, handle_arg_gdb,
3360 "port", "wait gdb connection to 'port'"},
3361 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3362 "path", "set the elf interpreter prefix to 'path'"},
3363 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3364 "size", "set the stack size to 'size' bytes"},
3365 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3366 "model", "select CPU (-cpu help for list)"},
3367 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3368 "var=value", "sets targets environment variable (see below)"},
3369 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3370 "var", "unsets targets environment variable (see below)"},
3371 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3372 "argv0", "forces target process argv[0] to be 'argv0'"},
3373 {"r", "QEMU_UNAME", true, handle_arg_uname,
3374 "uname", "set qemu uname release string to 'uname'"},
3375 #if defined(CONFIG_USE_GUEST_BASE)
3376 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3377 "address", "set guest_base address to 'address'"},
3378 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3379 "size", "reserve 'size' bytes for guest virtual address space"},
3380 #endif
3381 {"d", "QEMU_LOG", true, handle_arg_log,
3382 "item[,...]", "enable logging of specified items "
3383 "(use '-d help' for a list of items)"},
3384 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3385 "logfile", "write logs to 'logfile' (default stderr)"},
3386 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3387 "pagesize", "set the host page size to 'pagesize'"},
3388 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3389 "", "run in singlestep mode"},
3390 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3391 "", "log system calls"},
3392 {"version", "QEMU_VERSION", false, handle_arg_version,
3393 "", "display version information and exit"},
3394 {NULL, NULL, false, NULL, NULL, NULL}
3395 };
3396
3397 static void usage(void)
3398 {
3399 const struct qemu_argument *arginfo;
3400 int maxarglen;
3401 int maxenvlen;
3402
3403 printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
3404 "Linux CPU emulator (compiled for " TARGET_ARCH " emulation)\n"
3405 "\n"
3406 "Options and associated environment variables:\n"
3407 "\n");
3408
3409 /* Calculate column widths. We must always have at least enough space
3410 * for the column header.
3411 */
3412 maxarglen = strlen("Argument");
3413 maxenvlen = strlen("Env-variable");
3414
3415 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3416 int arglen = strlen(arginfo->argv);
3417 if (arginfo->has_arg) {
3418 arglen += strlen(arginfo->example) + 1;
3419 }
3420 if (strlen(arginfo->env) > maxenvlen) {
3421 maxenvlen = strlen(arginfo->env);
3422 }
3423 if (arglen > maxarglen) {
3424 maxarglen = arglen;
3425 }
3426 }
3427
3428 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3429 maxenvlen, "Env-variable");
3430
3431 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3432 if (arginfo->has_arg) {
3433 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3434 (int)(maxarglen - strlen(arginfo->argv) - 1),
3435 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3436 } else {
3437 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3438 maxenvlen, arginfo->env,
3439 arginfo->help);
3440 }
3441 }
3442
3443 printf("\n"
3444 "Defaults:\n"
3445 "QEMU_LD_PREFIX = %s\n"
3446 "QEMU_STACK_SIZE = %ld byte\n",
3447 interp_prefix,
3448 guest_stack_size);
3449
3450 printf("\n"
3451 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3452 "QEMU_UNSET_ENV environment variables to set and unset\n"
3453 "environment variables for the target process.\n"
3454 "It is possible to provide several variables by separating them\n"
3455 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3456 "provide the -E and -U options multiple times.\n"
3457 "The following lines are equivalent:\n"
3458 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3459 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3460 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3461 "Note that if you provide several changes to a single variable\n"
3462 "the last change will stay in effect.\n");
3463
3464 exit(1);
3465 }
3466
3467 static int parse_args(int argc, char **argv)
3468 {
3469 const char *r;
3470 int optind;
3471 const struct qemu_argument *arginfo;
3472
3473 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3474 if (arginfo->env == NULL) {
3475 continue;
3476 }
3477
3478 r = getenv(arginfo->env);
3479 if (r != NULL) {
3480 arginfo->handle_opt(r);
3481 }
3482 }
3483
3484 optind = 1;
3485 for (;;) {
3486 if (optind >= argc) {
3487 break;
3488 }
3489 r = argv[optind];
3490 if (r[0] != '-') {
3491 break;
3492 }
3493 optind++;
3494 r++;
3495 if (!strcmp(r, "-")) {
3496 break;
3497 }
3498
3499 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3500 if (!strcmp(r, arginfo->argv)) {
3501 if (arginfo->has_arg) {
3502 if (optind >= argc) {
3503 usage();
3504 }
3505 arginfo->handle_opt(argv[optind]);
3506 optind++;
3507 } else {
3508 arginfo->handle_opt(NULL);
3509 }
3510 break;
3511 }
3512 }
3513
3514 /* no option matched the current argv */
3515 if (arginfo->handle_opt == NULL) {
3516 usage();
3517 }
3518 }
3519
3520 if (optind >= argc) {
3521 usage();
3522 }
3523
3524 filename = argv[optind];
3525 exec_path = argv[optind];
3526
3527 return optind;
3528 }
3529
3530 int main(int argc, char **argv, char **envp)
3531 {
3532 struct target_pt_regs regs1, *regs = &regs1;
3533 struct image_info info1, *info = &info1;
3534 struct linux_binprm bprm;
3535 TaskState *ts;
3536 CPUArchState *env;
3537 int optind;
3538 char **target_environ, **wrk;
3539 char **target_argv;
3540 int target_argc;
3541 int i;
3542 int ret;
3543
3544 module_call_init(MODULE_INIT_QOM);
3545
3546 qemu_cache_utils_init(envp);
3547
3548 if ((envlist = envlist_create()) == NULL) {
3549 (void) fprintf(stderr, "Unable to allocate envlist\n");
3550 exit(1);
3551 }
3552
3553 /* add current environment into the list */
3554 for (wrk = environ; *wrk != NULL; wrk++) {
3555 (void) envlist_setenv(envlist, *wrk);
3556 }
3557
3558 /* Read the stack limit from the kernel. If it's "unlimited",
3559 then we can do little else besides use the default. */
3560 {
3561 struct rlimit lim;
3562 if (getrlimit(RLIMIT_STACK, &lim) == 0
3563 && lim.rlim_cur != RLIM_INFINITY
3564 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3565 guest_stack_size = lim.rlim_cur;
3566 }
3567 }
3568
3569 cpu_model = NULL;
3570 #if defined(cpudef_setup)
3571 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3572 #endif
3573
3574 optind = parse_args(argc, argv);
3575
3576 /* Zero out regs */
3577 memset(regs, 0, sizeof(struct target_pt_regs));
3578
3579 /* Zero out image_info */
3580 memset(info, 0, sizeof(struct image_info));
3581
3582 memset(&bprm, 0, sizeof (bprm));
3583
3584 /* Scan interp_prefix dir for replacement files. */
3585 init_paths(interp_prefix);
3586
3587 if (cpu_model == NULL) {
3588 #if defined(TARGET_I386)
3589 #ifdef TARGET_X86_64
3590 cpu_model = "qemu64";
3591 #else
3592 cpu_model = "qemu32";
3593 #endif
3594 #elif defined(TARGET_ARM)
3595 cpu_model = "any";
3596 #elif defined(TARGET_UNICORE32)
3597 cpu_model = "any";
3598 #elif defined(TARGET_M68K)
3599 cpu_model = "any";
3600 #elif defined(TARGET_SPARC)
3601 #ifdef TARGET_SPARC64
3602 cpu_model = "TI UltraSparc II";
3603 #else
3604 cpu_model = "Fujitsu MB86904";
3605 #endif
3606 #elif defined(TARGET_MIPS)
3607 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3608 cpu_model = "20Kc";
3609 #else
3610 cpu_model = "24Kf";
3611 #endif
3612 #elif defined TARGET_OPENRISC
3613 cpu_model = "or1200";
3614 #elif defined(TARGET_PPC)
3615 #ifdef TARGET_PPC64
3616 cpu_model = "970fx";
3617 #else
3618 cpu_model = "750";
3619 #endif
3620 #else
3621 cpu_model = "any";
3622 #endif
3623 }
3624 tcg_exec_init(0);
3625 cpu_exec_init_all();
3626 /* NOTE: we need to init the CPU at this stage to get
3627 qemu_host_page_size */
3628 env = cpu_init(cpu_model);
3629 if (!env) {
3630 fprintf(stderr, "Unable to find CPU definition\n");
3631 exit(1);
3632 }
3633 #if defined(TARGET_SPARC) || defined(TARGET_PPC)
3634 cpu_reset(ENV_GET_CPU(env));
3635 #endif
3636
3637 thread_env = env;
3638
3639 if (getenv("QEMU_STRACE")) {
3640 do_strace = 1;
3641 }
3642
3643 target_environ = envlist_to_environ(envlist, NULL);
3644 envlist_free(envlist);
3645
3646 #if defined(CONFIG_USE_GUEST_BASE)
3647 /*
3648 * Now that page sizes are configured in cpu_init() we can do
3649 * proper page alignment for guest_base.
3650 */
3651 guest_base = HOST_PAGE_ALIGN(guest_base);
3652
3653 if (reserved_va || have_guest_base) {
3654 guest_base = init_guest_space(guest_base, reserved_va, 0,
3655 have_guest_base);
3656 if (guest_base == (unsigned long)-1) {
3657 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3658 "space for use as guest address space (check your virtual "
3659 "memory ulimit setting or reserve less using -R option)\n",
3660 reserved_va);
3661 exit(1);
3662 }
3663
3664 if (reserved_va) {
3665 mmap_next_start = reserved_va;
3666 }
3667 }
3668 #endif /* CONFIG_USE_GUEST_BASE */
3669
3670 /*
3671 * Read in mmap_min_addr kernel parameter. This value is used
3672 * When loading the ELF image to determine whether guest_base
3673 * is needed. It is also used in mmap_find_vma.
3674 */
3675 {
3676 FILE *fp;
3677
3678 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3679 unsigned long tmp;
3680 if (fscanf(fp, "%lu", &tmp) == 1) {
3681 mmap_min_addr = tmp;
3682 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3683 }
3684 fclose(fp);
3685 }
3686 }
3687
3688 /*
3689 * Prepare copy of argv vector for target.
3690 */
3691 target_argc = argc - optind;
3692 target_argv = calloc(target_argc + 1, sizeof (char *));
3693 if (target_argv == NULL) {
3694 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3695 exit(1);
3696 }
3697
3698 /*
3699 * If argv0 is specified (using '-0' switch) we replace
3700 * argv[0] pointer with the given one.
3701 */
3702 i = 0;
3703 if (argv0 != NULL) {
3704 target_argv[i++] = strdup(argv0);
3705 }
3706 for (; i < target_argc; i++) {
3707 target_argv[i] = strdup(argv[optind + i]);
3708 }
3709 target_argv[target_argc] = NULL;
3710
3711 ts = g_malloc0 (sizeof(TaskState));
3712 init_task_state(ts);
3713 /* build Task State */
3714 ts->info = info;
3715 ts->bprm = &bprm;
3716 env->opaque = ts;
3717 task_settid(ts);
3718
3719 ret = loader_exec(filename, target_argv, target_environ, regs,
3720 info, &bprm);
3721 if (ret != 0) {
3722 printf("Error while loading %s: %s\n", filename, strerror(-ret));
3723 _exit(1);
3724 }
3725
3726 for (wrk = target_environ; *wrk; wrk++) {
3727 free(*wrk);
3728 }
3729
3730 free(target_environ);
3731
3732 if (qemu_log_enabled()) {
3733 #if defined(CONFIG_USE_GUEST_BASE)
3734 qemu_log("guest_base 0x%lx\n", guest_base);
3735 #endif
3736 log_page_dump();
3737
3738 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3739 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3740 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3741 info->start_code);
3742 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3743 info->start_data);
3744 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3745 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3746 info->start_stack);
3747 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3748 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3749 }
3750
3751 target_set_brk(info->brk);
3752 syscall_init();
3753 signal_init();
3754
3755 #if defined(CONFIG_USE_GUEST_BASE)
3756 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3757 generating the prologue until now so that the prologue can take
3758 the real value of GUEST_BASE into account. */
3759 tcg_prologue_init(&tcg_ctx);
3760 #endif
3761
3762 #if defined(TARGET_I386)
3763 cpu_x86_set_cpl(env, 3);
3764
3765 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
3766 env->hflags |= HF_PE_MASK;
3767 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
3768 env->cr[4] |= CR4_OSFXSR_MASK;
3769 env->hflags |= HF_OSFXSR_MASK;
3770 }
3771 #ifndef TARGET_ABI32
3772 /* enable 64 bit mode if possible */
3773 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
3774 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3775 exit(1);
3776 }
3777 env->cr[4] |= CR4_PAE_MASK;
3778 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
3779 env->hflags |= HF_LMA_MASK;
3780 #endif
3781
3782 /* flags setup : we activate the IRQs by default as in user mode */
3783 env->eflags |= IF_MASK;
3784
3785 /* linux register setup */
3786 #ifndef TARGET_ABI32
3787 env->regs[R_EAX] = regs->rax;
3788 env->regs[R_EBX] = regs->rbx;
3789 env->regs[R_ECX] = regs->rcx;
3790 env->regs[R_EDX] = regs->rdx;
3791 env->regs[R_ESI] = regs->rsi;
3792 env->regs[R_EDI] = regs->rdi;
3793 env->regs[R_EBP] = regs->rbp;
3794 env->regs[R_ESP] = regs->rsp;
3795 env->eip = regs->rip;
3796 #else
3797 env->regs[R_EAX] = regs->eax;
3798 env->regs[R_EBX] = regs->ebx;
3799 env->regs[R_ECX] = regs->ecx;
3800 env->regs[R_EDX] = regs->edx;
3801 env->regs[R_ESI] = regs->esi;
3802 env->regs[R_EDI] = regs->edi;
3803 env->regs[R_EBP] = regs->ebp;
3804 env->regs[R_ESP] = regs->esp;
3805 env->eip = regs->eip;
3806 #endif
3807
3808 /* linux interrupt setup */
3809 #ifndef TARGET_ABI32
3810 env->idt.limit = 511;
3811 #else
3812 env->idt.limit = 255;
3813 #endif
3814 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3815 PROT_READ|PROT_WRITE,
3816 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3817 idt_table = g2h(env->idt.base);
3818 set_idt(0, 0);
3819 set_idt(1, 0);
3820 set_idt(2, 0);
3821 set_idt(3, 3);
3822 set_idt(4, 3);
3823 set_idt(5, 0);
3824 set_idt(6, 0);
3825 set_idt(7, 0);
3826 set_idt(8, 0);
3827 set_idt(9, 0);
3828 set_idt(10, 0);
3829 set_idt(11, 0);
3830 set_idt(12, 0);
3831 set_idt(13, 0);
3832 set_idt(14, 0);
3833 set_idt(15, 0);
3834 set_idt(16, 0);
3835 set_idt(17, 0);
3836 set_idt(18, 0);
3837 set_idt(19, 0);
3838 set_idt(0x80, 3);
3839
3840 /* linux segment setup */
3841 {
3842 uint64_t *gdt_table;
3843 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3844 PROT_READ|PROT_WRITE,
3845 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3846 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
3847 gdt_table = g2h(env->gdt.base);
3848 #ifdef TARGET_ABI32
3849 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3850 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3851 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3852 #else
3853 /* 64 bit code segment */
3854 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3855 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3856 DESC_L_MASK |
3857 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3858 #endif
3859 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3860 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3861 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3862 }
3863 cpu_x86_load_seg(env, R_CS, __USER_CS);
3864 cpu_x86_load_seg(env, R_SS, __USER_DS);
3865 #ifdef TARGET_ABI32
3866 cpu_x86_load_seg(env, R_DS, __USER_DS);
3867 cpu_x86_load_seg(env, R_ES, __USER_DS);
3868 cpu_x86_load_seg(env, R_FS, __USER_DS);
3869 cpu_x86_load_seg(env, R_GS, __USER_DS);
3870 /* This hack makes Wine work... */
3871 env->segs[R_FS].selector = 0;
3872 #else
3873 cpu_x86_load_seg(env, R_DS, 0);
3874 cpu_x86_load_seg(env, R_ES, 0);
3875 cpu_x86_load_seg(env, R_FS, 0);
3876 cpu_x86_load_seg(env, R_GS, 0);
3877 #endif
3878 #elif defined(TARGET_ARM)
3879 {
3880 int i;
3881 cpsr_write(env, regs->uregs[16], 0xffffffff);
3882 for(i = 0; i < 16; i++) {
3883 env->regs[i] = regs->uregs[i];
3884 }
3885 /* Enable BE8. */
3886 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3887 && (info->elf_flags & EF_ARM_BE8)) {
3888 env->bswap_code = 1;
3889 }
3890 }
3891 #elif defined(TARGET_UNICORE32)
3892 {
3893 int i;
3894 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3895 for (i = 0; i < 32; i++) {
3896 env->regs[i] = regs->uregs[i];
3897 }
3898 }
3899 #elif defined(TARGET_SPARC)
3900 {
3901 int i;
3902 env->pc = regs->pc;
3903 env->npc = regs->npc;
3904 env->y = regs->y;
3905 for(i = 0; i < 8; i++)
3906 env->gregs[i] = regs->u_regs[i];
3907 for(i = 0; i < 8; i++)
3908 env->regwptr[i] = regs->u_regs[i + 8];
3909 }
3910 #elif defined(TARGET_PPC)
3911 {
3912 int i;
3913
3914 #if defined(TARGET_PPC64)
3915 #if defined(TARGET_ABI32)
3916 env->msr &= ~((target_ulong)1 << MSR_SF);
3917 #else
3918 env->msr |= (target_ulong)1 << MSR_SF;
3919 #endif
3920 #endif
3921 env->nip = regs->nip;
3922 for(i = 0; i < 32; i++) {
3923 env->gpr[i] = regs->gpr[i];
3924 }
3925 }
3926 #elif defined(TARGET_M68K)
3927 {
3928 env->pc = regs->pc;
3929 env->dregs[0] = regs->d0;
3930 env->dregs[1] = regs->d1;
3931 env->dregs[2] = regs->d2;
3932 env->dregs[3] = regs->d3;
3933 env->dregs[4] = regs->d4;
3934 env->dregs[5] = regs->d5;
3935 env->dregs[6] = regs->d6;
3936 env->dregs[7] = regs->d7;
3937 env->aregs[0] = regs->a0;
3938 env->aregs[1] = regs->a1;
3939 env->aregs[2] = regs->a2;
3940 env->aregs[3] = regs->a3;
3941 env->aregs[4] = regs->a4;
3942 env->aregs[5] = regs->a5;
3943 env->aregs[6] = regs->a6;
3944 env->aregs[7] = regs->usp;
3945 env->sr = regs->sr;
3946 ts->sim_syscalls = 1;
3947 }
3948 #elif defined(TARGET_MICROBLAZE)
3949 {
3950 env->regs[0] = regs->r0;
3951 env->regs[1] = regs->r1;
3952 env->regs[2] = regs->r2;
3953 env->regs[3] = regs->r3;
3954 env->regs[4] = regs->r4;
3955 env->regs[5] = regs->r5;
3956 env->regs[6] = regs->r6;
3957 env->regs[7] = regs->r7;
3958 env->regs[8] = regs->r8;
3959 env->regs[9] = regs->r9;
3960 env->regs[10] = regs->r10;
3961 env->regs[11] = regs->r11;
3962 env->regs[12] = regs->r12;
3963 env->regs[13] = regs->r13;
3964 env->regs[14] = regs->r14;
3965 env->regs[15] = regs->r15;
3966 env->regs[16] = regs->r16;
3967 env->regs[17] = regs->r17;
3968 env->regs[18] = regs->r18;
3969 env->regs[19] = regs->r19;
3970 env->regs[20] = regs->r20;
3971 env->regs[21] = regs->r21;
3972 env->regs[22] = regs->r22;
3973 env->regs[23] = regs->r23;
3974 env->regs[24] = regs->r24;
3975 env->regs[25] = regs->r25;
3976 env->regs[26] = regs->r26;
3977 env->regs[27] = regs->r27;
3978 env->regs[28] = regs->r28;
3979 env->regs[29] = regs->r29;
3980 env->regs[30] = regs->r30;
3981 env->regs[31] = regs->r31;
3982 env->sregs[SR_PC] = regs->pc;
3983 }
3984 #elif defined(TARGET_MIPS)
3985 {
3986 int i;
3987
3988 for(i = 0; i < 32; i++) {
3989 env->active_tc.gpr[i] = regs->regs[i];
3990 }
3991 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3992 if (regs->cp0_epc & 1) {
3993 env->hflags |= MIPS_HFLAG_M16;
3994 }
3995 }
3996 #elif defined(TARGET_OPENRISC)
3997 {
3998 int i;
3999
4000 for (i = 0; i < 32; i++) {
4001 env->gpr[i] = regs->gpr[i];
4002 }
4003
4004 env->sr = regs->sr;
4005 env->pc = regs->pc;
4006 }
4007 #elif defined(TARGET_SH4)
4008 {
4009 int i;
4010
4011 for(i = 0; i < 16; i++) {
4012 env->gregs[i] = regs->regs[i];
4013 }
4014 env->pc = regs->pc;
4015 }
4016 #elif defined(TARGET_ALPHA)
4017 {
4018 int i;
4019
4020 for(i = 0; i < 28; i++) {
4021 env->ir[i] = ((abi_ulong *)regs)[i];
4022 }
4023 env->ir[IR_SP] = regs->usp;
4024 env->pc = regs->pc;
4025 }
4026 #elif defined(TARGET_CRIS)
4027 {
4028 env->regs[0] = regs->r0;
4029 env->regs[1] = regs->r1;
4030 env->regs[2] = regs->r2;
4031 env->regs[3] = regs->r3;
4032 env->regs[4] = regs->r4;
4033 env->regs[5] = regs->r5;
4034 env->regs[6] = regs->r6;
4035 env->regs[7] = regs->r7;
4036 env->regs[8] = regs->r8;
4037 env->regs[9] = regs->r9;
4038 env->regs[10] = regs->r10;
4039 env->regs[11] = regs->r11;
4040 env->regs[12] = regs->r12;
4041 env->regs[13] = regs->r13;
4042 env->regs[14] = info->start_stack;
4043 env->regs[15] = regs->acr;
4044 env->pc = regs->erp;
4045 }
4046 #elif defined(TARGET_S390X)
4047 {
4048 int i;
4049 for (i = 0; i < 16; i++) {
4050 env->regs[i] = regs->gprs[i];
4051 }
4052 env->psw.mask = regs->psw.mask;
4053 env->psw.addr = regs->psw.addr;
4054 }
4055 #else
4056 #error unsupported target CPU
4057 #endif
4058
4059 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4060 ts->stack_base = info->start_stack;
4061 ts->heap_base = info->brk;
4062 /* This will be filled in on the first SYS_HEAPINFO call. */
4063 ts->heap_limit = 0;
4064 #endif
4065
4066 if (gdbstub_port) {
4067 if (gdbserver_start(gdbstub_port) < 0) {
4068 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4069 gdbstub_port);
4070 exit(1);
4071 }
4072 gdb_handlesig(env, 0);
4073 }
4074 cpu_loop(env);
4075 /* never exits */
4076 return 0;
4077 }
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