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1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36 #include "exec/log.h"
37 #include "trace/control.h"
38 #include "glib-compat.h"
39
40 char *exec_path;
41
42 int singlestep;
43 static const char *filename;
44 static const char *argv0;
45 static int gdbstub_port;
46 static envlist_t *envlist;
47 static const char *cpu_model;
48 unsigned long mmap_min_addr;
49 unsigned long guest_base;
50 int have_guest_base;
51
52 #define EXCP_DUMP(env, fmt, ...) \
53 do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61 } while (0)
62
63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64 /*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
71 # ifdef TARGET_MIPS
72 /* MIPS only supports 31 bits of virtual address space for user space */
73 unsigned long reserved_va = 0x77000000;
74 # else
75 unsigned long reserved_va = 0xf7000000;
76 # endif
77 #else
78 unsigned long reserved_va;
79 #endif
80
81 static void usage(int exitcode);
82
83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
84 const char *qemu_uname_release;
85
86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
89 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
90
91 void gemu_log(const char *fmt, ...)
92 {
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98 }
99
100 #if defined(TARGET_I386)
101 int cpu_get_pic_interrupt(CPUX86State *env)
102 {
103 return -1;
104 }
105 #endif
106
107 /***********************************************************/
108 /* Helper routines for implementing atomic operations. */
109
110 /* Make sure everything is in a consistent state for calling fork(). */
111 void fork_start(void)
112 {
113 cpu_list_lock();
114 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
115 mmap_fork_start();
116 }
117
118 void fork_end(int child)
119 {
120 mmap_fork_end(child);
121 if (child) {
122 CPUState *cpu, *next_cpu;
123 /* Child processes created by fork() only have a single thread.
124 Discard information about the parent threads. */
125 CPU_FOREACH_SAFE(cpu, next_cpu) {
126 if (cpu != thread_cpu) {
127 QTAILQ_REMOVE(&cpus, cpu, node);
128 }
129 }
130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
131 qemu_init_cpu_list();
132 gdbserver_fork(thread_cpu);
133 } else {
134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
135 cpu_list_unlock();
136 }
137 }
138
139 #ifdef TARGET_I386
140 /***********************************************************/
141 /* CPUX86 core interface */
142
143 uint64_t cpu_get_tsc(CPUX86State *env)
144 {
145 return cpu_get_host_ticks();
146 }
147
148 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
149 int flags)
150 {
151 unsigned int e1, e2;
152 uint32_t *p;
153 e1 = (addr << 16) | (limit & 0xffff);
154 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
155 e2 |= flags;
156 p = ptr;
157 p[0] = tswap32(e1);
158 p[1] = tswap32(e2);
159 }
160
161 static uint64_t *idt_table;
162 #ifdef TARGET_X86_64
163 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
164 uint64_t addr, unsigned int sel)
165 {
166 uint32_t *p, e1, e2;
167 e1 = (addr & 0xffff) | (sel << 16);
168 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
169 p = ptr;
170 p[0] = tswap32(e1);
171 p[1] = tswap32(e2);
172 p[2] = tswap32(addr >> 32);
173 p[3] = 0;
174 }
175 /* only dpl matters as we do only user space emulation */
176 static void set_idt(int n, unsigned int dpl)
177 {
178 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
179 }
180 #else
181 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
182 uint32_t addr, unsigned int sel)
183 {
184 uint32_t *p, e1, e2;
185 e1 = (addr & 0xffff) | (sel << 16);
186 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
187 p = ptr;
188 p[0] = tswap32(e1);
189 p[1] = tswap32(e2);
190 }
191
192 /* only dpl matters as we do only user space emulation */
193 static void set_idt(int n, unsigned int dpl)
194 {
195 set_gate(idt_table + n, 0, dpl, 0, 0);
196 }
197 #endif
198
199 void cpu_loop(CPUX86State *env)
200 {
201 CPUState *cs = CPU(x86_env_get_cpu(env));
202 int trapnr;
203 abi_ulong pc;
204 abi_ulong ret;
205 target_siginfo_t info;
206
207 for(;;) {
208 cpu_exec_start(cs);
209 trapnr = cpu_exec(cs);
210 cpu_exec_end(cs);
211 process_queued_cpu_work(cs);
212
213 switch(trapnr) {
214 case 0x80:
215 /* linux syscall from int $0x80 */
216 ret = do_syscall(env,
217 env->regs[R_EAX],
218 env->regs[R_EBX],
219 env->regs[R_ECX],
220 env->regs[R_EDX],
221 env->regs[R_ESI],
222 env->regs[R_EDI],
223 env->regs[R_EBP],
224 0, 0);
225 if (ret == -TARGET_ERESTARTSYS) {
226 env->eip -= 2;
227 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
228 env->regs[R_EAX] = ret;
229 }
230 break;
231 #ifndef TARGET_ABI32
232 case EXCP_SYSCALL:
233 /* linux syscall from syscall instruction */
234 ret = do_syscall(env,
235 env->regs[R_EAX],
236 env->regs[R_EDI],
237 env->regs[R_ESI],
238 env->regs[R_EDX],
239 env->regs[10],
240 env->regs[8],
241 env->regs[9],
242 0, 0);
243 if (ret == -TARGET_ERESTARTSYS) {
244 env->eip -= 2;
245 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
246 env->regs[R_EAX] = ret;
247 }
248 break;
249 #endif
250 case EXCP0B_NOSEG:
251 case EXCP0C_STACK:
252 info.si_signo = TARGET_SIGBUS;
253 info.si_errno = 0;
254 info.si_code = TARGET_SI_KERNEL;
255 info._sifields._sigfault._addr = 0;
256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
257 break;
258 case EXCP0D_GPF:
259 /* XXX: potential problem if ABI32 */
260 #ifndef TARGET_X86_64
261 if (env->eflags & VM_MASK) {
262 handle_vm86_fault(env);
263 } else
264 #endif
265 {
266 info.si_signo = TARGET_SIGSEGV;
267 info.si_errno = 0;
268 info.si_code = TARGET_SI_KERNEL;
269 info._sifields._sigfault._addr = 0;
270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
271 }
272 break;
273 case EXCP0E_PAGE:
274 info.si_signo = TARGET_SIGSEGV;
275 info.si_errno = 0;
276 if (!(env->error_code & 1))
277 info.si_code = TARGET_SEGV_MAPERR;
278 else
279 info.si_code = TARGET_SEGV_ACCERR;
280 info._sifields._sigfault._addr = env->cr[2];
281 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
282 break;
283 case EXCP00_DIVZ:
284 #ifndef TARGET_X86_64
285 if (env->eflags & VM_MASK) {
286 handle_vm86_trap(env, trapnr);
287 } else
288 #endif
289 {
290 /* division by zero */
291 info.si_signo = TARGET_SIGFPE;
292 info.si_errno = 0;
293 info.si_code = TARGET_FPE_INTDIV;
294 info._sifields._sigfault._addr = env->eip;
295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
296 }
297 break;
298 case EXCP01_DB:
299 case EXCP03_INT3:
300 #ifndef TARGET_X86_64
301 if (env->eflags & VM_MASK) {
302 handle_vm86_trap(env, trapnr);
303 } else
304 #endif
305 {
306 info.si_signo = TARGET_SIGTRAP;
307 info.si_errno = 0;
308 if (trapnr == EXCP01_DB) {
309 info.si_code = TARGET_TRAP_BRKPT;
310 info._sifields._sigfault._addr = env->eip;
311 } else {
312 info.si_code = TARGET_SI_KERNEL;
313 info._sifields._sigfault._addr = 0;
314 }
315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
316 }
317 break;
318 case EXCP04_INTO:
319 case EXCP05_BOUND:
320 #ifndef TARGET_X86_64
321 if (env->eflags & VM_MASK) {
322 handle_vm86_trap(env, trapnr);
323 } else
324 #endif
325 {
326 info.si_signo = TARGET_SIGSEGV;
327 info.si_errno = 0;
328 info.si_code = TARGET_SI_KERNEL;
329 info._sifields._sigfault._addr = 0;
330 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
331 }
332 break;
333 case EXCP06_ILLOP:
334 info.si_signo = TARGET_SIGILL;
335 info.si_errno = 0;
336 info.si_code = TARGET_ILL_ILLOPN;
337 info._sifields._sigfault._addr = env->eip;
338 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
339 break;
340 case EXCP_INTERRUPT:
341 /* just indicate that signals should be handled asap */
342 break;
343 case EXCP_DEBUG:
344 {
345 int sig;
346
347 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
348 if (sig)
349 {
350 info.si_signo = sig;
351 info.si_errno = 0;
352 info.si_code = TARGET_TRAP_BRKPT;
353 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
354 }
355 }
356 break;
357 case EXCP_ATOMIC:
358 cpu_exec_step_atomic(cs);
359 break;
360 default:
361 pc = env->segs[R_CS].base + env->eip;
362 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
363 (long)pc, trapnr);
364 abort();
365 }
366 process_pending_signals(env);
367 }
368 }
369 #endif
370
371 #ifdef TARGET_ARM
372
373 #define get_user_code_u32(x, gaddr, env) \
374 ({ abi_long __r = get_user_u32((x), (gaddr)); \
375 if (!__r && bswap_code(arm_sctlr_b(env))) { \
376 (x) = bswap32(x); \
377 } \
378 __r; \
379 })
380
381 #define get_user_code_u16(x, gaddr, env) \
382 ({ abi_long __r = get_user_u16((x), (gaddr)); \
383 if (!__r && bswap_code(arm_sctlr_b(env))) { \
384 (x) = bswap16(x); \
385 } \
386 __r; \
387 })
388
389 #define get_user_data_u32(x, gaddr, env) \
390 ({ abi_long __r = get_user_u32((x), (gaddr)); \
391 if (!__r && arm_cpu_bswap_data(env)) { \
392 (x) = bswap32(x); \
393 } \
394 __r; \
395 })
396
397 #define get_user_data_u16(x, gaddr, env) \
398 ({ abi_long __r = get_user_u16((x), (gaddr)); \
399 if (!__r && arm_cpu_bswap_data(env)) { \
400 (x) = bswap16(x); \
401 } \
402 __r; \
403 })
404
405 #define put_user_data_u32(x, gaddr, env) \
406 ({ typeof(x) __x = (x); \
407 if (arm_cpu_bswap_data(env)) { \
408 __x = bswap32(__x); \
409 } \
410 put_user_u32(__x, (gaddr)); \
411 })
412
413 #define put_user_data_u16(x, gaddr, env) \
414 ({ typeof(x) __x = (x); \
415 if (arm_cpu_bswap_data(env)) { \
416 __x = bswap16(__x); \
417 } \
418 put_user_u16(__x, (gaddr)); \
419 })
420
421 #ifdef TARGET_ABI32
422 /* Commpage handling -- there is no commpage for AArch64 */
423
424 /*
425 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
426 * Input:
427 * r0 = pointer to oldval
428 * r1 = pointer to newval
429 * r2 = pointer to target value
430 *
431 * Output:
432 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
433 * C set if *ptr was changed, clear if no exchange happened
434 *
435 * Note segv's in kernel helpers are a bit tricky, we can set the
436 * data address sensibly but the PC address is just the entry point.
437 */
438 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
439 {
440 uint64_t oldval, newval, val;
441 uint32_t addr, cpsr;
442 target_siginfo_t info;
443
444 /* Based on the 32 bit code in do_kernel_trap */
445
446 /* XXX: This only works between threads, not between processes.
447 It's probably possible to implement this with native host
448 operations. However things like ldrex/strex are much harder so
449 there's not much point trying. */
450 start_exclusive();
451 cpsr = cpsr_read(env);
452 addr = env->regs[2];
453
454 if (get_user_u64(oldval, env->regs[0])) {
455 env->exception.vaddress = env->regs[0];
456 goto segv;
457 };
458
459 if (get_user_u64(newval, env->regs[1])) {
460 env->exception.vaddress = env->regs[1];
461 goto segv;
462 };
463
464 if (get_user_u64(val, addr)) {
465 env->exception.vaddress = addr;
466 goto segv;
467 }
468
469 if (val == oldval) {
470 val = newval;
471
472 if (put_user_u64(val, addr)) {
473 env->exception.vaddress = addr;
474 goto segv;
475 };
476
477 env->regs[0] = 0;
478 cpsr |= CPSR_C;
479 } else {
480 env->regs[0] = -1;
481 cpsr &= ~CPSR_C;
482 }
483 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
484 end_exclusive();
485 return;
486
487 segv:
488 end_exclusive();
489 /* We get the PC of the entry address - which is as good as anything,
490 on a real kernel what you get depends on which mode it uses. */
491 info.si_signo = TARGET_SIGSEGV;
492 info.si_errno = 0;
493 /* XXX: check env->error_code */
494 info.si_code = TARGET_SEGV_MAPERR;
495 info._sifields._sigfault._addr = env->exception.vaddress;
496 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
497 }
498
499 /* Handle a jump to the kernel code page. */
500 static int
501 do_kernel_trap(CPUARMState *env)
502 {
503 uint32_t addr;
504 uint32_t cpsr;
505 uint32_t val;
506
507 switch (env->regs[15]) {
508 case 0xffff0fa0: /* __kernel_memory_barrier */
509 /* ??? No-op. Will need to do better for SMP. */
510 break;
511 case 0xffff0fc0: /* __kernel_cmpxchg */
512 /* XXX: This only works between threads, not between processes.
513 It's probably possible to implement this with native host
514 operations. However things like ldrex/strex are much harder so
515 there's not much point trying. */
516 start_exclusive();
517 cpsr = cpsr_read(env);
518 addr = env->regs[2];
519 /* FIXME: This should SEGV if the access fails. */
520 if (get_user_u32(val, addr))
521 val = ~env->regs[0];
522 if (val == env->regs[0]) {
523 val = env->regs[1];
524 /* FIXME: Check for segfaults. */
525 put_user_u32(val, addr);
526 env->regs[0] = 0;
527 cpsr |= CPSR_C;
528 } else {
529 env->regs[0] = -1;
530 cpsr &= ~CPSR_C;
531 }
532 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
533 end_exclusive();
534 break;
535 case 0xffff0fe0: /* __kernel_get_tls */
536 env->regs[0] = cpu_get_tls(env);
537 break;
538 case 0xffff0f60: /* __kernel_cmpxchg64 */
539 arm_kernel_cmpxchg64_helper(env);
540 break;
541
542 default:
543 return 1;
544 }
545 /* Jump back to the caller. */
546 addr = env->regs[14];
547 if (addr & 1) {
548 env->thumb = 1;
549 addr &= ~1;
550 }
551 env->regs[15] = addr;
552
553 return 0;
554 }
555
556 void cpu_loop(CPUARMState *env)
557 {
558 CPUState *cs = CPU(arm_env_get_cpu(env));
559 int trapnr;
560 unsigned int n, insn;
561 target_siginfo_t info;
562 uint32_t addr;
563 abi_ulong ret;
564
565 for(;;) {
566 cpu_exec_start(cs);
567 trapnr = cpu_exec(cs);
568 cpu_exec_end(cs);
569 process_queued_cpu_work(cs);
570
571 switch(trapnr) {
572 case EXCP_UDEF:
573 {
574 TaskState *ts = cs->opaque;
575 uint32_t opcode;
576 int rc;
577
578 /* we handle the FPU emulation here, as Linux */
579 /* we get the opcode */
580 /* FIXME - what to do if get_user() fails? */
581 get_user_code_u32(opcode, env->regs[15], env);
582
583 rc = EmulateAll(opcode, &ts->fpa, env);
584 if (rc == 0) { /* illegal instruction */
585 info.si_signo = TARGET_SIGILL;
586 info.si_errno = 0;
587 info.si_code = TARGET_ILL_ILLOPN;
588 info._sifields._sigfault._addr = env->regs[15];
589 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
590 } else if (rc < 0) { /* FP exception */
591 int arm_fpe=0;
592
593 /* translate softfloat flags to FPSR flags */
594 if (-rc & float_flag_invalid)
595 arm_fpe |= BIT_IOC;
596 if (-rc & float_flag_divbyzero)
597 arm_fpe |= BIT_DZC;
598 if (-rc & float_flag_overflow)
599 arm_fpe |= BIT_OFC;
600 if (-rc & float_flag_underflow)
601 arm_fpe |= BIT_UFC;
602 if (-rc & float_flag_inexact)
603 arm_fpe |= BIT_IXC;
604
605 FPSR fpsr = ts->fpa.fpsr;
606 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
607
608 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
609 info.si_signo = TARGET_SIGFPE;
610 info.si_errno = 0;
611
612 /* ordered by priority, least first */
613 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
614 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
615 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
616 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
617 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
618
619 info._sifields._sigfault._addr = env->regs[15];
620 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
621 } else {
622 env->regs[15] += 4;
623 }
624
625 /* accumulate unenabled exceptions */
626 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
627 fpsr |= BIT_IXC;
628 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
629 fpsr |= BIT_UFC;
630 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
631 fpsr |= BIT_OFC;
632 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
633 fpsr |= BIT_DZC;
634 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
635 fpsr |= BIT_IOC;
636 ts->fpa.fpsr=fpsr;
637 } else { /* everything OK */
638 /* increment PC */
639 env->regs[15] += 4;
640 }
641 }
642 break;
643 case EXCP_SWI:
644 case EXCP_BKPT:
645 {
646 env->eabi = 1;
647 /* system call */
648 if (trapnr == EXCP_BKPT) {
649 if (env->thumb) {
650 /* FIXME - what to do if get_user() fails? */
651 get_user_code_u16(insn, env->regs[15], env);
652 n = insn & 0xff;
653 env->regs[15] += 2;
654 } else {
655 /* FIXME - what to do if get_user() fails? */
656 get_user_code_u32(insn, env->regs[15], env);
657 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
658 env->regs[15] += 4;
659 }
660 } else {
661 if (env->thumb) {
662 /* FIXME - what to do if get_user() fails? */
663 get_user_code_u16(insn, env->regs[15] - 2, env);
664 n = insn & 0xff;
665 } else {
666 /* FIXME - what to do if get_user() fails? */
667 get_user_code_u32(insn, env->regs[15] - 4, env);
668 n = insn & 0xffffff;
669 }
670 }
671
672 if (n == ARM_NR_cacheflush) {
673 /* nop */
674 } else if (n == ARM_NR_semihosting
675 || n == ARM_NR_thumb_semihosting) {
676 env->regs[0] = do_arm_semihosting (env);
677 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
678 /* linux syscall */
679 if (env->thumb || n == 0) {
680 n = env->regs[7];
681 } else {
682 n -= ARM_SYSCALL_BASE;
683 env->eabi = 0;
684 }
685 if ( n > ARM_NR_BASE) {
686 switch (n) {
687 case ARM_NR_cacheflush:
688 /* nop */
689 break;
690 case ARM_NR_set_tls:
691 cpu_set_tls(env, env->regs[0]);
692 env->regs[0] = 0;
693 break;
694 case ARM_NR_breakpoint:
695 env->regs[15] -= env->thumb ? 2 : 4;
696 goto excp_debug;
697 default:
698 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
699 n);
700 env->regs[0] = -TARGET_ENOSYS;
701 break;
702 }
703 } else {
704 ret = do_syscall(env,
705 n,
706 env->regs[0],
707 env->regs[1],
708 env->regs[2],
709 env->regs[3],
710 env->regs[4],
711 env->regs[5],
712 0, 0);
713 if (ret == -TARGET_ERESTARTSYS) {
714 env->regs[15] -= env->thumb ? 2 : 4;
715 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
716 env->regs[0] = ret;
717 }
718 }
719 } else {
720 goto error;
721 }
722 }
723 break;
724 case EXCP_SEMIHOST:
725 env->regs[0] = do_arm_semihosting(env);
726 break;
727 case EXCP_INTERRUPT:
728 /* just indicate that signals should be handled asap */
729 break;
730 case EXCP_PREFETCH_ABORT:
731 case EXCP_DATA_ABORT:
732 addr = env->exception.vaddress;
733 {
734 info.si_signo = TARGET_SIGSEGV;
735 info.si_errno = 0;
736 /* XXX: check env->error_code */
737 info.si_code = TARGET_SEGV_MAPERR;
738 info._sifields._sigfault._addr = addr;
739 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
740 }
741 break;
742 case EXCP_DEBUG:
743 excp_debug:
744 {
745 int sig;
746
747 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
748 if (sig)
749 {
750 info.si_signo = sig;
751 info.si_errno = 0;
752 info.si_code = TARGET_TRAP_BRKPT;
753 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
754 }
755 }
756 break;
757 case EXCP_KERNEL_TRAP:
758 if (do_kernel_trap(env))
759 goto error;
760 break;
761 case EXCP_YIELD:
762 /* nothing to do here for user-mode, just resume guest code */
763 break;
764 case EXCP_ATOMIC:
765 cpu_exec_step_atomic(cs);
766 break;
767 default:
768 error:
769 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
770 abort();
771 }
772 process_pending_signals(env);
773 }
774 }
775
776 #else
777
778 /*
779 * Handle AArch64 store-release exclusive
780 *
781 * rs = gets the status result of store exclusive
782 * rt = is the register that is stored
783 * rt2 = is the second register store (in STP)
784 *
785 */
786 static int do_strex_a64(CPUARMState *env)
787 {
788 uint64_t val;
789 int size;
790 bool is_pair;
791 int rc = 1;
792 int segv = 0;
793 uint64_t addr;
794 int rs, rt, rt2;
795
796 start_exclusive();
797 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
798 size = extract32(env->exclusive_info, 0, 2);
799 is_pair = extract32(env->exclusive_info, 2, 1);
800 rs = extract32(env->exclusive_info, 4, 5);
801 rt = extract32(env->exclusive_info, 9, 5);
802 rt2 = extract32(env->exclusive_info, 14, 5);
803
804 addr = env->exclusive_addr;
805
806 if (addr != env->exclusive_test) {
807 goto finish;
808 }
809
810 switch (size) {
811 case 0:
812 segv = get_user_u8(val, addr);
813 break;
814 case 1:
815 segv = get_user_u16(val, addr);
816 break;
817 case 2:
818 segv = get_user_u32(val, addr);
819 break;
820 case 3:
821 segv = get_user_u64(val, addr);
822 break;
823 default:
824 abort();
825 }
826 if (segv) {
827 env->exception.vaddress = addr;
828 goto error;
829 }
830 if (val != env->exclusive_val) {
831 goto finish;
832 }
833 if (is_pair) {
834 if (size == 2) {
835 segv = get_user_u32(val, addr + 4);
836 } else {
837 segv = get_user_u64(val, addr + 8);
838 }
839 if (segv) {
840 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
841 goto error;
842 }
843 if (val != env->exclusive_high) {
844 goto finish;
845 }
846 }
847 /* handle the zero register */
848 val = rt == 31 ? 0 : env->xregs[rt];
849 switch (size) {
850 case 0:
851 segv = put_user_u8(val, addr);
852 break;
853 case 1:
854 segv = put_user_u16(val, addr);
855 break;
856 case 2:
857 segv = put_user_u32(val, addr);
858 break;
859 case 3:
860 segv = put_user_u64(val, addr);
861 break;
862 }
863 if (segv) {
864 goto error;
865 }
866 if (is_pair) {
867 /* handle the zero register */
868 val = rt2 == 31 ? 0 : env->xregs[rt2];
869 if (size == 2) {
870 segv = put_user_u32(val, addr + 4);
871 } else {
872 segv = put_user_u64(val, addr + 8);
873 }
874 if (segv) {
875 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
876 goto error;
877 }
878 }
879 rc = 0;
880 finish:
881 env->pc += 4;
882 /* rs == 31 encodes a write to the ZR, thus throwing away
883 * the status return. This is rather silly but valid.
884 */
885 if (rs < 31) {
886 env->xregs[rs] = rc;
887 }
888 error:
889 /* instruction faulted, PC does not advance */
890 /* either way a strex releases any exclusive lock we have */
891 env->exclusive_addr = -1;
892 end_exclusive();
893 return segv;
894 }
895
896 /* AArch64 main loop */
897 void cpu_loop(CPUARMState *env)
898 {
899 CPUState *cs = CPU(arm_env_get_cpu(env));
900 int trapnr, sig;
901 abi_long ret;
902 target_siginfo_t info;
903
904 for (;;) {
905 cpu_exec_start(cs);
906 trapnr = cpu_exec(cs);
907 cpu_exec_end(cs);
908 process_queued_cpu_work(cs);
909
910 switch (trapnr) {
911 case EXCP_SWI:
912 ret = do_syscall(env,
913 env->xregs[8],
914 env->xregs[0],
915 env->xregs[1],
916 env->xregs[2],
917 env->xregs[3],
918 env->xregs[4],
919 env->xregs[5],
920 0, 0);
921 if (ret == -TARGET_ERESTARTSYS) {
922 env->pc -= 4;
923 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
924 env->xregs[0] = ret;
925 }
926 break;
927 case EXCP_INTERRUPT:
928 /* just indicate that signals should be handled asap */
929 break;
930 case EXCP_UDEF:
931 info.si_signo = TARGET_SIGILL;
932 info.si_errno = 0;
933 info.si_code = TARGET_ILL_ILLOPN;
934 info._sifields._sigfault._addr = env->pc;
935 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
936 break;
937 case EXCP_STREX:
938 if (!do_strex_a64(env)) {
939 break;
940 }
941 /* fall through for segv */
942 case EXCP_PREFETCH_ABORT:
943 case EXCP_DATA_ABORT:
944 info.si_signo = TARGET_SIGSEGV;
945 info.si_errno = 0;
946 /* XXX: check env->error_code */
947 info.si_code = TARGET_SEGV_MAPERR;
948 info._sifields._sigfault._addr = env->exception.vaddress;
949 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
950 break;
951 case EXCP_DEBUG:
952 case EXCP_BKPT:
953 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
954 if (sig) {
955 info.si_signo = sig;
956 info.si_errno = 0;
957 info.si_code = TARGET_TRAP_BRKPT;
958 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
959 }
960 break;
961 case EXCP_SEMIHOST:
962 env->xregs[0] = do_arm_semihosting(env);
963 break;
964 case EXCP_YIELD:
965 /* nothing to do here for user-mode, just resume guest code */
966 break;
967 case EXCP_ATOMIC:
968 cpu_exec_step_atomic(cs);
969 break;
970 default:
971 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
972 abort();
973 }
974 process_pending_signals(env);
975 /* Exception return on AArch64 always clears the exclusive monitor,
976 * so any return to running guest code implies this.
977 * A strex (successful or otherwise) also clears the monitor, so
978 * we don't need to specialcase EXCP_STREX.
979 */
980 env->exclusive_addr = -1;
981 }
982 }
983 #endif /* ndef TARGET_ABI32 */
984
985 #endif
986
987 #ifdef TARGET_UNICORE32
988
989 void cpu_loop(CPUUniCore32State *env)
990 {
991 CPUState *cs = CPU(uc32_env_get_cpu(env));
992 int trapnr;
993 unsigned int n, insn;
994 target_siginfo_t info;
995
996 for (;;) {
997 cpu_exec_start(cs);
998 trapnr = cpu_exec(cs);
999 cpu_exec_end(cs);
1000 process_queued_cpu_work(cs);
1001
1002 switch (trapnr) {
1003 case UC32_EXCP_PRIV:
1004 {
1005 /* system call */
1006 get_user_u32(insn, env->regs[31] - 4);
1007 n = insn & 0xffffff;
1008
1009 if (n >= UC32_SYSCALL_BASE) {
1010 /* linux syscall */
1011 n -= UC32_SYSCALL_BASE;
1012 if (n == UC32_SYSCALL_NR_set_tls) {
1013 cpu_set_tls(env, env->regs[0]);
1014 env->regs[0] = 0;
1015 } else {
1016 abi_long ret = do_syscall(env,
1017 n,
1018 env->regs[0],
1019 env->regs[1],
1020 env->regs[2],
1021 env->regs[3],
1022 env->regs[4],
1023 env->regs[5],
1024 0, 0);
1025 if (ret == -TARGET_ERESTARTSYS) {
1026 env->regs[31] -= 4;
1027 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1028 env->regs[0] = ret;
1029 }
1030 }
1031 } else {
1032 goto error;
1033 }
1034 }
1035 break;
1036 case UC32_EXCP_DTRAP:
1037 case UC32_EXCP_ITRAP:
1038 info.si_signo = TARGET_SIGSEGV;
1039 info.si_errno = 0;
1040 /* XXX: check env->error_code */
1041 info.si_code = TARGET_SEGV_MAPERR;
1042 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1043 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1044 break;
1045 case EXCP_INTERRUPT:
1046 /* just indicate that signals should be handled asap */
1047 break;
1048 case EXCP_DEBUG:
1049 {
1050 int sig;
1051
1052 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1053 if (sig) {
1054 info.si_signo = sig;
1055 info.si_errno = 0;
1056 info.si_code = TARGET_TRAP_BRKPT;
1057 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1058 }
1059 }
1060 break;
1061 case EXCP_ATOMIC:
1062 cpu_exec_step_atomic(cs);
1063 break;
1064 default:
1065 goto error;
1066 }
1067 process_pending_signals(env);
1068 }
1069
1070 error:
1071 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1072 abort();
1073 }
1074 #endif
1075
1076 #ifdef TARGET_SPARC
1077 #define SPARC64_STACK_BIAS 2047
1078
1079 //#define DEBUG_WIN
1080
1081 /* WARNING: dealing with register windows _is_ complicated. More info
1082 can be found at http://www.sics.se/~psm/sparcstack.html */
1083 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1084 {
1085 index = (index + cwp * 16) % (16 * env->nwindows);
1086 /* wrap handling : if cwp is on the last window, then we use the
1087 registers 'after' the end */
1088 if (index < 8 && env->cwp == env->nwindows - 1)
1089 index += 16 * env->nwindows;
1090 return index;
1091 }
1092
1093 /* save the register window 'cwp1' */
1094 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1095 {
1096 unsigned int i;
1097 abi_ulong sp_ptr;
1098
1099 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1100 #ifdef TARGET_SPARC64
1101 if (sp_ptr & 3)
1102 sp_ptr += SPARC64_STACK_BIAS;
1103 #endif
1104 #if defined(DEBUG_WIN)
1105 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1106 sp_ptr, cwp1);
1107 #endif
1108 for(i = 0; i < 16; i++) {
1109 /* FIXME - what to do if put_user() fails? */
1110 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1111 sp_ptr += sizeof(abi_ulong);
1112 }
1113 }
1114
1115 static void save_window(CPUSPARCState *env)
1116 {
1117 #ifndef TARGET_SPARC64
1118 unsigned int new_wim;
1119 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1120 ((1LL << env->nwindows) - 1);
1121 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1122 env->wim = new_wim;
1123 #else
1124 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1125 env->cansave++;
1126 env->canrestore--;
1127 #endif
1128 }
1129
1130 static void restore_window(CPUSPARCState *env)
1131 {
1132 #ifndef TARGET_SPARC64
1133 unsigned int new_wim;
1134 #endif
1135 unsigned int i, cwp1;
1136 abi_ulong sp_ptr;
1137
1138 #ifndef TARGET_SPARC64
1139 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1140 ((1LL << env->nwindows) - 1);
1141 #endif
1142
1143 /* restore the invalid window */
1144 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1145 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1146 #ifdef TARGET_SPARC64
1147 if (sp_ptr & 3)
1148 sp_ptr += SPARC64_STACK_BIAS;
1149 #endif
1150 #if defined(DEBUG_WIN)
1151 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1152 sp_ptr, cwp1);
1153 #endif
1154 for(i = 0; i < 16; i++) {
1155 /* FIXME - what to do if get_user() fails? */
1156 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1157 sp_ptr += sizeof(abi_ulong);
1158 }
1159 #ifdef TARGET_SPARC64
1160 env->canrestore++;
1161 if (env->cleanwin < env->nwindows - 1)
1162 env->cleanwin++;
1163 env->cansave--;
1164 #else
1165 env->wim = new_wim;
1166 #endif
1167 }
1168
1169 static void flush_windows(CPUSPARCState *env)
1170 {
1171 int offset, cwp1;
1172
1173 offset = 1;
1174 for(;;) {
1175 /* if restore would invoke restore_window(), then we can stop */
1176 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1177 #ifndef TARGET_SPARC64
1178 if (env->wim & (1 << cwp1))
1179 break;
1180 #else
1181 if (env->canrestore == 0)
1182 break;
1183 env->cansave++;
1184 env->canrestore--;
1185 #endif
1186 save_window_offset(env, cwp1);
1187 offset++;
1188 }
1189 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1190 #ifndef TARGET_SPARC64
1191 /* set wim so that restore will reload the registers */
1192 env->wim = 1 << cwp1;
1193 #endif
1194 #if defined(DEBUG_WIN)
1195 printf("flush_windows: nb=%d\n", offset - 1);
1196 #endif
1197 }
1198
1199 void cpu_loop (CPUSPARCState *env)
1200 {
1201 CPUState *cs = CPU(sparc_env_get_cpu(env));
1202 int trapnr;
1203 abi_long ret;
1204 target_siginfo_t info;
1205
1206 while (1) {
1207 cpu_exec_start(cs);
1208 trapnr = cpu_exec(cs);
1209 cpu_exec_end(cs);
1210 process_queued_cpu_work(cs);
1211
1212 /* Compute PSR before exposing state. */
1213 if (env->cc_op != CC_OP_FLAGS) {
1214 cpu_get_psr(env);
1215 }
1216
1217 switch (trapnr) {
1218 #ifndef TARGET_SPARC64
1219 case 0x88:
1220 case 0x90:
1221 #else
1222 case 0x110:
1223 case 0x16d:
1224 #endif
1225 ret = do_syscall (env, env->gregs[1],
1226 env->regwptr[0], env->regwptr[1],
1227 env->regwptr[2], env->regwptr[3],
1228 env->regwptr[4], env->regwptr[5],
1229 0, 0);
1230 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1231 break;
1232 }
1233 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1234 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1235 env->xcc |= PSR_CARRY;
1236 #else
1237 env->psr |= PSR_CARRY;
1238 #endif
1239 ret = -ret;
1240 } else {
1241 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1242 env->xcc &= ~PSR_CARRY;
1243 #else
1244 env->psr &= ~PSR_CARRY;
1245 #endif
1246 }
1247 env->regwptr[0] = ret;
1248 /* next instruction */
1249 env->pc = env->npc;
1250 env->npc = env->npc + 4;
1251 break;
1252 case 0x83: /* flush windows */
1253 #ifdef TARGET_ABI32
1254 case 0x103:
1255 #endif
1256 flush_windows(env);
1257 /* next instruction */
1258 env->pc = env->npc;
1259 env->npc = env->npc + 4;
1260 break;
1261 #ifndef TARGET_SPARC64
1262 case TT_WIN_OVF: /* window overflow */
1263 save_window(env);
1264 break;
1265 case TT_WIN_UNF: /* window underflow */
1266 restore_window(env);
1267 break;
1268 case TT_TFAULT:
1269 case TT_DFAULT:
1270 {
1271 info.si_signo = TARGET_SIGSEGV;
1272 info.si_errno = 0;
1273 /* XXX: check env->error_code */
1274 info.si_code = TARGET_SEGV_MAPERR;
1275 info._sifields._sigfault._addr = env->mmuregs[4];
1276 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1277 }
1278 break;
1279 #else
1280 case TT_SPILL: /* window overflow */
1281 save_window(env);
1282 break;
1283 case TT_FILL: /* window underflow */
1284 restore_window(env);
1285 break;
1286 case TT_TFAULT:
1287 case TT_DFAULT:
1288 {
1289 info.si_signo = TARGET_SIGSEGV;
1290 info.si_errno = 0;
1291 /* XXX: check env->error_code */
1292 info.si_code = TARGET_SEGV_MAPERR;
1293 if (trapnr == TT_DFAULT)
1294 info._sifields._sigfault._addr = env->dmmuregs[4];
1295 else
1296 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1297 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1298 }
1299 break;
1300 #ifndef TARGET_ABI32
1301 case 0x16e:
1302 flush_windows(env);
1303 sparc64_get_context(env);
1304 break;
1305 case 0x16f:
1306 flush_windows(env);
1307 sparc64_set_context(env);
1308 break;
1309 #endif
1310 #endif
1311 case EXCP_INTERRUPT:
1312 /* just indicate that signals should be handled asap */
1313 break;
1314 case TT_ILL_INSN:
1315 {
1316 info.si_signo = TARGET_SIGILL;
1317 info.si_errno = 0;
1318 info.si_code = TARGET_ILL_ILLOPC;
1319 info._sifields._sigfault._addr = env->pc;
1320 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1321 }
1322 break;
1323 case EXCP_DEBUG:
1324 {
1325 int sig;
1326
1327 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1328 if (sig)
1329 {
1330 info.si_signo = sig;
1331 info.si_errno = 0;
1332 info.si_code = TARGET_TRAP_BRKPT;
1333 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1334 }
1335 }
1336 break;
1337 case EXCP_ATOMIC:
1338 cpu_exec_step_atomic(cs);
1339 break;
1340 default:
1341 printf ("Unhandled trap: 0x%x\n", trapnr);
1342 cpu_dump_state(cs, stderr, fprintf, 0);
1343 exit(EXIT_FAILURE);
1344 }
1345 process_pending_signals (env);
1346 }
1347 }
1348
1349 #endif
1350
1351 #ifdef TARGET_PPC
1352 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1353 {
1354 return cpu_get_host_ticks();
1355 }
1356
1357 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1358 {
1359 return cpu_ppc_get_tb(env);
1360 }
1361
1362 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1363 {
1364 return cpu_ppc_get_tb(env) >> 32;
1365 }
1366
1367 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1368 {
1369 return cpu_ppc_get_tb(env);
1370 }
1371
1372 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1373 {
1374 return cpu_ppc_get_tb(env) >> 32;
1375 }
1376
1377 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1378 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1379
1380 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1381 {
1382 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1383 }
1384
1385 /* XXX: to be fixed */
1386 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1387 {
1388 return -1;
1389 }
1390
1391 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1392 {
1393 return -1;
1394 }
1395
1396 static int do_store_exclusive(CPUPPCState *env)
1397 {
1398 target_ulong addr;
1399 target_ulong page_addr;
1400 target_ulong val, val2 __attribute__((unused)) = 0;
1401 int flags;
1402 int segv = 0;
1403
1404 addr = env->reserve_ea;
1405 page_addr = addr & TARGET_PAGE_MASK;
1406 start_exclusive();
1407 mmap_lock();
1408 flags = page_get_flags(page_addr);
1409 if ((flags & PAGE_READ) == 0) {
1410 segv = 1;
1411 } else {
1412 int reg = env->reserve_info & 0x1f;
1413 int size = env->reserve_info >> 5;
1414 int stored = 0;
1415
1416 if (addr == env->reserve_addr) {
1417 switch (size) {
1418 case 1: segv = get_user_u8(val, addr); break;
1419 case 2: segv = get_user_u16(val, addr); break;
1420 case 4: segv = get_user_u32(val, addr); break;
1421 #if defined(TARGET_PPC64)
1422 case 8: segv = get_user_u64(val, addr); break;
1423 case 16: {
1424 segv = get_user_u64(val, addr);
1425 if (!segv) {
1426 segv = get_user_u64(val2, addr + 8);
1427 }
1428 break;
1429 }
1430 #endif
1431 default: abort();
1432 }
1433 if (!segv && val == env->reserve_val) {
1434 val = env->gpr[reg];
1435 switch (size) {
1436 case 1: segv = put_user_u8(val, addr); break;
1437 case 2: segv = put_user_u16(val, addr); break;
1438 case 4: segv = put_user_u32(val, addr); break;
1439 #if defined(TARGET_PPC64)
1440 case 8: segv = put_user_u64(val, addr); break;
1441 case 16: {
1442 if (val2 == env->reserve_val2) {
1443 if (msr_le) {
1444 val2 = val;
1445 val = env->gpr[reg+1];
1446 } else {
1447 val2 = env->gpr[reg+1];
1448 }
1449 segv = put_user_u64(val, addr);
1450 if (!segv) {
1451 segv = put_user_u64(val2, addr + 8);
1452 }
1453 }
1454 break;
1455 }
1456 #endif
1457 default: abort();
1458 }
1459 if (!segv) {
1460 stored = 1;
1461 }
1462 }
1463 }
1464 env->crf[0] = (stored << 1) | xer_so;
1465 env->reserve_addr = (target_ulong)-1;
1466 }
1467 if (!segv) {
1468 env->nip += 4;
1469 }
1470 mmap_unlock();
1471 end_exclusive();
1472 return segv;
1473 }
1474
1475 void cpu_loop(CPUPPCState *env)
1476 {
1477 CPUState *cs = CPU(ppc_env_get_cpu(env));
1478 target_siginfo_t info;
1479 int trapnr;
1480 target_ulong ret;
1481
1482 for(;;) {
1483 cpu_exec_start(cs);
1484 trapnr = cpu_exec(cs);
1485 cpu_exec_end(cs);
1486 process_queued_cpu_work(cs);
1487
1488 switch(trapnr) {
1489 case POWERPC_EXCP_NONE:
1490 /* Just go on */
1491 break;
1492 case POWERPC_EXCP_CRITICAL: /* Critical input */
1493 cpu_abort(cs, "Critical interrupt while in user mode. "
1494 "Aborting\n");
1495 break;
1496 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1497 cpu_abort(cs, "Machine check exception while in user mode. "
1498 "Aborting\n");
1499 break;
1500 case POWERPC_EXCP_DSI: /* Data storage exception */
1501 /* XXX: check this. Seems bugged */
1502 switch (env->error_code & 0xFF000000) {
1503 case 0x40000000:
1504 case 0x42000000:
1505 info.si_signo = TARGET_SIGSEGV;
1506 info.si_errno = 0;
1507 info.si_code = TARGET_SEGV_MAPERR;
1508 break;
1509 case 0x04000000:
1510 info.si_signo = TARGET_SIGILL;
1511 info.si_errno = 0;
1512 info.si_code = TARGET_ILL_ILLADR;
1513 break;
1514 case 0x08000000:
1515 info.si_signo = TARGET_SIGSEGV;
1516 info.si_errno = 0;
1517 info.si_code = TARGET_SEGV_ACCERR;
1518 break;
1519 default:
1520 /* Let's send a regular segfault... */
1521 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1522 env->error_code);
1523 info.si_signo = TARGET_SIGSEGV;
1524 info.si_errno = 0;
1525 info.si_code = TARGET_SEGV_MAPERR;
1526 break;
1527 }
1528 info._sifields._sigfault._addr = env->nip;
1529 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1530 break;
1531 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1532 /* XXX: check this */
1533 switch (env->error_code & 0xFF000000) {
1534 case 0x40000000:
1535 info.si_signo = TARGET_SIGSEGV;
1536 info.si_errno = 0;
1537 info.si_code = TARGET_SEGV_MAPERR;
1538 break;
1539 case 0x10000000:
1540 case 0x08000000:
1541 info.si_signo = TARGET_SIGSEGV;
1542 info.si_errno = 0;
1543 info.si_code = TARGET_SEGV_ACCERR;
1544 break;
1545 default:
1546 /* Let's send a regular segfault... */
1547 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1548 env->error_code);
1549 info.si_signo = TARGET_SIGSEGV;
1550 info.si_errno = 0;
1551 info.si_code = TARGET_SEGV_MAPERR;
1552 break;
1553 }
1554 info._sifields._sigfault._addr = env->nip - 4;
1555 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1556 break;
1557 case POWERPC_EXCP_EXTERNAL: /* External input */
1558 cpu_abort(cs, "External interrupt while in user mode. "
1559 "Aborting\n");
1560 break;
1561 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1562 /* XXX: check this */
1563 info.si_signo = TARGET_SIGBUS;
1564 info.si_errno = 0;
1565 info.si_code = TARGET_BUS_ADRALN;
1566 info._sifields._sigfault._addr = env->nip;
1567 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1568 break;
1569 case POWERPC_EXCP_PROGRAM: /* Program exception */
1570 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1571 /* XXX: check this */
1572 switch (env->error_code & ~0xF) {
1573 case POWERPC_EXCP_FP:
1574 info.si_signo = TARGET_SIGFPE;
1575 info.si_errno = 0;
1576 switch (env->error_code & 0xF) {
1577 case POWERPC_EXCP_FP_OX:
1578 info.si_code = TARGET_FPE_FLTOVF;
1579 break;
1580 case POWERPC_EXCP_FP_UX:
1581 info.si_code = TARGET_FPE_FLTUND;
1582 break;
1583 case POWERPC_EXCP_FP_ZX:
1584 case POWERPC_EXCP_FP_VXZDZ:
1585 info.si_code = TARGET_FPE_FLTDIV;
1586 break;
1587 case POWERPC_EXCP_FP_XX:
1588 info.si_code = TARGET_FPE_FLTRES;
1589 break;
1590 case POWERPC_EXCP_FP_VXSOFT:
1591 info.si_code = TARGET_FPE_FLTINV;
1592 break;
1593 case POWERPC_EXCP_FP_VXSNAN:
1594 case POWERPC_EXCP_FP_VXISI:
1595 case POWERPC_EXCP_FP_VXIDI:
1596 case POWERPC_EXCP_FP_VXIMZ:
1597 case POWERPC_EXCP_FP_VXVC:
1598 case POWERPC_EXCP_FP_VXSQRT:
1599 case POWERPC_EXCP_FP_VXCVI:
1600 info.si_code = TARGET_FPE_FLTSUB;
1601 break;
1602 default:
1603 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1604 env->error_code);
1605 break;
1606 }
1607 break;
1608 case POWERPC_EXCP_INVAL:
1609 info.si_signo = TARGET_SIGILL;
1610 info.si_errno = 0;
1611 switch (env->error_code & 0xF) {
1612 case POWERPC_EXCP_INVAL_INVAL:
1613 info.si_code = TARGET_ILL_ILLOPC;
1614 break;
1615 case POWERPC_EXCP_INVAL_LSWX:
1616 info.si_code = TARGET_ILL_ILLOPN;
1617 break;
1618 case POWERPC_EXCP_INVAL_SPR:
1619 info.si_code = TARGET_ILL_PRVREG;
1620 break;
1621 case POWERPC_EXCP_INVAL_FP:
1622 info.si_code = TARGET_ILL_COPROC;
1623 break;
1624 default:
1625 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1626 env->error_code & 0xF);
1627 info.si_code = TARGET_ILL_ILLADR;
1628 break;
1629 }
1630 break;
1631 case POWERPC_EXCP_PRIV:
1632 info.si_signo = TARGET_SIGILL;
1633 info.si_errno = 0;
1634 switch (env->error_code & 0xF) {
1635 case POWERPC_EXCP_PRIV_OPC:
1636 info.si_code = TARGET_ILL_PRVOPC;
1637 break;
1638 case POWERPC_EXCP_PRIV_REG:
1639 info.si_code = TARGET_ILL_PRVREG;
1640 break;
1641 default:
1642 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1643 env->error_code & 0xF);
1644 info.si_code = TARGET_ILL_PRVOPC;
1645 break;
1646 }
1647 break;
1648 case POWERPC_EXCP_TRAP:
1649 cpu_abort(cs, "Tried to call a TRAP\n");
1650 break;
1651 default:
1652 /* Should not happen ! */
1653 cpu_abort(cs, "Unknown program exception (%02x)\n",
1654 env->error_code);
1655 break;
1656 }
1657 info._sifields._sigfault._addr = env->nip;
1658 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1659 break;
1660 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1661 info.si_signo = TARGET_SIGILL;
1662 info.si_errno = 0;
1663 info.si_code = TARGET_ILL_COPROC;
1664 info._sifields._sigfault._addr = env->nip;
1665 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1666 break;
1667 case POWERPC_EXCP_SYSCALL: /* System call exception */
1668 cpu_abort(cs, "Syscall exception while in user mode. "
1669 "Aborting\n");
1670 break;
1671 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1672 info.si_signo = TARGET_SIGILL;
1673 info.si_errno = 0;
1674 info.si_code = TARGET_ILL_COPROC;
1675 info._sifields._sigfault._addr = env->nip;
1676 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1677 break;
1678 case POWERPC_EXCP_DECR: /* Decrementer exception */
1679 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1680 "Aborting\n");
1681 break;
1682 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1683 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1684 "Aborting\n");
1685 break;
1686 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1687 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1688 "Aborting\n");
1689 break;
1690 case POWERPC_EXCP_DTLB: /* Data TLB error */
1691 cpu_abort(cs, "Data TLB exception while in user mode. "
1692 "Aborting\n");
1693 break;
1694 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1695 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1696 "Aborting\n");
1697 break;
1698 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1699 info.si_signo = TARGET_SIGILL;
1700 info.si_errno = 0;
1701 info.si_code = TARGET_ILL_COPROC;
1702 info._sifields._sigfault._addr = env->nip;
1703 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1704 break;
1705 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1706 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1707 break;
1708 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1709 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1710 break;
1711 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1712 cpu_abort(cs, "Performance monitor exception not handled\n");
1713 break;
1714 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1715 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1716 "Aborting\n");
1717 break;
1718 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1719 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1720 "Aborting\n");
1721 break;
1722 case POWERPC_EXCP_RESET: /* System reset exception */
1723 cpu_abort(cs, "Reset interrupt while in user mode. "
1724 "Aborting\n");
1725 break;
1726 case POWERPC_EXCP_DSEG: /* Data segment exception */
1727 cpu_abort(cs, "Data segment exception while in user mode. "
1728 "Aborting\n");
1729 break;
1730 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1731 cpu_abort(cs, "Instruction segment exception "
1732 "while in user mode. Aborting\n");
1733 break;
1734 /* PowerPC 64 with hypervisor mode support */
1735 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1736 cpu_abort(cs, "Hypervisor decrementer interrupt "
1737 "while in user mode. Aborting\n");
1738 break;
1739 case POWERPC_EXCP_TRACE: /* Trace exception */
1740 /* Nothing to do:
1741 * we use this exception to emulate step-by-step execution mode.
1742 */
1743 break;
1744 /* PowerPC 64 with hypervisor mode support */
1745 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1746 cpu_abort(cs, "Hypervisor data storage exception "
1747 "while in user mode. Aborting\n");
1748 break;
1749 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1750 cpu_abort(cs, "Hypervisor instruction storage exception "
1751 "while in user mode. Aborting\n");
1752 break;
1753 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1754 cpu_abort(cs, "Hypervisor data segment exception "
1755 "while in user mode. Aborting\n");
1756 break;
1757 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1758 cpu_abort(cs, "Hypervisor instruction segment exception "
1759 "while in user mode. Aborting\n");
1760 break;
1761 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1762 info.si_signo = TARGET_SIGILL;
1763 info.si_errno = 0;
1764 info.si_code = TARGET_ILL_COPROC;
1765 info._sifields._sigfault._addr = env->nip;
1766 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1767 break;
1768 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1769 cpu_abort(cs, "Programmable interval timer interrupt "
1770 "while in user mode. Aborting\n");
1771 break;
1772 case POWERPC_EXCP_IO: /* IO error exception */
1773 cpu_abort(cs, "IO error exception while in user mode. "
1774 "Aborting\n");
1775 break;
1776 case POWERPC_EXCP_RUNM: /* Run mode exception */
1777 cpu_abort(cs, "Run mode exception while in user mode. "
1778 "Aborting\n");
1779 break;
1780 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1781 cpu_abort(cs, "Emulation trap exception not handled\n");
1782 break;
1783 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1784 cpu_abort(cs, "Instruction fetch TLB exception "
1785 "while in user-mode. Aborting");
1786 break;
1787 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1788 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1789 "Aborting");
1790 break;
1791 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1792 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1793 "Aborting");
1794 break;
1795 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1796 cpu_abort(cs, "Floating-point assist exception not handled\n");
1797 break;
1798 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1799 cpu_abort(cs, "Instruction address breakpoint exception "
1800 "not handled\n");
1801 break;
1802 case POWERPC_EXCP_SMI: /* System management interrupt */
1803 cpu_abort(cs, "System management interrupt while in user mode. "
1804 "Aborting\n");
1805 break;
1806 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1807 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1808 "Aborting\n");
1809 break;
1810 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1811 cpu_abort(cs, "Performance monitor exception not handled\n");
1812 break;
1813 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1814 cpu_abort(cs, "Vector assist exception not handled\n");
1815 break;
1816 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1817 cpu_abort(cs, "Soft patch exception not handled\n");
1818 break;
1819 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1820 cpu_abort(cs, "Maintenance exception while in user mode. "
1821 "Aborting\n");
1822 break;
1823 case POWERPC_EXCP_STOP: /* stop translation */
1824 /* We did invalidate the instruction cache. Go on */
1825 break;
1826 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1827 /* We just stopped because of a branch. Go on */
1828 break;
1829 case POWERPC_EXCP_SYSCALL_USER:
1830 /* system call in user-mode emulation */
1831 /* WARNING:
1832 * PPC ABI uses overflow flag in cr0 to signal an error
1833 * in syscalls.
1834 */
1835 env->crf[0] &= ~0x1;
1836 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1837 env->gpr[5], env->gpr[6], env->gpr[7],
1838 env->gpr[8], 0, 0);
1839 if (ret == -TARGET_ERESTARTSYS) {
1840 break;
1841 }
1842 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1843 /* Returning from a successful sigreturn syscall.
1844 Avoid corrupting register state. */
1845 break;
1846 }
1847 env->nip += 4;
1848 if (ret > (target_ulong)(-515)) {
1849 env->crf[0] |= 0x1;
1850 ret = -ret;
1851 }
1852 env->gpr[3] = ret;
1853 break;
1854 case POWERPC_EXCP_STCX:
1855 if (do_store_exclusive(env)) {
1856 info.si_signo = TARGET_SIGSEGV;
1857 info.si_errno = 0;
1858 info.si_code = TARGET_SEGV_MAPERR;
1859 info._sifields._sigfault._addr = env->nip;
1860 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1861 }
1862 break;
1863 case EXCP_DEBUG:
1864 {
1865 int sig;
1866
1867 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1868 if (sig) {
1869 info.si_signo = sig;
1870 info.si_errno = 0;
1871 info.si_code = TARGET_TRAP_BRKPT;
1872 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1873 }
1874 }
1875 break;
1876 case EXCP_INTERRUPT:
1877 /* just indicate that signals should be handled asap */
1878 break;
1879 case EXCP_ATOMIC:
1880 cpu_exec_step_atomic(cs);
1881 break;
1882 default:
1883 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
1884 break;
1885 }
1886 process_pending_signals(env);
1887 }
1888 }
1889 #endif
1890
1891 #ifdef TARGET_MIPS
1892
1893 # ifdef TARGET_ABI_MIPSO32
1894 # define MIPS_SYS(name, args) args,
1895 static const uint8_t mips_syscall_args[] = {
1896 MIPS_SYS(sys_syscall , 8) /* 4000 */
1897 MIPS_SYS(sys_exit , 1)
1898 MIPS_SYS(sys_fork , 0)
1899 MIPS_SYS(sys_read , 3)
1900 MIPS_SYS(sys_write , 3)
1901 MIPS_SYS(sys_open , 3) /* 4005 */
1902 MIPS_SYS(sys_close , 1)
1903 MIPS_SYS(sys_waitpid , 3)
1904 MIPS_SYS(sys_creat , 2)
1905 MIPS_SYS(sys_link , 2)
1906 MIPS_SYS(sys_unlink , 1) /* 4010 */
1907 MIPS_SYS(sys_execve , 0)
1908 MIPS_SYS(sys_chdir , 1)
1909 MIPS_SYS(sys_time , 1)
1910 MIPS_SYS(sys_mknod , 3)
1911 MIPS_SYS(sys_chmod , 2) /* 4015 */
1912 MIPS_SYS(sys_lchown , 3)
1913 MIPS_SYS(sys_ni_syscall , 0)
1914 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1915 MIPS_SYS(sys_lseek , 3)
1916 MIPS_SYS(sys_getpid , 0) /* 4020 */
1917 MIPS_SYS(sys_mount , 5)
1918 MIPS_SYS(sys_umount , 1)
1919 MIPS_SYS(sys_setuid , 1)
1920 MIPS_SYS(sys_getuid , 0)
1921 MIPS_SYS(sys_stime , 1) /* 4025 */
1922 MIPS_SYS(sys_ptrace , 4)
1923 MIPS_SYS(sys_alarm , 1)
1924 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1925 MIPS_SYS(sys_pause , 0)
1926 MIPS_SYS(sys_utime , 2) /* 4030 */
1927 MIPS_SYS(sys_ni_syscall , 0)
1928 MIPS_SYS(sys_ni_syscall , 0)
1929 MIPS_SYS(sys_access , 2)
1930 MIPS_SYS(sys_nice , 1)
1931 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1932 MIPS_SYS(sys_sync , 0)
1933 MIPS_SYS(sys_kill , 2)
1934 MIPS_SYS(sys_rename , 2)
1935 MIPS_SYS(sys_mkdir , 2)
1936 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1937 MIPS_SYS(sys_dup , 1)
1938 MIPS_SYS(sys_pipe , 0)
1939 MIPS_SYS(sys_times , 1)
1940 MIPS_SYS(sys_ni_syscall , 0)
1941 MIPS_SYS(sys_brk , 1) /* 4045 */
1942 MIPS_SYS(sys_setgid , 1)
1943 MIPS_SYS(sys_getgid , 0)
1944 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1945 MIPS_SYS(sys_geteuid , 0)
1946 MIPS_SYS(sys_getegid , 0) /* 4050 */
1947 MIPS_SYS(sys_acct , 0)
1948 MIPS_SYS(sys_umount2 , 2)
1949 MIPS_SYS(sys_ni_syscall , 0)
1950 MIPS_SYS(sys_ioctl , 3)
1951 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1952 MIPS_SYS(sys_ni_syscall , 2)
1953 MIPS_SYS(sys_setpgid , 2)
1954 MIPS_SYS(sys_ni_syscall , 0)
1955 MIPS_SYS(sys_olduname , 1)
1956 MIPS_SYS(sys_umask , 1) /* 4060 */
1957 MIPS_SYS(sys_chroot , 1)
1958 MIPS_SYS(sys_ustat , 2)
1959 MIPS_SYS(sys_dup2 , 2)
1960 MIPS_SYS(sys_getppid , 0)
1961 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1962 MIPS_SYS(sys_setsid , 0)
1963 MIPS_SYS(sys_sigaction , 3)
1964 MIPS_SYS(sys_sgetmask , 0)
1965 MIPS_SYS(sys_ssetmask , 1)
1966 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1967 MIPS_SYS(sys_setregid , 2)
1968 MIPS_SYS(sys_sigsuspend , 0)
1969 MIPS_SYS(sys_sigpending , 1)
1970 MIPS_SYS(sys_sethostname , 2)
1971 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1972 MIPS_SYS(sys_getrlimit , 2)
1973 MIPS_SYS(sys_getrusage , 2)
1974 MIPS_SYS(sys_gettimeofday, 2)
1975 MIPS_SYS(sys_settimeofday, 2)
1976 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1977 MIPS_SYS(sys_setgroups , 2)
1978 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1979 MIPS_SYS(sys_symlink , 2)
1980 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1981 MIPS_SYS(sys_readlink , 3) /* 4085 */
1982 MIPS_SYS(sys_uselib , 1)
1983 MIPS_SYS(sys_swapon , 2)
1984 MIPS_SYS(sys_reboot , 3)
1985 MIPS_SYS(old_readdir , 3)
1986 MIPS_SYS(old_mmap , 6) /* 4090 */
1987 MIPS_SYS(sys_munmap , 2)
1988 MIPS_SYS(sys_truncate , 2)
1989 MIPS_SYS(sys_ftruncate , 2)
1990 MIPS_SYS(sys_fchmod , 2)
1991 MIPS_SYS(sys_fchown , 3) /* 4095 */
1992 MIPS_SYS(sys_getpriority , 2)
1993 MIPS_SYS(sys_setpriority , 3)
1994 MIPS_SYS(sys_ni_syscall , 0)
1995 MIPS_SYS(sys_statfs , 2)
1996 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1997 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1998 MIPS_SYS(sys_socketcall , 2)
1999 MIPS_SYS(sys_syslog , 3)
2000 MIPS_SYS(sys_setitimer , 3)
2001 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2002 MIPS_SYS(sys_newstat , 2)
2003 MIPS_SYS(sys_newlstat , 2)
2004 MIPS_SYS(sys_newfstat , 2)
2005 MIPS_SYS(sys_uname , 1)
2006 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2007 MIPS_SYS(sys_vhangup , 0)
2008 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2009 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2010 MIPS_SYS(sys_wait4 , 4)
2011 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2012 MIPS_SYS(sys_sysinfo , 1)
2013 MIPS_SYS(sys_ipc , 6)
2014 MIPS_SYS(sys_fsync , 1)
2015 MIPS_SYS(sys_sigreturn , 0)
2016 MIPS_SYS(sys_clone , 6) /* 4120 */
2017 MIPS_SYS(sys_setdomainname, 2)
2018 MIPS_SYS(sys_newuname , 1)
2019 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2020 MIPS_SYS(sys_adjtimex , 1)
2021 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2022 MIPS_SYS(sys_sigprocmask , 3)
2023 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2024 MIPS_SYS(sys_init_module , 5)
2025 MIPS_SYS(sys_delete_module, 1)
2026 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2027 MIPS_SYS(sys_quotactl , 0)
2028 MIPS_SYS(sys_getpgid , 1)
2029 MIPS_SYS(sys_fchdir , 1)
2030 MIPS_SYS(sys_bdflush , 2)
2031 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2032 MIPS_SYS(sys_personality , 1)
2033 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2034 MIPS_SYS(sys_setfsuid , 1)
2035 MIPS_SYS(sys_setfsgid , 1)
2036 MIPS_SYS(sys_llseek , 5) /* 4140 */
2037 MIPS_SYS(sys_getdents , 3)
2038 MIPS_SYS(sys_select , 5)
2039 MIPS_SYS(sys_flock , 2)
2040 MIPS_SYS(sys_msync , 3)
2041 MIPS_SYS(sys_readv , 3) /* 4145 */
2042 MIPS_SYS(sys_writev , 3)
2043 MIPS_SYS(sys_cacheflush , 3)
2044 MIPS_SYS(sys_cachectl , 3)
2045 MIPS_SYS(sys_sysmips , 4)
2046 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2047 MIPS_SYS(sys_getsid , 1)
2048 MIPS_SYS(sys_fdatasync , 0)
2049 MIPS_SYS(sys_sysctl , 1)
2050 MIPS_SYS(sys_mlock , 2)
2051 MIPS_SYS(sys_munlock , 2) /* 4155 */
2052 MIPS_SYS(sys_mlockall , 1)
2053 MIPS_SYS(sys_munlockall , 0)
2054 MIPS_SYS(sys_sched_setparam, 2)
2055 MIPS_SYS(sys_sched_getparam, 2)
2056 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2057 MIPS_SYS(sys_sched_getscheduler, 1)
2058 MIPS_SYS(sys_sched_yield , 0)
2059 MIPS_SYS(sys_sched_get_priority_max, 1)
2060 MIPS_SYS(sys_sched_get_priority_min, 1)
2061 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2062 MIPS_SYS(sys_nanosleep, 2)
2063 MIPS_SYS(sys_mremap , 5)
2064 MIPS_SYS(sys_accept , 3)
2065 MIPS_SYS(sys_bind , 3)
2066 MIPS_SYS(sys_connect , 3) /* 4170 */
2067 MIPS_SYS(sys_getpeername , 3)
2068 MIPS_SYS(sys_getsockname , 3)
2069 MIPS_SYS(sys_getsockopt , 5)
2070 MIPS_SYS(sys_listen , 2)
2071 MIPS_SYS(sys_recv , 4) /* 4175 */
2072 MIPS_SYS(sys_recvfrom , 6)
2073 MIPS_SYS(sys_recvmsg , 3)
2074 MIPS_SYS(sys_send , 4)
2075 MIPS_SYS(sys_sendmsg , 3)
2076 MIPS_SYS(sys_sendto , 6) /* 4180 */
2077 MIPS_SYS(sys_setsockopt , 5)
2078 MIPS_SYS(sys_shutdown , 2)
2079 MIPS_SYS(sys_socket , 3)
2080 MIPS_SYS(sys_socketpair , 4)
2081 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2082 MIPS_SYS(sys_getresuid , 3)
2083 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2084 MIPS_SYS(sys_poll , 3)
2085 MIPS_SYS(sys_nfsservctl , 3)
2086 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2087 MIPS_SYS(sys_getresgid , 3)
2088 MIPS_SYS(sys_prctl , 5)
2089 MIPS_SYS(sys_rt_sigreturn, 0)
2090 MIPS_SYS(sys_rt_sigaction, 4)
2091 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2092 MIPS_SYS(sys_rt_sigpending, 2)
2093 MIPS_SYS(sys_rt_sigtimedwait, 4)
2094 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2095 MIPS_SYS(sys_rt_sigsuspend, 0)
2096 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2097 MIPS_SYS(sys_pwrite64 , 6)
2098 MIPS_SYS(sys_chown , 3)
2099 MIPS_SYS(sys_getcwd , 2)
2100 MIPS_SYS(sys_capget , 2)
2101 MIPS_SYS(sys_capset , 2) /* 4205 */
2102 MIPS_SYS(sys_sigaltstack , 2)
2103 MIPS_SYS(sys_sendfile , 4)
2104 MIPS_SYS(sys_ni_syscall , 0)
2105 MIPS_SYS(sys_ni_syscall , 0)
2106 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2107 MIPS_SYS(sys_truncate64 , 4)
2108 MIPS_SYS(sys_ftruncate64 , 4)
2109 MIPS_SYS(sys_stat64 , 2)
2110 MIPS_SYS(sys_lstat64 , 2)
2111 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2112 MIPS_SYS(sys_pivot_root , 2)
2113 MIPS_SYS(sys_mincore , 3)
2114 MIPS_SYS(sys_madvise , 3)
2115 MIPS_SYS(sys_getdents64 , 3)
2116 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2117 MIPS_SYS(sys_ni_syscall , 0)
2118 MIPS_SYS(sys_gettid , 0)
2119 MIPS_SYS(sys_readahead , 5)
2120 MIPS_SYS(sys_setxattr , 5)
2121 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2122 MIPS_SYS(sys_fsetxattr , 5)
2123 MIPS_SYS(sys_getxattr , 4)
2124 MIPS_SYS(sys_lgetxattr , 4)
2125 MIPS_SYS(sys_fgetxattr , 4)
2126 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2127 MIPS_SYS(sys_llistxattr , 3)
2128 MIPS_SYS(sys_flistxattr , 3)
2129 MIPS_SYS(sys_removexattr , 2)
2130 MIPS_SYS(sys_lremovexattr, 2)
2131 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2132 MIPS_SYS(sys_tkill , 2)
2133 MIPS_SYS(sys_sendfile64 , 5)
2134 MIPS_SYS(sys_futex , 6)
2135 MIPS_SYS(sys_sched_setaffinity, 3)
2136 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2137 MIPS_SYS(sys_io_setup , 2)
2138 MIPS_SYS(sys_io_destroy , 1)
2139 MIPS_SYS(sys_io_getevents, 5)
2140 MIPS_SYS(sys_io_submit , 3)
2141 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2142 MIPS_SYS(sys_exit_group , 1)
2143 MIPS_SYS(sys_lookup_dcookie, 3)
2144 MIPS_SYS(sys_epoll_create, 1)
2145 MIPS_SYS(sys_epoll_ctl , 4)
2146 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2147 MIPS_SYS(sys_remap_file_pages, 5)
2148 MIPS_SYS(sys_set_tid_address, 1)
2149 MIPS_SYS(sys_restart_syscall, 0)
2150 MIPS_SYS(sys_fadvise64_64, 7)
2151 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2152 MIPS_SYS(sys_fstatfs64 , 2)
2153 MIPS_SYS(sys_timer_create, 3)
2154 MIPS_SYS(sys_timer_settime, 4)
2155 MIPS_SYS(sys_timer_gettime, 2)
2156 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2157 MIPS_SYS(sys_timer_delete, 1)
2158 MIPS_SYS(sys_clock_settime, 2)
2159 MIPS_SYS(sys_clock_gettime, 2)
2160 MIPS_SYS(sys_clock_getres, 2)
2161 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2162 MIPS_SYS(sys_tgkill , 3)
2163 MIPS_SYS(sys_utimes , 2)
2164 MIPS_SYS(sys_mbind , 4)
2165 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2166 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2167 MIPS_SYS(sys_mq_open , 4)
2168 MIPS_SYS(sys_mq_unlink , 1)
2169 MIPS_SYS(sys_mq_timedsend, 5)
2170 MIPS_SYS(sys_mq_timedreceive, 5)
2171 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2172 MIPS_SYS(sys_mq_getsetattr, 3)
2173 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2174 MIPS_SYS(sys_waitid , 4)
2175 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2176 MIPS_SYS(sys_add_key , 5)
2177 MIPS_SYS(sys_request_key, 4)
2178 MIPS_SYS(sys_keyctl , 5)
2179 MIPS_SYS(sys_set_thread_area, 1)
2180 MIPS_SYS(sys_inotify_init, 0)
2181 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2182 MIPS_SYS(sys_inotify_rm_watch, 2)
2183 MIPS_SYS(sys_migrate_pages, 4)
2184 MIPS_SYS(sys_openat, 4)
2185 MIPS_SYS(sys_mkdirat, 3)
2186 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2187 MIPS_SYS(sys_fchownat, 5)
2188 MIPS_SYS(sys_futimesat, 3)
2189 MIPS_SYS(sys_fstatat64, 4)
2190 MIPS_SYS(sys_unlinkat, 3)
2191 MIPS_SYS(sys_renameat, 4) /* 4295 */
2192 MIPS_SYS(sys_linkat, 5)
2193 MIPS_SYS(sys_symlinkat, 3)
2194 MIPS_SYS(sys_readlinkat, 4)
2195 MIPS_SYS(sys_fchmodat, 3)
2196 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2197 MIPS_SYS(sys_pselect6, 6)
2198 MIPS_SYS(sys_ppoll, 5)
2199 MIPS_SYS(sys_unshare, 1)
2200 MIPS_SYS(sys_splice, 6)
2201 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2202 MIPS_SYS(sys_tee, 4)
2203 MIPS_SYS(sys_vmsplice, 4)
2204 MIPS_SYS(sys_move_pages, 6)
2205 MIPS_SYS(sys_set_robust_list, 2)
2206 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2207 MIPS_SYS(sys_kexec_load, 4)
2208 MIPS_SYS(sys_getcpu, 3)
2209 MIPS_SYS(sys_epoll_pwait, 6)
2210 MIPS_SYS(sys_ioprio_set, 3)
2211 MIPS_SYS(sys_ioprio_get, 2)
2212 MIPS_SYS(sys_utimensat, 4)
2213 MIPS_SYS(sys_signalfd, 3)
2214 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2215 MIPS_SYS(sys_eventfd, 1)
2216 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2217 MIPS_SYS(sys_timerfd_create, 2)
2218 MIPS_SYS(sys_timerfd_gettime, 2)
2219 MIPS_SYS(sys_timerfd_settime, 4)
2220 MIPS_SYS(sys_signalfd4, 4)
2221 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2222 MIPS_SYS(sys_epoll_create1, 1)
2223 MIPS_SYS(sys_dup3, 3)
2224 MIPS_SYS(sys_pipe2, 2)
2225 MIPS_SYS(sys_inotify_init1, 1)
2226 MIPS_SYS(sys_preadv, 5) /* 4330 */
2227 MIPS_SYS(sys_pwritev, 5)
2228 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2229 MIPS_SYS(sys_perf_event_open, 5)
2230 MIPS_SYS(sys_accept4, 4)
2231 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2232 MIPS_SYS(sys_fanotify_init, 2)
2233 MIPS_SYS(sys_fanotify_mark, 6)
2234 MIPS_SYS(sys_prlimit64, 4)
2235 MIPS_SYS(sys_name_to_handle_at, 5)
2236 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2237 MIPS_SYS(sys_clock_adjtime, 2)
2238 MIPS_SYS(sys_syncfs, 1)
2239 MIPS_SYS(sys_sendmmsg, 4)
2240 MIPS_SYS(sys_setns, 2)
2241 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2242 MIPS_SYS(sys_process_vm_writev, 6)
2243 MIPS_SYS(sys_kcmp, 5)
2244 MIPS_SYS(sys_finit_module, 3)
2245 MIPS_SYS(sys_sched_setattr, 2)
2246 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2247 MIPS_SYS(sys_renameat2, 5)
2248 MIPS_SYS(sys_seccomp, 3)
2249 MIPS_SYS(sys_getrandom, 3)
2250 MIPS_SYS(sys_memfd_create, 2)
2251 MIPS_SYS(sys_bpf, 3) /* 355 */
2252 MIPS_SYS(sys_execveat, 5)
2253 MIPS_SYS(sys_userfaultfd, 1)
2254 MIPS_SYS(sys_membarrier, 2)
2255 MIPS_SYS(sys_mlock2, 3)
2256 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2257 MIPS_SYS(sys_preadv2, 6)
2258 MIPS_SYS(sys_pwritev2, 6)
2259 };
2260 # undef MIPS_SYS
2261 # endif /* O32 */
2262
2263 static int do_store_exclusive(CPUMIPSState *env)
2264 {
2265 target_ulong addr;
2266 target_ulong page_addr;
2267 target_ulong val;
2268 int flags;
2269 int segv = 0;
2270 int reg;
2271 int d;
2272
2273 addr = env->lladdr;
2274 page_addr = addr & TARGET_PAGE_MASK;
2275 start_exclusive();
2276 mmap_lock();
2277 flags = page_get_flags(page_addr);
2278 if ((flags & PAGE_READ) == 0) {
2279 segv = 1;
2280 } else {
2281 reg = env->llreg & 0x1f;
2282 d = (env->llreg & 0x20) != 0;
2283 if (d) {
2284 segv = get_user_s64(val, addr);
2285 } else {
2286 segv = get_user_s32(val, addr);
2287 }
2288 if (!segv) {
2289 if (val != env->llval) {
2290 env->active_tc.gpr[reg] = 0;
2291 } else {
2292 if (d) {
2293 segv = put_user_u64(env->llnewval, addr);
2294 } else {
2295 segv = put_user_u32(env->llnewval, addr);
2296 }
2297 if (!segv) {
2298 env->active_tc.gpr[reg] = 1;
2299 }
2300 }
2301 }
2302 }
2303 env->lladdr = -1;
2304 if (!segv) {
2305 env->active_tc.PC += 4;
2306 }
2307 mmap_unlock();
2308 end_exclusive();
2309 return segv;
2310 }
2311
2312 /* Break codes */
2313 enum {
2314 BRK_OVERFLOW = 6,
2315 BRK_DIVZERO = 7
2316 };
2317
2318 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2319 unsigned int code)
2320 {
2321 int ret = -1;
2322
2323 switch (code) {
2324 case BRK_OVERFLOW:
2325 case BRK_DIVZERO:
2326 info->si_signo = TARGET_SIGFPE;
2327 info->si_errno = 0;
2328 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2329 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2330 ret = 0;
2331 break;
2332 default:
2333 info->si_signo = TARGET_SIGTRAP;
2334 info->si_errno = 0;
2335 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2336 ret = 0;
2337 break;
2338 }
2339
2340 return ret;
2341 }
2342
2343 void cpu_loop(CPUMIPSState *env)
2344 {
2345 CPUState *cs = CPU(mips_env_get_cpu(env));
2346 target_siginfo_t info;
2347 int trapnr;
2348 abi_long ret;
2349 # ifdef TARGET_ABI_MIPSO32
2350 unsigned int syscall_num;
2351 # endif
2352
2353 for(;;) {
2354 cpu_exec_start(cs);
2355 trapnr = cpu_exec(cs);
2356 cpu_exec_end(cs);
2357 process_queued_cpu_work(cs);
2358
2359 switch(trapnr) {
2360 case EXCP_SYSCALL:
2361 env->active_tc.PC += 4;
2362 # ifdef TARGET_ABI_MIPSO32
2363 syscall_num = env->active_tc.gpr[2] - 4000;
2364 if (syscall_num >= sizeof(mips_syscall_args)) {
2365 ret = -TARGET_ENOSYS;
2366 } else {
2367 int nb_args;
2368 abi_ulong sp_reg;
2369 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2370
2371 nb_args = mips_syscall_args[syscall_num];
2372 sp_reg = env->active_tc.gpr[29];
2373 switch (nb_args) {
2374 /* these arguments are taken from the stack */
2375 case 8:
2376 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2377 goto done_syscall;
2378 }
2379 case 7:
2380 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2381 goto done_syscall;
2382 }
2383 case 6:
2384 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2385 goto done_syscall;
2386 }
2387 case 5:
2388 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2389 goto done_syscall;
2390 }
2391 default:
2392 break;
2393 }
2394 ret = do_syscall(env, env->active_tc.gpr[2],
2395 env->active_tc.gpr[4],
2396 env->active_tc.gpr[5],
2397 env->active_tc.gpr[6],
2398 env->active_tc.gpr[7],
2399 arg5, arg6, arg7, arg8);
2400 }
2401 done_syscall:
2402 # else
2403 ret = do_syscall(env, env->active_tc.gpr[2],
2404 env->active_tc.gpr[4], env->active_tc.gpr[5],
2405 env->active_tc.gpr[6], env->active_tc.gpr[7],
2406 env->active_tc.gpr[8], env->active_tc.gpr[9],
2407 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2408 # endif /* O32 */
2409 if (ret == -TARGET_ERESTARTSYS) {
2410 env->active_tc.PC -= 4;
2411 break;
2412 }
2413 if (ret == -TARGET_QEMU_ESIGRETURN) {
2414 /* Returning from a successful sigreturn syscall.
2415 Avoid clobbering register state. */
2416 break;
2417 }
2418 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2419 env->active_tc.gpr[7] = 1; /* error flag */
2420 ret = -ret;
2421 } else {
2422 env->active_tc.gpr[7] = 0; /* error flag */
2423 }
2424 env->active_tc.gpr[2] = ret;
2425 break;
2426 case EXCP_TLBL:
2427 case EXCP_TLBS:
2428 case EXCP_AdEL:
2429 case EXCP_AdES:
2430 info.si_signo = TARGET_SIGSEGV;
2431 info.si_errno = 0;
2432 /* XXX: check env->error_code */
2433 info.si_code = TARGET_SEGV_MAPERR;
2434 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2435 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2436 break;
2437 case EXCP_CpU:
2438 case EXCP_RI:
2439 info.si_signo = TARGET_SIGILL;
2440 info.si_errno = 0;
2441 info.si_code = 0;
2442 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2443 break;
2444 case EXCP_INTERRUPT:
2445 /* just indicate that signals should be handled asap */
2446 break;
2447 case EXCP_DEBUG:
2448 {
2449 int sig;
2450
2451 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2452 if (sig)
2453 {
2454 info.si_signo = sig;
2455 info.si_errno = 0;
2456 info.si_code = TARGET_TRAP_BRKPT;
2457 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2458 }
2459 }
2460 break;
2461 case EXCP_SC:
2462 if (do_store_exclusive(env)) {
2463 info.si_signo = TARGET_SIGSEGV;
2464 info.si_errno = 0;
2465 info.si_code = TARGET_SEGV_MAPERR;
2466 info._sifields._sigfault._addr = env->active_tc.PC;
2467 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2468 }
2469 break;
2470 case EXCP_DSPDIS:
2471 info.si_signo = TARGET_SIGILL;
2472 info.si_errno = 0;
2473 info.si_code = TARGET_ILL_ILLOPC;
2474 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2475 break;
2476 /* The code below was inspired by the MIPS Linux kernel trap
2477 * handling code in arch/mips/kernel/traps.c.
2478 */
2479 case EXCP_BREAK:
2480 {
2481 abi_ulong trap_instr;
2482 unsigned int code;
2483
2484 if (env->hflags & MIPS_HFLAG_M16) {
2485 if (env->insn_flags & ASE_MICROMIPS) {
2486 /* microMIPS mode */
2487 ret = get_user_u16(trap_instr, env->active_tc.PC);
2488 if (ret != 0) {
2489 goto error;
2490 }
2491
2492 if ((trap_instr >> 10) == 0x11) {
2493 /* 16-bit instruction */
2494 code = trap_instr & 0xf;
2495 } else {
2496 /* 32-bit instruction */
2497 abi_ulong instr_lo;
2498
2499 ret = get_user_u16(instr_lo,
2500 env->active_tc.PC + 2);
2501 if (ret != 0) {
2502 goto error;
2503 }
2504 trap_instr = (trap_instr << 16) | instr_lo;
2505 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2506 /* Unfortunately, microMIPS also suffers from
2507 the old assembler bug... */
2508 if (code >= (1 << 10)) {
2509 code >>= 10;
2510 }
2511 }
2512 } else {
2513 /* MIPS16e mode */
2514 ret = get_user_u16(trap_instr, env->active_tc.PC);
2515 if (ret != 0) {
2516 goto error;
2517 }
2518 code = (trap_instr >> 6) & 0x3f;
2519 }
2520 } else {
2521 ret = get_user_u32(trap_instr, env->active_tc.PC);
2522 if (ret != 0) {
2523 goto error;
2524 }
2525
2526 /* As described in the original Linux kernel code, the
2527 * below checks on 'code' are to work around an old
2528 * assembly bug.
2529 */
2530 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2531 if (code >= (1 << 10)) {
2532 code >>= 10;
2533 }
2534 }
2535
2536 if (do_break(env, &info, code) != 0) {
2537 goto error;
2538 }
2539 }
2540 break;
2541 case EXCP_TRAP:
2542 {
2543 abi_ulong trap_instr;
2544 unsigned int code = 0;
2545
2546 if (env->hflags & MIPS_HFLAG_M16) {
2547 /* microMIPS mode */
2548 abi_ulong instr[2];
2549
2550 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2551 get_user_u16(instr[1], env->active_tc.PC + 2);
2552
2553 trap_instr = (instr[0] << 16) | instr[1];
2554 } else {
2555 ret = get_user_u32(trap_instr, env->active_tc.PC);
2556 }
2557
2558 if (ret != 0) {
2559 goto error;
2560 }
2561
2562 /* The immediate versions don't provide a code. */
2563 if (!(trap_instr & 0xFC000000)) {
2564 if (env->hflags & MIPS_HFLAG_M16) {
2565 /* microMIPS mode */
2566 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2567 } else {
2568 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2569 }
2570 }
2571
2572 if (do_break(env, &info, code) != 0) {
2573 goto error;
2574 }
2575 }
2576 break;
2577 case EXCP_ATOMIC:
2578 cpu_exec_step_atomic(cs);
2579 break;
2580 default:
2581 error:
2582 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2583 abort();
2584 }
2585 process_pending_signals(env);
2586 }
2587 }
2588 #endif
2589
2590 #ifdef TARGET_OPENRISC
2591
2592 void cpu_loop(CPUOpenRISCState *env)
2593 {
2594 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2595 int trapnr, gdbsig;
2596 abi_long ret;
2597
2598 for (;;) {
2599 cpu_exec_start(cs);
2600 trapnr = cpu_exec(cs);
2601 cpu_exec_end(cs);
2602 process_queued_cpu_work(cs);
2603 gdbsig = 0;
2604
2605 switch (trapnr) {
2606 case EXCP_RESET:
2607 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2608 exit(EXIT_FAILURE);
2609 break;
2610 case EXCP_BUSERR:
2611 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2612 gdbsig = TARGET_SIGBUS;
2613 break;
2614 case EXCP_DPF:
2615 case EXCP_IPF:
2616 cpu_dump_state(cs, stderr, fprintf, 0);
2617 gdbsig = TARGET_SIGSEGV;
2618 break;
2619 case EXCP_TICK:
2620 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2621 break;
2622 case EXCP_ALIGN:
2623 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2624 gdbsig = TARGET_SIGBUS;
2625 break;
2626 case EXCP_ILLEGAL:
2627 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2628 gdbsig = TARGET_SIGILL;
2629 break;
2630 case EXCP_INT:
2631 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2632 break;
2633 case EXCP_DTLBMISS:
2634 case EXCP_ITLBMISS:
2635 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2636 break;
2637 case EXCP_RANGE:
2638 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2639 gdbsig = TARGET_SIGSEGV;
2640 break;
2641 case EXCP_SYSCALL:
2642 env->pc += 4; /* 0xc00; */
2643 ret = do_syscall(env,
2644 env->gpr[11], /* return value */
2645 env->gpr[3], /* r3 - r7 are params */
2646 env->gpr[4],
2647 env->gpr[5],
2648 env->gpr[6],
2649 env->gpr[7],
2650 env->gpr[8], 0, 0);
2651 if (ret == -TARGET_ERESTARTSYS) {
2652 env->pc -= 4;
2653 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2654 env->gpr[11] = ret;
2655 }
2656 break;
2657 case EXCP_FPE:
2658 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2659 break;
2660 case EXCP_TRAP:
2661 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2662 gdbsig = TARGET_SIGTRAP;
2663 break;
2664 case EXCP_NR:
2665 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2666 break;
2667 case EXCP_ATOMIC:
2668 cpu_exec_step_atomic(cs);
2669 break;
2670 default:
2671 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2672 trapnr);
2673 gdbsig = TARGET_SIGILL;
2674 break;
2675 }
2676 if (gdbsig) {
2677 gdb_handlesig(cs, gdbsig);
2678 if (gdbsig != TARGET_SIGTRAP) {
2679 exit(EXIT_FAILURE);
2680 }
2681 }
2682
2683 process_pending_signals(env);
2684 }
2685 }
2686
2687 #endif /* TARGET_OPENRISC */
2688
2689 #ifdef TARGET_SH4
2690 void cpu_loop(CPUSH4State *env)
2691 {
2692 CPUState *cs = CPU(sh_env_get_cpu(env));
2693 int trapnr, ret;
2694 target_siginfo_t info;
2695
2696 while (1) {
2697 cpu_exec_start(cs);
2698 trapnr = cpu_exec(cs);
2699 cpu_exec_end(cs);
2700 process_queued_cpu_work(cs);
2701
2702 switch (trapnr) {
2703 case 0x160:
2704 env->pc += 2;
2705 ret = do_syscall(env,
2706 env->gregs[3],
2707 env->gregs[4],
2708 env->gregs[5],
2709 env->gregs[6],
2710 env->gregs[7],
2711 env->gregs[0],
2712 env->gregs[1],
2713 0, 0);
2714 if (ret == -TARGET_ERESTARTSYS) {
2715 env->pc -= 2;
2716 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2717 env->gregs[0] = ret;
2718 }
2719 break;
2720 case EXCP_INTERRUPT:
2721 /* just indicate that signals should be handled asap */
2722 break;
2723 case EXCP_DEBUG:
2724 {
2725 int sig;
2726
2727 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2728 if (sig)
2729 {
2730 info.si_signo = sig;
2731 info.si_errno = 0;
2732 info.si_code = TARGET_TRAP_BRKPT;
2733 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2734 }
2735 }
2736 break;
2737 case 0xa0:
2738 case 0xc0:
2739 info.si_signo = TARGET_SIGSEGV;
2740 info.si_errno = 0;
2741 info.si_code = TARGET_SEGV_MAPERR;
2742 info._sifields._sigfault._addr = env->tea;
2743 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2744 break;
2745
2746 case EXCP_ATOMIC:
2747 cpu_exec_step_atomic(cs);
2748 break;
2749 default:
2750 printf ("Unhandled trap: 0x%x\n", trapnr);
2751 cpu_dump_state(cs, stderr, fprintf, 0);
2752 exit(EXIT_FAILURE);
2753 }
2754 process_pending_signals (env);
2755 }
2756 }
2757 #endif
2758
2759 #ifdef TARGET_CRIS
2760 void cpu_loop(CPUCRISState *env)
2761 {
2762 CPUState *cs = CPU(cris_env_get_cpu(env));
2763 int trapnr, ret;
2764 target_siginfo_t info;
2765
2766 while (1) {
2767 cpu_exec_start(cs);
2768 trapnr = cpu_exec(cs);
2769 cpu_exec_end(cs);
2770 process_queued_cpu_work(cs);
2771
2772 switch (trapnr) {
2773 case 0xaa:
2774 {
2775 info.si_signo = TARGET_SIGSEGV;
2776 info.si_errno = 0;
2777 /* XXX: check env->error_code */
2778 info.si_code = TARGET_SEGV_MAPERR;
2779 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2780 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2781 }
2782 break;
2783 case EXCP_INTERRUPT:
2784 /* just indicate that signals should be handled asap */
2785 break;
2786 case EXCP_BREAK:
2787 ret = do_syscall(env,
2788 env->regs[9],
2789 env->regs[10],
2790 env->regs[11],
2791 env->regs[12],
2792 env->regs[13],
2793 env->pregs[7],
2794 env->pregs[11],
2795 0, 0);
2796 if (ret == -TARGET_ERESTARTSYS) {
2797 env->pc -= 2;
2798 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2799 env->regs[10] = ret;
2800 }
2801 break;
2802 case EXCP_DEBUG:
2803 {
2804 int sig;
2805
2806 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2807 if (sig)
2808 {
2809 info.si_signo = sig;
2810 info.si_errno = 0;
2811 info.si_code = TARGET_TRAP_BRKPT;
2812 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2813 }
2814 }
2815 break;
2816 case EXCP_ATOMIC:
2817 cpu_exec_step_atomic(cs);
2818 break;
2819 default:
2820 printf ("Unhandled trap: 0x%x\n", trapnr);
2821 cpu_dump_state(cs, stderr, fprintf, 0);
2822 exit(EXIT_FAILURE);
2823 }
2824 process_pending_signals (env);
2825 }
2826 }
2827 #endif
2828
2829 #ifdef TARGET_MICROBLAZE
2830 void cpu_loop(CPUMBState *env)
2831 {
2832 CPUState *cs = CPU(mb_env_get_cpu(env));
2833 int trapnr, ret;
2834 target_siginfo_t info;
2835
2836 while (1) {
2837 cpu_exec_start(cs);
2838 trapnr = cpu_exec(cs);
2839 cpu_exec_end(cs);
2840 process_queued_cpu_work(cs);
2841
2842 switch (trapnr) {
2843 case 0xaa:
2844 {
2845 info.si_signo = TARGET_SIGSEGV;
2846 info.si_errno = 0;
2847 /* XXX: check env->error_code */
2848 info.si_code = TARGET_SEGV_MAPERR;
2849 info._sifields._sigfault._addr = 0;
2850 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2851 }
2852 break;
2853 case EXCP_INTERRUPT:
2854 /* just indicate that signals should be handled asap */
2855 break;
2856 case EXCP_BREAK:
2857 /* Return address is 4 bytes after the call. */
2858 env->regs[14] += 4;
2859 env->sregs[SR_PC] = env->regs[14];
2860 ret = do_syscall(env,
2861 env->regs[12],
2862 env->regs[5],
2863 env->regs[6],
2864 env->regs[7],
2865 env->regs[8],
2866 env->regs[9],
2867 env->regs[10],
2868 0, 0);
2869 if (ret == -TARGET_ERESTARTSYS) {
2870 /* Wind back to before the syscall. */
2871 env->sregs[SR_PC] -= 4;
2872 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2873 env->regs[3] = ret;
2874 }
2875 /* All syscall exits result in guest r14 being equal to the
2876 * PC we return to, because the kernel syscall exit "rtbd" does
2877 * this. (This is true even for sigreturn(); note that r14 is
2878 * not a userspace-usable register, as the kernel may clobber it
2879 * at any point.)
2880 */
2881 env->regs[14] = env->sregs[SR_PC];
2882 break;
2883 case EXCP_HW_EXCP:
2884 env->regs[17] = env->sregs[SR_PC] + 4;
2885 if (env->iflags & D_FLAG) {
2886 env->sregs[SR_ESR] |= 1 << 12;
2887 env->sregs[SR_PC] -= 4;
2888 /* FIXME: if branch was immed, replay the imm as well. */
2889 }
2890
2891 env->iflags &= ~(IMM_FLAG | D_FLAG);
2892
2893 switch (env->sregs[SR_ESR] & 31) {
2894 case ESR_EC_DIVZERO:
2895 info.si_signo = TARGET_SIGFPE;
2896 info.si_errno = 0;
2897 info.si_code = TARGET_FPE_FLTDIV;
2898 info._sifields._sigfault._addr = 0;
2899 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2900 break;
2901 case ESR_EC_FPU:
2902 info.si_signo = TARGET_SIGFPE;
2903 info.si_errno = 0;
2904 if (env->sregs[SR_FSR] & FSR_IO) {
2905 info.si_code = TARGET_FPE_FLTINV;
2906 }
2907 if (env->sregs[SR_FSR] & FSR_DZ) {
2908 info.si_code = TARGET_FPE_FLTDIV;
2909 }
2910 info._sifields._sigfault._addr = 0;
2911 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2912 break;
2913 default:
2914 printf ("Unhandled hw-exception: 0x%x\n",
2915 env->sregs[SR_ESR] & ESR_EC_MASK);
2916 cpu_dump_state(cs, stderr, fprintf, 0);
2917 exit(EXIT_FAILURE);
2918 break;
2919 }
2920 break;
2921 case EXCP_DEBUG:
2922 {
2923 int sig;
2924
2925 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2926 if (sig)
2927 {
2928 info.si_signo = sig;
2929 info.si_errno = 0;
2930 info.si_code = TARGET_TRAP_BRKPT;
2931 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2932 }
2933 }
2934 break;
2935 case EXCP_ATOMIC:
2936 cpu_exec_step_atomic(cs);
2937 break;
2938 default:
2939 printf ("Unhandled trap: 0x%x\n", trapnr);
2940 cpu_dump_state(cs, stderr, fprintf, 0);
2941 exit(EXIT_FAILURE);
2942 }
2943 process_pending_signals (env);
2944 }
2945 }
2946 #endif
2947
2948 #ifdef TARGET_M68K
2949
2950 void cpu_loop(CPUM68KState *env)
2951 {
2952 CPUState *cs = CPU(m68k_env_get_cpu(env));
2953 int trapnr;
2954 unsigned int n;
2955 target_siginfo_t info;
2956 TaskState *ts = cs->opaque;
2957
2958 for(;;) {
2959 cpu_exec_start(cs);
2960 trapnr = cpu_exec(cs);
2961 cpu_exec_end(cs);
2962 process_queued_cpu_work(cs);
2963
2964 switch(trapnr) {
2965 case EXCP_ILLEGAL:
2966 {
2967 if (ts->sim_syscalls) {
2968 uint16_t nr;
2969 get_user_u16(nr, env->pc + 2);
2970 env->pc += 4;
2971 do_m68k_simcall(env, nr);
2972 } else {
2973 goto do_sigill;
2974 }
2975 }
2976 break;
2977 case EXCP_HALT_INSN:
2978 /* Semihosing syscall. */
2979 env->pc += 4;
2980 do_m68k_semihosting(env, env->dregs[0]);
2981 break;
2982 case EXCP_LINEA:
2983 case EXCP_LINEF:
2984 case EXCP_UNSUPPORTED:
2985 do_sigill:
2986 info.si_signo = TARGET_SIGILL;
2987 info.si_errno = 0;
2988 info.si_code = TARGET_ILL_ILLOPN;
2989 info._sifields._sigfault._addr = env->pc;
2990 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2991 break;
2992 case EXCP_TRAP0:
2993 {
2994 abi_long ret;
2995 ts->sim_syscalls = 0;
2996 n = env->dregs[0];
2997 env->pc += 2;
2998 ret = do_syscall(env,
2999 n,
3000 env->dregs[1],
3001 env->dregs[2],
3002 env->dregs[3],
3003 env->dregs[4],
3004 env->dregs[5],
3005 env->aregs[0],
3006 0, 0);
3007 if (ret == -TARGET_ERESTARTSYS) {
3008 env->pc -= 2;
3009 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3010 env->dregs[0] = ret;
3011 }
3012 }
3013 break;
3014 case EXCP_INTERRUPT:
3015 /* just indicate that signals should be handled asap */
3016 break;
3017 case EXCP_ACCESS:
3018 {
3019 info.si_signo = TARGET_SIGSEGV;
3020 info.si_errno = 0;
3021 /* XXX: check env->error_code */
3022 info.si_code = TARGET_SEGV_MAPERR;
3023 info._sifields._sigfault._addr = env->mmu.ar;
3024 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3025 }
3026 break;
3027 case EXCP_DEBUG:
3028 {
3029 int sig;
3030
3031 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3032 if (sig)
3033 {
3034 info.si_signo = sig;
3035 info.si_errno = 0;
3036 info.si_code = TARGET_TRAP_BRKPT;
3037 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3038 }
3039 }
3040 break;
3041 case EXCP_ATOMIC:
3042 cpu_exec_step_atomic(cs);
3043 break;
3044 default:
3045 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3046 abort();
3047 }
3048 process_pending_signals(env);
3049 }
3050 }
3051 #endif /* TARGET_M68K */
3052
3053 #ifdef TARGET_ALPHA
3054 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3055 {
3056 target_ulong addr, val, tmp;
3057 target_siginfo_t info;
3058 int ret = 0;
3059
3060 addr = env->lock_addr;
3061 tmp = env->lock_st_addr;
3062 env->lock_addr = -1;
3063 env->lock_st_addr = 0;
3064
3065 start_exclusive();
3066 mmap_lock();
3067
3068 if (addr == tmp) {
3069 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3070 goto do_sigsegv;
3071 }
3072
3073 if (val == env->lock_value) {
3074 tmp = env->ir[reg];
3075 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3076 goto do_sigsegv;
3077 }
3078 ret = 1;
3079 }
3080 }
3081 env->ir[reg] = ret;
3082 env->pc += 4;
3083
3084 mmap_unlock();
3085 end_exclusive();
3086 return;
3087
3088 do_sigsegv:
3089 mmap_unlock();
3090 end_exclusive();
3091
3092 info.si_signo = TARGET_SIGSEGV;
3093 info.si_errno = 0;
3094 info.si_code = TARGET_SEGV_MAPERR;
3095 info._sifields._sigfault._addr = addr;
3096 queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info);
3097 }
3098
3099 void cpu_loop(CPUAlphaState *env)
3100 {
3101 CPUState *cs = CPU(alpha_env_get_cpu(env));
3102 int trapnr;
3103 target_siginfo_t info;
3104 abi_long sysret;
3105
3106 while (1) {
3107 cpu_exec_start(cs);
3108 trapnr = cpu_exec(cs);
3109 cpu_exec_end(cs);
3110 process_queued_cpu_work(cs);
3111
3112 /* All of the traps imply a transition through PALcode, which
3113 implies an REI instruction has been executed. Which means
3114 that the intr_flag should be cleared. */
3115 env->intr_flag = 0;
3116
3117 switch (trapnr) {
3118 case EXCP_RESET:
3119 fprintf(stderr, "Reset requested. Exit\n");
3120 exit(EXIT_FAILURE);
3121 break;
3122 case EXCP_MCHK:
3123 fprintf(stderr, "Machine check exception. Exit\n");
3124 exit(EXIT_FAILURE);
3125 break;
3126 case EXCP_SMP_INTERRUPT:
3127 case EXCP_CLK_INTERRUPT:
3128 case EXCP_DEV_INTERRUPT:
3129 fprintf(stderr, "External interrupt. Exit\n");
3130 exit(EXIT_FAILURE);
3131 break;
3132 case EXCP_MMFAULT:
3133 env->lock_addr = -1;
3134 info.si_signo = TARGET_SIGSEGV;
3135 info.si_errno = 0;
3136 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3137 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3138 info._sifields._sigfault._addr = env->trap_arg0;
3139 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3140 break;
3141 case EXCP_UNALIGN:
3142 env->lock_addr = -1;
3143 info.si_signo = TARGET_SIGBUS;
3144 info.si_errno = 0;
3145 info.si_code = TARGET_BUS_ADRALN;
3146 info._sifields._sigfault._addr = env->trap_arg0;
3147 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3148 break;
3149 case EXCP_OPCDEC:
3150 do_sigill:
3151 env->lock_addr = -1;
3152 info.si_signo = TARGET_SIGILL;
3153 info.si_errno = 0;
3154 info.si_code = TARGET_ILL_ILLOPC;
3155 info._sifields._sigfault._addr = env->pc;
3156 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3157 break;
3158 case EXCP_ARITH:
3159 env->lock_addr = -1;
3160 info.si_signo = TARGET_SIGFPE;
3161 info.si_errno = 0;
3162 info.si_code = TARGET_FPE_FLTINV;
3163 info._sifields._sigfault._addr = env->pc;
3164 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3165 break;
3166 case EXCP_FEN:
3167 /* No-op. Linux simply re-enables the FPU. */
3168 break;
3169 case EXCP_CALL_PAL:
3170 env->lock_addr = -1;
3171 switch (env->error_code) {
3172 case 0x80:
3173 /* BPT */
3174 info.si_signo = TARGET_SIGTRAP;
3175 info.si_errno = 0;
3176 info.si_code = TARGET_TRAP_BRKPT;
3177 info._sifields._sigfault._addr = env->pc;
3178 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3179 break;
3180 case 0x81:
3181 /* BUGCHK */
3182 info.si_signo = TARGET_SIGTRAP;
3183 info.si_errno = 0;
3184 info.si_code = 0;
3185 info._sifields._sigfault._addr = env->pc;
3186 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3187 break;
3188 case 0x83:
3189 /* CALLSYS */
3190 trapnr = env->ir[IR_V0];
3191 sysret = do_syscall(env, trapnr,
3192 env->ir[IR_A0], env->ir[IR_A1],
3193 env->ir[IR_A2], env->ir[IR_A3],
3194 env->ir[IR_A4], env->ir[IR_A5],
3195 0, 0);
3196 if (sysret == -TARGET_ERESTARTSYS) {
3197 env->pc -= 4;
3198 break;
3199 }
3200 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3201 break;
3202 }
3203 /* Syscall writes 0 to V0 to bypass error check, similar
3204 to how this is handled internal to Linux kernel.
3205 (Ab)use trapnr temporarily as boolean indicating error. */
3206 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3207 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3208 env->ir[IR_A3] = trapnr;
3209 break;
3210 case 0x86:
3211 /* IMB */
3212 /* ??? We can probably elide the code using page_unprotect
3213 that is checking for self-modifying code. Instead we
3214 could simply call tb_flush here. Until we work out the
3215 changes required to turn off the extra write protection,
3216 this can be a no-op. */
3217 break;
3218 case 0x9E:
3219 /* RDUNIQUE */
3220 /* Handled in the translator for usermode. */
3221 abort();
3222 case 0x9F:
3223 /* WRUNIQUE */
3224 /* Handled in the translator for usermode. */
3225 abort();
3226 case 0xAA:
3227 /* GENTRAP */
3228 info.si_signo = TARGET_SIGFPE;
3229 switch (env->ir[IR_A0]) {
3230 case TARGET_GEN_INTOVF:
3231 info.si_code = TARGET_FPE_INTOVF;
3232 break;
3233 case TARGET_GEN_INTDIV:
3234 info.si_code = TARGET_FPE_INTDIV;
3235 break;
3236 case TARGET_GEN_FLTOVF:
3237 info.si_code = TARGET_FPE_FLTOVF;
3238 break;
3239 case TARGET_GEN_FLTUND:
3240 info.si_code = TARGET_FPE_FLTUND;
3241 break;
3242 case TARGET_GEN_FLTINV:
3243 info.si_code = TARGET_FPE_FLTINV;
3244 break;
3245 case TARGET_GEN_FLTINE:
3246 info.si_code = TARGET_FPE_FLTRES;
3247 break;
3248 case TARGET_GEN_ROPRAND:
3249 info.si_code = 0;
3250 break;
3251 default:
3252 info.si_signo = TARGET_SIGTRAP;
3253 info.si_code = 0;
3254 break;
3255 }
3256 info.si_errno = 0;
3257 info._sifields._sigfault._addr = env->pc;
3258 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3259 break;
3260 default:
3261 goto do_sigill;
3262 }
3263 break;
3264 case EXCP_DEBUG:
3265 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3266 if (info.si_signo) {
3267 env->lock_addr = -1;
3268 info.si_errno = 0;
3269 info.si_code = TARGET_TRAP_BRKPT;
3270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3271 }
3272 break;
3273 case EXCP_STL_C:
3274 case EXCP_STQ_C:
3275 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3276 break;
3277 case EXCP_INTERRUPT:
3278 /* Just indicate that signals should be handled asap. */
3279 break;
3280 case EXCP_ATOMIC:
3281 cpu_exec_step_atomic(cs);
3282 break;
3283 default:
3284 printf ("Unhandled trap: 0x%x\n", trapnr);
3285 cpu_dump_state(cs, stderr, fprintf, 0);
3286 exit(EXIT_FAILURE);
3287 }
3288 process_pending_signals (env);
3289 }
3290 }
3291 #endif /* TARGET_ALPHA */
3292
3293 #ifdef TARGET_S390X
3294 void cpu_loop(CPUS390XState *env)
3295 {
3296 CPUState *cs = CPU(s390_env_get_cpu(env));
3297 int trapnr, n, sig;
3298 target_siginfo_t info;
3299 target_ulong addr;
3300 abi_long ret;
3301
3302 while (1) {
3303 cpu_exec_start(cs);
3304 trapnr = cpu_exec(cs);
3305 cpu_exec_end(cs);
3306 process_queued_cpu_work(cs);
3307
3308 switch (trapnr) {
3309 case EXCP_INTERRUPT:
3310 /* Just indicate that signals should be handled asap. */
3311 break;
3312
3313 case EXCP_SVC:
3314 n = env->int_svc_code;
3315 if (!n) {
3316 /* syscalls > 255 */
3317 n = env->regs[1];
3318 }
3319 env->psw.addr += env->int_svc_ilen;
3320 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3321 env->regs[4], env->regs[5],
3322 env->regs[6], env->regs[7], 0, 0);
3323 if (ret == -TARGET_ERESTARTSYS) {
3324 env->psw.addr -= env->int_svc_ilen;
3325 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3326 env->regs[2] = ret;
3327 }
3328 break;
3329
3330 case EXCP_DEBUG:
3331 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3332 if (sig) {
3333 n = TARGET_TRAP_BRKPT;
3334 goto do_signal_pc;
3335 }
3336 break;
3337 case EXCP_PGM:
3338 n = env->int_pgm_code;
3339 switch (n) {
3340 case PGM_OPERATION:
3341 case PGM_PRIVILEGED:
3342 sig = TARGET_SIGILL;
3343 n = TARGET_ILL_ILLOPC;
3344 goto do_signal_pc;
3345 case PGM_PROTECTION:
3346 case PGM_ADDRESSING:
3347 sig = TARGET_SIGSEGV;
3348 /* XXX: check env->error_code */
3349 n = TARGET_SEGV_MAPERR;
3350 addr = env->__excp_addr;
3351 goto do_signal;
3352 case PGM_EXECUTE:
3353 case PGM_SPECIFICATION:
3354 case PGM_SPECIAL_OP:
3355 case PGM_OPERAND:
3356 do_sigill_opn:
3357 sig = TARGET_SIGILL;
3358 n = TARGET_ILL_ILLOPN;
3359 goto do_signal_pc;
3360
3361 case PGM_FIXPT_OVERFLOW:
3362 sig = TARGET_SIGFPE;
3363 n = TARGET_FPE_INTOVF;
3364 goto do_signal_pc;
3365 case PGM_FIXPT_DIVIDE:
3366 sig = TARGET_SIGFPE;
3367 n = TARGET_FPE_INTDIV;
3368 goto do_signal_pc;
3369
3370 case PGM_DATA:
3371 n = (env->fpc >> 8) & 0xff;
3372 if (n == 0xff) {
3373 /* compare-and-trap */
3374 goto do_sigill_opn;
3375 } else {
3376 /* An IEEE exception, simulated or otherwise. */
3377 if (n & 0x80) {
3378 n = TARGET_FPE_FLTINV;
3379 } else if (n & 0x40) {
3380 n = TARGET_FPE_FLTDIV;
3381 } else if (n & 0x20) {
3382 n = TARGET_FPE_FLTOVF;
3383 } else if (n & 0x10) {
3384 n = TARGET_FPE_FLTUND;
3385 } else if (n & 0x08) {
3386 n = TARGET_FPE_FLTRES;
3387 } else {
3388 /* ??? Quantum exception; BFP, DFP error. */
3389 goto do_sigill_opn;
3390 }
3391 sig = TARGET_SIGFPE;
3392 goto do_signal_pc;
3393 }
3394
3395 default:
3396 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3397 cpu_dump_state(cs, stderr, fprintf, 0);
3398 exit(EXIT_FAILURE);
3399 }
3400 break;
3401
3402 do_signal_pc:
3403 addr = env->psw.addr;
3404 do_signal:
3405 info.si_signo = sig;
3406 info.si_errno = 0;
3407 info.si_code = n;
3408 info._sifields._sigfault._addr = addr;
3409 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3410 break;
3411
3412 case EXCP_ATOMIC:
3413 cpu_exec_step_atomic(cs);
3414 break;
3415 default:
3416 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3417 cpu_dump_state(cs, stderr, fprintf, 0);
3418 exit(EXIT_FAILURE);
3419 }
3420 process_pending_signals (env);
3421 }
3422 }
3423
3424 #endif /* TARGET_S390X */
3425
3426 #ifdef TARGET_TILEGX
3427
3428 static void gen_sigill_reg(CPUTLGState *env)
3429 {
3430 target_siginfo_t info;
3431
3432 info.si_signo = TARGET_SIGILL;
3433 info.si_errno = 0;
3434 info.si_code = TARGET_ILL_PRVREG;
3435 info._sifields._sigfault._addr = env->pc;
3436 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3437 }
3438
3439 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3440 {
3441 target_siginfo_t info;
3442
3443 info.si_signo = signo;
3444 info.si_errno = 0;
3445 info._sifields._sigfault._addr = env->pc;
3446
3447 if (signo == TARGET_SIGSEGV) {
3448 /* The passed in sigcode is a dummy; check for a page mapping
3449 and pass either MAPERR or ACCERR. */
3450 target_ulong addr = env->excaddr;
3451 info._sifields._sigfault._addr = addr;
3452 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3453 sigcode = TARGET_SEGV_MAPERR;
3454 } else {
3455 sigcode = TARGET_SEGV_ACCERR;
3456 }
3457 }
3458 info.si_code = sigcode;
3459
3460 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3461 }
3462
3463 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3464 {
3465 env->excaddr = addr;
3466 do_signal(env, TARGET_SIGSEGV, 0);
3467 }
3468
3469 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3470 {
3471 if (unlikely(reg >= TILEGX_R_COUNT)) {
3472 switch (reg) {
3473 case TILEGX_R_SN:
3474 case TILEGX_R_ZERO:
3475 return;
3476 case TILEGX_R_IDN0:
3477 case TILEGX_R_IDN1:
3478 case TILEGX_R_UDN0:
3479 case TILEGX_R_UDN1:
3480 case TILEGX_R_UDN2:
3481 case TILEGX_R_UDN3:
3482 gen_sigill_reg(env);
3483 return;
3484 default:
3485 g_assert_not_reached();
3486 }
3487 }
3488 env->regs[reg] = val;
3489 }
3490
3491 /*
3492 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3493 * memory at the address held in the first source register. If the values are
3494 * not equal, then no memory operation is performed. If the values are equal,
3495 * the 8-byte quantity from the second source register is written into memory
3496 * at the address held in the first source register. In either case, the result
3497 * of the instruction is the value read from memory. The compare and write to
3498 * memory are atomic and thus can be used for synchronization purposes. This
3499 * instruction only operates for addresses aligned to a 8-byte boundary.
3500 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3501 *
3502 * Functional Description (64-bit)
3503 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3504 * rf[Dest] = memVal;
3505 * if (memVal == SPR[CmpValueSPR])
3506 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3507 *
3508 * Functional Description (32-bit)
3509 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3510 * rf[Dest] = memVal;
3511 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3512 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3513 *
3514 *
3515 * This function also processes exch and exch4 which need not process SPR.
3516 */
3517 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3518 {
3519 target_ulong addr;
3520 target_long val, sprval;
3521
3522 start_exclusive();
3523
3524 addr = env->atomic_srca;
3525 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3526 goto sigsegv_maperr;
3527 }
3528
3529 if (cmp) {
3530 if (quad) {
3531 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3532 } else {
3533 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3534 }
3535 }
3536
3537 if (!cmp || val == sprval) {
3538 target_long valb = env->atomic_srcb;
3539 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3540 goto sigsegv_maperr;
3541 }
3542 }
3543
3544 set_regval(env, env->atomic_dstr, val);
3545 end_exclusive();
3546 return;
3547
3548 sigsegv_maperr:
3549 end_exclusive();
3550 gen_sigsegv_maperr(env, addr);
3551 }
3552
3553 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3554 {
3555 int8_t write = 1;
3556 target_ulong addr;
3557 target_long val, valb;
3558
3559 start_exclusive();
3560
3561 addr = env->atomic_srca;
3562 valb = env->atomic_srcb;
3563 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3564 goto sigsegv_maperr;
3565 }
3566
3567 switch (trapnr) {
3568 case TILEGX_EXCP_OPCODE_FETCHADD:
3569 case TILEGX_EXCP_OPCODE_FETCHADD4:
3570 valb += val;
3571 break;
3572 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3573 valb += val;
3574 if (valb < 0) {
3575 write = 0;
3576 }
3577 break;
3578 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3579 valb += val;
3580 if ((int32_t)valb < 0) {
3581 write = 0;
3582 }
3583 break;
3584 case TILEGX_EXCP_OPCODE_FETCHAND:
3585 case TILEGX_EXCP_OPCODE_FETCHAND4:
3586 valb &= val;
3587 break;
3588 case TILEGX_EXCP_OPCODE_FETCHOR:
3589 case TILEGX_EXCP_OPCODE_FETCHOR4:
3590 valb |= val;
3591 break;
3592 default:
3593 g_assert_not_reached();
3594 }
3595
3596 if (write) {
3597 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3598 goto sigsegv_maperr;
3599 }
3600 }
3601
3602 set_regval(env, env->atomic_dstr, val);
3603 end_exclusive();
3604 return;
3605
3606 sigsegv_maperr:
3607 end_exclusive();
3608 gen_sigsegv_maperr(env, addr);
3609 }
3610
3611 void cpu_loop(CPUTLGState *env)
3612 {
3613 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3614 int trapnr;
3615
3616 while (1) {
3617 cpu_exec_start(cs);
3618 trapnr = cpu_exec(cs);
3619 cpu_exec_end(cs);
3620 process_queued_cpu_work(cs);
3621
3622 switch (trapnr) {
3623 case TILEGX_EXCP_SYSCALL:
3624 {
3625 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3626 env->regs[0], env->regs[1],
3627 env->regs[2], env->regs[3],
3628 env->regs[4], env->regs[5],
3629 env->regs[6], env->regs[7]);
3630 if (ret == -TARGET_ERESTARTSYS) {
3631 env->pc -= 8;
3632 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3633 env->regs[TILEGX_R_RE] = ret;
3634 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3635 }
3636 break;
3637 }
3638 case TILEGX_EXCP_OPCODE_EXCH:
3639 do_exch(env, true, false);
3640 break;
3641 case TILEGX_EXCP_OPCODE_EXCH4:
3642 do_exch(env, false, false);
3643 break;
3644 case TILEGX_EXCP_OPCODE_CMPEXCH:
3645 do_exch(env, true, true);
3646 break;
3647 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3648 do_exch(env, false, true);
3649 break;
3650 case TILEGX_EXCP_OPCODE_FETCHADD:
3651 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3652 case TILEGX_EXCP_OPCODE_FETCHAND:
3653 case TILEGX_EXCP_OPCODE_FETCHOR:
3654 do_fetch(env, trapnr, true);
3655 break;
3656 case TILEGX_EXCP_OPCODE_FETCHADD4:
3657 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3658 case TILEGX_EXCP_OPCODE_FETCHAND4:
3659 case TILEGX_EXCP_OPCODE_FETCHOR4:
3660 do_fetch(env, trapnr, false);
3661 break;
3662 case TILEGX_EXCP_SIGNAL:
3663 do_signal(env, env->signo, env->sigcode);
3664 break;
3665 case TILEGX_EXCP_REG_IDN_ACCESS:
3666 case TILEGX_EXCP_REG_UDN_ACCESS:
3667 gen_sigill_reg(env);
3668 break;
3669 case EXCP_ATOMIC:
3670 cpu_exec_step_atomic(cs);
3671 break;
3672 default:
3673 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3674 g_assert_not_reached();
3675 }
3676 process_pending_signals(env);
3677 }
3678 }
3679
3680 #endif
3681
3682 THREAD CPUState *thread_cpu;
3683
3684 bool qemu_cpu_is_self(CPUState *cpu)
3685 {
3686 return thread_cpu == cpu;
3687 }
3688
3689 void qemu_cpu_kick(CPUState *cpu)
3690 {
3691 cpu_exit(cpu);
3692 }
3693
3694 void task_settid(TaskState *ts)
3695 {
3696 if (ts->ts_tid == 0) {
3697 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3698 }
3699 }
3700
3701 void stop_all_tasks(void)
3702 {
3703 /*
3704 * We trust that when using NPTL, start_exclusive()
3705 * handles thread stopping correctly.
3706 */
3707 start_exclusive();
3708 }
3709
3710 /* Assumes contents are already zeroed. */
3711 void init_task_state(TaskState *ts)
3712 {
3713 ts->used = 1;
3714 }
3715
3716 CPUArchState *cpu_copy(CPUArchState *env)
3717 {
3718 CPUState *cpu = ENV_GET_CPU(env);
3719 CPUState *new_cpu = cpu_init(cpu_model);
3720 CPUArchState *new_env = new_cpu->env_ptr;
3721 CPUBreakpoint *bp;
3722 CPUWatchpoint *wp;
3723
3724 /* Reset non arch specific state */
3725 cpu_reset(new_cpu);
3726
3727 memcpy(new_env, env, sizeof(CPUArchState));
3728
3729 /* Clone all break/watchpoints.
3730 Note: Once we support ptrace with hw-debug register access, make sure
3731 BP_CPU break/watchpoints are handled correctly on clone. */
3732 QTAILQ_INIT(&new_cpu->breakpoints);
3733 QTAILQ_INIT(&new_cpu->watchpoints);
3734 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3735 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3736 }
3737 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3738 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3739 }
3740
3741 return new_env;
3742 }
3743
3744 static void handle_arg_help(const char *arg)
3745 {
3746 usage(EXIT_SUCCESS);
3747 }
3748
3749 static void handle_arg_log(const char *arg)
3750 {
3751 int mask;
3752
3753 mask = qemu_str_to_log_mask(arg);
3754 if (!mask) {
3755 qemu_print_log_usage(stdout);
3756 exit(EXIT_FAILURE);
3757 }
3758 qemu_log_needs_buffers();
3759 qemu_set_log(mask);
3760 }
3761
3762 static void handle_arg_log_filename(const char *arg)
3763 {
3764 qemu_set_log_filename(arg, &error_fatal);
3765 }
3766
3767 static void handle_arg_set_env(const char *arg)
3768 {
3769 char *r, *p, *token;
3770 r = p = strdup(arg);
3771 while ((token = strsep(&p, ",")) != NULL) {
3772 if (envlist_setenv(envlist, token) != 0) {
3773 usage(EXIT_FAILURE);
3774 }
3775 }
3776 free(r);
3777 }
3778
3779 static void handle_arg_unset_env(const char *arg)
3780 {
3781 char *r, *p, *token;
3782 r = p = strdup(arg);
3783 while ((token = strsep(&p, ",")) != NULL) {
3784 if (envlist_unsetenv(envlist, token) != 0) {
3785 usage(EXIT_FAILURE);
3786 }
3787 }
3788 free(r);
3789 }
3790
3791 static void handle_arg_argv0(const char *arg)
3792 {
3793 argv0 = strdup(arg);
3794 }
3795
3796 static void handle_arg_stack_size(const char *arg)
3797 {
3798 char *p;
3799 guest_stack_size = strtoul(arg, &p, 0);
3800 if (guest_stack_size == 0) {
3801 usage(EXIT_FAILURE);
3802 }
3803
3804 if (*p == 'M') {
3805 guest_stack_size *= 1024 * 1024;
3806 } else if (*p == 'k' || *p == 'K') {
3807 guest_stack_size *= 1024;
3808 }
3809 }
3810
3811 static void handle_arg_ld_prefix(const char *arg)
3812 {
3813 interp_prefix = strdup(arg);
3814 }
3815
3816 static void handle_arg_pagesize(const char *arg)
3817 {
3818 qemu_host_page_size = atoi(arg);
3819 if (qemu_host_page_size == 0 ||
3820 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3821 fprintf(stderr, "page size must be a power of two\n");
3822 exit(EXIT_FAILURE);
3823 }
3824 }
3825
3826 static void handle_arg_randseed(const char *arg)
3827 {
3828 unsigned long long seed;
3829
3830 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3831 fprintf(stderr, "Invalid seed number: %s\n", arg);
3832 exit(EXIT_FAILURE);
3833 }
3834 srand(seed);
3835 }
3836
3837 static void handle_arg_gdb(const char *arg)
3838 {
3839 gdbstub_port = atoi(arg);
3840 }
3841
3842 static void handle_arg_uname(const char *arg)
3843 {
3844 qemu_uname_release = strdup(arg);
3845 }
3846
3847 static void handle_arg_cpu(const char *arg)
3848 {
3849 cpu_model = strdup(arg);
3850 if (cpu_model == NULL || is_help_option(cpu_model)) {
3851 /* XXX: implement xxx_cpu_list for targets that still miss it */
3852 #if defined(cpu_list)
3853 cpu_list(stdout, &fprintf);
3854 #endif
3855 exit(EXIT_FAILURE);
3856 }
3857 }
3858
3859 static void handle_arg_guest_base(const char *arg)
3860 {
3861 guest_base = strtol(arg, NULL, 0);
3862 have_guest_base = 1;
3863 }
3864
3865 static void handle_arg_reserved_va(const char *arg)
3866 {
3867 char *p;
3868 int shift = 0;
3869 reserved_va = strtoul(arg, &p, 0);
3870 switch (*p) {
3871 case 'k':
3872 case 'K':
3873 shift = 10;
3874 break;
3875 case 'M':
3876 shift = 20;
3877 break;
3878 case 'G':
3879 shift = 30;
3880 break;
3881 }
3882 if (shift) {
3883 unsigned long unshifted = reserved_va;
3884 p++;
3885 reserved_va <<= shift;
3886 if (((reserved_va >> shift) != unshifted)
3887 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3888 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3889 #endif
3890 ) {
3891 fprintf(stderr, "Reserved virtual address too big\n");
3892 exit(EXIT_FAILURE);
3893 }
3894 }
3895 if (*p) {
3896 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3897 exit(EXIT_FAILURE);
3898 }
3899 }
3900
3901 static void handle_arg_singlestep(const char *arg)
3902 {
3903 singlestep = 1;
3904 }
3905
3906 static void handle_arg_strace(const char *arg)
3907 {
3908 do_strace = 1;
3909 }
3910
3911 static void handle_arg_version(const char *arg)
3912 {
3913 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3914 "\n" QEMU_COPYRIGHT "\n");
3915 exit(EXIT_SUCCESS);
3916 }
3917
3918 static char *trace_file;
3919 static void handle_arg_trace(const char *arg)
3920 {
3921 g_free(trace_file);
3922 trace_file = trace_opt_parse(arg);
3923 }
3924
3925 struct qemu_argument {
3926 const char *argv;
3927 const char *env;
3928 bool has_arg;
3929 void (*handle_opt)(const char *arg);
3930 const char *example;
3931 const char *help;
3932 };
3933
3934 static const struct qemu_argument arg_table[] = {
3935 {"h", "", false, handle_arg_help,
3936 "", "print this help"},
3937 {"help", "", false, handle_arg_help,
3938 "", ""},
3939 {"g", "QEMU_GDB", true, handle_arg_gdb,
3940 "port", "wait gdb connection to 'port'"},
3941 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3942 "path", "set the elf interpreter prefix to 'path'"},
3943 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3944 "size", "set the stack size to 'size' bytes"},
3945 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3946 "model", "select CPU (-cpu help for list)"},
3947 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3948 "var=value", "sets targets environment variable (see below)"},
3949 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3950 "var", "unsets targets environment variable (see below)"},
3951 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3952 "argv0", "forces target process argv[0] to be 'argv0'"},
3953 {"r", "QEMU_UNAME", true, handle_arg_uname,
3954 "uname", "set qemu uname release string to 'uname'"},
3955 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3956 "address", "set guest_base address to 'address'"},
3957 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3958 "size", "reserve 'size' bytes for guest virtual address space"},
3959 {"d", "QEMU_LOG", true, handle_arg_log,
3960 "item[,...]", "enable logging of specified items "
3961 "(use '-d help' for a list of items)"},
3962 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3963 "logfile", "write logs to 'logfile' (default stderr)"},
3964 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3965 "pagesize", "set the host page size to 'pagesize'"},
3966 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3967 "", "run in singlestep mode"},
3968 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3969 "", "log system calls"},
3970 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3971 "", "Seed for pseudo-random number generator"},
3972 {"trace", "QEMU_TRACE", true, handle_arg_trace,
3973 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
3974 {"version", "QEMU_VERSION", false, handle_arg_version,
3975 "", "display version information and exit"},
3976 {NULL, NULL, false, NULL, NULL, NULL}
3977 };
3978
3979 static void usage(int exitcode)
3980 {
3981 const struct qemu_argument *arginfo;
3982 int maxarglen;
3983 int maxenvlen;
3984
3985 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3986 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3987 "\n"
3988 "Options and associated environment variables:\n"
3989 "\n");
3990
3991 /* Calculate column widths. We must always have at least enough space
3992 * for the column header.
3993 */
3994 maxarglen = strlen("Argument");
3995 maxenvlen = strlen("Env-variable");
3996
3997 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3998 int arglen = strlen(arginfo->argv);
3999 if (arginfo->has_arg) {
4000 arglen += strlen(arginfo->example) + 1;
4001 }
4002 if (strlen(arginfo->env) > maxenvlen) {
4003 maxenvlen = strlen(arginfo->env);
4004 }
4005 if (arglen > maxarglen) {
4006 maxarglen = arglen;
4007 }
4008 }
4009
4010 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4011 maxenvlen, "Env-variable");
4012
4013 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4014 if (arginfo->has_arg) {
4015 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4016 (int)(maxarglen - strlen(arginfo->argv) - 1),
4017 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4018 } else {
4019 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4020 maxenvlen, arginfo->env,
4021 arginfo->help);
4022 }
4023 }
4024
4025 printf("\n"
4026 "Defaults:\n"
4027 "QEMU_LD_PREFIX = %s\n"
4028 "QEMU_STACK_SIZE = %ld byte\n",
4029 interp_prefix,
4030 guest_stack_size);
4031
4032 printf("\n"
4033 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4034 "QEMU_UNSET_ENV environment variables to set and unset\n"
4035 "environment variables for the target process.\n"
4036 "It is possible to provide several variables by separating them\n"
4037 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4038 "provide the -E and -U options multiple times.\n"
4039 "The following lines are equivalent:\n"
4040 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4041 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4042 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4043 "Note that if you provide several changes to a single variable\n"
4044 "the last change will stay in effect.\n");
4045
4046 exit(exitcode);
4047 }
4048
4049 static int parse_args(int argc, char **argv)
4050 {
4051 const char *r;
4052 int optind;
4053 const struct qemu_argument *arginfo;
4054
4055 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4056 if (arginfo->env == NULL) {
4057 continue;
4058 }
4059
4060 r = getenv(arginfo->env);
4061 if (r != NULL) {
4062 arginfo->handle_opt(r);
4063 }
4064 }
4065
4066 optind = 1;
4067 for (;;) {
4068 if (optind >= argc) {
4069 break;
4070 }
4071 r = argv[optind];
4072 if (r[0] != '-') {
4073 break;
4074 }
4075 optind++;
4076 r++;
4077 if (!strcmp(r, "-")) {
4078 break;
4079 }
4080 /* Treat --foo the same as -foo. */
4081 if (r[0] == '-') {
4082 r++;
4083 }
4084
4085 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4086 if (!strcmp(r, arginfo->argv)) {
4087 if (arginfo->has_arg) {
4088 if (optind >= argc) {
4089 (void) fprintf(stderr,
4090 "qemu: missing argument for option '%s'\n", r);
4091 exit(EXIT_FAILURE);
4092 }
4093 arginfo->handle_opt(argv[optind]);
4094 optind++;
4095 } else {
4096 arginfo->handle_opt(NULL);
4097 }
4098 break;
4099 }
4100 }
4101
4102 /* no option matched the current argv */
4103 if (arginfo->handle_opt == NULL) {
4104 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4105 exit(EXIT_FAILURE);
4106 }
4107 }
4108
4109 if (optind >= argc) {
4110 (void) fprintf(stderr, "qemu: no user program specified\n");
4111 exit(EXIT_FAILURE);
4112 }
4113
4114 filename = argv[optind];
4115 exec_path = argv[optind];
4116
4117 return optind;
4118 }
4119
4120 int main(int argc, char **argv, char **envp)
4121 {
4122 struct target_pt_regs regs1, *regs = &regs1;
4123 struct image_info info1, *info = &info1;
4124 struct linux_binprm bprm;
4125 TaskState *ts;
4126 CPUArchState *env;
4127 CPUState *cpu;
4128 int optind;
4129 char **target_environ, **wrk;
4130 char **target_argv;
4131 int target_argc;
4132 int i;
4133 int ret;
4134 int execfd;
4135
4136 module_call_init(MODULE_INIT_TRACE);
4137 qemu_init_cpu_list();
4138 module_call_init(MODULE_INIT_QOM);
4139
4140 if ((envlist = envlist_create()) == NULL) {
4141 (void) fprintf(stderr, "Unable to allocate envlist\n");
4142 exit(EXIT_FAILURE);
4143 }
4144
4145 /* add current environment into the list */
4146 for (wrk = environ; *wrk != NULL; wrk++) {
4147 (void) envlist_setenv(envlist, *wrk);
4148 }
4149
4150 /* Read the stack limit from the kernel. If it's "unlimited",
4151 then we can do little else besides use the default. */
4152 {
4153 struct rlimit lim;
4154 if (getrlimit(RLIMIT_STACK, &lim) == 0
4155 && lim.rlim_cur != RLIM_INFINITY
4156 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4157 guest_stack_size = lim.rlim_cur;
4158 }
4159 }
4160
4161 cpu_model = NULL;
4162
4163 srand(time(NULL));
4164
4165 qemu_add_opts(&qemu_trace_opts);
4166
4167 optind = parse_args(argc, argv);
4168
4169 if (!trace_init_backends()) {
4170 exit(1);
4171 }
4172 trace_init_file(trace_file);
4173
4174 /* Zero out regs */
4175 memset(regs, 0, sizeof(struct target_pt_regs));
4176
4177 /* Zero out image_info */
4178 memset(info, 0, sizeof(struct image_info));
4179
4180 memset(&bprm, 0, sizeof (bprm));
4181
4182 /* Scan interp_prefix dir for replacement files. */
4183 init_paths(interp_prefix);
4184
4185 init_qemu_uname_release();
4186
4187 if (cpu_model == NULL) {
4188 #if defined(TARGET_I386)
4189 #ifdef TARGET_X86_64
4190 cpu_model = "qemu64";
4191 #else
4192 cpu_model = "qemu32";
4193 #endif
4194 #elif defined(TARGET_ARM)
4195 cpu_model = "any";
4196 #elif defined(TARGET_UNICORE32)
4197 cpu_model = "any";
4198 #elif defined(TARGET_M68K)
4199 cpu_model = "any";
4200 #elif defined(TARGET_SPARC)
4201 #ifdef TARGET_SPARC64
4202 cpu_model = "TI UltraSparc II";
4203 #else
4204 cpu_model = "Fujitsu MB86904";
4205 #endif
4206 #elif defined(TARGET_MIPS)
4207 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4208 cpu_model = "5KEf";
4209 #else
4210 cpu_model = "24Kf";
4211 #endif
4212 #elif defined TARGET_OPENRISC
4213 cpu_model = "or1200";
4214 #elif defined(TARGET_PPC)
4215 # ifdef TARGET_PPC64
4216 cpu_model = "POWER8";
4217 # else
4218 cpu_model = "750";
4219 # endif
4220 #elif defined TARGET_SH4
4221 cpu_model = TYPE_SH7785_CPU;
4222 #else
4223 cpu_model = "any";
4224 #endif
4225 }
4226 tcg_exec_init(0);
4227 /* NOTE: we need to init the CPU at this stage to get
4228 qemu_host_page_size */
4229 cpu = cpu_init(cpu_model);
4230 if (!cpu) {
4231 fprintf(stderr, "Unable to find CPU definition\n");
4232 exit(EXIT_FAILURE);
4233 }
4234 env = cpu->env_ptr;
4235 cpu_reset(cpu);
4236
4237 thread_cpu = cpu;
4238
4239 if (getenv("QEMU_STRACE")) {
4240 do_strace = 1;
4241 }
4242
4243 if (getenv("QEMU_RAND_SEED")) {
4244 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4245 }
4246
4247 target_environ = envlist_to_environ(envlist, NULL);
4248 envlist_free(envlist);
4249
4250 /*
4251 * Now that page sizes are configured in cpu_init() we can do
4252 * proper page alignment for guest_base.
4253 */
4254 guest_base = HOST_PAGE_ALIGN(guest_base);
4255
4256 if (reserved_va || have_guest_base) {
4257 guest_base = init_guest_space(guest_base, reserved_va, 0,
4258 have_guest_base);
4259 if (guest_base == (unsigned long)-1) {
4260 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4261 "space for use as guest address space (check your virtual "
4262 "memory ulimit setting or reserve less using -R option)\n",
4263 reserved_va);
4264 exit(EXIT_FAILURE);
4265 }
4266
4267 if (reserved_va) {
4268 mmap_next_start = reserved_va;
4269 }
4270 }
4271
4272 /*
4273 * Read in mmap_min_addr kernel parameter. This value is used
4274 * When loading the ELF image to determine whether guest_base
4275 * is needed. It is also used in mmap_find_vma.
4276 */
4277 {
4278 FILE *fp;
4279
4280 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4281 unsigned long tmp;
4282 if (fscanf(fp, "%lu", &tmp) == 1) {
4283 mmap_min_addr = tmp;
4284 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4285 }
4286 fclose(fp);
4287 }
4288 }
4289
4290 /*
4291 * Prepare copy of argv vector for target.
4292 */
4293 target_argc = argc - optind;
4294 target_argv = calloc(target_argc + 1, sizeof (char *));
4295 if (target_argv == NULL) {
4296 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4297 exit(EXIT_FAILURE);
4298 }
4299
4300 /*
4301 * If argv0 is specified (using '-0' switch) we replace
4302 * argv[0] pointer with the given one.
4303 */
4304 i = 0;
4305 if (argv0 != NULL) {
4306 target_argv[i++] = strdup(argv0);
4307 }
4308 for (; i < target_argc; i++) {
4309 target_argv[i] = strdup(argv[optind + i]);
4310 }
4311 target_argv[target_argc] = NULL;
4312
4313 ts = g_new0(TaskState, 1);
4314 init_task_state(ts);
4315 /* build Task State */
4316 ts->info = info;
4317 ts->bprm = &bprm;
4318 cpu->opaque = ts;
4319 task_settid(ts);
4320
4321 execfd = qemu_getauxval(AT_EXECFD);
4322 if (execfd == 0) {
4323 execfd = open(filename, O_RDONLY);
4324 if (execfd < 0) {
4325 printf("Error while loading %s: %s\n", filename, strerror(errno));
4326 _exit(EXIT_FAILURE);
4327 }
4328 }
4329
4330 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4331 info, &bprm);
4332 if (ret != 0) {
4333 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4334 _exit(EXIT_FAILURE);
4335 }
4336
4337 for (wrk = target_environ; *wrk; wrk++) {
4338 free(*wrk);
4339 }
4340
4341 free(target_environ);
4342
4343 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4344 qemu_log("guest_base 0x%lx\n", guest_base);
4345 log_page_dump();
4346
4347 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4348 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4349 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4350 info->start_code);
4351 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4352 info->start_data);
4353 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4354 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4355 info->start_stack);
4356 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4357 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4358 }
4359
4360 target_set_brk(info->brk);
4361 syscall_init();
4362 signal_init();
4363
4364 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4365 generating the prologue until now so that the prologue can take
4366 the real value of GUEST_BASE into account. */
4367 tcg_prologue_init(&tcg_ctx);
4368
4369 #if defined(TARGET_I386)
4370 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4371 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4372 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4373 env->cr[4] |= CR4_OSFXSR_MASK;
4374 env->hflags |= HF_OSFXSR_MASK;
4375 }
4376 #ifndef TARGET_ABI32
4377 /* enable 64 bit mode if possible */
4378 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4379 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4380 exit(EXIT_FAILURE);
4381 }
4382 env->cr[4] |= CR4_PAE_MASK;
4383 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4384 env->hflags |= HF_LMA_MASK;
4385 #endif
4386
4387 /* flags setup : we activate the IRQs by default as in user mode */
4388 env->eflags |= IF_MASK;
4389
4390 /* linux register setup */
4391 #ifndef TARGET_ABI32
4392 env->regs[R_EAX] = regs->rax;
4393 env->regs[R_EBX] = regs->rbx;
4394 env->regs[R_ECX] = regs->rcx;
4395 env->regs[R_EDX] = regs->rdx;
4396 env->regs[R_ESI] = regs->rsi;
4397 env->regs[R_EDI] = regs->rdi;
4398 env->regs[R_EBP] = regs->rbp;
4399 env->regs[R_ESP] = regs->rsp;
4400 env->eip = regs->rip;
4401 #else
4402 env->regs[R_EAX] = regs->eax;
4403 env->regs[R_EBX] = regs->ebx;
4404 env->regs[R_ECX] = regs->ecx;
4405 env->regs[R_EDX] = regs->edx;
4406 env->regs[R_ESI] = regs->esi;
4407 env->regs[R_EDI] = regs->edi;
4408 env->regs[R_EBP] = regs->ebp;
4409 env->regs[R_ESP] = regs->esp;
4410 env->eip = regs->eip;
4411 #endif
4412
4413 /* linux interrupt setup */
4414 #ifndef TARGET_ABI32
4415 env->idt.limit = 511;
4416 #else
4417 env->idt.limit = 255;
4418 #endif
4419 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4420 PROT_READ|PROT_WRITE,
4421 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4422 idt_table = g2h(env->idt.base);
4423 set_idt(0, 0);
4424 set_idt(1, 0);
4425 set_idt(2, 0);
4426 set_idt(3, 3);
4427 set_idt(4, 3);
4428 set_idt(5, 0);
4429 set_idt(6, 0);
4430 set_idt(7, 0);
4431 set_idt(8, 0);
4432 set_idt(9, 0);
4433 set_idt(10, 0);
4434 set_idt(11, 0);
4435 set_idt(12, 0);
4436 set_idt(13, 0);
4437 set_idt(14, 0);
4438 set_idt(15, 0);
4439 set_idt(16, 0);
4440 set_idt(17, 0);
4441 set_idt(18, 0);
4442 set_idt(19, 0);
4443 set_idt(0x80, 3);
4444
4445 /* linux segment setup */
4446 {
4447 uint64_t *gdt_table;
4448 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4449 PROT_READ|PROT_WRITE,
4450 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4451 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4452 gdt_table = g2h(env->gdt.base);
4453 #ifdef TARGET_ABI32
4454 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4455 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4456 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4457 #else
4458 /* 64 bit code segment */
4459 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4460 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4461 DESC_L_MASK |
4462 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4463 #endif
4464 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4465 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4466 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4467 }
4468 cpu_x86_load_seg(env, R_CS, __USER_CS);
4469 cpu_x86_load_seg(env, R_SS, __USER_DS);
4470 #ifdef TARGET_ABI32
4471 cpu_x86_load_seg(env, R_DS, __USER_DS);
4472 cpu_x86_load_seg(env, R_ES, __USER_DS);
4473 cpu_x86_load_seg(env, R_FS, __USER_DS);
4474 cpu_x86_load_seg(env, R_GS, __USER_DS);
4475 /* This hack makes Wine work... */
4476 env->segs[R_FS].selector = 0;
4477 #else
4478 cpu_x86_load_seg(env, R_DS, 0);
4479 cpu_x86_load_seg(env, R_ES, 0);
4480 cpu_x86_load_seg(env, R_FS, 0);
4481 cpu_x86_load_seg(env, R_GS, 0);
4482 #endif
4483 #elif defined(TARGET_AARCH64)
4484 {
4485 int i;
4486
4487 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4488 fprintf(stderr,
4489 "The selected ARM CPU does not support 64 bit mode\n");
4490 exit(EXIT_FAILURE);
4491 }
4492
4493 for (i = 0; i < 31; i++) {
4494 env->xregs[i] = regs->regs[i];
4495 }
4496 env->pc = regs->pc;
4497 env->xregs[31] = regs->sp;
4498 }
4499 #elif defined(TARGET_ARM)
4500 {
4501 int i;
4502 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4503 CPSRWriteByInstr);
4504 for(i = 0; i < 16; i++) {
4505 env->regs[i] = regs->uregs[i];
4506 }
4507 #ifdef TARGET_WORDS_BIGENDIAN
4508 /* Enable BE8. */
4509 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4510 && (info->elf_flags & EF_ARM_BE8)) {
4511 env->uncached_cpsr |= CPSR_E;
4512 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4513 } else {
4514 env->cp15.sctlr_el[1] |= SCTLR_B;
4515 }
4516 #endif
4517 }
4518 #elif defined(TARGET_UNICORE32)
4519 {
4520 int i;
4521 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4522 for (i = 0; i < 32; i++) {
4523 env->regs[i] = regs->uregs[i];
4524 }
4525 }
4526 #elif defined(TARGET_SPARC)
4527 {
4528 int i;
4529 env->pc = regs->pc;
4530 env->npc = regs->npc;
4531 env->y = regs->y;
4532 for(i = 0; i < 8; i++)
4533 env->gregs[i] = regs->u_regs[i];
4534 for(i = 0; i < 8; i++)
4535 env->regwptr[i] = regs->u_regs[i + 8];
4536 }
4537 #elif defined(TARGET_PPC)
4538 {
4539 int i;
4540
4541 #if defined(TARGET_PPC64)
4542 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4543 #if defined(TARGET_ABI32)
4544 env->msr &= ~((target_ulong)1 << flag);
4545 #else
4546 env->msr |= (target_ulong)1 << flag;
4547 #endif
4548 #endif
4549 env->nip = regs->nip;
4550 for(i = 0; i < 32; i++) {
4551 env->gpr[i] = regs->gpr[i];
4552 }
4553 }
4554 #elif defined(TARGET_M68K)
4555 {
4556 env->pc = regs->pc;
4557 env->dregs[0] = regs->d0;
4558 env->dregs[1] = regs->d1;
4559 env->dregs[2] = regs->d2;
4560 env->dregs[3] = regs->d3;
4561 env->dregs[4] = regs->d4;
4562 env->dregs[5] = regs->d5;
4563 env->dregs[6] = regs->d6;
4564 env->dregs[7] = regs->d7;
4565 env->aregs[0] = regs->a0;
4566 env->aregs[1] = regs->a1;
4567 env->aregs[2] = regs->a2;
4568 env->aregs[3] = regs->a3;
4569 env->aregs[4] = regs->a4;
4570 env->aregs[5] = regs->a5;
4571 env->aregs[6] = regs->a6;
4572 env->aregs[7] = regs->usp;
4573 env->sr = regs->sr;
4574 ts->sim_syscalls = 1;
4575 }
4576 #elif defined(TARGET_MICROBLAZE)
4577 {
4578 env->regs[0] = regs->r0;
4579 env->regs[1] = regs->r1;
4580 env->regs[2] = regs->r2;
4581 env->regs[3] = regs->r3;
4582 env->regs[4] = regs->r4;
4583 env->regs[5] = regs->r5;
4584 env->regs[6] = regs->r6;
4585 env->regs[7] = regs->r7;
4586 env->regs[8] = regs->r8;
4587 env->regs[9] = regs->r9;
4588 env->regs[10] = regs->r10;
4589 env->regs[11] = regs->r11;
4590 env->regs[12] = regs->r12;
4591 env->regs[13] = regs->r13;
4592 env->regs[14] = regs->r14;
4593 env->regs[15] = regs->r15;
4594 env->regs[16] = regs->r16;
4595 env->regs[17] = regs->r17;
4596 env->regs[18] = regs->r18;
4597 env->regs[19] = regs->r19;
4598 env->regs[20] = regs->r20;
4599 env->regs[21] = regs->r21;
4600 env->regs[22] = regs->r22;
4601 env->regs[23] = regs->r23;
4602 env->regs[24] = regs->r24;
4603 env->regs[25] = regs->r25;
4604 env->regs[26] = regs->r26;
4605 env->regs[27] = regs->r27;
4606 env->regs[28] = regs->r28;
4607 env->regs[29] = regs->r29;
4608 env->regs[30] = regs->r30;
4609 env->regs[31] = regs->r31;
4610 env->sregs[SR_PC] = regs->pc;
4611 }
4612 #elif defined(TARGET_MIPS)
4613 {
4614 int i;
4615
4616 for(i = 0; i < 32; i++) {
4617 env->active_tc.gpr[i] = regs->regs[i];
4618 }
4619 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4620 if (regs->cp0_epc & 1) {
4621 env->hflags |= MIPS_HFLAG_M16;
4622 }
4623 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4624 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4625 if ((env->active_fpu.fcr31_rw_bitmask &
4626 (1 << FCR31_NAN2008)) == 0) {
4627 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4628 exit(1);
4629 }
4630 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4631 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4632 } else {
4633 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4634 }
4635 restore_snan_bit_mode(env);
4636 }
4637 }
4638 #elif defined(TARGET_OPENRISC)
4639 {
4640 int i;
4641
4642 for (i = 0; i < 32; i++) {
4643 env->gpr[i] = regs->gpr[i];
4644 }
4645
4646 env->sr = regs->sr;
4647 env->pc = regs->pc;
4648 }
4649 #elif defined(TARGET_SH4)
4650 {
4651 int i;
4652
4653 for(i = 0; i < 16; i++) {
4654 env->gregs[i] = regs->regs[i];
4655 }
4656 env->pc = regs->pc;
4657 }
4658 #elif defined(TARGET_ALPHA)
4659 {
4660 int i;
4661
4662 for(i = 0; i < 28; i++) {
4663 env->ir[i] = ((abi_ulong *)regs)[i];
4664 }
4665 env->ir[IR_SP] = regs->usp;
4666 env->pc = regs->pc;
4667 }
4668 #elif defined(TARGET_CRIS)
4669 {
4670 env->regs[0] = regs->r0;
4671 env->regs[1] = regs->r1;
4672 env->regs[2] = regs->r2;
4673 env->regs[3] = regs->r3;
4674 env->regs[4] = regs->r4;
4675 env->regs[5] = regs->r5;
4676 env->regs[6] = regs->r6;
4677 env->regs[7] = regs->r7;
4678 env->regs[8] = regs->r8;
4679 env->regs[9] = regs->r9;
4680 env->regs[10] = regs->r10;
4681 env->regs[11] = regs->r11;
4682 env->regs[12] = regs->r12;
4683 env->regs[13] = regs->r13;
4684 env->regs[14] = info->start_stack;
4685 env->regs[15] = regs->acr;
4686 env->pc = regs->erp;
4687 }
4688 #elif defined(TARGET_S390X)
4689 {
4690 int i;
4691 for (i = 0; i < 16; i++) {
4692 env->regs[i] = regs->gprs[i];
4693 }
4694 env->psw.mask = regs->psw.mask;
4695 env->psw.addr = regs->psw.addr;
4696 }
4697 #elif defined(TARGET_TILEGX)
4698 {
4699 int i;
4700 for (i = 0; i < TILEGX_R_COUNT; i++) {
4701 env->regs[i] = regs->regs[i];
4702 }
4703 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4704 env->spregs[i] = 0;
4705 }
4706 env->pc = regs->pc;
4707 }
4708 #else
4709 #error unsupported target CPU
4710 #endif
4711
4712 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4713 ts->stack_base = info->start_stack;
4714 ts->heap_base = info->brk;
4715 /* This will be filled in on the first SYS_HEAPINFO call. */
4716 ts->heap_limit = 0;
4717 #endif
4718
4719 if (gdbstub_port) {
4720 if (gdbserver_start(gdbstub_port) < 0) {
4721 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4722 gdbstub_port);
4723 exit(EXIT_FAILURE);
4724 }
4725 gdb_handlesig(cpu, 0);
4726 }
4727 cpu_loop(env);
4728 /* never exits */
4729 return 0;
4730 }
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