4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
23 #include "cpu_loop-common.h"
24 #include "signal-common.h"
27 #include "fpu_helper.h"
29 # ifdef TARGET_ABI_MIPSO32
30 # define MIPS_SYSCALL_NUMBER_UNUSED -1
31 static const int8_t mips_syscall_args
[] = {
32 #include "syscall-args-o32.c.inc"
42 static int do_break(CPUMIPSState
*env
, target_siginfo_t
*info
,
50 info
->si_signo
= TARGET_SIGFPE
;
52 info
->si_code
= (code
== BRK_OVERFLOW
) ? FPE_INTOVF
: FPE_INTDIV
;
53 queue_signal(env
, info
->si_signo
, QEMU_SI_FAULT
, &*info
);
57 info
->si_signo
= TARGET_SIGTRAP
;
59 queue_signal(env
, info
->si_signo
, QEMU_SI_FAULT
, &*info
);
67 void cpu_loop(CPUMIPSState
*env
)
69 CPUState
*cs
= env_cpu(env
);
70 target_siginfo_t info
;
73 # ifdef TARGET_ABI_MIPSO32
74 unsigned int syscall_num
;
79 trapnr
= cpu_exec(cs
);
81 process_queued_cpu_work(cs
);
85 env
->active_tc
.PC
+= 4;
86 # ifdef TARGET_ABI_MIPSO32
87 syscall_num
= env
->active_tc
.gpr
[2] - 4000;
88 if (syscall_num
>= sizeof(mips_syscall_args
)) {
89 /* syscall_num is larger that any defined for MIPS O32 */
91 } else if (mips_syscall_args
[syscall_num
] ==
92 MIPS_SYSCALL_NUMBER_UNUSED
) {
93 /* syscall_num belongs to the range not defined for MIPS O32 */
96 /* syscall_num is valid */
99 abi_ulong arg5
= 0, arg6
= 0, arg7
= 0, arg8
= 0;
101 nb_args
= mips_syscall_args
[syscall_num
];
102 sp_reg
= env
->active_tc
.gpr
[29];
104 /* these arguments are taken from the stack */
106 if ((ret
= get_user_ual(arg8
, sp_reg
+ 28)) != 0) {
111 if ((ret
= get_user_ual(arg7
, sp_reg
+ 24)) != 0) {
116 if ((ret
= get_user_ual(arg6
, sp_reg
+ 20)) != 0) {
121 if ((ret
= get_user_ual(arg5
, sp_reg
+ 16)) != 0) {
128 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
129 env
->active_tc
.gpr
[4],
130 env
->active_tc
.gpr
[5],
131 env
->active_tc
.gpr
[6],
132 env
->active_tc
.gpr
[7],
133 arg5
, arg6
, arg7
, arg8
);
137 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
138 env
->active_tc
.gpr
[4], env
->active_tc
.gpr
[5],
139 env
->active_tc
.gpr
[6], env
->active_tc
.gpr
[7],
140 env
->active_tc
.gpr
[8], env
->active_tc
.gpr
[9],
141 env
->active_tc
.gpr
[10], env
->active_tc
.gpr
[11]);
143 if (ret
== -TARGET_ERESTARTSYS
) {
144 env
->active_tc
.PC
-= 4;
147 if (ret
== -TARGET_QEMU_ESIGRETURN
) {
148 /* Returning from a successful sigreturn syscall.
149 Avoid clobbering register state. */
152 if ((abi_ulong
)ret
>= (abi_ulong
)-1133) {
153 env
->active_tc
.gpr
[7] = 1; /* error flag */
156 env
->active_tc
.gpr
[7] = 0; /* error flag */
158 env
->active_tc
.gpr
[2] = ret
;
164 info
.si_signo
= TARGET_SIGSEGV
;
166 /* XXX: check env->error_code */
167 info
.si_code
= TARGET_SEGV_MAPERR
;
168 info
._sifields
._sigfault
._addr
= env
->CP0_BadVAddr
;
169 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
173 info
.si_signo
= TARGET_SIGILL
;
176 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
179 /* just indicate that signals should be handled asap */
182 info
.si_signo
= TARGET_SIGTRAP
;
184 info
.si_code
= TARGET_TRAP_BRKPT
;
185 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
188 info
.si_signo
= TARGET_SIGILL
;
190 info
.si_code
= TARGET_ILL_ILLOPC
;
191 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
194 info
.si_signo
= TARGET_SIGFPE
;
196 info
.si_code
= TARGET_FPE_FLTUNK
;
197 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_INVALID
) {
198 info
.si_code
= TARGET_FPE_FLTINV
;
199 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_DIV0
) {
200 info
.si_code
= TARGET_FPE_FLTDIV
;
201 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_OVERFLOW
) {
202 info
.si_code
= TARGET_FPE_FLTOVF
;
203 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_UNDERFLOW
) {
204 info
.si_code
= TARGET_FPE_FLTUND
;
205 } else if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & FP_INEXACT
) {
206 info
.si_code
= TARGET_FPE_FLTRES
;
208 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
210 /* The code below was inspired by the MIPS Linux kernel trap
211 * handling code in arch/mips/kernel/traps.c.
215 abi_ulong trap_instr
;
218 if (env
->hflags
& MIPS_HFLAG_M16
) {
219 if (env
->insn_flags
& ASE_MICROMIPS
) {
221 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
226 if ((trap_instr
>> 10) == 0x11) {
227 /* 16-bit instruction */
228 code
= trap_instr
& 0xf;
230 /* 32-bit instruction */
233 ret
= get_user_u16(instr_lo
,
234 env
->active_tc
.PC
+ 2);
238 trap_instr
= (trap_instr
<< 16) | instr_lo
;
239 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
240 /* Unfortunately, microMIPS also suffers from
241 the old assembler bug... */
242 if (code
>= (1 << 10)) {
248 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
252 code
= (trap_instr
>> 6) & 0x3f;
255 ret
= get_user_u32(trap_instr
, env
->active_tc
.PC
);
260 /* As described in the original Linux kernel code, the
261 * below checks on 'code' are to work around an old
264 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
265 if (code
>= (1 << 10)) {
270 if (do_break(env
, &info
, code
) != 0) {
277 abi_ulong trap_instr
;
278 unsigned int code
= 0;
280 if (env
->hflags
& MIPS_HFLAG_M16
) {
284 ret
= get_user_u16(instr
[0], env
->active_tc
.PC
) ||
285 get_user_u16(instr
[1], env
->active_tc
.PC
+ 2);
287 trap_instr
= (instr
[0] << 16) | instr
[1];
289 ret
= get_user_u32(trap_instr
, env
->active_tc
.PC
);
296 /* The immediate versions don't provide a code. */
297 if (!(trap_instr
& 0xFC000000)) {
298 if (env
->hflags
& MIPS_HFLAG_M16
) {
300 code
= ((trap_instr
>> 12) & ((1 << 4) - 1));
302 code
= ((trap_instr
>> 6) & ((1 << 10) - 1));
306 if (do_break(env
, &info
, code
) != 0) {
312 cpu_exec_step_atomic(cs
);
316 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
319 process_pending_signals(env
);
323 void target_cpu_copy_regs(CPUArchState
*env
, struct target_pt_regs
*regs
)
325 CPUState
*cpu
= env_cpu(env
);
326 TaskState
*ts
= cpu
->opaque
;
327 struct image_info
*info
= ts
->info
;
338 static const struct mode_req fpu_reqs
[] = {
339 [MIPS_ABI_FP_ANY
] = { true, true, true, true, true },
340 [MIPS_ABI_FP_DOUBLE
] = { false, false, false, true, true },
341 [MIPS_ABI_FP_SINGLE
] = { true, false, false, false, false },
342 [MIPS_ABI_FP_SOFT
] = { false, true, false, false, false },
343 [MIPS_ABI_FP_OLD_64
] = { false, false, false, false, false },
344 [MIPS_ABI_FP_XX
] = { false, false, true, true, true },
345 [MIPS_ABI_FP_64
] = { false, false, true, false, false },
346 [MIPS_ABI_FP_64A
] = { false, false, true, false, true }
350 * Mode requirements when .MIPS.abiflags is not present in the ELF.
351 * Not present means that everything is acceptable except FR1.
353 static struct mode_req none_req
= { true, true, false, true, true };
355 struct mode_req prog_req
;
356 struct mode_req interp_req
;
358 for(i
= 0; i
< 32; i
++) {
359 env
->active_tc
.gpr
[i
] = regs
->regs
[i
];
361 env
->active_tc
.PC
= regs
->cp0_epc
& ~(target_ulong
)1;
362 if (regs
->cp0_epc
& 1) {
363 env
->hflags
|= MIPS_HFLAG_M16
;
366 #ifdef TARGET_ABI_MIPSO32
367 # define MAX_FP_ABI MIPS_ABI_FP_64A
369 # define MAX_FP_ABI MIPS_ABI_FP_SOFT
371 if ((info
->fp_abi
> MAX_FP_ABI
&& info
->fp_abi
!= MIPS_ABI_FP_UNKNOWN
)
372 || (info
->interp_fp_abi
> MAX_FP_ABI
&&
373 info
->interp_fp_abi
!= MIPS_ABI_FP_UNKNOWN
)) {
374 fprintf(stderr
, "qemu: Unexpected FPU mode\n");
378 prog_req
= (info
->fp_abi
== MIPS_ABI_FP_UNKNOWN
) ? none_req
379 : fpu_reqs
[info
->fp_abi
];
380 interp_req
= (info
->interp_fp_abi
== MIPS_ABI_FP_UNKNOWN
) ? none_req
381 : fpu_reqs
[info
->interp_fp_abi
];
383 prog_req
.single
&= interp_req
.single
;
384 prog_req
.soft
&= interp_req
.soft
;
385 prog_req
.fr1
&= interp_req
.fr1
;
386 prog_req
.frdefault
&= interp_req
.frdefault
;
387 prog_req
.fre
&= interp_req
.fre
;
389 bool cpu_has_mips_r2_r6
= env
->insn_flags
& ISA_MIPS_R2
||
390 env
->insn_flags
& ISA_MIPS_R6
;
392 if (prog_req
.fre
&& !prog_req
.frdefault
&& !prog_req
.fr1
) {
393 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
394 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
395 env
->hflags
|= MIPS_HFLAG_FRE
;
397 } else if ((prog_req
.fr1
&& prog_req
.frdefault
) ||
398 (prog_req
.single
&& !prog_req
.frdefault
)) {
399 if ((env
->active_fpu
.fcr0
& (1 << FCR0_F64
)
400 && cpu_has_mips_r2_r6
) || prog_req
.fr1
) {
401 env
->CP0_Status
|= (1 << CP0St_FR
);
402 env
->hflags
|= MIPS_HFLAG_F64
;
404 } else if (!prog_req
.fre
&& !prog_req
.frdefault
&&
405 !prog_req
.fr1
&& !prog_req
.single
&& !prog_req
.soft
) {
406 fprintf(stderr
, "qemu: Can't find a matching FPU mode\n");
410 if (env
->insn_flags
& ISA_NANOMIPS32
) {
413 if (((info
->elf_flags
& EF_MIPS_NAN2008
) != 0) !=
414 ((env
->active_fpu
.fcr31
& (1 << FCR31_NAN2008
)) != 0)) {
415 if ((env
->active_fpu
.fcr31_rw_bitmask
&
416 (1 << FCR31_NAN2008
)) == 0) {
417 fprintf(stderr
, "ELF binary's NaN mode not supported by CPU\n");
420 if ((info
->elf_flags
& EF_MIPS_NAN2008
) != 0) {
421 env
->active_fpu
.fcr31
|= (1 << FCR31_NAN2008
);
423 env
->active_fpu
.fcr31
&= ~(1 << FCR31_NAN2008
);
425 restore_snan_bit_mode(env
);