patches/kernel/0014-EDAC-amd64-Add-PCI-device-IDs-for-family-19h-model-5.patch

   1 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
   2 From: Marc Bevand <m@zorinaq.com>
   3 Date: Tue, 21 Dec 2021 15:31:12 -0800
   4 Subject: [PATCH] EDAC/amd64: Add PCI device IDs for family 19h model 50h
   5
   6 Add the new family 19h model 50h PCI IDs (device 18h functions 0 and 6)
   7 to support Ryzen 5000 APUs ("Cezanne").
   8
   9 Signed-off-by: Marc Bevand <m@zorinaq.com>
  10 Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
  11 ---
  12  drivers/edac/amd64_edac.c | 15 +++++++++++++++
  13  drivers/edac/amd64_edac.h |  3 +++
  14  2 files changed, 18 insertions(+)
  15
  16 diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
  17 index c6c58f01067f..f8ef2edf8abf 100644
  18 --- a/drivers/edac/amd64_edac.c
  19 +++ b/drivers/edac/amd64_edac.c
  20 @@ -2660,6 +2660,16 @@ static struct amd64_family_type family_types[] = {
  21                         .dbam_to_cs             = f17_addr_mask_to_cs_size,
  22                 }
  23         },
  24 +       [F19_M50H_CPUS] = {
  25 +               .ctl_name = "F19h_M50h",
  26 +               .f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0,
  27 +               .f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6,
  28 +               .max_mcs = 2,
  29 +               .ops = {
  30 +                       .early_channel_count    = f17_early_channel_count,
  31 +                       .dbam_to_cs             = f17_addr_mask_to_cs_size,
  32 +               }
  33 +       },
  34  };
  35
  36  /*
  37 @@ -3706,6 +3716,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
  38                         pvt->ops = &family_types[F17_M70H_CPUS].ops;
  39                         fam_type->ctl_name = "F19h_M20h";
  40                         break;
  41 +               } else if (pvt->model >= 0x50 && pvt->model <= 0x5f) {
  42 +                       fam_type = &family_types[F19_M50H_CPUS];
  43 +                       pvt->ops = &family_types[F19_M50H_CPUS].ops;
  44 +                       fam_type->ctl_name = "F19h_M50h";
  45 +                       break;
  46                 } else if (pvt->model >= 0xa0 && pvt->model <= 0xaf) {
  47                         fam_type = &family_types[F19_M10H_CPUS];
  48                         pvt->ops = &family_types[F19_M10H_CPUS].ops;
  49 diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
  50 index 650cab401e21..352bda9803f6 100644
  51 --- a/drivers/edac/amd64_edac.h
  52 +++ b/drivers/edac/amd64_edac.h
  53 @@ -128,6 +128,8 @@
  54  #define PCI_DEVICE_ID_AMD_19H_DF_F6    0x1656
  55  #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F0 0x14ad
  56  #define PCI_DEVICE_ID_AMD_19H_M10H_DF_F6 0x14b3
  57 +#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a
  58 +#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670
  59
  60  /*
  61   * Function 1 - Address Map
  62 @@ -301,6 +303,7 @@ enum amd_families {
  63         F17_M70H_CPUS,
  64         F19_CPUS,
  65         F19_M10H_CPUS,
  66 +       F19_M50H_CPUS,
  67         NUM_FAMILIES,
  68  };
  69