pc-bios/petalogix-s3adsp1800.dts

   1 /*
   2  * Copyright (c) 2020 Xilinx Inc.
   3  * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /dts-v1/;
   9
  10 / {
  11         #address-cells = <0x01>;
  12         #size-cells = <0x01>;
  13         compatible = "xlnx,microblaze";
  14         model = "testing";
  15
  16         memory@90000000 {
  17                 device_type = "memory";
  18                 reg = <0x90000000 0x8000000>;
  19         };
  20
  21         chosen {
  22                 bootargs = "console=ttyUL0,115200";
  23                 stdout-path = "/plb/serial@84000000";
  24         };
  25
  26         cpus {
  27                 #address-cells = <0x01>;
  28                 #size-cells = <0x00>;
  29                 #cpus = <0x01>;
  30
  31                 cpu@0 {
  32                         clock-frequency = <0x3b9aca0>;
  33                         compatible = "xlnx,microblaze-7.10.d";
  34                         d-cache-baseaddr = <0x90000000>;
  35                         d-cache-highaddr = <0x97ffffff>;
  36                         d-cache-line-size = <0x10>;
  37                         d-cache-size = <0x800>;
  38                         device_type = "cpu";
  39                         i-cache-baseaddr = <0x90000000>;
  40                         i-cache-highaddr = <0x97ffffff>;
  41                         i-cache-line-size = <0x10>;
  42                         i-cache-size = <0x800>;
  43                         model = "microblaze,7.10.d";
  44                         reg = <0x00>;
  45                         timebase-frequency = <0x3b9aca0>;
  46                         xlnx,addr-tag-bits = <0x10>;
  47                         xlnx,allow-dcache-wr = <0x01>;
  48                         xlnx,allow-icache-wr = <0x01>;
  49                         xlnx,area-optimized = <0x00>;
  50                         xlnx,cache-byte-size = <0x800>;
  51                         xlnx,d-lmb = <0x01>;
  52                         xlnx,d-opb = <0x00>;
  53                         xlnx,d-plb = <0x01>;
  54                         xlnx,data-size = <0x20>;
  55                         xlnx,dcache-addr-tag = <0x10>;
  56                         xlnx,dcache-always-used = <0x00>;
  57                         xlnx,dcache-byte-size = <0x800>;
  58                         xlnx,dcache-line-len = <0x04>;
  59                         xlnx,dcache-use-fsl = <0x01>;
  60                         xlnx,debug-enabled = <0x01>;
  61                         xlnx,div-zero-exception = <0x00>;
  62                         xlnx,dopb-bus-exception = <0x00>;
  63                         xlnx,dynamic-bus-sizing = <0x01>;
  64                         xlnx,edge-is-positive = <0x01>;
  65                         xlnx,family = "spartan3adsp";
  66                         xlnx,fpu-exception = <0x00>;
  67                         xlnx,fsl-data-size = <0x20>;
  68                         xlnx,fsl-exception = <0x00>;
  69                         xlnx,fsl-links = <0x00>;
  70                         xlnx,i-lmb = <0x01>;
  71                         xlnx,i-opb = <0x00>;
  72                         xlnx,i-plb = <0x01>;
  73                         xlnx,icache-always-used = <0x00>;
  74                         xlnx,icache-line-len = <0x04>;
  75                         xlnx,icache-use-fsl = <0x01>;
  76                         xlnx,ill-opcode-exception = <0x00>;
  77                         xlnx,instance = "microblaze_0";
  78                         xlnx,interconnect = <0x01>;
  79                         xlnx,interrupt-is-edge = <0x00>;
  80                         xlnx,iopb-bus-exception = <0x00>;
  81                         xlnx,mmu-dtlb-size = <0x04>;
  82                         xlnx,mmu-itlb-size = <0x02>;
  83                         xlnx,mmu-tlb-access = <0x03>;
  84                         xlnx,mmu-zones = <0x10>;
  85                         xlnx,number-of-pc-brk = <0x03>;
  86                         xlnx,number-of-rd-addr-brk = <0x02>;
  87                         xlnx,number-of-wr-addr-brk = <0x02>;
  88                         xlnx,opcode-0x0-illegal = <0x00>;
  89                         xlnx,pvr = <0x01>;
  90                         xlnx,pvr-user1 = <0x00>;
  91                         xlnx,pvr-user2 = <0x00>;
  92                         xlnx,reset-msr = <0x00>;
  93                         xlnx,sco = <0x00>;
  94                         xlnx,unaligned-exceptions = <0x01>;
  95                         xlnx,use-barrel = <0x01>;
  96                         xlnx,use-dcache = <0x01>;
  97                         xlnx,use-div = <0x00>;
  98                         xlnx,use-ext-brk = <0x01>;
  99                         xlnx,use-ext-nm-brk = <0x01>;
 100                         xlnx,use-extended-fsl-instr = <0x00>;
 101                         xlnx,use-fpu = <0x00>;
 102                         xlnx,use-hw-mul = <0x01>;
 103                         xlnx,use-icache = <0x01>;
 104                         xlnx,use-interrupt = <0x01>;
 105                         xlnx,use-mmu = <0x03>;
 106                         xlnx,use-msr-instr = <0x01>;
 107                         xlnx,use-pcmp-instr = <0x01>;
 108                 };
 109         };
 110
 111         plb {
 112                 #address-cells = <0x01>;
 113                 #size-cells = <0x01>;
 114                 compatible = "xlnx,plb-v46-1.03.a\0simple-bus";
 115                 ranges;
 116
 117                 ethernet@81000000 {
 118                         compatible = "xlnx,xps-ethernetlite-2.00.a";
 119                         device_type = "network";
 120                         interrupt-parent = <0x01>;
 121                         interrupts = <0x01 0x00>;
 122                         local-mac-address = [02 00 00 00 00 00];
 123                         reg = <0x81000000 0x10000>;
 124                         xlnx,duplex = <0x01>;
 125                         xlnx,family = "spartan3adsp";
 126                         xlnx,rx-ping-pong = <0x00>;
 127                         xlnx,tx-ping-pong = <0x00>;
 128                 };
 129
 130                 flash@a0000000 {
 131                         bank-width = <0x01>;
 132                         compatible = "xlnx,xps-mch-emc-2.00.a\0cfi-flash";
 133                         reg = <0xa0000000 0x1000000>;
 134                         xlnx,family = "spartan3adsp";
 135                         xlnx,include-datawidth-matching-0 = <0x01>;
 136                         xlnx,include-datawidth-matching-1 = <0x00>;
 137                         xlnx,include-datawidth-matching-2 = <0x00>;
 138                         xlnx,include-datawidth-matching-3 = <0x00>;
 139                         xlnx,include-negedge-ioregs = <0x00>;
 140                         xlnx,include-plb-ipif = <0x01>;
 141                         xlnx,include-wrbuf = <0x01>;
 142                         xlnx,max-mem-width = <0x08>;
 143                         xlnx,mch-native-dwidth = <0x20>;
 144                         xlnx,mch-plb-clk-period-ps = <0x3e80>;
 145                         xlnx,mch-splb-awidth = <0x20>;
 146                         xlnx,mch0-accessbuf-depth = <0x10>;
 147                         xlnx,mch0-protocol = <0x00>;
 148                         xlnx,mch0-rddatabuf-depth = <0x10>;
 149                         xlnx,mch1-accessbuf-depth = <0x10>;
 150                         xlnx,mch1-protocol = <0x00>;
 151                         xlnx,mch1-rddatabuf-depth = <0x10>;
 152                         xlnx,mch2-accessbuf-depth = <0x10>;
 153                         xlnx,mch2-protocol = <0x00>;
 154                         xlnx,mch2-rddatabuf-depth = <0x10>;
 155                         xlnx,mch3-accessbuf-depth = <0x10>;
 156                         xlnx,mch3-protocol = <0x00>;
 157                         xlnx,mch3-rddatabuf-depth = <0x10>;
 158                         xlnx,mem0-width = <0x08>;
 159                         xlnx,mem1-width = <0x20>;
 160                         xlnx,mem2-width = <0x20>;
 161                         xlnx,mem3-width = <0x20>;
 162                         xlnx,num-banks-mem = <0x01>;
 163                         xlnx,num-channels = <0x00>;
 164                         xlnx,priority-mode = <0x00>;
 165                         xlnx,synch-mem-0 = <0x00>;
 166                         xlnx,synch-mem-1 = <0x00>;
 167                         xlnx,synch-mem-2 = <0x00>;
 168                         xlnx,synch-mem-3 = <0x00>;
 169                         xlnx,synch-pipedelay-0 = <0x02>;
 170                         xlnx,synch-pipedelay-1 = <0x02>;
 171                         xlnx,synch-pipedelay-2 = <0x02>;
 172                         xlnx,synch-pipedelay-3 = <0x02>;
 173                         xlnx,tavdv-ps-mem-0 = <0x11170>;
 174                         xlnx,tavdv-ps-mem-1 = <0x3a98>;
 175                         xlnx,tavdv-ps-mem-2 = <0x3a98>;
 176                         xlnx,tavdv-ps-mem-3 = <0x3a98>;
 177                         xlnx,tcedv-ps-mem-0 = <0x11170>;
 178                         xlnx,tcedv-ps-mem-1 = <0x3a98>;
 179                         xlnx,tcedv-ps-mem-2 = <0x3a98>;
 180                         xlnx,tcedv-ps-mem-3 = <0x3a98>;
 181                         xlnx,thzce-ps-mem-0 = <0x61a8>;
 182                         xlnx,thzce-ps-mem-1 = <0x1b58>;
 183                         xlnx,thzce-ps-mem-2 = <0x1b58>;
 184                         xlnx,thzce-ps-mem-3 = <0x1b58>;
 185                         xlnx,thzoe-ps-mem-0 = <0x61a8>;
 186                         xlnx,thzoe-ps-mem-1 = <0x1b58>;
 187                         xlnx,thzoe-ps-mem-2 = <0x1b58>;
 188                         xlnx,thzoe-ps-mem-3 = <0x1b58>;
 189                         xlnx,tlzwe-ps-mem-0 = <0x1388>;
 190                         xlnx,tlzwe-ps-mem-1 = <0x00>;
 191                         xlnx,tlzwe-ps-mem-2 = <0x00>;
 192                         xlnx,tlzwe-ps-mem-3 = <0x00>;
 193                         xlnx,twc-ps-mem-0 = <0x11170>;
 194                         xlnx,twc-ps-mem-1 = <0x3a98>;
 195                         xlnx,twc-ps-mem-2 = <0x3a98>;
 196                         xlnx,twc-ps-mem-3 = <0x3a98>;
 197                         xlnx,twp-ps-mem-0 = <0xafc8>;
 198                         xlnx,twp-ps-mem-1 = <0x2ee0>;
 199                         xlnx,twp-ps-mem-2 = <0x2ee0>;
 200                         xlnx,twp-ps-mem-3 = <0x2ee0>;
 201                         xlnx,xcl0-linesize = <0x04>;
 202                         xlnx,xcl0-writexfer = <0x01>;
 203                         xlnx,xcl1-linesize = <0x04>;
 204                         xlnx,xcl1-writexfer = <0x01>;
 205                         xlnx,xcl2-linesize = <0x04>;
 206                         xlnx,xcl2-writexfer = <0x01>;
 207                         xlnx,xcl3-linesize = <0x04>;
 208                         xlnx,xcl3-writexfer = <0x01>;
 209                 };
 210
 211                 gpio@81400000 {
 212                         compatible = "xlnx,xps-gpio-1.00.a";
 213                         interrupt-parent = <0x01>;
 214                         interrupts = <0x02 0x02>;
 215                         reg = <0x81400000 0x10000>;
 216                         xlnx,all-inputs = <0x00>;
 217                         xlnx,all-inputs-2 = <0x00>;
 218                         xlnx,dout-default = <0x00>;
 219                         xlnx,dout-default-2 = <0x00>;
 220                         xlnx,family = "spartan3adsp";
 221                         xlnx,gpio-width = <0x08>;
 222                         xlnx,interrupt-present = <0x01>;
 223                         xlnx,is-bidir = <0x00>;
 224                         xlnx,is-bidir-2 = <0x01>;
 225                         xlnx,is-dual = <0x00>;
 226                         xlnx,tri-default = <0xffffffff>;
 227                         xlnx,tri-default-2 = <0xffffffff>;
 228                 };
 229
 230                 serial@84000000 {
 231                         clock-frequency = <0x3b9aca0>;
 232                         compatible = "xlnx,xps-uartlite-1.00.a";
 233                         current-speed = <0x1c200>;
 234                         device_type = "serial";
 235                         interrupt-parent = <0x01>;
 236                         interrupts = <0x03 0x00>;
 237                         port-number = <0x00>;
 238                         reg = <0x84000000 0x10000>;
 239                         xlnx,baudrate = <0x1c200>;
 240                         xlnx,data-bits = <0x08>;
 241                         xlnx,family = "spartan3adsp";
 242                         xlnx,odd-parity = <0x00>;
 243                         xlnx,use-parity = <0x00>;
 244                 };
 245
 246                 debug@84400000 {
 247                         compatible = "xlnx,mdm-1.00.d";
 248                         reg = <0x84400000 0x10000>;
 249                         xlnx,family = "spartan3adsp";
 250                         xlnx,interconnect = <0x01>;
 251                         xlnx,jtag-chain = <0x02>;
 252                         xlnx,mb-dbg-ports = <0x01>;
 253                         xlnx,uart-width = <0x08>;
 254                         xlnx,use-uart = <0x01>;
 255                         xlnx,write-fsl-ports = <0x00>;
 256                 };
 257
 258                 interrupt-controller@81800000 {
 259                         #interrupt-cells = <0x02>;
 260                         compatible = "xlnx,xps-intc-1.00.a";
 261                         interrupt-controller;
 262                         reg = <0x81800000 0x10000>;
 263                         xlnx,kind-of-intr = <0x0a>;
 264                         xlnx,num-intr-inputs = <0x04>;
 265                         linux,phandle = <0x01>;
 266                 };
 267
 268                 timer@83c00000 {
 269                         compatible = "xlnx,xps-timer-1.00.a";
 270                         interrupt-parent = <0x01>;
 271                         interrupts = <0x00 0x02>;
 272                         reg = <0x83c00000 0x10000>;
 273                         xlnx,count-width = <0x20>;
 274                         xlnx,family = "spartan3adsp";
 275                         xlnx,gen0-assert = <0x01>;
 276                         xlnx,gen1-assert = <0x01>;
 277                         xlnx,one-timer-only = <0x00>;
 278                         xlnx,trig0-assert = <0x01>;
 279                         xlnx,trig1-assert = <0x01>;
 280                 };
 281         };
 282 };