qapi/cxl.json

   1 # -*- Mode: Python -*-
   2 # vim: filetype=python
   3
   4 ##
   5 # = CXL devices
   6 ##
   7
   8 ##
   9 # @CxlEventLog:
  10 #
  11 # CXL has a number of separate event logs for different types of
  12 # events.  Each such event log is handled and signaled independently.
  13 #
  14 # @informational: Information Event Log
  15 #
  16 # @warning: Warning Event Log
  17 #
  18 # @failure: Failure Event Log
  19 #
  20 # @fatal: Fatal Event Log
  21 #
  22 # Since: 8.1
  23 ##
  24 { 'enum': 'CxlEventLog',
  25   'data': ['informational',
  26            'warning',
  27            'failure',
  28            'fatal']
  29  }
  30
  31 ##
  32 # @cxl-inject-general-media-event:
  33 #
  34 # Inject an event record for a General Media Event (CXL r3.0
  35 # 8.2.9.2.1.1).  This event type is reported via one of the event logs
  36 # specified via the log parameter.
  37 #
  38 # @path: CXL type 3 device canonical QOM path
  39 #
  40 # @log: event log to add the event to
  41 #
  42 # @flags: Event Record Flags.  See CXL r3.0 Table 8-42 Common Event
  43 #     Record Format, Event Record Flags for subfield definitions.
  44 #
  45 # @dpa: Device Physical Address (relative to @path device).  Note
  46 #     lower bits include some flags.  See CXL r3.0 Table 8-43 General
  47 #     Media Event Record, Physical Address.
  48 #
  49 # @descriptor: Memory Event Descriptor with additional memory event
  50 #     information.  See CXL r3.0 Table 8-43 General Media Event
  51 #     Record, Memory Event Descriptor for bit definitions.
  52 #
  53 # @type: Type of memory event that occurred.  See CXL r3.0 Table 8-43
  54 #     General Media Event Record, Memory Event Type for possible
  55 #     values.
  56 #
  57 # @transaction-type: Type of first transaction that caused the event
  58 #     to occur.  See CXL r3.0 Table 8-43 General Media Event Record,
  59 #     Transaction Type for possible values.
  60 #
  61 # @channel: The channel of the memory event location.  A channel is an
  62 #     interface that can be independently accessed for a transaction.
  63 #
  64 # @rank: The rank of the memory event location.  A rank is a set of
  65 #     memory devices on a channel that together execute a transaction.
  66 #
  67 # @device: Bitmask that represents all devices in the rank associated
  68 #     with the memory event location.
  69 #
  70 # @component-id: Device specific component identifier for the event.
  71 #     May describe a field replaceable sub-component of the device.
  72 #
  73 # Since: 8.1
  74 ##
  75 { 'command': 'cxl-inject-general-media-event',
  76   'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
  77             'dpa': 'uint64', 'descriptor': 'uint8',
  78             'type': 'uint8', 'transaction-type': 'uint8',
  79             '*channel': 'uint8', '*rank': 'uint8',
  80             '*device': 'uint32', '*component-id': 'str' } }
  81
  82 ##
  83 # @cxl-inject-dram-event:
  84 #
  85 # Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2).
  86 # This event type is reported via one of the event logs specified via
  87 # the log parameter.
  88 #
  89 # @path: CXL type 3 device canonical QOM path
  90 #
  91 # @log: Event log to add the event to
  92 #
  93 # @flags: Event Record Flags.  See CXL r3.0 Table 8-42 Common Event
  94 #     Record Format, Event Record Flags for subfield definitions.
  95 #
  96 # @dpa: Device Physical Address (relative to @path device).  Note
  97 #     lower bits include some flags.  See CXL r3.0 Table 8-44 DRAM
  98 #     Event Record, Physical Address.
  99 #
 100 # @descriptor: Memory Event Descriptor with additional memory event
 101 #     information.  See CXL r3.0 Table 8-44 DRAM Event Record, Memory
 102 #     Event Descriptor for bit definitions.
 103 #
 104 # @type: Type of memory event that occurred.  See CXL r3.0 Table 8-44
 105 #     DRAM Event Record, Memory Event Type for possible values.
 106 #
 107 # @transaction-type: Type of first transaction that caused the event
 108 #     to occur.  See CXL r3.0 Table 8-44 DRAM Event Record,
 109 #     Transaction Type for possible values.
 110 #
 111 # @channel: The channel of the memory event location.  A channel is an
 112 #     interface that can be independently accessed for a transaction.
 113 #
 114 # @rank: The rank of the memory event location.  A rank is a set of
 115 #     memory devices on a channel that together execute a transaction.
 116 #
 117 # @nibble-mask: Identifies one or more nibbles that the error affects
 118 #
 119 # @bank-group: Bank group of the memory event location, incorporating
 120 #     a number of Banks.
 121 #
 122 # @bank: Bank of the memory event location.  A single bank is accessed
 123 #     per read or write of the memory.
 124 #
 125 # @row: Row address within the DRAM.
 126 #
 127 # @column: Column address within the DRAM.
 128 #
 129 # @correction-mask: Bits within each nibble.  Used in order of bits
 130 #     set in the nibble-mask.  Up to 4 nibbles may be covered.
 131 #
 132 # Since: 8.1
 133 ##
 134 { 'command': 'cxl-inject-dram-event',
 135   'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8',
 136             'dpa': 'uint64', 'descriptor': 'uint8',
 137             'type': 'uint8', 'transaction-type': 'uint8',
 138             '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32',
 139             '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
 140             '*column': 'uint16', '*correction-mask': [ 'uint64' ]
 141            }}
 142
 143 ##
 144 # @cxl-inject-poison:
 145 #
 146 # Poison records indicate that a CXL memory device knows that a
 147 # particular memory region may be corrupted.  This may be because of
 148 # locally detected errors (e.g. ECC failure) or poisoned writes
 149 # received from other components in the system.  This injection
 150 # mechanism enables testing of the OS handling of poison records which
 151 # may be queried via the CXL mailbox.
 152 #
 153 # @path: CXL type 3 device canonical QOM path
 154 #
 155 # @start: Start address; must be 64 byte aligned.
 156 #
 157 # @length: Length of poison to inject; must be a multiple of 64 bytes.
 158 #
 159 # Since: 8.1
 160 ##
 161 { 'command': 'cxl-inject-poison',
 162   'data': { 'path': 'str', 'start': 'uint64', 'length': 'size' }}
 163
 164 ##
 165 # @CxlUncorErrorType:
 166 #
 167 # Type of uncorrectable CXL error to inject.  These errors are
 168 # reported via an AER uncorrectable internal error with additional
 169 # information logged at the CXL device.
 170 #
 171 # @cache-data-parity: Data error such as data parity or data ECC error
 172 #     CXL.cache
 173 #
 174 # @cache-address-parity: Address parity or other errors associated
 175 #     with the address field on CXL.cache
 176 #
 177 # @cache-be-parity: Byte enable parity or other byte enable errors on
 178 #     CXL.cache
 179 #
 180 # @cache-data-ecc: ECC error on CXL.cache
 181 #
 182 # @mem-data-parity: Data error such as data parity or data ECC error
 183 #     on CXL.mem
 184 #
 185 # @mem-address-parity: Address parity or other errors associated with
 186 #     the address field on CXL.mem
 187 #
 188 # @mem-be-parity: Byte enable parity or other byte enable errors on
 189 #     CXL.mem.
 190 #
 191 # @mem-data-ecc: Data ECC error on CXL.mem.
 192 #
 193 # @reinit-threshold: REINIT threshold hit.
 194 #
 195 # @rsvd-encoding: Received unrecognized encoding.
 196 #
 197 # @poison-received: Received poison from the peer.
 198 #
 199 # @receiver-overflow: Buffer overflows (first 3 bits of header log
 200 #     indicate which)
 201 #
 202 # @internal: Component specific error
 203 #
 204 # @cxl-ide-tx: Integrity and data encryption tx error.
 205 #
 206 # @cxl-ide-rx: Integrity and data encryption rx error.
 207 #
 208 # Since: 8.0
 209 ##
 210
 211 { 'enum': 'CxlUncorErrorType',
 212   'data': ['cache-data-parity',
 213            'cache-address-parity',
 214            'cache-be-parity',
 215            'cache-data-ecc',
 216            'mem-data-parity',
 217            'mem-address-parity',
 218            'mem-be-parity',
 219            'mem-data-ecc',
 220            'reinit-threshold',
 221            'rsvd-encoding',
 222            'poison-received',
 223            'receiver-overflow',
 224            'internal',
 225            'cxl-ide-tx',
 226            'cxl-ide-rx'
 227            ]
 228  }
 229
 230 ##
 231 # @CXLUncorErrorRecord:
 232 #
 233 # Record of a single error including header log.
 234 #
 235 # @type: Type of error
 236 #
 237 # @header: 16 DWORD of header.
 238 #
 239 # Since: 8.0
 240 ##
 241 { 'struct': 'CXLUncorErrorRecord',
 242   'data': {
 243       'type': 'CxlUncorErrorType',
 244       'header': [ 'uint32' ]
 245   }
 246 }
 247
 248 ##
 249 # @cxl-inject-uncorrectable-errors:
 250 #
 251 # Command to allow injection of multiple errors in one go.  This
 252 # allows testing of multiple header log handling in the OS.
 253 #
 254 # @path: CXL Type 3 device canonical QOM path
 255 #
 256 # @errors: Errors to inject
 257 #
 258 # Since: 8.0
 259 ##
 260 { 'command': 'cxl-inject-uncorrectable-errors',
 261   'data': { 'path': 'str',
 262              'errors': [ 'CXLUncorErrorRecord' ] }}
 263
 264 ##
 265 # @CxlCorErrorType:
 266 #
 267 # Type of CXL correctable error to inject
 268 #
 269 # @cache-data-ecc: Data ECC error on CXL.cache
 270 #
 271 # @mem-data-ecc: Data ECC error on CXL.mem
 272 #
 273 # @crc-threshold: Component specific and applicable to 68 byte Flit
 274 #     mode only.
 275 #
 276 # @cache-poison-received: Received poison from a peer on CXL.cache.
 277 #
 278 # @mem-poison-received: Received poison from a peer on CXL.mem
 279 #
 280 # @physical: Received error indication from the physical layer.
 281 #
 282 # Since: 8.0
 283 ##
 284 { 'enum': 'CxlCorErrorType',
 285   'data': ['cache-data-ecc',
 286            'mem-data-ecc',
 287            'crc-threshold',
 288            'retry-threshold',
 289            'cache-poison-received',
 290            'mem-poison-received',
 291            'physical']
 292 }
 293
 294 ##
 295 # @cxl-inject-correctable-error:
 296 #
 297 # Command to inject a single correctable error.  Multiple error
 298 # injection of this error type is not interesting as there is no
 299 # associated header log.  These errors are reported via AER as a
 300 # correctable internal error, with additional detail available from
 301 # the CXL device.
 302 #
 303 # @path: CXL Type 3 device canonical QOM path
 304 #
 305 # @type: Type of error.
 306 #
 307 # Since: 8.0
 308 ##
 309 {'command': 'cxl-inject-correctable-error',
 310  'data': {'path': 'str', 'type': 'CxlCorErrorType'}}