qtest.c

   1 /*
   2  * Test Server
   3  *
   4  * Copyright IBM, Corp. 2011
   5  *
   6  * Authors:
   7  *  Anthony Liguori   <aliguori@us.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  */
  13
  14 #include "sysemu/qtest.h"
  15 #include "hw/qdev.h"
  16 #include "sysemu/char.h"
  17 #include "exec/ioport.h"
  18 #include "exec/memory.h"
  19 #include "hw/irq.h"
  20 #include "sysemu/accel.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/cpus.h"
  23 #include "qemu/config-file.h"
  24 #include "qemu/option.h"
  25 #include "qemu/error-report.h"
  26
  27 #define MAX_IRQ 256
  28
  29 bool qtest_allowed;
  30
  31 static DeviceState *irq_intercept_dev;
  32 static FILE *qtest_log_fp;
  33 static CharDriverState *qtest_chr;
  34 static GString *inbuf;
  35 static int irq_levels[MAX_IRQ];
  36 static qemu_timeval start_time;
  37 static bool qtest_opened;
  38
  39 #define FMT_timeval "%ld.%06ld"
  40
  41 /**
  42  * QTest Protocol
  43  *
  44  * Line based protocol, request/response based.  Server can send async messages
  45  * so clients should always handle many async messages before the response
  46  * comes in.
  47  *
  48  * Valid requests
  49  *
  50  * Clock management:
  51  *
  52  * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL.  qtest commands
  53  * let you adjust the value of the clock (monotonically).  All the commands
  54  * return the current value of the clock in nanoseconds.
  55  *
  56  *  > clock_step
  57  *  < OK VALUE
  58  *
  59  *     Advance the clock to the next deadline.  Useful when waiting for
  60  *     asynchronous events.
  61  *
  62  *  > clock_step NS
  63  *  < OK VALUE
  64  *
  65  *     Advance the clock by NS nanoseconds.
  66  *
  67  *  > clock_set NS
  68  *  < OK VALUE
  69  *
  70  *     Advance the clock to NS nanoseconds (do nothing if it's already past).
  71  *
  72  * PIO and memory access:
  73  *
  74  *  > outb ADDR VALUE
  75  *  < OK
  76  *
  77  *  > outw ADDR VALUE
  78  *  < OK
  79  *
  80  *  > outl ADDR VALUE
  81  *  < OK
  82  *
  83  *  > inb ADDR
  84  *  < OK VALUE
  85  *
  86  *  > inw ADDR
  87  *  < OK VALUE
  88  *
  89  *  > inl ADDR
  90  *  < OK VALUE
  91  *
  92  *  > writeb ADDR VALUE
  93  *  < OK
  94  *
  95  *  > writew ADDR VALUE
  96  *  < OK
  97  *
  98  *  > writel ADDR VALUE
  99  *  < OK
 100  *
 101  *  > writeq ADDR VALUE
 102  *  < OK
 103  *
 104  *  > readb ADDR
 105  *  < OK VALUE
 106  *
 107  *  > readw ADDR
 108  *  < OK VALUE
 109  *
 110  *  > readl ADDR
 111  *  < OK VALUE
 112  *
 113  *  > readq ADDR
 114  *  < OK VALUE
 115  *
 116  *  > read ADDR SIZE
 117  *  < OK DATA
 118  *
 119  *  > write ADDR SIZE DATA
 120  *  < OK
 121  *
 122  * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
 123  *
 124  * DATA is an arbitrarily long hex number prefixed with '0x'.  If it's smaller
 125  * than the expected size, the value will be zero filled at the end of the data
 126  * sequence.
 127  *
 128  * IRQ management:
 129  *
 130  *  > irq_intercept_in QOM-PATH
 131  *  < OK
 132  *
 133  *  > irq_intercept_out QOM-PATH
 134  *  < OK
 135  *
 136  * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
 137  * QOM-PATH.  When the pin is triggered, one of the following async messages
 138  * will be printed to the qtest stream:
 139  *
 140  *  IRQ raise NUM
 141  *  IRQ lower NUM
 142  *
 143  * where NUM is an IRQ number.  For the PC, interrupts can be intercepted
 144  * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
 145  * NUM=0 even though it is remapped to GSI 2).
 146  */
 147
 148 static int hex2nib(char ch)
 149 {
 150     if (ch >= '0' && ch <= '9') {
 151         return ch - '0';
 152     } else if (ch >= 'a' && ch <= 'f') {
 153         return 10 + (ch - 'a');
 154     } else if (ch >= 'A' && ch <= 'F') {
 155         return 10 + (ch - 'A');
 156     } else {
 157         return -1;
 158     }
 159 }
 160
 161 static void qtest_get_time(qemu_timeval *tv)
 162 {
 163     qemu_gettimeofday(tv);
 164     tv->tv_sec -= start_time.tv_sec;
 165     tv->tv_usec -= start_time.tv_usec;
 166     if (tv->tv_usec < 0) {
 167         tv->tv_usec += 1000000;
 168         tv->tv_sec -= 1;
 169     }
 170 }
 171
 172 static void qtest_send_prefix(CharDriverState *chr)
 173 {
 174     qemu_timeval tv;
 175
 176     if (!qtest_log_fp || !qtest_opened) {
 177         return;
 178     }
 179
 180     qtest_get_time(&tv);
 181     fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
 182             (long) tv.tv_sec, (long) tv.tv_usec);
 183 }
 184
 185 static void do_qtest_send(CharDriverState *chr, const char *str, size_t len)
 186 {
 187     qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
 188     if (qtest_log_fp && qtest_opened) {
 189         fprintf(qtest_log_fp, "%s", str);
 190     }
 191 }
 192
 193 static void qtest_send(CharDriverState *chr, const char *str)
 194 {
 195     do_qtest_send(chr, str, strlen(str));
 196 }
 197
 198 static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState *chr,
 199                                            const char *fmt, ...)
 200 {
 201     va_list ap;
 202     gchar *buffer;
 203
 204     va_start(ap, fmt);
 205     buffer = g_strdup_vprintf(fmt, ap);
 206     qtest_send(chr, buffer);
 207     va_end(ap);
 208 }
 209
 210 static void qtest_irq_handler(void *opaque, int n, int level)
 211 {
 212     qemu_irq old_irq = *(qemu_irq *)opaque;
 213     qemu_set_irq(old_irq, level);
 214
 215     if (irq_levels[n] != level) {
 216         CharDriverState *chr = qtest_chr;
 217         irq_levels[n] = level;
 218         qtest_send_prefix(chr);
 219         qtest_sendf(chr, "IRQ %s %d\n",
 220                     level ? "raise" : "lower", n);
 221     }
 222 }
 223
 224 static void qtest_process_command(CharDriverState *chr, gchar **words)
 225 {
 226     const gchar *command;
 227
 228     g_assert(words);
 229
 230     command = words[0];
 231
 232     if (qtest_log_fp) {
 233         qemu_timeval tv;
 234         int i;
 235
 236         qtest_get_time(&tv);
 237         fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
 238                 (long) tv.tv_sec, (long) tv.tv_usec);
 239         for (i = 0; words[i]; i++) {
 240             fprintf(qtest_log_fp, " %s", words[i]);
 241         }
 242         fprintf(qtest_log_fp, "\n");
 243     }
 244
 245     g_assert(command);
 246     if (strcmp(words[0], "irq_intercept_out") == 0
 247         || strcmp(words[0], "irq_intercept_in") == 0) {
 248         DeviceState *dev;
 249         NamedGPIOList *ngl;
 250
 251         g_assert(words[1]);
 252         dev = DEVICE(object_resolve_path(words[1], NULL));
 253         if (!dev) {
 254             qtest_send_prefix(chr);
 255             qtest_send(chr, "FAIL Unknown device\n");
 256             return;
 257         }
 258
 259         if (irq_intercept_dev) {
 260             qtest_send_prefix(chr);
 261             if (irq_intercept_dev != dev) {
 262                 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
 263             } else {
 264                 qtest_send(chr, "OK\n");
 265             }
 266             return;
 267         }
 268
 269         QLIST_FOREACH(ngl, &dev->gpios, node) {
 270             /* We don't support intercept of named GPIOs yet */
 271             if (ngl->name) {
 272                 continue;
 273             }
 274             if (words[0][14] == 'o') {
 275                 int i;
 276                 for (i = 0; i < ngl->num_out; ++i) {
 277                     qemu_irq *disconnected = g_new0(qemu_irq, 1);
 278                     qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
 279                                                       disconnected, i);
 280
 281                     *disconnected = qdev_intercept_gpio_out(dev, icpt,
 282                                                             ngl->name, i);
 283                 }
 284             } else {
 285                 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
 286                                       ngl->num_in);
 287             }
 288         }
 289         irq_intercept_dev = dev;
 290         qtest_send_prefix(chr);
 291         qtest_send(chr, "OK\n");
 292
 293     } else if (strcmp(words[0], "outb") == 0 ||
 294                strcmp(words[0], "outw") == 0 ||
 295                strcmp(words[0], "outl") == 0) {
 296         uint16_t addr;
 297         uint32_t value;
 298
 299         g_assert(words[1] && words[2]);
 300         addr = strtoul(words[1], NULL, 0);
 301         value = strtoul(words[2], NULL, 0);
 302
 303         if (words[0][3] == 'b') {
 304             cpu_outb(addr, value);
 305         } else if (words[0][3] == 'w') {
 306             cpu_outw(addr, value);
 307         } else if (words[0][3] == 'l') {
 308             cpu_outl(addr, value);
 309         }
 310         qtest_send_prefix(chr);
 311         qtest_send(chr, "OK\n");
 312     } else if (strcmp(words[0], "inb") == 0 ||
 313         strcmp(words[0], "inw") == 0 ||
 314         strcmp(words[0], "inl") == 0) {
 315         uint16_t addr;
 316         uint32_t value = -1U;
 317
 318         g_assert(words[1]);
 319         addr = strtoul(words[1], NULL, 0);
 320
 321         if (words[0][2] == 'b') {
 322             value = cpu_inb(addr);
 323         } else if (words[0][2] == 'w') {
 324             value = cpu_inw(addr);
 325         } else if (words[0][2] == 'l') {
 326             value = cpu_inl(addr);
 327         }
 328         qtest_send_prefix(chr);
 329         qtest_sendf(chr, "OK 0x%04x\n", value);
 330     } else if (strcmp(words[0], "writeb") == 0 ||
 331                strcmp(words[0], "writew") == 0 ||
 332                strcmp(words[0], "writel") == 0 ||
 333                strcmp(words[0], "writeq") == 0) {
 334         uint64_t addr;
 335         uint64_t value;
 336
 337         g_assert(words[1] && words[2]);
 338         addr = strtoull(words[1], NULL, 0);
 339         value = strtoull(words[2], NULL, 0);
 340
 341         if (words[0][5] == 'b') {
 342             uint8_t data = value;
 343             cpu_physical_memory_write(addr, &data, 1);
 344         } else if (words[0][5] == 'w') {
 345             uint16_t data = value;
 346             tswap16s(&data);
 347             cpu_physical_memory_write(addr, &data, 2);
 348         } else if (words[0][5] == 'l') {
 349             uint32_t data = value;
 350             tswap32s(&data);
 351             cpu_physical_memory_write(addr, &data, 4);
 352         } else if (words[0][5] == 'q') {
 353             uint64_t data = value;
 354             tswap64s(&data);
 355             cpu_physical_memory_write(addr, &data, 8);
 356         }
 357         qtest_send_prefix(chr);
 358         qtest_send(chr, "OK\n");
 359     } else if (strcmp(words[0], "readb") == 0 ||
 360                strcmp(words[0], "readw") == 0 ||
 361                strcmp(words[0], "readl") == 0 ||
 362                strcmp(words[0], "readq") == 0) {
 363         uint64_t addr;
 364         uint64_t value = UINT64_C(-1);
 365
 366         g_assert(words[1]);
 367         addr = strtoull(words[1], NULL, 0);
 368
 369         if (words[0][4] == 'b') {
 370             uint8_t data;
 371             cpu_physical_memory_read(addr, &data, 1);
 372             value = data;
 373         } else if (words[0][4] == 'w') {
 374             uint16_t data;
 375             cpu_physical_memory_read(addr, &data, 2);
 376             value = tswap16(data);
 377         } else if (words[0][4] == 'l') {
 378             uint32_t data;
 379             cpu_physical_memory_read(addr, &data, 4);
 380             value = tswap32(data);
 381         } else if (words[0][4] == 'q') {
 382             cpu_physical_memory_read(addr, &value, 8);
 383             tswap64s(&value);
 384         }
 385         qtest_send_prefix(chr);
 386         qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
 387     } else if (strcmp(words[0], "read") == 0) {
 388         uint64_t addr, len, i;
 389         uint8_t *data;
 390
 391         g_assert(words[1] && words[2]);
 392         addr = strtoull(words[1], NULL, 0);
 393         len = strtoull(words[2], NULL, 0);
 394
 395         data = g_malloc(len);
 396         cpu_physical_memory_read(addr, data, len);
 397
 398         qtest_send_prefix(chr);
 399         qtest_send(chr, "OK 0x");
 400         for (i = 0; i < len; i++) {
 401             qtest_sendf(chr, "%02x", data[i]);
 402         }
 403         qtest_send(chr, "\n");
 404
 405         g_free(data);
 406     } else if (strcmp(words[0], "write") == 0) {
 407         uint64_t addr, len, i;
 408         uint8_t *data;
 409         size_t data_len;
 410
 411         g_assert(words[1] && words[2] && words[3]);
 412         addr = strtoull(words[1], NULL, 0);
 413         len = strtoull(words[2], NULL, 0);
 414
 415         data_len = strlen(words[3]);
 416         if (data_len < 3) {
 417             qtest_send(chr, "ERR invalid argument size\n");
 418             return;
 419         }
 420
 421         data = g_malloc(len);
 422         for (i = 0; i < len; i++) {
 423             if ((i * 2 + 4) <= data_len) {
 424                 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
 425                 data[i] |= hex2nib(words[3][i * 2 + 3]);
 426             } else {
 427                 data[i] = 0;
 428             }
 429         }
 430         cpu_physical_memory_write(addr, data, len);
 431         g_free(data);
 432
 433         qtest_send_prefix(chr);
 434         qtest_send(chr, "OK\n");
 435     } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
 436         int64_t ns;
 437
 438         if (words[1]) {
 439             ns = strtoll(words[1], NULL, 0);
 440         } else {
 441             ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
 442         }
 443         qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
 444         qtest_send_prefix(chr);
 445         qtest_sendf(chr, "OK %"PRIi64"\n",
 446                     (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 447     } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
 448         int64_t ns;
 449
 450         g_assert(words[1]);
 451         ns = strtoll(words[1], NULL, 0);
 452         qtest_clock_warp(ns);
 453         qtest_send_prefix(chr);
 454         qtest_sendf(chr, "OK %"PRIi64"\n",
 455                     (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 456     } else {
 457         qtest_send_prefix(chr);
 458         qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
 459     }
 460 }
 461
 462 static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
 463 {
 464     char *end;
 465
 466     while ((end = strchr(inbuf->str, '\n')) != NULL) {
 467         size_t offset;
 468         GString *cmd;
 469         gchar **words;
 470
 471         offset = end - inbuf->str;
 472
 473         cmd = g_string_new_len(inbuf->str, offset);
 474         g_string_erase(inbuf, 0, offset + 1);
 475
 476         words = g_strsplit(cmd->str, " ", 0);
 477         qtest_process_command(chr, words);
 478         g_strfreev(words);
 479
 480         g_string_free(cmd, TRUE);
 481     }
 482 }
 483
 484 static void qtest_read(void *opaque, const uint8_t *buf, int size)
 485 {
 486     CharDriverState *chr = opaque;
 487
 488     g_string_append_len(inbuf, (const gchar *)buf, size);
 489     qtest_process_inbuf(chr, inbuf);
 490 }
 491
 492 static int qtest_can_read(void *opaque)
 493 {
 494     return 1024;
 495 }
 496
 497 static void qtest_event(void *opaque, int event)
 498 {
 499     int i;
 500
 501     switch (event) {
 502     case CHR_EVENT_OPENED:
 503         /*
 504          * We used to call qemu_system_reset() here, hoping we could
 505          * use the same process for multiple tests that way.  Never
 506          * used.  Injects an extra reset even when it's not used, and
 507          * that can mess up tests, e.g. -boot once.
 508          */
 509         for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
 510             irq_levels[i] = 0;
 511         }
 512         qemu_gettimeofday(&start_time);
 513         qtest_opened = true;
 514         if (qtest_log_fp) {
 515             fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
 516                     (long) start_time.tv_sec, (long) start_time.tv_usec);
 517         }
 518         break;
 519     case CHR_EVENT_CLOSED:
 520         qtest_opened = false;
 521         if (qtest_log_fp) {
 522             qemu_timeval tv;
 523             qtest_get_time(&tv);
 524             fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
 525                     (long) tv.tv_sec, (long) tv.tv_usec);
 526         }
 527         break;
 528     default:
 529         break;
 530     }
 531 }
 532
 533 static int qtest_init_accel(MachineState *ms)
 534 {
 535     QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
 536                                       &error_abort);
 537     qemu_opt_set(opts, "shift", "0", &error_abort);
 538     configure_icount(opts, &error_abort);
 539     qemu_opts_del(opts);
 540     return 0;
 541 }
 542
 543 void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
 544 {
 545     CharDriverState *chr;
 546
 547     chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
 548
 549     if (chr == NULL) {
 550         error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
 551                    qtest_chrdev);
 552         return;
 553     }
 554
 555     if (qtest_log) {
 556         if (strcmp(qtest_log, "none") != 0) {
 557             qtest_log_fp = fopen(qtest_log, "w+");
 558         }
 559     } else {
 560         qtest_log_fp = stderr;
 561     }
 562
 563     qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
 564     qemu_chr_fe_set_echo(chr, true);
 565
 566     inbuf = g_string_new("");
 567     qtest_chr = chr;
 568 }
 569
 570 bool qtest_driver(void)
 571 {
 572     return qtest_chr;
 573 }
 574
 575 static void qtest_accel_class_init(ObjectClass *oc, void *data)
 576 {
 577     AccelClass *ac = ACCEL_CLASS(oc);
 578     ac->name = "QTest";
 579     ac->available = qtest_available;
 580     ac->init_machine = qtest_init_accel;
 581     ac->allowed = &qtest_allowed;
 582 }
 583
 584 #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
 585
 586 static const TypeInfo qtest_accel_type = {
 587     .name = TYPE_QTEST_ACCEL,
 588     .parent = TYPE_ACCEL,
 589     .class_init = qtest_accel_class_init,
 590 };
 591
 592 static void qtest_type_init(void)
 593 {
 594     type_register_static(&qtest_accel_type);
 595 }
 596
 597 type_init(qtest_type_init);