softmmu_header.h

   1 /*
   2  *  Software MMU support
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if DATA_SIZE == 8
  21 #define SUFFIX q
  22 #define USUFFIX q
  23 #define DATA_TYPE uint64_t
  24 #elif DATA_SIZE == 4
  25 #define SUFFIX l
  26 #define USUFFIX l
  27 #define DATA_TYPE uint32_t
  28 #elif DATA_SIZE == 2
  29 #define SUFFIX w
  30 #define USUFFIX uw
  31 #define DATA_TYPE uint16_t
  32 #define DATA_STYPE int16_t
  33 #elif DATA_SIZE == 1
  34 #define SUFFIX b
  35 #define USUFFIX ub
  36 #define DATA_TYPE uint8_t
  37 #define DATA_STYPE int8_t
  38 #else
  39 #error unsupported data size
  40 #endif
  41
  42 #if ACCESS_TYPE == 0
  43
  44 #define CPU_MEM_INDEX 0
  45 #define MMUSUFFIX _mmu
  46
  47 #elif ACCESS_TYPE == 1
  48
  49 #define CPU_MEM_INDEX 1
  50 #define MMUSUFFIX _mmu
  51
  52 #elif ACCESS_TYPE == 2
  53
  54 #ifdef TARGET_I386
  55 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
  56 #elif defined (TARGET_PPC)
  57 #define CPU_MEM_INDEX (msr_pr)
  58 #elif defined (TARGET_MIPS)
  59 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
  60 #elif defined (TARGET_SPARC)
  61 #define CPU_MEM_INDEX ((env->psrs) == 0)
  62 #elif defined (TARGET_ARM)
  63 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
  64 #elif defined (TARGET_SH4)
  65 #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
  66 #elif defined (TARGET_ALPHA)
  67 #define CPU_MEM_INDEX ((env->ps >> 3) & 3)
  68 #elif defined (TARGET_M68K)
  69 #define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
  70 #elif defined (TARGET_CRIS)
  71 /* CRIS FIXME: I guess we want to validate supervisor mode acceses here.  */
  72 #define CPU_MEM_INDEX (0)
  73 #else
  74 #error unsupported CPU
  75 #endif
  76 #define MMUSUFFIX _mmu
  77
  78 #elif ACCESS_TYPE == 3
  79
  80 #ifdef TARGET_I386
  81 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
  82 #elif defined (TARGET_PPC)
  83 #define CPU_MEM_INDEX (msr_pr)
  84 #elif defined (TARGET_MIPS)
  85 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
  86 #elif defined (TARGET_SPARC)
  87 #define CPU_MEM_INDEX ((env->psrs) == 0)
  88 #elif defined (TARGET_ARM)
  89 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
  90 #elif defined (TARGET_SH4)
  91 #define CPU_MEM_INDEX ((env->sr & SR_MD) == 0)
  92 #elif defined (TARGET_ALPHA)
  93 #define CPU_MEM_INDEX ((env->ps >> 3) & 3)
  94 #elif defined (TARGET_M68K)
  95 #define CPU_MEM_INDEX ((env->sr & SR_S) == 0)
  96 #elif defined (TARGET_CRIS)
  97 /* CRIS FIXME: I guess we want to validate supervisor mode acceses here.  */
  98 #define CPU_MEM_INDEX (0)
  99 #else
 100 #error unsupported CPU
 101 #endif
 102 #define MMUSUFFIX _cmmu
 103
 104 #else
 105 #error invalid ACCESS_TYPE
 106 #endif
 107
 108 #if DATA_SIZE == 8
 109 #define RES_TYPE uint64_t
 110 #else
 111 #define RES_TYPE int
 112 #endif
 113
 114 #if ACCESS_TYPE == 3
 115 #define ADDR_READ addr_code
 116 #else
 117 #define ADDR_READ addr_read
 118 #endif
 119
 120 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
 121                                                          int is_user);
 122 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
 123
 124 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
 125     (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
 126
 127 #define CPU_TLB_ENTRY_BITS 4
 128
 129 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
 130 {
 131     int res;
 132
 133     asm volatile ("movl %1, %%edx\n"
 134                   "movl %1, %%eax\n"
 135                   "shrl %3, %%edx\n"
 136                   "andl %4, %%eax\n"
 137                   "andl %2, %%edx\n"
 138                   "leal %5(%%edx, %%ebp), %%edx\n"
 139                   "cmpl (%%edx), %%eax\n"
 140                   "movl %1, %%eax\n"
 141                   "je 1f\n"
 142                   "pushl %6\n"
 143                   "call %7\n"
 144                   "popl %%edx\n"
 145                   "movl %%eax, %0\n"
 146                   "jmp 2f\n"
 147                   "1:\n"
 148                   "addl 12(%%edx), %%eax\n"
 149 #if DATA_SIZE == 1
 150                   "movzbl (%%eax), %0\n"
 151 #elif DATA_SIZE == 2
 152                   "movzwl (%%eax), %0\n"
 153 #elif DATA_SIZE == 4
 154                   "movl (%%eax), %0\n"
 155 #else
 156 #error unsupported size
 157 #endif
 158                   "2:\n"
 159                   : "=r" (res)
 160                   : "r" (ptr),
 161                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
 162                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
 163                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 164                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
 165                   "i" (CPU_MEM_INDEX),
 166                   "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
 167                   : "%eax", "%ecx", "%edx", "memory", "cc");
 168     return res;
 169 }
 170
 171 #if DATA_SIZE <= 2
 172 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 173 {
 174     int res;
 175
 176     asm volatile ("movl %1, %%edx\n"
 177                   "movl %1, %%eax\n"
 178                   "shrl %3, %%edx\n"
 179                   "andl %4, %%eax\n"
 180                   "andl %2, %%edx\n"
 181                   "leal %5(%%edx, %%ebp), %%edx\n"
 182                   "cmpl (%%edx), %%eax\n"
 183                   "movl %1, %%eax\n"
 184                   "je 1f\n"
 185                   "pushl %6\n"
 186                   "call %7\n"
 187                   "popl %%edx\n"
 188 #if DATA_SIZE == 1
 189                   "movsbl %%al, %0\n"
 190 #elif DATA_SIZE == 2
 191                   "movswl %%ax, %0\n"
 192 #else
 193 #error unsupported size
 194 #endif
 195                   "jmp 2f\n"
 196                   "1:\n"
 197                   "addl 12(%%edx), %%eax\n"
 198 #if DATA_SIZE == 1
 199                   "movsbl (%%eax), %0\n"
 200 #elif DATA_SIZE == 2
 201                   "movswl (%%eax), %0\n"
 202 #else
 203 #error unsupported size
 204 #endif
 205                   "2:\n"
 206                   : "=r" (res)
 207                   : "r" (ptr),
 208                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
 209                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
 210                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 211                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_read)),
 212                   "i" (CPU_MEM_INDEX),
 213                   "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
 214                   : "%eax", "%ecx", "%edx", "memory", "cc");
 215     return res;
 216 }
 217 #endif
 218
 219 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 220 {
 221     asm volatile ("movl %0, %%edx\n"
 222                   "movl %0, %%eax\n"
 223                   "shrl %3, %%edx\n"
 224                   "andl %4, %%eax\n"
 225                   "andl %2, %%edx\n"
 226                   "leal %5(%%edx, %%ebp), %%edx\n"
 227                   "cmpl (%%edx), %%eax\n"
 228                   "movl %0, %%eax\n"
 229                   "je 1f\n"
 230 #if DATA_SIZE == 1
 231                   "movzbl %b1, %%edx\n"
 232 #elif DATA_SIZE == 2
 233                   "movzwl %w1, %%edx\n"
 234 #elif DATA_SIZE == 4
 235                   "movl %1, %%edx\n"
 236 #else
 237 #error unsupported size
 238 #endif
 239                   "pushl %6\n"
 240                   "call %7\n"
 241                   "popl %%eax\n"
 242                   "jmp 2f\n"
 243                   "1:\n"
 244                   "addl 8(%%edx), %%eax\n"
 245 #if DATA_SIZE == 1
 246                   "movb %b1, (%%eax)\n"
 247 #elif DATA_SIZE == 2
 248                   "movw %w1, (%%eax)\n"
 249 #elif DATA_SIZE == 4
 250                   "movl %1, (%%eax)\n"
 251 #else
 252 #error unsupported size
 253 #endif
 254                   "2:\n"
 255                   :
 256                   : "r" (ptr),
 257 /* NOTE: 'q' would be needed as constraint, but we could not use it
 258    with T1 ! */
 259                   "r" (v),
 260                   "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
 261                   "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
 262                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 263                   "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
 264                   "i" (CPU_MEM_INDEX),
 265                   "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
 266                   : "%eax", "%ecx", "%edx", "memory", "cc");
 267 }
 268
 269 #else
 270
 271 /* generic load/store macros */
 272
 273 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
 274 {
 275     int index;
 276     RES_TYPE res;
 277     target_ulong addr;
 278     unsigned long physaddr;
 279     int is_user;
 280
 281     addr = ptr;
 282     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 283     is_user = CPU_MEM_INDEX;
 284     if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
 285                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 286         res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
 287     } else {
 288         physaddr = addr + env->tlb_table[is_user][index].addend;
 289         res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
 290     }
 291     return res;
 292 }
 293
 294 #if DATA_SIZE <= 2
 295 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 296 {
 297     int res, index;
 298     target_ulong addr;
 299     unsigned long physaddr;
 300     int is_user;
 301
 302     addr = ptr;
 303     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 304     is_user = CPU_MEM_INDEX;
 305     if (__builtin_expect(env->tlb_table[is_user][index].ADDR_READ !=
 306                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 307         res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
 308     } else {
 309         physaddr = addr + env->tlb_table[is_user][index].addend;
 310         res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
 311     }
 312     return res;
 313 }
 314 #endif
 315
 316 #if ACCESS_TYPE != 3
 317
 318 /* generic store macro */
 319
 320 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 321 {
 322     int index;
 323     target_ulong addr;
 324     unsigned long physaddr;
 325     int is_user;
 326
 327     addr = ptr;
 328     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 329     is_user = CPU_MEM_INDEX;
 330     if (__builtin_expect(env->tlb_table[is_user][index].addr_write !=
 331                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 332         glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
 333     } else {
 334         physaddr = addr + env->tlb_table[is_user][index].addend;
 335         glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
 336     }
 337 }
 338
 339 #endif /* ACCESS_TYPE != 3 */
 340
 341 #endif /* !asm */
 342
 343 #if ACCESS_TYPE != 3
 344
 345 #if DATA_SIZE == 8
 346 static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
 347 {
 348     union {
 349         float64 d;
 350         uint64_t i;
 351     } u;
 352     u.i = glue(ldq, MEMSUFFIX)(ptr);
 353     return u.d;
 354 }
 355
 356 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
 357 {
 358     union {
 359         float64 d;
 360         uint64_t i;
 361     } u;
 362     u.d = v;
 363     glue(stq, MEMSUFFIX)(ptr, u.i);
 364 }
 365 #endif /* DATA_SIZE == 8 */
 366
 367 #if DATA_SIZE == 4
 368 static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
 369 {
 370     union {
 371         float32 f;
 372         uint32_t i;
 373     } u;
 374     u.i = glue(ldl, MEMSUFFIX)(ptr);
 375     return u.f;
 376 }
 377
 378 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
 379 {
 380     union {
 381         float32 f;
 382         uint32_t i;
 383     } u;
 384     u.f = v;
 385     glue(stl, MEMSUFFIX)(ptr, u.i);
 386 }
 387 #endif /* DATA_SIZE == 4 */
 388
 389 #endif /* ACCESS_TYPE != 3 */
 390
 391 #undef RES_TYPE
 392 #undef DATA_TYPE
 393 #undef DATA_STYPE
 394 #undef SUFFIX
 395 #undef USUFFIX
 396 #undef DATA_SIZE
 397 #undef CPU_MEM_INDEX
 398 #undef MMUSUFFIX
 399 #undef ADDR_READ