softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * Generate helpers used by TCG for qemu_ld/st ops and code load
   5  * functions.
   6  *
   7  * Included from target op helpers and exec.c.
   8  *
   9  *  Copyright (c) 2003 Fabrice Bellard
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License as published by the Free Software Foundation; either
  14  * version 2 of the License, or (at your option) any later version.
  15  *
  16  * This library is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * Lesser General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU Lesser General Public
  22  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24 #include "qemu/timer.h"
  25 #include "exec/address-spaces.h"
  26 #include "exec/memory.h"
  27
  28 #define DATA_SIZE (1 << SHIFT)
  29
  30 #if DATA_SIZE == 8
  31 #define SUFFIX q
  32 #define LSUFFIX q
  33 #define SDATA_TYPE  int64_t
  34 #define DATA_TYPE  uint64_t
  35 #elif DATA_SIZE == 4
  36 #define SUFFIX l
  37 #define LSUFFIX l
  38 #define SDATA_TYPE  int32_t
  39 #define DATA_TYPE  uint32_t
  40 #elif DATA_SIZE == 2
  41 #define SUFFIX w
  42 #define LSUFFIX uw
  43 #define SDATA_TYPE  int16_t
  44 #define DATA_TYPE  uint16_t
  45 #elif DATA_SIZE == 1
  46 #define SUFFIX b
  47 #define LSUFFIX ub
  48 #define SDATA_TYPE  int8_t
  49 #define DATA_TYPE  uint8_t
  50 #else
  51 #error unsupported data size
  52 #endif
  53
  54
  55 /* For the benefit of TCG generated code, we want to avoid the complication
  56    of ABI-specific return type promotion and always return a value extended
  57    to the register size of the host.  This is tcg_target_long, except in the
  58    case of a 32-bit host and 64-bit data, and for that we always have
  59    uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
  60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
  61 # define WORD_TYPE  DATA_TYPE
  62 # define USUFFIX    SUFFIX
  63 #else
  64 # define WORD_TYPE  tcg_target_ulong
  65 # define USUFFIX    glue(u, SUFFIX)
  66 # define SSUFFIX    glue(s, SUFFIX)
  67 #endif
  68
  69 #ifdef SOFTMMU_CODE_ACCESS
  70 #define READ_ACCESS_TYPE MMU_INST_FETCH
  71 #define ADDR_READ addr_code
  72 #else
  73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
  74 #define ADDR_READ addr_read
  75 #endif
  76
  77 #if DATA_SIZE == 8
  78 # define BSWAP(X)  bswap64(X)
  79 #elif DATA_SIZE == 4
  80 # define BSWAP(X)  bswap32(X)
  81 #elif DATA_SIZE == 2
  82 # define BSWAP(X)  bswap16(X)
  83 #else
  84 # define BSWAP(X)  (X)
  85 #endif
  86
  87 #ifdef TARGET_WORDS_BIGENDIAN
  88 # define TGT_BE(X)  (X)
  89 # define TGT_LE(X)  BSWAP(X)
  90 #else
  91 # define TGT_BE(X)  BSWAP(X)
  92 # define TGT_LE(X)  (X)
  93 #endif
  94
  95 #if DATA_SIZE == 1
  96 # define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
  97 # define helper_be_ld_name  helper_le_ld_name
  98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
  99 # define helper_be_lds_name helper_le_lds_name
 100 # define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
 101 # define helper_be_st_name  helper_le_st_name
 102 #else
 103 # define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
 104 # define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
 105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
 106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
 107 # define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
 108 # define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
 109 #endif
 110
 111 #ifdef TARGET_WORDS_BIGENDIAN
 112 # define helper_te_ld_name  helper_be_ld_name
 113 # define helper_te_st_name  helper_be_st_name
 114 #else
 115 # define helper_te_ld_name  helper_le_ld_name
 116 # define helper_te_st_name  helper_le_st_name
 117 #endif
 118
 119 /* macro to check the victim tlb */
 120 #define VICTIM_TLB_HIT(ty)                                                    \
 121 ({                                                                            \
 122     /* we are about to do a page table walk. our last hope is the             \
 123      * victim tlb. try to refill from the victim tlb before walking the       \
 124      * page table. */                                                         \
 125     int vidx;                                                                 \
 126     CPUIOTLBEntry tmpiotlb;                                                   \
 127     CPUTLBEntry tmptlb;                                                       \
 128     for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) {                         \
 129         if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
 130             /* found entry in victim tlb, swap tlb and iotlb */               \
 131             tmptlb = env->tlb_table[mmu_idx][index];                          \
 132             env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
 133             env->tlb_v_table[mmu_idx][vidx] = tmptlb;                         \
 134             tmpiotlb = env->iotlb[mmu_idx][index];                            \
 135             env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx];         \
 136             env->iotlb_v[mmu_idx][vidx] = tmpiotlb;                           \
 137             break;                                                            \
 138         }                                                                     \
 139     }                                                                         \
 140     /* return true when there is a vtlb hit, i.e. vidx >=0 */                 \
 141     vidx >= 0;                                                                \
 142 })
 143
 144 #ifndef SOFTMMU_CODE_ACCESS
 145 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
 146                                               CPUIOTLBEntry *iotlbentry,
 147                                               target_ulong addr,
 148                                               uintptr_t retaddr)
 149 {
 150     uint64_t val;
 151     CPUState *cpu = ENV_GET_CPU(env);
 152     hwaddr physaddr = iotlbentry->addr;
 153     MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
 154
 155     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 156     cpu->mem_io_pc = retaddr;
 157     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
 158         cpu_io_recompile(cpu, retaddr);
 159     }
 160
 161     cpu->mem_io_vaddr = addr;
 162     memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT,
 163                                 iotlbentry->attrs);
 164     return val;
 165 }
 166 #endif
 167
 168 #ifdef SOFTMMU_CODE_ACCESS
 169 static __attribute__((unused))
 170 #endif
 171 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr,
 172                             TCGMemOpIdx oi, uintptr_t retaddr)
 173 {
 174     unsigned mmu_idx = get_mmuidx(oi);
 175     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 176     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 177     uintptr_t haddr;
 178     DATA_TYPE res;
 179
 180     /* Adjust the given return address.  */
 181     retaddr -= GETPC_ADJ;
 182
 183     /* If the TLB entry is for a different page, reload and try again.  */
 184     if ((addr & TARGET_PAGE_MASK)
 185          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 186 #ifdef ALIGNED_ONLY
 187         if ((addr & (DATA_SIZE - 1)) != 0) {
 188             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 189                                  mmu_idx, retaddr);
 190         }
 191 #endif
 192         if (!VICTIM_TLB_HIT(ADDR_READ)) {
 193             tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 194                      mmu_idx, retaddr);
 195         }
 196         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 197     }
 198
 199     /* Handle an IO access.  */
 200     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 201         CPUIOTLBEntry *iotlbentry;
 202         if ((addr & (DATA_SIZE - 1)) != 0) {
 203             goto do_unaligned_access;
 204         }
 205         iotlbentry = &env->iotlb[mmu_idx][index];
 206
 207         /* ??? Note that the io helpers always read data in the target
 208            byte ordering.  We should push the LE/BE request down into io.  */
 209         res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
 210         res = TGT_LE(res);
 211         return res;
 212     }
 213
 214     /* Handle slow unaligned access (it spans two pages or IO).  */
 215     if (DATA_SIZE > 1
 216         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 217                     >= TARGET_PAGE_SIZE)) {
 218         target_ulong addr1, addr2;
 219         DATA_TYPE res1, res2;
 220         unsigned shift;
 221     do_unaligned_access:
 222 #ifdef ALIGNED_ONLY
 223         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 224                              mmu_idx, retaddr);
 225 #endif
 226         addr1 = addr & ~(DATA_SIZE - 1);
 227         addr2 = addr1 + DATA_SIZE;
 228         /* Note the adjustment at the beginning of the function.
 229            Undo that for the recursion.  */
 230         res1 = helper_le_ld_name(env, addr1, oi, retaddr + GETPC_ADJ);
 231         res2 = helper_le_ld_name(env, addr2, oi, retaddr + GETPC_ADJ);
 232         shift = (addr & (DATA_SIZE - 1)) * 8;
 233
 234         /* Little-endian combine.  */
 235         res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 236         return res;
 237     }
 238
 239     /* Handle aligned access or unaligned access in the same page.  */
 240 #ifdef ALIGNED_ONLY
 241     if ((addr & (DATA_SIZE - 1)) != 0) {
 242         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 243                              mmu_idx, retaddr);
 244     }
 245 #endif
 246
 247     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 248 #if DATA_SIZE == 1
 249     res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
 250 #else
 251     res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
 252 #endif
 253     return res;
 254 }
 255
 256 #if DATA_SIZE > 1
 257 #ifdef SOFTMMU_CODE_ACCESS
 258 static __attribute__((unused))
 259 #endif
 260 WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr,
 261                             TCGMemOpIdx oi, uintptr_t retaddr)
 262 {
 263     unsigned mmu_idx = get_mmuidx(oi);
 264     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 265     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 266     uintptr_t haddr;
 267     DATA_TYPE res;
 268
 269     /* Adjust the given return address.  */
 270     retaddr -= GETPC_ADJ;
 271
 272     /* If the TLB entry is for a different page, reload and try again.  */
 273     if ((addr & TARGET_PAGE_MASK)
 274          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 275 #ifdef ALIGNED_ONLY
 276         if ((addr & (DATA_SIZE - 1)) != 0) {
 277             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 278                                  mmu_idx, retaddr);
 279         }
 280 #endif
 281         if (!VICTIM_TLB_HIT(ADDR_READ)) {
 282             tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 283                      mmu_idx, retaddr);
 284         }
 285         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 286     }
 287
 288     /* Handle an IO access.  */
 289     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 290         CPUIOTLBEntry *iotlbentry;
 291         if ((addr & (DATA_SIZE - 1)) != 0) {
 292             goto do_unaligned_access;
 293         }
 294         iotlbentry = &env->iotlb[mmu_idx][index];
 295
 296         /* ??? Note that the io helpers always read data in the target
 297            byte ordering.  We should push the LE/BE request down into io.  */
 298         res = glue(io_read, SUFFIX)(env, iotlbentry, addr, retaddr);
 299         res = TGT_BE(res);
 300         return res;
 301     }
 302
 303     /* Handle slow unaligned access (it spans two pages or IO).  */
 304     if (DATA_SIZE > 1
 305         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 306                     >= TARGET_PAGE_SIZE)) {
 307         target_ulong addr1, addr2;
 308         DATA_TYPE res1, res2;
 309         unsigned shift;
 310     do_unaligned_access:
 311 #ifdef ALIGNED_ONLY
 312         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 313                              mmu_idx, retaddr);
 314 #endif
 315         addr1 = addr & ~(DATA_SIZE - 1);
 316         addr2 = addr1 + DATA_SIZE;
 317         /* Note the adjustment at the beginning of the function.
 318            Undo that for the recursion.  */
 319         res1 = helper_be_ld_name(env, addr1, oi, retaddr + GETPC_ADJ);
 320         res2 = helper_be_ld_name(env, addr2, oi, retaddr + GETPC_ADJ);
 321         shift = (addr & (DATA_SIZE - 1)) * 8;
 322
 323         /* Big-endian combine.  */
 324         res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 325         return res;
 326     }
 327
 328     /* Handle aligned access or unaligned access in the same page.  */
 329 #ifdef ALIGNED_ONLY
 330     if ((addr & (DATA_SIZE - 1)) != 0) {
 331         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 332                              mmu_idx, retaddr);
 333     }
 334 #endif
 335
 336     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 337     res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
 338     return res;
 339 }
 340 #endif /* DATA_SIZE > 1 */
 341
 342 DATA_TYPE
 343 glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 344                                          int mmu_idx)
 345 {
 346     TCGMemOpIdx oi = make_memop_idx(SHIFT, mmu_idx);
 347     return helper_te_ld_name (env, addr, oi, GETRA());
 348 }
 349
 350 #ifndef SOFTMMU_CODE_ACCESS
 351
 352 /* Provide signed versions of the load routines as well.  We can of course
 353    avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
 354 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
 355 WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
 356                              TCGMemOpIdx oi, uintptr_t retaddr)
 357 {
 358     return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr);
 359 }
 360
 361 # if DATA_SIZE > 1
 362 WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
 363                              TCGMemOpIdx oi, uintptr_t retaddr)
 364 {
 365     return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr);
 366 }
 367 # endif
 368 #endif
 369
 370 static inline void glue(io_write, SUFFIX)(CPUArchState *env,
 371                                           CPUIOTLBEntry *iotlbentry,
 372                                           DATA_TYPE val,
 373                                           target_ulong addr,
 374                                           uintptr_t retaddr)
 375 {
 376     CPUState *cpu = ENV_GET_CPU(env);
 377     hwaddr physaddr = iotlbentry->addr;
 378     MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
 379
 380     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 381     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
 382         cpu_io_recompile(cpu, retaddr);
 383     }
 384
 385     cpu->mem_io_vaddr = addr;
 386     cpu->mem_io_pc = retaddr;
 387     memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT,
 388                                  iotlbentry->attrs);
 389 }
 390
 391 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 392                        TCGMemOpIdx oi, uintptr_t retaddr)
 393 {
 394     unsigned mmu_idx = get_mmuidx(oi);
 395     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 396     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 397     uintptr_t haddr;
 398
 399     /* Adjust the given return address.  */
 400     retaddr -= GETPC_ADJ;
 401
 402     /* If the TLB entry is for a different page, reload and try again.  */
 403     if ((addr & TARGET_PAGE_MASK)
 404         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 405 #ifdef ALIGNED_ONLY
 406         if ((addr & (DATA_SIZE - 1)) != 0) {
 407             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 408                                  mmu_idx, retaddr);
 409         }
 410 #endif
 411         if (!VICTIM_TLB_HIT(addr_write)) {
 412             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 413         }
 414         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 415     }
 416
 417     /* Handle an IO access.  */
 418     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 419         CPUIOTLBEntry *iotlbentry;
 420         if ((addr & (DATA_SIZE - 1)) != 0) {
 421             goto do_unaligned_access;
 422         }
 423         iotlbentry = &env->iotlb[mmu_idx][index];
 424
 425         /* ??? Note that the io helpers always read data in the target
 426            byte ordering.  We should push the LE/BE request down into io.  */
 427         val = TGT_LE(val);
 428         glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
 429         return;
 430     }
 431
 432     /* Handle slow unaligned access (it spans two pages or IO).  */
 433     if (DATA_SIZE > 1
 434         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 435                      >= TARGET_PAGE_SIZE)) {
 436         int i;
 437     do_unaligned_access:
 438 #ifdef ALIGNED_ONLY
 439         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 440                              mmu_idx, retaddr);
 441 #endif
 442         /* XXX: not efficient, but simple */
 443         /* Note: relies on the fact that tlb_fill() does not remove the
 444          * previous page from the TLB cache.  */
 445         for (i = DATA_SIZE - 1; i >= 0; i--) {
 446             /* Little-endian extract.  */
 447             uint8_t val8 = val >> (i * 8);
 448             /* Note the adjustment at the beginning of the function.
 449                Undo that for the recursion.  */
 450             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 451                                             oi, retaddr + GETPC_ADJ);
 452         }
 453         return;
 454     }
 455
 456     /* Handle aligned access or unaligned access in the same page.  */
 457 #ifdef ALIGNED_ONLY
 458     if ((addr & (DATA_SIZE - 1)) != 0) {
 459         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 460                              mmu_idx, retaddr);
 461     }
 462 #endif
 463
 464     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 465 #if DATA_SIZE == 1
 466     glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
 467 #else
 468     glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
 469 #endif
 470 }
 471
 472 #if DATA_SIZE > 1
 473 void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 474                        TCGMemOpIdx oi, uintptr_t retaddr)
 475 {
 476     unsigned mmu_idx = get_mmuidx(oi);
 477     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 478     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 479     uintptr_t haddr;
 480
 481     /* Adjust the given return address.  */
 482     retaddr -= GETPC_ADJ;
 483
 484     /* If the TLB entry is for a different page, reload and try again.  */
 485     if ((addr & TARGET_PAGE_MASK)
 486         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 487 #ifdef ALIGNED_ONLY
 488         if ((addr & (DATA_SIZE - 1)) != 0) {
 489             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 490                                  mmu_idx, retaddr);
 491         }
 492 #endif
 493         if (!VICTIM_TLB_HIT(addr_write)) {
 494             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 495         }
 496         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 497     }
 498
 499     /* Handle an IO access.  */
 500     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 501         CPUIOTLBEntry *iotlbentry;
 502         if ((addr & (DATA_SIZE - 1)) != 0) {
 503             goto do_unaligned_access;
 504         }
 505         iotlbentry = &env->iotlb[mmu_idx][index];
 506
 507         /* ??? Note that the io helpers always read data in the target
 508            byte ordering.  We should push the LE/BE request down into io.  */
 509         val = TGT_BE(val);
 510         glue(io_write, SUFFIX)(env, iotlbentry, val, addr, retaddr);
 511         return;
 512     }
 513
 514     /* Handle slow unaligned access (it spans two pages or IO).  */
 515     if (DATA_SIZE > 1
 516         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 517                      >= TARGET_PAGE_SIZE)) {
 518         int i;
 519     do_unaligned_access:
 520 #ifdef ALIGNED_ONLY
 521         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 522                              mmu_idx, retaddr);
 523 #endif
 524         /* XXX: not efficient, but simple */
 525         /* Note: relies on the fact that tlb_fill() does not remove the
 526          * previous page from the TLB cache.  */
 527         for (i = DATA_SIZE - 1; i >= 0; i--) {
 528             /* Big-endian extract.  */
 529             uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
 530             /* Note the adjustment at the beginning of the function.
 531                Undo that for the recursion.  */
 532             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 533                                             oi, retaddr + GETPC_ADJ);
 534         }
 535         return;
 536     }
 537
 538     /* Handle aligned access or unaligned access in the same page.  */
 539 #ifdef ALIGNED_ONLY
 540     if ((addr & (DATA_SIZE - 1)) != 0) {
 541         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 542                              mmu_idx, retaddr);
 543     }
 544 #endif
 545
 546     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 547     glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
 548 }
 549 #endif /* DATA_SIZE > 1 */
 550
 551 void
 552 glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 553                                          DATA_TYPE val, int mmu_idx)
 554 {
 555     TCGMemOpIdx oi = make_memop_idx(SHIFT, mmu_idx);
 556     helper_te_st_name(env, addr, val, oi, GETRA());
 557 }
 558
 559 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 560
 561 #undef READ_ACCESS_TYPE
 562 #undef SHIFT
 563 #undef DATA_TYPE
 564 #undef SUFFIX
 565 #undef LSUFFIX
 566 #undef DATA_SIZE
 567 #undef ADDR_READ
 568 #undef WORD_TYPE
 569 #undef SDATA_TYPE
 570 #undef USUFFIX
 571 #undef SSUFFIX
 572 #undef BSWAP
 573 #undef TGT_BE
 574 #undef TGT_LE
 575 #undef CPU_BE
 576 #undef CPU_LE
 577 #undef helper_le_ld_name
 578 #undef helper_be_ld_name
 579 #undef helper_le_lds_name
 580 #undef helper_be_lds_name
 581 #undef helper_le_st_name
 582 #undef helper_be_st_name
 583 #undef helper_te_ld_name
 584 #undef helper_te_st_name