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405ba3590e085be2f982d5fcb2a2047b45c033ef
4 * Generate helpers used by TCG for qemu_ld/st ops and code load
7 * Included from target op helpers and exec.c.
9 * Copyright (c) 2003 Fabrice Bellard
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or (at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/timer.h"
25 #include "exec/address-spaces.h"
26 #include "exec/memory.h"
28 #define DATA_SIZE (1 << SHIFT)
33 #define SDATA_TYPE int64_t
34 #define DATA_TYPE uint64_t
38 #define SDATA_TYPE int32_t
39 #define DATA_TYPE uint32_t
43 #define SDATA_TYPE int16_t
44 #define DATA_TYPE uint16_t
48 #define SDATA_TYPE int8_t
49 #define DATA_TYPE uint8_t
51 #error unsupported data size
55 /* For the benefit of TCG generated code, we want to avoid the complication
56 of ABI-specific return type promotion and always return a value extended
57 to the register size of the host. This is tcg_target_long, except in the
58 case of a 32-bit host and 64-bit data, and for that we always have
59 uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */
60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
61 # define WORD_TYPE DATA_TYPE
62 # define USUFFIX SUFFIX
64 # define WORD_TYPE tcg_target_ulong
65 # define USUFFIX glue(u, SUFFIX)
66 # define SSUFFIX glue(s, SUFFIX)
69 #ifdef SOFTMMU_CODE_ACCESS
70 #define READ_ACCESS_TYPE MMU_INST_FETCH
71 #define ADDR_READ addr_code
73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
74 #define ADDR_READ addr_read
78 # define BSWAP(X) bswap64(X)
80 # define BSWAP(X) bswap32(X)
82 # define BSWAP(X) bswap16(X)
87 #ifdef TARGET_WORDS_BIGENDIAN
88 # define TGT_BE(X) (X)
89 # define TGT_LE(X) BSWAP(X)
91 # define TGT_BE(X) BSWAP(X)
92 # define TGT_LE(X) (X)
96 # define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
97 # define helper_be_ld_name helper_le_ld_name
98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
99 # define helper_be_lds_name helper_le_lds_name
100 # define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
101 # define helper_be_st_name helper_le_st_name
103 # define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
104 # define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
107 # define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
108 # define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
111 #ifdef TARGET_WORDS_BIGENDIAN
112 # define helper_te_ld_name helper_be_ld_name
113 # define helper_te_st_name helper_be_st_name
115 # define helper_te_ld_name helper_le_ld_name
116 # define helper_te_st_name helper_le_st_name
119 #ifndef SOFTMMU_CODE_ACCESS
120 static inline DATA_TYPE
glue(io_read
, SUFFIX
)(CPUArchState
*env
,
121 CPUIOTLBEntry
*iotlbentry
,
126 CPUState
*cpu
= ENV_GET_CPU(env
);
127 hwaddr physaddr
= iotlbentry
->addr
;
128 MemoryRegion
*mr
= iotlb_to_region(cpu
, physaddr
, iotlbentry
->attrs
);
130 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
131 cpu
->mem_io_pc
= retaddr
;
132 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !cpu
->can_do_io
) {
133 cpu_io_recompile(cpu
, retaddr
);
136 cpu
->mem_io_vaddr
= addr
;
137 memory_region_dispatch_read(mr
, physaddr
, &val
, 1 << SHIFT
,
143 WORD_TYPE
helper_le_ld_name(CPUArchState
*env
, target_ulong addr
,
144 TCGMemOpIdx oi
, uintptr_t retaddr
)
146 unsigned mmu_idx
= get_mmuidx(oi
);
147 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
148 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
149 int a_bits
= get_alignment_bits(get_memop(oi
));
153 /* Adjust the given return address. */
154 retaddr
-= GETPC_ADJ
;
156 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
157 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
161 /* If the TLB entry is for a different page, reload and try again. */
162 if ((addr
& TARGET_PAGE_MASK
)
163 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
164 if (!VICTIM_TLB_HIT(ADDR_READ
)) {
165 tlb_fill(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
168 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
171 /* Handle an IO access. */
172 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
173 CPUIOTLBEntry
*iotlbentry
;
174 if ((addr
& (DATA_SIZE
- 1)) != 0) {
175 goto do_unaligned_access
;
177 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
179 /* ??? Note that the io helpers always read data in the target
180 byte ordering. We should push the LE/BE request down into io. */
181 res
= glue(io_read
, SUFFIX
)(env
, iotlbentry
, addr
, retaddr
);
186 /* Handle slow unaligned access (it spans two pages or IO). */
188 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
189 >= TARGET_PAGE_SIZE
)) {
190 target_ulong addr1
, addr2
;
191 DATA_TYPE res1
, res2
;
194 addr1
= addr
& ~(DATA_SIZE
- 1);
195 addr2
= addr1
+ DATA_SIZE
;
196 /* Note the adjustment at the beginning of the function.
197 Undo that for the recursion. */
198 res1
= helper_le_ld_name(env
, addr1
, oi
, retaddr
+ GETPC_ADJ
);
199 res2
= helper_le_ld_name(env
, addr2
, oi
, retaddr
+ GETPC_ADJ
);
200 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
202 /* Little-endian combine. */
203 res
= (res1
>> shift
) | (res2
<< ((DATA_SIZE
* 8) - shift
));
207 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
209 res
= glue(glue(ld
, LSUFFIX
), _p
)((uint8_t *)haddr
);
211 res
= glue(glue(ld
, LSUFFIX
), _le_p
)((uint8_t *)haddr
);
217 WORD_TYPE
helper_be_ld_name(CPUArchState
*env
, target_ulong addr
,
218 TCGMemOpIdx oi
, uintptr_t retaddr
)
220 unsigned mmu_idx
= get_mmuidx(oi
);
221 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
222 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
223 int a_bits
= get_alignment_bits(get_memop(oi
));
227 /* Adjust the given return address. */
228 retaddr
-= GETPC_ADJ
;
230 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
231 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
235 /* If the TLB entry is for a different page, reload and try again. */
236 if ((addr
& TARGET_PAGE_MASK
)
237 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
238 if (!VICTIM_TLB_HIT(ADDR_READ
)) {
239 tlb_fill(ENV_GET_CPU(env
), addr
, READ_ACCESS_TYPE
,
242 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].ADDR_READ
;
245 /* Handle an IO access. */
246 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
247 CPUIOTLBEntry
*iotlbentry
;
248 if ((addr
& (DATA_SIZE
- 1)) != 0) {
249 goto do_unaligned_access
;
251 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
253 /* ??? Note that the io helpers always read data in the target
254 byte ordering. We should push the LE/BE request down into io. */
255 res
= glue(io_read
, SUFFIX
)(env
, iotlbentry
, addr
, retaddr
);
260 /* Handle slow unaligned access (it spans two pages or IO). */
262 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
263 >= TARGET_PAGE_SIZE
)) {
264 target_ulong addr1
, addr2
;
265 DATA_TYPE res1
, res2
;
268 addr1
= addr
& ~(DATA_SIZE
- 1);
269 addr2
= addr1
+ DATA_SIZE
;
270 /* Note the adjustment at the beginning of the function.
271 Undo that for the recursion. */
272 res1
= helper_be_ld_name(env
, addr1
, oi
, retaddr
+ GETPC_ADJ
);
273 res2
= helper_be_ld_name(env
, addr2
, oi
, retaddr
+ GETPC_ADJ
);
274 shift
= (addr
& (DATA_SIZE
- 1)) * 8;
276 /* Big-endian combine. */
277 res
= (res1
<< shift
) | (res2
>> ((DATA_SIZE
* 8) - shift
));
281 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
282 res
= glue(glue(ld
, LSUFFIX
), _be_p
)((uint8_t *)haddr
);
285 #endif /* DATA_SIZE > 1 */
287 #ifndef SOFTMMU_CODE_ACCESS
289 /* Provide signed versions of the load routines as well. We can of course
290 avoid this for 64-bit data, or for 32-bit data on 32-bit host. */
291 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
292 WORD_TYPE
helper_le_lds_name(CPUArchState
*env
, target_ulong addr
,
293 TCGMemOpIdx oi
, uintptr_t retaddr
)
295 return (SDATA_TYPE
)helper_le_ld_name(env
, addr
, oi
, retaddr
);
299 WORD_TYPE
helper_be_lds_name(CPUArchState
*env
, target_ulong addr
,
300 TCGMemOpIdx oi
, uintptr_t retaddr
)
302 return (SDATA_TYPE
)helper_be_ld_name(env
, addr
, oi
, retaddr
);
307 static inline void glue(io_write
, SUFFIX
)(CPUArchState
*env
,
308 CPUIOTLBEntry
*iotlbentry
,
313 CPUState
*cpu
= ENV_GET_CPU(env
);
314 hwaddr physaddr
= iotlbentry
->addr
;
315 MemoryRegion
*mr
= iotlb_to_region(cpu
, physaddr
, iotlbentry
->attrs
);
317 physaddr
= (physaddr
& TARGET_PAGE_MASK
) + addr
;
318 if (mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !cpu
->can_do_io
) {
319 cpu_io_recompile(cpu
, retaddr
);
322 cpu
->mem_io_vaddr
= addr
;
323 cpu
->mem_io_pc
= retaddr
;
324 memory_region_dispatch_write(mr
, physaddr
, val
, 1 << SHIFT
,
328 void helper_le_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
329 TCGMemOpIdx oi
, uintptr_t retaddr
)
331 unsigned mmu_idx
= get_mmuidx(oi
);
332 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
333 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
334 int a_bits
= get_alignment_bits(get_memop(oi
));
337 /* Adjust the given return address. */
338 retaddr
-= GETPC_ADJ
;
340 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
341 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
345 /* If the TLB entry is for a different page, reload and try again. */
346 if ((addr
& TARGET_PAGE_MASK
)
347 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
348 if (!VICTIM_TLB_HIT(addr_write
)) {
349 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
351 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
354 /* Handle an IO access. */
355 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
356 CPUIOTLBEntry
*iotlbentry
;
357 if ((addr
& (DATA_SIZE
- 1)) != 0) {
358 goto do_unaligned_access
;
360 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
362 /* ??? Note that the io helpers always read data in the target
363 byte ordering. We should push the LE/BE request down into io. */
365 glue(io_write
, SUFFIX
)(env
, iotlbentry
, val
, addr
, retaddr
);
369 /* Handle slow unaligned access (it spans two pages or IO). */
371 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
372 >= TARGET_PAGE_SIZE
)) {
375 /* XXX: not efficient, but simple */
376 /* Note: relies on the fact that tlb_fill() does not remove the
377 * previous page from the TLB cache. */
378 for (i
= DATA_SIZE
- 1; i
>= 0; i
--) {
379 /* Little-endian extract. */
380 uint8_t val8
= val
>> (i
* 8);
381 /* Note the adjustment at the beginning of the function.
382 Undo that for the recursion. */
383 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
384 oi
, retaddr
+ GETPC_ADJ
);
389 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
391 glue(glue(st
, SUFFIX
), _p
)((uint8_t *)haddr
, val
);
393 glue(glue(st
, SUFFIX
), _le_p
)((uint8_t *)haddr
, val
);
398 void helper_be_st_name(CPUArchState
*env
, target_ulong addr
, DATA_TYPE val
,
399 TCGMemOpIdx oi
, uintptr_t retaddr
)
401 unsigned mmu_idx
= get_mmuidx(oi
);
402 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
403 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
404 int a_bits
= get_alignment_bits(get_memop(oi
));
407 /* Adjust the given return address. */
408 retaddr
-= GETPC_ADJ
;
410 if (a_bits
> 0 && (addr
& ((1 << a_bits
) - 1)) != 0) {
411 cpu_unaligned_access(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
,
415 /* If the TLB entry is for a different page, reload and try again. */
416 if ((addr
& TARGET_PAGE_MASK
)
417 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
418 if (!VICTIM_TLB_HIT(addr_write
)) {
419 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
421 tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
424 /* Handle an IO access. */
425 if (unlikely(tlb_addr
& ~TARGET_PAGE_MASK
)) {
426 CPUIOTLBEntry
*iotlbentry
;
427 if ((addr
& (DATA_SIZE
- 1)) != 0) {
428 goto do_unaligned_access
;
430 iotlbentry
= &env
->iotlb
[mmu_idx
][index
];
432 /* ??? Note that the io helpers always read data in the target
433 byte ordering. We should push the LE/BE request down into io. */
435 glue(io_write
, SUFFIX
)(env
, iotlbentry
, val
, addr
, retaddr
);
439 /* Handle slow unaligned access (it spans two pages or IO). */
441 && unlikely((addr
& ~TARGET_PAGE_MASK
) + DATA_SIZE
- 1
442 >= TARGET_PAGE_SIZE
)) {
445 /* XXX: not efficient, but simple */
446 /* Note: relies on the fact that tlb_fill() does not remove the
447 * previous page from the TLB cache. */
448 for (i
= DATA_SIZE
- 1; i
>= 0; i
--) {
449 /* Big-endian extract. */
450 uint8_t val8
= val
>> (((DATA_SIZE
- 1) * 8) - (i
* 8));
451 /* Note the adjustment at the beginning of the function.
452 Undo that for the recursion. */
453 glue(helper_ret_stb
, MMUSUFFIX
)(env
, addr
+ i
, val8
,
454 oi
, retaddr
+ GETPC_ADJ
);
459 haddr
= addr
+ env
->tlb_table
[mmu_idx
][index
].addend
;
460 glue(glue(st
, SUFFIX
), _be_p
)((uint8_t *)haddr
, val
);
462 #endif /* DATA_SIZE > 1 */
465 /* Probe for whether the specified guest write access is permitted.
466 * If it is not permitted then an exception will be taken in the same
467 * way as if this were a real write access (and we will not return).
468 * Otherwise the function will return, and there will be a valid
469 * entry in the TLB for this access.
471 void probe_write(CPUArchState
*env
, target_ulong addr
, int mmu_idx
,
474 int index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
475 target_ulong tlb_addr
= env
->tlb_table
[mmu_idx
][index
].addr_write
;
477 if ((addr
& TARGET_PAGE_MASK
)
478 != (tlb_addr
& (TARGET_PAGE_MASK
| TLB_INVALID_MASK
))) {
479 /* TLB entry is for a different page */
480 if (!VICTIM_TLB_HIT(addr_write
)) {
481 tlb_fill(ENV_GET_CPU(env
), addr
, MMU_DATA_STORE
, mmu_idx
, retaddr
);
486 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
488 #undef READ_ACCESS_TYPE
504 #undef helper_le_ld_name
505 #undef helper_be_ld_name
506 #undef helper_le_lds_name
507 #undef helper_be_lds_name
508 #undef helper_le_st_name
509 #undef helper_be_st_name
510 #undef helper_te_ld_name
511 #undef helper_te_st_name