softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  * Generate helpers used by TCG for qemu_ld/st ops and code load
   5  * functions.
   6  *
   7  * Included from target op helpers and exec.c.
   8  *
   9  *  Copyright (c) 2003 Fabrice Bellard
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License as published by the Free Software Foundation; either
  14  * version 2 of the License, or (at your option) any later version.
  15  *
  16  * This library is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * Lesser General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU Lesser General Public
  22  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24 #include "qemu/timer.h"
  25 #include "exec/address-spaces.h"
  26 #include "exec/memory.h"
  27
  28 #define DATA_SIZE (1 << SHIFT)
  29
  30 #if DATA_SIZE == 8
  31 #define SUFFIX q
  32 #define LSUFFIX q
  33 #define SDATA_TYPE  int64_t
  34 #define DATA_TYPE  uint64_t
  35 #elif DATA_SIZE == 4
  36 #define SUFFIX l
  37 #define LSUFFIX l
  38 #define SDATA_TYPE  int32_t
  39 #define DATA_TYPE  uint32_t
  40 #elif DATA_SIZE == 2
  41 #define SUFFIX w
  42 #define LSUFFIX uw
  43 #define SDATA_TYPE  int16_t
  44 #define DATA_TYPE  uint16_t
  45 #elif DATA_SIZE == 1
  46 #define SUFFIX b
  47 #define LSUFFIX ub
  48 #define SDATA_TYPE  int8_t
  49 #define DATA_TYPE  uint8_t
  50 #else
  51 #error unsupported data size
  52 #endif
  53
  54
  55 /* For the benefit of TCG generated code, we want to avoid the complication
  56    of ABI-specific return type promotion and always return a value extended
  57    to the register size of the host.  This is tcg_target_long, except in the
  58    case of a 32-bit host and 64-bit data, and for that we always have
  59    uint64_t.  Don't bother with this widened value for SOFTMMU_CODE_ACCESS.  */
  60 #if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8
  61 # define WORD_TYPE  DATA_TYPE
  62 # define USUFFIX    SUFFIX
  63 #else
  64 # define WORD_TYPE  tcg_target_ulong
  65 # define USUFFIX    glue(u, SUFFIX)
  66 # define SSUFFIX    glue(s, SUFFIX)
  67 #endif
  68
  69 #ifdef SOFTMMU_CODE_ACCESS
  70 #define READ_ACCESS_TYPE MMU_INST_FETCH
  71 #define ADDR_READ addr_code
  72 #else
  73 #define READ_ACCESS_TYPE MMU_DATA_LOAD
  74 #define ADDR_READ addr_read
  75 #endif
  76
  77 #if DATA_SIZE == 8
  78 # define BSWAP(X)  bswap64(X)
  79 #elif DATA_SIZE == 4
  80 # define BSWAP(X)  bswap32(X)
  81 #elif DATA_SIZE == 2
  82 # define BSWAP(X)  bswap16(X)
  83 #else
  84 # define BSWAP(X)  (X)
  85 #endif
  86
  87 #ifdef TARGET_WORDS_BIGENDIAN
  88 # define TGT_BE(X)  (X)
  89 # define TGT_LE(X)  BSWAP(X)
  90 #else
  91 # define TGT_BE(X)  BSWAP(X)
  92 # define TGT_LE(X)  (X)
  93 #endif
  94
  95 #if DATA_SIZE == 1
  96 # define helper_le_ld_name  glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)
  97 # define helper_be_ld_name  helper_le_ld_name
  98 # define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX)
  99 # define helper_be_lds_name helper_le_lds_name
 100 # define helper_le_st_name  glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)
 101 # define helper_be_st_name  helper_le_st_name
 102 #else
 103 # define helper_le_ld_name  glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX)
 104 # define helper_be_ld_name  glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX)
 105 # define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX)
 106 # define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX)
 107 # define helper_le_st_name  glue(glue(helper_le_st, SUFFIX), MMUSUFFIX)
 108 # define helper_be_st_name  glue(glue(helper_be_st, SUFFIX), MMUSUFFIX)
 109 #endif
 110
 111 #ifdef TARGET_WORDS_BIGENDIAN
 112 # define helper_te_ld_name  helper_be_ld_name
 113 # define helper_te_st_name  helper_be_st_name
 114 #else
 115 # define helper_te_ld_name  helper_le_ld_name
 116 # define helper_te_st_name  helper_le_st_name
 117 #endif
 118
 119 /* macro to check the victim tlb */
 120 #define VICTIM_TLB_HIT(ty)                                                    \
 121 ({                                                                            \
 122     /* we are about to do a page table walk. our last hope is the             \
 123      * victim tlb. try to refill from the victim tlb before walking the       \
 124      * page table. */                                                         \
 125     int vidx;                                                                 \
 126     hwaddr tmpiotlb;                                                          \
 127     CPUTLBEntry tmptlb;                                                       \
 128     for (vidx = CPU_VTLB_SIZE-1; vidx >= 0; --vidx) {                         \
 129         if (env->tlb_v_table[mmu_idx][vidx].ty == (addr & TARGET_PAGE_MASK)) {\
 130             /* found entry in victim tlb, swap tlb and iotlb */               \
 131             tmptlb = env->tlb_table[mmu_idx][index];                          \
 132             env->tlb_table[mmu_idx][index] = env->tlb_v_table[mmu_idx][vidx]; \
 133             env->tlb_v_table[mmu_idx][vidx] = tmptlb;                         \
 134             tmpiotlb = env->iotlb[mmu_idx][index];                            \
 135             env->iotlb[mmu_idx][index] = env->iotlb_v[mmu_idx][vidx];         \
 136             env->iotlb_v[mmu_idx][vidx] = tmpiotlb;                           \
 137             break;                                                            \
 138         }                                                                     \
 139     }                                                                         \
 140     /* return true when there is a vtlb hit, i.e. vidx >=0 */                 \
 141     vidx >= 0;                                                                \
 142 })
 143
 144 #ifndef SOFTMMU_CODE_ACCESS
 145 static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
 146                                               hwaddr physaddr,
 147                                               target_ulong addr,
 148                                               uintptr_t retaddr)
 149 {
 150     uint64_t val;
 151     CPUState *cpu = ENV_GET_CPU(env);
 152     MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
 153
 154     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 155     cpu->mem_io_pc = retaddr;
 156     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
 157         cpu_io_recompile(cpu, retaddr);
 158     }
 159
 160     cpu->mem_io_vaddr = addr;
 161     memory_region_dispatch_read(mr, physaddr, &val, 1 << SHIFT,
 162                                 MEMTXATTRS_UNSPECIFIED);
 163     return val;
 164 }
 165 #endif
 166
 167 #ifdef SOFTMMU_CODE_ACCESS
 168 static __attribute__((unused))
 169 #endif
 170 WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
 171                             uintptr_t retaddr)
 172 {
 173     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 174     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 175     uintptr_t haddr;
 176     DATA_TYPE res;
 177
 178     /* Adjust the given return address.  */
 179     retaddr -= GETPC_ADJ;
 180
 181     /* If the TLB entry is for a different page, reload and try again.  */
 182     if ((addr & TARGET_PAGE_MASK)
 183          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 184 #ifdef ALIGNED_ONLY
 185         if ((addr & (DATA_SIZE - 1)) != 0) {
 186             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 187                                  mmu_idx, retaddr);
 188         }
 189 #endif
 190         if (!VICTIM_TLB_HIT(ADDR_READ)) {
 191             tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 192                      mmu_idx, retaddr);
 193         }
 194         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 195     }
 196
 197     /* Handle an IO access.  */
 198     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 199         hwaddr ioaddr;
 200         if ((addr & (DATA_SIZE - 1)) != 0) {
 201             goto do_unaligned_access;
 202         }
 203         ioaddr = env->iotlb[mmu_idx][index];
 204
 205         /* ??? Note that the io helpers always read data in the target
 206            byte ordering.  We should push the LE/BE request down into io.  */
 207         res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
 208         res = TGT_LE(res);
 209         return res;
 210     }
 211
 212     /* Handle slow unaligned access (it spans two pages or IO).  */
 213     if (DATA_SIZE > 1
 214         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 215                     >= TARGET_PAGE_SIZE)) {
 216         target_ulong addr1, addr2;
 217         DATA_TYPE res1, res2;
 218         unsigned shift;
 219     do_unaligned_access:
 220 #ifdef ALIGNED_ONLY
 221         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 222                              mmu_idx, retaddr);
 223 #endif
 224         addr1 = addr & ~(DATA_SIZE - 1);
 225         addr2 = addr1 + DATA_SIZE;
 226         /* Note the adjustment at the beginning of the function.
 227            Undo that for the recursion.  */
 228         res1 = helper_le_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
 229         res2 = helper_le_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
 230         shift = (addr & (DATA_SIZE - 1)) * 8;
 231
 232         /* Little-endian combine.  */
 233         res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 234         return res;
 235     }
 236
 237     /* Handle aligned access or unaligned access in the same page.  */
 238 #ifdef ALIGNED_ONLY
 239     if ((addr & (DATA_SIZE - 1)) != 0) {
 240         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 241                              mmu_idx, retaddr);
 242     }
 243 #endif
 244
 245     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 246 #if DATA_SIZE == 1
 247     res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr);
 248 #else
 249     res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr);
 250 #endif
 251     return res;
 252 }
 253
 254 #if DATA_SIZE > 1
 255 #ifdef SOFTMMU_CODE_ACCESS
 256 static __attribute__((unused))
 257 #endif
 258 WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
 259                             uintptr_t retaddr)
 260 {
 261     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 262     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 263     uintptr_t haddr;
 264     DATA_TYPE res;
 265
 266     /* Adjust the given return address.  */
 267     retaddr -= GETPC_ADJ;
 268
 269     /* If the TLB entry is for a different page, reload and try again.  */
 270     if ((addr & TARGET_PAGE_MASK)
 271          != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 272 #ifdef ALIGNED_ONLY
 273         if ((addr & (DATA_SIZE - 1)) != 0) {
 274             cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 275                                  mmu_idx, retaddr);
 276         }
 277 #endif
 278         if (!VICTIM_TLB_HIT(ADDR_READ)) {
 279             tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 280                      mmu_idx, retaddr);
 281         }
 282         tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
 283     }
 284
 285     /* Handle an IO access.  */
 286     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 287         hwaddr ioaddr;
 288         if ((addr & (DATA_SIZE - 1)) != 0) {
 289             goto do_unaligned_access;
 290         }
 291         ioaddr = env->iotlb[mmu_idx][index];
 292
 293         /* ??? Note that the io helpers always read data in the target
 294            byte ordering.  We should push the LE/BE request down into io.  */
 295         res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr);
 296         res = TGT_BE(res);
 297         return res;
 298     }
 299
 300     /* Handle slow unaligned access (it spans two pages or IO).  */
 301     if (DATA_SIZE > 1
 302         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 303                     >= TARGET_PAGE_SIZE)) {
 304         target_ulong addr1, addr2;
 305         DATA_TYPE res1, res2;
 306         unsigned shift;
 307     do_unaligned_access:
 308 #ifdef ALIGNED_ONLY
 309         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 310                              mmu_idx, retaddr);
 311 #endif
 312         addr1 = addr & ~(DATA_SIZE - 1);
 313         addr2 = addr1 + DATA_SIZE;
 314         /* Note the adjustment at the beginning of the function.
 315            Undo that for the recursion.  */
 316         res1 = helper_be_ld_name(env, addr1, mmu_idx, retaddr + GETPC_ADJ);
 317         res2 = helper_be_ld_name(env, addr2, mmu_idx, retaddr + GETPC_ADJ);
 318         shift = (addr & (DATA_SIZE - 1)) * 8;
 319
 320         /* Big-endian combine.  */
 321         res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 322         return res;
 323     }
 324
 325     /* Handle aligned access or unaligned access in the same page.  */
 326 #ifdef ALIGNED_ONLY
 327     if ((addr & (DATA_SIZE - 1)) != 0) {
 328         cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
 329                              mmu_idx, retaddr);
 330     }
 331 #endif
 332
 333     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 334     res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr);
 335     return res;
 336 }
 337 #endif /* DATA_SIZE > 1 */
 338
 339 DATA_TYPE
 340 glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 341                                          int mmu_idx)
 342 {
 343     return helper_te_ld_name (env, addr, mmu_idx, GETRA());
 344 }
 345
 346 #ifndef SOFTMMU_CODE_ACCESS
 347
 348 /* Provide signed versions of the load routines as well.  We can of course
 349    avoid this for 64-bit data, or for 32-bit data on 32-bit host.  */
 350 #if DATA_SIZE * 8 < TCG_TARGET_REG_BITS
 351 WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr,
 352                              int mmu_idx, uintptr_t retaddr)
 353 {
 354     return (SDATA_TYPE)helper_le_ld_name(env, addr, mmu_idx, retaddr);
 355 }
 356
 357 # if DATA_SIZE > 1
 358 WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr,
 359                              int mmu_idx, uintptr_t retaddr)
 360 {
 361     return (SDATA_TYPE)helper_be_ld_name(env, addr, mmu_idx, retaddr);
 362 }
 363 # endif
 364 #endif
 365
 366 static inline void glue(io_write, SUFFIX)(CPUArchState *env,
 367                                           hwaddr physaddr,
 368                                           DATA_TYPE val,
 369                                           target_ulong addr,
 370                                           uintptr_t retaddr)
 371 {
 372     CPUState *cpu = ENV_GET_CPU(env);
 373     MemoryRegion *mr = iotlb_to_region(cpu, physaddr);
 374
 375     physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
 376     if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
 377         cpu_io_recompile(cpu, retaddr);
 378     }
 379
 380     cpu->mem_io_vaddr = addr;
 381     cpu->mem_io_pc = retaddr;
 382     memory_region_dispatch_write(mr, physaddr, val, 1 << SHIFT,
 383                                  MEMTXATTRS_UNSPECIFIED);
 384 }
 385
 386 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 387                        int mmu_idx, uintptr_t retaddr)
 388 {
 389     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 390     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 391     uintptr_t haddr;
 392
 393     /* Adjust the given return address.  */
 394     retaddr -= GETPC_ADJ;
 395
 396     /* If the TLB entry is for a different page, reload and try again.  */
 397     if ((addr & TARGET_PAGE_MASK)
 398         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 399 #ifdef ALIGNED_ONLY
 400         if ((addr & (DATA_SIZE - 1)) != 0) {
 401             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 402                                  mmu_idx, retaddr);
 403         }
 404 #endif
 405         if (!VICTIM_TLB_HIT(addr_write)) {
 406             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 407         }
 408         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 409     }
 410
 411     /* Handle an IO access.  */
 412     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 413         hwaddr ioaddr;
 414         if ((addr & (DATA_SIZE - 1)) != 0) {
 415             goto do_unaligned_access;
 416         }
 417         ioaddr = env->iotlb[mmu_idx][index];
 418
 419         /* ??? Note that the io helpers always read data in the target
 420            byte ordering.  We should push the LE/BE request down into io.  */
 421         val = TGT_LE(val);
 422         glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
 423         return;
 424     }
 425
 426     /* Handle slow unaligned access (it spans two pages or IO).  */
 427     if (DATA_SIZE > 1
 428         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 429                      >= TARGET_PAGE_SIZE)) {
 430         int i;
 431     do_unaligned_access:
 432 #ifdef ALIGNED_ONLY
 433         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 434                              mmu_idx, retaddr);
 435 #endif
 436         /* XXX: not efficient, but simple */
 437         /* Note: relies on the fact that tlb_fill() does not remove the
 438          * previous page from the TLB cache.  */
 439         for (i = DATA_SIZE - 1; i >= 0; i--) {
 440             /* Little-endian extract.  */
 441             uint8_t val8 = val >> (i * 8);
 442             /* Note the adjustment at the beginning of the function.
 443                Undo that for the recursion.  */
 444             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 445                                             mmu_idx, retaddr + GETPC_ADJ);
 446         }
 447         return;
 448     }
 449
 450     /* Handle aligned access or unaligned access in the same page.  */
 451 #ifdef ALIGNED_ONLY
 452     if ((addr & (DATA_SIZE - 1)) != 0) {
 453         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 454                              mmu_idx, retaddr);
 455     }
 456 #endif
 457
 458     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 459 #if DATA_SIZE == 1
 460     glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val);
 461 #else
 462     glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val);
 463 #endif
 464 }
 465
 466 #if DATA_SIZE > 1
 467 void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
 468                        int mmu_idx, uintptr_t retaddr)
 469 {
 470     int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 471     target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 472     uintptr_t haddr;
 473
 474     /* Adjust the given return address.  */
 475     retaddr -= GETPC_ADJ;
 476
 477     /* If the TLB entry is for a different page, reload and try again.  */
 478     if ((addr & TARGET_PAGE_MASK)
 479         != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 480 #ifdef ALIGNED_ONLY
 481         if ((addr & (DATA_SIZE - 1)) != 0) {
 482             cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 483                                  mmu_idx, retaddr);
 484         }
 485 #endif
 486         if (!VICTIM_TLB_HIT(addr_write)) {
 487             tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
 488         }
 489         tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
 490     }
 491
 492     /* Handle an IO access.  */
 493     if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
 494         hwaddr ioaddr;
 495         if ((addr & (DATA_SIZE - 1)) != 0) {
 496             goto do_unaligned_access;
 497         }
 498         ioaddr = env->iotlb[mmu_idx][index];
 499
 500         /* ??? Note that the io helpers always read data in the target
 501            byte ordering.  We should push the LE/BE request down into io.  */
 502         val = TGT_BE(val);
 503         glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr);
 504         return;
 505     }
 506
 507     /* Handle slow unaligned access (it spans two pages or IO).  */
 508     if (DATA_SIZE > 1
 509         && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
 510                      >= TARGET_PAGE_SIZE)) {
 511         int i;
 512     do_unaligned_access:
 513 #ifdef ALIGNED_ONLY
 514         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 515                              mmu_idx, retaddr);
 516 #endif
 517         /* XXX: not efficient, but simple */
 518         /* Note: relies on the fact that tlb_fill() does not remove the
 519          * previous page from the TLB cache.  */
 520         for (i = DATA_SIZE - 1; i >= 0; i--) {
 521             /* Big-endian extract.  */
 522             uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8));
 523             /* Note the adjustment at the beginning of the function.
 524                Undo that for the recursion.  */
 525             glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8,
 526                                             mmu_idx, retaddr + GETPC_ADJ);
 527         }
 528         return;
 529     }
 530
 531     /* Handle aligned access or unaligned access in the same page.  */
 532 #ifdef ALIGNED_ONLY
 533     if ((addr & (DATA_SIZE - 1)) != 0) {
 534         cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
 535                              mmu_idx, retaddr);
 536     }
 537 #endif
 538
 539     haddr = addr + env->tlb_table[mmu_idx][index].addend;
 540     glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val);
 541 }
 542 #endif /* DATA_SIZE > 1 */
 543
 544 void
 545 glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
 546                                          DATA_TYPE val, int mmu_idx)
 547 {
 548     helper_te_st_name(env, addr, val, mmu_idx, GETRA());
 549 }
 550
 551 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 552
 553 #undef READ_ACCESS_TYPE
 554 #undef SHIFT
 555 #undef DATA_TYPE
 556 #undef SUFFIX
 557 #undef LSUFFIX
 558 #undef DATA_SIZE
 559 #undef ADDR_READ
 560 #undef WORD_TYPE
 561 #undef SDATA_TYPE
 562 #undef USUFFIX
 563 #undef SSUFFIX
 564 #undef BSWAP
 565 #undef TGT_BE
 566 #undef TGT_LE
 567 #undef CPU_BE
 568 #undef CPU_LE
 569 #undef helper_le_ld_name
 570 #undef helper_be_ld_name
 571 #undef helper_le_lds_name
 572 #undef helper_be_lds_name
 573 #undef helper_le_st_name
 574 #undef helper_be_st_name
 575 #undef helper_te_ld_name
 576 #undef helper_te_st_name