sound/hda/hdac_stream.c

   1 /*
   2  * HD-audio stream operations
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/export.h>
   8 #include <linux/clocksource.h>
   9 #include <sound/core.h>
  10 #include <sound/pcm.h>
  11 #include <sound/hdaudio.h>
  12 #include <sound/hda_register.h>
  13
  14 /**
  15  * snd_hdac_stream_init - initialize each stream (aka device)
  16  * @bus: HD-audio core bus
  17  * @azx_dev: HD-audio core stream object to initialize
  18  * @idx: stream index number
  19  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  20  * @tag: the tag id to assign
  21  *
  22  * Assign the starting bdl address to each stream (device) and initialize.
  23  */
  24 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  25                           int idx, int direction, int tag)
  26 {
  27         azx_dev->bus = bus;
  28         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  29         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
  30         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  31         azx_dev->sd_int_sta_mask = 1 << idx;
  32         azx_dev->index = idx;
  33         azx_dev->direction = direction;
  34         azx_dev->stream_tag = tag;
  35         snd_hdac_dsp_lock_init(azx_dev);
  36         list_add_tail(&azx_dev->list, &bus->stream_list);
  37 }
  38 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
  39
  40 /**
  41  * snd_hdac_stream_start - start a stream
  42  * @azx_dev: HD-audio core stream to start
  43  * @fresh_start: false = wallclock timestamp relative to period wallclock
  44  *
  45  * Start a stream, set start_wallclk and set the running flag.
  46  */
  47 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
  48 {
  49         struct hdac_bus *bus = azx_dev->bus;
  50
  51         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
  52         if (!fresh_start)
  53                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
  54
  55         /* enable SIE */
  56         snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
  57         /* set DMA start and interrupt mask */
  58         snd_hdac_stream_updateb(azx_dev, SD_CTL,
  59                                 0, SD_CTL_DMA_START | SD_INT_MASK);
  60         azx_dev->running = true;
  61 }
  62 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
  63
  64 /**
  65  * snd_hdac_stream_clear - stop a stream DMA
  66  * @azx_dev: HD-audio core stream to stop
  67  */
  68 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
  69 {
  70         snd_hdac_stream_updateb(azx_dev, SD_CTL,
  71                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
  72         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
  73         azx_dev->running = false;
  74 }
  75 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
  76
  77 /**
  78  * snd_hdac_stream_stop - stop a stream
  79  * @azx_dev: HD-audio core stream to stop
  80  *
  81  * Stop a stream DMA and disable stream interrupt
  82  */
  83 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
  84 {
  85         snd_hdac_stream_clear(azx_dev);
  86         /* disable SIE */
  87         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
  88 }
  89 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
  90
  91 /**
  92  * snd_hdac_stream_reset - reset a stream
  93  * @azx_dev: HD-audio core stream to reset
  94  */
  95 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
  96 {
  97         unsigned char val;
  98         int timeout;
  99
 100         snd_hdac_stream_clear(azx_dev);
 101
 102         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 103         udelay(3);
 104         timeout = 300;
 105         do {
 106                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 107                         SD_CTL_STREAM_RESET;
 108                 if (val)
 109                         break;
 110         } while (--timeout);
 111         val &= ~SD_CTL_STREAM_RESET;
 112         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
 113         udelay(3);
 114
 115         timeout = 300;
 116         /* waiting for hardware to report that the stream is out of reset */
 117         do {
 118                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 119                         SD_CTL_STREAM_RESET;
 120                 if (!val)
 121                         break;
 122         } while (--timeout);
 123
 124         /* reset first position - may not be synced with hw at this time */
 125         if (azx_dev->posbuf)
 126                 *azx_dev->posbuf = 0;
 127 }
 128 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 129
 130 /**
 131  * snd_hdac_stream_setup -  set up the SD for streaming
 132  * @azx_dev: HD-audio core stream to set up
 133  */
 134 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 135 {
 136         struct hdac_bus *bus = azx_dev->bus;
 137         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 138         unsigned int val;
 139
 140         /* make sure the run bit is zero for SD */
 141         snd_hdac_stream_clear(azx_dev);
 142         /* program the stream_tag */
 143         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 144         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 145                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 146         if (!bus->snoop)
 147                 val |= SD_CTL_TRAFFIC_PRIO;
 148         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 149
 150         /* program the length of samples in cyclic buffer */
 151         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 152
 153         /* program the stream format */
 154         /* this value needs to be the same as the one programmed */
 155         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 156
 157         /* program the stream LVI (last valid index) of the BDL */
 158         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 159
 160         /* program the BDL address */
 161         /* lower BDL address */
 162         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 163         /* upper BDL address */
 164         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 165                                upper_32_bits(azx_dev->bdl.addr));
 166
 167         /* enable the position buffer */
 168         if (bus->use_posbuf && bus->posbuf.addr) {
 169                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 170                         snd_hdac_chip_writel(bus, DPLBASE,
 171                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 172         }
 173
 174         /* set the interrupt enable bits in the descriptor control register */
 175         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 176
 177         if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
 178                 azx_dev->fifo_size =
 179                         snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 180         else
 181                 azx_dev->fifo_size = 0;
 182
 183         /* when LPIB delay correction gives a small negative value,
 184          * we ignore it; currently set the threshold statically to
 185          * 64 frames
 186          */
 187         if (runtime->period_size > 64)
 188                 azx_dev->delay_negative_threshold =
 189                         -frames_to_bytes(runtime, 64);
 190         else
 191                 azx_dev->delay_negative_threshold = 0;
 192
 193         /* wallclk has 24Mhz clock source */
 194         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 195                                     runtime->rate) * 1000);
 196
 197         return 0;
 198 }
 199 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 200
 201 /**
 202  * snd_hdac_stream_cleanup - cleanup a stream
 203  * @azx_dev: HD-audio core stream to clean up
 204  */
 205 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 206 {
 207         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 208         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 209         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 210         azx_dev->bufsize = 0;
 211         azx_dev->period_bytes = 0;
 212         azx_dev->format_val = 0;
 213 }
 214 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 215
 216 /**
 217  * snd_hdac_stream_assign - assign a stream for the PCM
 218  * @bus: HD-audio core bus
 219  * @substream: PCM substream to assign
 220  *
 221  * Look for an unused stream for the given PCM substream, assign it
 222  * and return the stream object.  If no stream is free, returns NULL.
 223  * The function tries to keep using the same stream object when it's used
 224  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 225  * or matching entry is returned.  This is needed for some strange codecs.
 226  */
 227 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 228                                            struct snd_pcm_substream *substream)
 229 {
 230         struct hdac_stream *azx_dev;
 231         struct hdac_stream *res = NULL;
 232
 233         /* make a non-zero unique key for the substream */
 234         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 235                 (substream->stream + 1);
 236
 237         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 238                 if (azx_dev->direction != substream->stream)
 239                         continue;
 240                 if (azx_dev->opened)
 241                         continue;
 242                 if (azx_dev->assigned_key == key) {
 243                         res = azx_dev;
 244                         break;
 245                 }
 246                 if (!res || bus->reverse_assign)
 247                         res = azx_dev;
 248         }
 249         if (res) {
 250                 spin_lock_irq(&bus->reg_lock);
 251                 res->opened = 1;
 252                 res->running = 0;
 253                 res->assigned_key = key;
 254                 res->substream = substream;
 255                 spin_unlock_irq(&bus->reg_lock);
 256         }
 257         return res;
 258 }
 259 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 260
 261 /**
 262  * snd_hdac_stream_release - release the assigned stream
 263  * @azx_dev: HD-audio core stream to release
 264  *
 265  * Release the stream that has been assigned by snd_hdac_stream_assign().
 266  */
 267 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 268 {
 269         struct hdac_bus *bus = azx_dev->bus;
 270
 271         spin_lock_irq(&bus->reg_lock);
 272         azx_dev->opened = 0;
 273         azx_dev->running = 0;
 274         azx_dev->substream = NULL;
 275         spin_unlock_irq(&bus->reg_lock);
 276 }
 277 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 278
 279 /*
 280  * set up a BDL entry
 281  */
 282 static int setup_bdle(struct hdac_bus *bus,
 283                       struct snd_dma_buffer *dmab,
 284                       struct hdac_stream *azx_dev, __le32 **bdlp,
 285                       int ofs, int size, int with_ioc)
 286 {
 287         __le32 *bdl = *bdlp;
 288
 289         while (size > 0) {
 290                 dma_addr_t addr;
 291                 int chunk;
 292
 293                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 294                         return -EINVAL;
 295
 296                 addr = snd_sgbuf_get_addr(dmab, ofs);
 297                 /* program the address field of the BDL entry */
 298                 bdl[0] = cpu_to_le32((u32)addr);
 299                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 300                 /* program the size field of the BDL entry */
 301                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 302                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 303                 if (bus->align_bdle_4k) {
 304                         u32 remain = 0x1000 - (ofs & 0xfff);
 305
 306                         if (chunk > remain)
 307                                 chunk = remain;
 308                 }
 309                 bdl[2] = cpu_to_le32(chunk);
 310                 /* program the IOC to enable interrupt
 311                  * only when the whole fragment is processed
 312                  */
 313                 size -= chunk;
 314                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 315                 bdl += 4;
 316                 azx_dev->frags++;
 317                 ofs += chunk;
 318         }
 319         *bdlp = bdl;
 320         return ofs;
 321 }
 322
 323 /**
 324  * snd_hdac_stream_setup_periods - set up BDL entries
 325  * @azx_dev: HD-audio core stream to set up
 326  *
 327  * Set up the buffer descriptor table of the given stream based on the
 328  * period and buffer sizes of the assigned PCM substream.
 329  */
 330 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 331 {
 332         struct hdac_bus *bus = azx_dev->bus;
 333         struct snd_pcm_substream *substream = azx_dev->substream;
 334         struct snd_pcm_runtime *runtime = substream->runtime;
 335         __le32 *bdl;
 336         int i, ofs, periods, period_bytes;
 337         int pos_adj, pos_align;
 338
 339         /* reset BDL address */
 340         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 341         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 342
 343         period_bytes = azx_dev->period_bytes;
 344         periods = azx_dev->bufsize / period_bytes;
 345
 346         /* program the initial BDL entries */
 347         bdl = (__le32 *)azx_dev->bdl.area;
 348         ofs = 0;
 349         azx_dev->frags = 0;
 350
 351         pos_adj = bus->bdl_pos_adj;
 352         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 353                 pos_align = pos_adj;
 354                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 355                 if (!pos_adj)
 356                         pos_adj = pos_align;
 357                 else
 358                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 359                                 pos_align;
 360                 pos_adj = frames_to_bytes(runtime, pos_adj);
 361                 if (pos_adj >= period_bytes) {
 362                         dev_warn(bus->dev, "Too big adjustment %d\n",
 363                                  pos_adj);
 364                         pos_adj = 0;
 365                 } else {
 366                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 367                                          azx_dev,
 368                                          &bdl, ofs, pos_adj, true);
 369                         if (ofs < 0)
 370                                 goto error;
 371                 }
 372         } else
 373                 pos_adj = 0;
 374
 375         for (i = 0; i < periods; i++) {
 376                 if (i == periods - 1 && pos_adj)
 377                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 378                                          azx_dev, &bdl, ofs,
 379                                          period_bytes - pos_adj, 0);
 380                 else
 381                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 382                                          azx_dev, &bdl, ofs,
 383                                          period_bytes,
 384                                          !azx_dev->no_period_wakeup);
 385                 if (ofs < 0)
 386                         goto error;
 387         }
 388         return 0;
 389
 390  error:
 391         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 392                 azx_dev->bufsize, period_bytes);
 393         return -EINVAL;
 394 }
 395 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 396
 397 /* snd_hdac_stream_set_params - set stream parameters
 398  * @azx_dev: HD-audio core stream for which parameters are to be set
 399  * @format_val: format value parameter
 400  *
 401  * Setup the HD-audio core stream parameters from substream of the stream
 402  * and passed format value
 403  */
 404 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 405                                  unsigned int format_val)
 406 {
 407
 408         unsigned int bufsize, period_bytes;
 409         struct snd_pcm_substream *substream = azx_dev->substream;
 410         struct snd_pcm_runtime *runtime;
 411         int err;
 412
 413         if (!substream)
 414                 return -EINVAL;
 415         runtime = substream->runtime;
 416         bufsize = snd_pcm_lib_buffer_bytes(substream);
 417         period_bytes = snd_pcm_lib_period_bytes(substream);
 418
 419         if (bufsize != azx_dev->bufsize ||
 420             period_bytes != azx_dev->period_bytes ||
 421             format_val != azx_dev->format_val ||
 422             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 423                 azx_dev->bufsize = bufsize;
 424                 azx_dev->period_bytes = period_bytes;
 425                 azx_dev->format_val = format_val;
 426                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 427                 err = snd_hdac_stream_setup_periods(azx_dev);
 428                 if (err < 0)
 429                         return err;
 430         }
 431         return 0;
 432 }
 433 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 434
 435 static cycle_t azx_cc_read(const struct cyclecounter *cc)
 436 {
 437         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 438
 439         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 440 }
 441
 442 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 443                                  bool force, cycle_t last)
 444 {
 445         struct timecounter *tc = &azx_dev->tc;
 446         struct cyclecounter *cc = &azx_dev->cc;
 447         u64 nsec;
 448
 449         cc->read = azx_cc_read;
 450         cc->mask = CLOCKSOURCE_MASK(32);
 451
 452         /*
 453          * Converting from 24 MHz to ns means applying a 125/3 factor.
 454          * To avoid any saturation issues in intermediate operations,
 455          * the 125 factor is applied first. The division is applied
 456          * last after reading the timecounter value.
 457          * Applying the 1/3 factor as part of the multiplication
 458          * requires at least 20 bits for a decent precision, however
 459          * overflows occur after about 4 hours or less, not a option.
 460          */
 461
 462         cc->mult = 125; /* saturation after 195 years */
 463         cc->shift = 0;
 464
 465         nsec = 0; /* audio time is elapsed time since trigger */
 466         timecounter_init(tc, cc, nsec);
 467         if (force) {
 468                 /*
 469                  * force timecounter to use predefined value,
 470                  * used for synchronized starts
 471                  */
 472                 tc->cycle_last = last;
 473         }
 474 }
 475
 476 /**
 477  * snd_hdac_stream_timecounter_init - initialize time counter
 478  * @azx_dev: HD-audio core stream (master stream)
 479  * @streams: bit flags of streams to set up
 480  *
 481  * Initializes the time counter of streams marked by the bit flags (each
 482  * bit corresponds to the stream index).
 483  * The trigger timestamp of PCM substream assigned to the given stream is
 484  * updated accordingly, too.
 485  */
 486 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 487                                       unsigned int streams)
 488 {
 489         struct hdac_bus *bus = azx_dev->bus;
 490         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 491         struct hdac_stream *s;
 492         bool inited = false;
 493         cycle_t cycle_last = 0;
 494         int i = 0;
 495
 496         list_for_each_entry(s, &bus->stream_list, list) {
 497                 if (streams & (1 << i)) {
 498                         azx_timecounter_init(s, inited, cycle_last);
 499                         if (!inited) {
 500                                 inited = true;
 501                                 cycle_last = s->tc.cycle_last;
 502                         }
 503                 }
 504                 i++;
 505         }
 506
 507         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 508         runtime->trigger_tstamp_latched = true;
 509 }
 510 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 511
 512 /**
 513  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 514  * @azx_dev: HD-audio core stream (master stream)
 515  * @streams: bit flags of streams to sync
 516  */
 517 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 518                                   unsigned int streams, unsigned int reg)
 519 {
 520         struct hdac_bus *bus = azx_dev->bus;
 521         unsigned int val;
 522
 523         if (!reg)
 524                 reg = AZX_REG_SSYNC;
 525         val = _snd_hdac_chip_read(l, bus, reg);
 526         if (set)
 527                 val |= streams;
 528         else
 529                 val &= ~streams;
 530         _snd_hdac_chip_write(l, bus, reg, val);
 531 }
 532 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 533
 534 /**
 535  * snd_hdac_stream_sync - sync with start/strop trigger operation
 536  * @azx_dev: HD-audio core stream (master stream)
 537  * @start: true = start, false = stop
 538  * @streams: bit flags of streams to sync
 539  *
 540  * For @start = true, wait until all FIFOs get ready.
 541  * For @start = false, wait until all RUN bits are cleared.
 542  */
 543 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 544                           unsigned int streams)
 545 {
 546         struct hdac_bus *bus = azx_dev->bus;
 547         int i, nwait, timeout;
 548         struct hdac_stream *s;
 549
 550         for (timeout = 5000; timeout; timeout--) {
 551                 nwait = 0;
 552                 i = 0;
 553                 list_for_each_entry(s, &bus->stream_list, list) {
 554                         if (streams & (1 << i)) {
 555                                 if (start) {
 556                                         /* check FIFO gets ready */
 557                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
 558                                               SD_STS_FIFO_READY))
 559                                                 nwait++;
 560                                 } else {
 561                                         /* check RUN bit is cleared */
 562                                         if (snd_hdac_stream_readb(s, SD_CTL) &
 563                                             SD_CTL_DMA_START)
 564                                                 nwait++;
 565                                 }
 566                         }
 567                         i++;
 568                 }
 569                 if (!nwait)
 570                         break;
 571                 cpu_relax();
 572         }
 573 }
 574 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 575
 576 #ifdef CONFIG_SND_HDA_DSP_LOADER
 577 /**
 578  * snd_hdac_dsp_prepare - prepare for DSP loading
 579  * @azx_dev: HD-audio core stream used for DSP loading
 580  * @format: HD-audio stream format
 581  * @byte_size: data chunk byte size
 582  * @bufp: allocated buffer
 583  *
 584  * Allocate the buffer for the given size and set up the given stream for
 585  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 586  */
 587 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 588                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 589 {
 590         struct hdac_bus *bus = azx_dev->bus;
 591         u32 *bdl;
 592         int err;
 593
 594         snd_hdac_dsp_lock(azx_dev);
 595         spin_lock_irq(&bus->reg_lock);
 596         if (azx_dev->running || azx_dev->locked) {
 597                 spin_unlock_irq(&bus->reg_lock);
 598                 err = -EBUSY;
 599                 goto unlock;
 600         }
 601         azx_dev->locked = true;
 602         spin_unlock_irq(&bus->reg_lock);
 603
 604         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
 605                                            byte_size, bufp);
 606         if (err < 0)
 607                 goto err_alloc;
 608
 609         azx_dev->bufsize = byte_size;
 610         azx_dev->period_bytes = byte_size;
 611         azx_dev->format_val = format;
 612
 613         snd_hdac_stream_reset(azx_dev);
 614
 615         /* reset BDL address */
 616         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 617         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 618
 619         azx_dev->frags = 0;
 620         bdl = (u32 *)azx_dev->bdl.area;
 621         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 622         if (err < 0)
 623                 goto error;
 624
 625         snd_hdac_stream_setup(azx_dev);
 626         snd_hdac_dsp_unlock(azx_dev);
 627         return azx_dev->stream_tag;
 628
 629  error:
 630         bus->io_ops->dma_free_pages(bus, bufp);
 631  err_alloc:
 632         spin_lock_irq(&bus->reg_lock);
 633         azx_dev->locked = false;
 634         spin_unlock_irq(&bus->reg_lock);
 635  unlock:
 636         snd_hdac_dsp_unlock(azx_dev);
 637         return err;
 638 }
 639 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 640
 641 /**
 642  * snd_hdac_dsp_trigger - start / stop DSP loading
 643  * @azx_dev: HD-audio core stream used for DSP loading
 644  * @start: trigger start or stop
 645  */
 646 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 647 {
 648         if (start)
 649                 snd_hdac_stream_start(azx_dev, true);
 650         else
 651                 snd_hdac_stream_stop(azx_dev);
 652 }
 653 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 654
 655 /**
 656  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 657  * @azx_dev: HD-audio core stream used for DSP loading
 658  * @dmab: buffer used by DSP loading
 659  */
 660 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 661                           struct snd_dma_buffer *dmab)
 662 {
 663         struct hdac_bus *bus = azx_dev->bus;
 664
 665         if (!dmab->area || !azx_dev->locked)
 666                 return;
 667
 668         snd_hdac_dsp_lock(azx_dev);
 669         /* reset BDL address */
 670         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 671         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 672         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 673         azx_dev->bufsize = 0;
 674         azx_dev->period_bytes = 0;
 675         azx_dev->format_val = 0;
 676
 677         bus->io_ops->dma_free_pages(bus, dmab);
 678         dmab->area = NULL;
 679
 680         spin_lock_irq(&bus->reg_lock);
 681         azx_dev->locked = false;
 682         spin_unlock_irq(&bus->reg_lock);
 683         snd_hdac_dsp_unlock(azx_dev);
 684 }
 685 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
 686 #endif /* CONFIG_SND_HDA_DSP_LOADER */