2 * HD-audio stream operations
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <linux/clocksource.h>
9 #include <sound/core.h>
10 #include <sound/pcm.h>
11 #include <sound/hdaudio.h>
12 #include <sound/hda_register.h>
15 * snd_hdac_stream_init - initialize each stream (aka device)
16 * @bus: HD-audio core bus
17 * @azx_dev: HD-audio core stream object to initialize
18 * @idx: stream index number
19 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
20 * @tag: the tag id to assign
22 * Assign the starting bdl address to each stream (device) and initialize.
24 void snd_hdac_stream_init(struct hdac_bus
*bus
, struct hdac_stream
*azx_dev
,
25 int idx
, int direction
, int tag
)
28 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
29 azx_dev
->sd_addr
= bus
->remap_addr
+ (0x20 * idx
+ 0x80);
30 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
31 azx_dev
->sd_int_sta_mask
= 1 << idx
;
33 azx_dev
->direction
= direction
;
34 azx_dev
->stream_tag
= tag
;
35 snd_hdac_dsp_lock_init(azx_dev
);
36 list_add_tail(&azx_dev
->list
, &bus
->stream_list
);
38 EXPORT_SYMBOL_GPL(snd_hdac_stream_init
);
41 * snd_hdac_stream_start - start a stream
42 * @azx_dev: HD-audio core stream to start
43 * @fresh_start: false = wallclock timestamp relative to period wallclock
45 * Start a stream, set start_wallclk and set the running flag.
47 void snd_hdac_stream_start(struct hdac_stream
*azx_dev
, bool fresh_start
)
49 struct hdac_bus
*bus
= azx_dev
->bus
;
51 azx_dev
->start_wallclk
= snd_hdac_chip_readl(bus
, WALLCLK
);
53 azx_dev
->start_wallclk
-= azx_dev
->period_wallclk
;
56 snd_hdac_chip_updatel(bus
, INTCTL
, 0, 1 << azx_dev
->index
);
57 /* set DMA start and interrupt mask */
58 snd_hdac_stream_updateb(azx_dev
, SD_CTL
,
59 0, SD_CTL_DMA_START
| SD_INT_MASK
);
60 azx_dev
->running
= true;
62 EXPORT_SYMBOL_GPL(snd_hdac_stream_start
);
65 * snd_hdac_stream_clear - stop a stream DMA
66 * @azx_dev: HD-audio core stream to stop
68 void snd_hdac_stream_clear(struct hdac_stream
*azx_dev
)
70 snd_hdac_stream_updateb(azx_dev
, SD_CTL
,
71 SD_CTL_DMA_START
| SD_INT_MASK
, 0);
72 snd_hdac_stream_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
73 azx_dev
->running
= false;
75 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear
);
78 * snd_hdac_stream_stop - stop a stream
79 * @azx_dev: HD-audio core stream to stop
81 * Stop a stream DMA and disable stream interrupt
83 void snd_hdac_stream_stop(struct hdac_stream
*azx_dev
)
85 snd_hdac_stream_clear(azx_dev
);
87 snd_hdac_chip_updatel(azx_dev
->bus
, INTCTL
, 1 << azx_dev
->index
, 0);
89 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop
);
92 * snd_hdac_stream_reset - reset a stream
93 * @azx_dev: HD-audio core stream to reset
95 void snd_hdac_stream_reset(struct hdac_stream
*azx_dev
)
100 snd_hdac_stream_clear(azx_dev
);
102 snd_hdac_stream_updateb(azx_dev
, SD_CTL
, 0, SD_CTL_STREAM_RESET
);
106 val
= snd_hdac_stream_readb(azx_dev
, SD_CTL
) &
111 val
&= ~SD_CTL_STREAM_RESET
;
112 snd_hdac_stream_writeb(azx_dev
, SD_CTL
, val
);
116 /* waiting for hardware to report that the stream is out of reset */
118 val
= snd_hdac_stream_readb(azx_dev
, SD_CTL
) &
124 /* reset first position - may not be synced with hw at this time */
126 *azx_dev
->posbuf
= 0;
128 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset
);
131 * snd_hdac_stream_setup - set up the SD for streaming
132 * @azx_dev: HD-audio core stream to set up
134 int snd_hdac_stream_setup(struct hdac_stream
*azx_dev
)
136 struct hdac_bus
*bus
= azx_dev
->bus
;
137 struct snd_pcm_runtime
*runtime
= azx_dev
->substream
->runtime
;
140 /* make sure the run bit is zero for SD */
141 snd_hdac_stream_clear(azx_dev
);
142 /* program the stream_tag */
143 val
= snd_hdac_stream_readl(azx_dev
, SD_CTL
);
144 val
= (val
& ~SD_CTL_STREAM_TAG_MASK
) |
145 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
);
147 val
|= SD_CTL_TRAFFIC_PRIO
;
148 snd_hdac_stream_writel(azx_dev
, SD_CTL
, val
);
150 /* program the length of samples in cyclic buffer */
151 snd_hdac_stream_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
153 /* program the stream format */
154 /* this value needs to be the same as the one programmed */
155 snd_hdac_stream_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
157 /* program the stream LVI (last valid index) of the BDL */
158 snd_hdac_stream_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
160 /* program the BDL address */
161 /* lower BDL address */
162 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
163 /* upper BDL address */
164 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
,
165 upper_32_bits(azx_dev
->bdl
.addr
));
167 /* enable the position buffer */
168 if (bus
->use_posbuf
&& bus
->posbuf
.addr
) {
169 if (!(snd_hdac_chip_readl(bus
, DPLBASE
) & AZX_DPLBASE_ENABLE
))
170 snd_hdac_chip_writel(bus
, DPLBASE
,
171 (u32
)bus
->posbuf
.addr
| AZX_DPLBASE_ENABLE
);
174 /* set the interrupt enable bits in the descriptor control register */
175 snd_hdac_stream_updatel(azx_dev
, SD_CTL
, 0, SD_INT_MASK
);
177 if (azx_dev
->direction
== SNDRV_PCM_STREAM_PLAYBACK
)
179 snd_hdac_stream_readw(azx_dev
, SD_FIFOSIZE
) + 1;
181 azx_dev
->fifo_size
= 0;
183 /* when LPIB delay correction gives a small negative value,
184 * we ignore it; currently set the threshold statically to
187 if (runtime
->period_size
> 64)
188 azx_dev
->delay_negative_threshold
=
189 -frames_to_bytes(runtime
, 64);
191 azx_dev
->delay_negative_threshold
= 0;
193 /* wallclk has 24Mhz clock source */
194 azx_dev
->period_wallclk
= (((runtime
->period_size
* 24000) /
195 runtime
->rate
) * 1000);
199 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup
);
202 * snd_hdac_stream_cleanup - cleanup a stream
203 * @azx_dev: HD-audio core stream to clean up
205 void snd_hdac_stream_cleanup(struct hdac_stream
*azx_dev
)
207 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
208 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
209 snd_hdac_stream_writel(azx_dev
, SD_CTL
, 0);
210 azx_dev
->bufsize
= 0;
211 azx_dev
->period_bytes
= 0;
212 azx_dev
->format_val
= 0;
214 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup
);
217 * snd_hdac_stream_assign - assign a stream for the PCM
218 * @bus: HD-audio core bus
219 * @substream: PCM substream to assign
221 * Look for an unused stream for the given PCM substream, assign it
222 * and return the stream object. If no stream is free, returns NULL.
223 * The function tries to keep using the same stream object when it's used
224 * beforehand. Also, when bus->reverse_assign flag is set, the last free
225 * or matching entry is returned. This is needed for some strange codecs.
227 struct hdac_stream
*snd_hdac_stream_assign(struct hdac_bus
*bus
,
228 struct snd_pcm_substream
*substream
)
230 struct hdac_stream
*azx_dev
;
231 struct hdac_stream
*res
= NULL
;
233 /* make a non-zero unique key for the substream */
234 int key
= (substream
->pcm
->device
<< 16) | (substream
->number
<< 2) |
235 (substream
->stream
+ 1);
237 list_for_each_entry(azx_dev
, &bus
->stream_list
, list
) {
238 if (azx_dev
->direction
!= substream
->stream
)
242 if (azx_dev
->assigned_key
== key
) {
246 if (!res
|| bus
->reverse_assign
)
250 spin_lock_irq(&bus
->reg_lock
);
253 res
->assigned_key
= key
;
254 res
->substream
= substream
;
255 spin_unlock_irq(&bus
->reg_lock
);
259 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign
);
262 * snd_hdac_stream_release - release the assigned stream
263 * @azx_dev: HD-audio core stream to release
265 * Release the stream that has been assigned by snd_hdac_stream_assign().
267 void snd_hdac_stream_release(struct hdac_stream
*azx_dev
)
269 struct hdac_bus
*bus
= azx_dev
->bus
;
271 spin_lock_irq(&bus
->reg_lock
);
273 azx_dev
->running
= 0;
274 azx_dev
->substream
= NULL
;
275 spin_unlock_irq(&bus
->reg_lock
);
277 EXPORT_SYMBOL_GPL(snd_hdac_stream_release
);
282 static int setup_bdle(struct hdac_bus
*bus
,
283 struct snd_dma_buffer
*dmab
,
284 struct hdac_stream
*azx_dev
, __le32
**bdlp
,
285 int ofs
, int size
, int with_ioc
)
293 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
296 addr
= snd_sgbuf_get_addr(dmab
, ofs
);
297 /* program the address field of the BDL entry */
298 bdl
[0] = cpu_to_le32((u32
)addr
);
299 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
300 /* program the size field of the BDL entry */
301 chunk
= snd_sgbuf_get_chunk_size(dmab
, ofs
, size
);
302 /* one BDLE cannot cross 4K boundary on CTHDA chips */
303 if (bus
->align_bdle_4k
) {
304 u32 remain
= 0x1000 - (ofs
& 0xfff);
309 bdl
[2] = cpu_to_le32(chunk
);
310 /* program the IOC to enable interrupt
311 * only when the whole fragment is processed
314 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
324 * snd_hdac_stream_setup_periods - set up BDL entries
325 * @azx_dev: HD-audio core stream to set up
327 * Set up the buffer descriptor table of the given stream based on the
328 * period and buffer sizes of the assigned PCM substream.
330 int snd_hdac_stream_setup_periods(struct hdac_stream
*azx_dev
)
332 struct hdac_bus
*bus
= azx_dev
->bus
;
333 struct snd_pcm_substream
*substream
= azx_dev
->substream
;
334 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
336 int i
, ofs
, periods
, period_bytes
;
337 int pos_adj
, pos_align
;
339 /* reset BDL address */
340 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
341 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
343 period_bytes
= azx_dev
->period_bytes
;
344 periods
= azx_dev
->bufsize
/ period_bytes
;
346 /* program the initial BDL entries */
347 bdl
= (__le32
*)azx_dev
->bdl
.area
;
351 pos_adj
= bus
->bdl_pos_adj
;
352 if (!azx_dev
->no_period_wakeup
&& pos_adj
> 0) {
354 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
358 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
360 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
361 if (pos_adj
>= period_bytes
) {
362 dev_warn(bus
->dev
, "Too big adjustment %d\n",
366 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
368 &bdl
, ofs
, pos_adj
, true);
375 for (i
= 0; i
< periods
; i
++) {
376 if (i
== periods
- 1 && pos_adj
)
377 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
379 period_bytes
- pos_adj
, 0);
381 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
384 !azx_dev
->no_period_wakeup
);
391 dev_err(bus
->dev
, "Too many BDL entries: buffer=%d, period=%d\n",
392 azx_dev
->bufsize
, period_bytes
);
395 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods
);
397 static cycle_t
azx_cc_read(const struct cyclecounter
*cc
)
399 struct hdac_stream
*azx_dev
= container_of(cc
, struct hdac_stream
, cc
);
401 return snd_hdac_chip_readl(azx_dev
->bus
, WALLCLK
);
404 static void azx_timecounter_init(struct hdac_stream
*azx_dev
,
405 bool force
, cycle_t last
)
407 struct timecounter
*tc
= &azx_dev
->tc
;
408 struct cyclecounter
*cc
= &azx_dev
->cc
;
411 cc
->read
= azx_cc_read
;
412 cc
->mask
= CLOCKSOURCE_MASK(32);
415 * Converting from 24 MHz to ns means applying a 125/3 factor.
416 * To avoid any saturation issues in intermediate operations,
417 * the 125 factor is applied first. The division is applied
418 * last after reading the timecounter value.
419 * Applying the 1/3 factor as part of the multiplication
420 * requires at least 20 bits for a decent precision, however
421 * overflows occur after about 4 hours or less, not a option.
424 cc
->mult
= 125; /* saturation after 195 years */
427 nsec
= 0; /* audio time is elapsed time since trigger */
428 timecounter_init(tc
, cc
, nsec
);
431 * force timecounter to use predefined value,
432 * used for synchronized starts
434 tc
->cycle_last
= last
;
439 * snd_hdac_stream_timecounter_init - initialize time counter
440 * @azx_dev: HD-audio core stream (master stream)
441 * @streams: bit flags of streams to set up
443 * Initializes the time counter of streams marked by the bit flags (each
444 * bit corresponds to the stream index).
445 * The trigger timestamp of PCM substream assigned to the given stream is
446 * updated accordingly, too.
448 void snd_hdac_stream_timecounter_init(struct hdac_stream
*azx_dev
,
449 unsigned int streams
)
451 struct hdac_bus
*bus
= azx_dev
->bus
;
452 struct snd_pcm_runtime
*runtime
= azx_dev
->substream
->runtime
;
453 struct hdac_stream
*s
;
455 cycle_t cycle_last
= 0;
458 list_for_each_entry(s
, &bus
->stream_list
, list
) {
459 if (streams
& (1 << i
)) {
460 azx_timecounter_init(s
, inited
, cycle_last
);
463 cycle_last
= s
->tc
.cycle_last
;
469 snd_pcm_gettime(runtime
, &runtime
->trigger_tstamp
);
470 runtime
->trigger_tstamp_latched
= true;
472 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init
);
475 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
476 * @azx_dev: HD-audio core stream (master stream)
477 * @streams: bit flags of streams to sync
479 void snd_hdac_stream_sync_trigger(struct hdac_stream
*azx_dev
, bool set
,
480 unsigned int streams
, unsigned int reg
)
482 struct hdac_bus
*bus
= azx_dev
->bus
;
487 val
= _snd_hdac_chip_read(l
, bus
, reg
);
492 _snd_hdac_chip_write(l
, bus
, reg
, val
);
494 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger
);
497 * snd_hdac_stream_sync - sync with start/strop trigger operation
498 * @azx_dev: HD-audio core stream (master stream)
499 * @start: true = start, false = stop
500 * @streams: bit flags of streams to sync
502 * For @start = true, wait until all FIFOs get ready.
503 * For @start = false, wait until all RUN bits are cleared.
505 void snd_hdac_stream_sync(struct hdac_stream
*azx_dev
, bool start
,
506 unsigned int streams
)
508 struct hdac_bus
*bus
= azx_dev
->bus
;
509 int i
, nwait
, timeout
;
510 struct hdac_stream
*s
;
512 for (timeout
= 5000; timeout
; timeout
--) {
515 list_for_each_entry(s
, &bus
->stream_list
, list
) {
516 if (streams
& (1 << i
)) {
518 /* check FIFO gets ready */
519 if (!(snd_hdac_stream_readb(s
, SD_STS
) &
523 /* check RUN bit is cleared */
524 if (snd_hdac_stream_readb(s
, SD_CTL
) &
536 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync
);
538 #ifdef CONFIG_SND_HDA_DSP_LOADER
540 * snd_hdac_dsp_prepare - prepare for DSP loading
541 * @azx_dev: HD-audio core stream used for DSP loading
542 * @format: HD-audio stream format
543 * @byte_size: data chunk byte size
544 * @bufp: allocated buffer
546 * Allocate the buffer for the given size and set up the given stream for
547 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
549 int snd_hdac_dsp_prepare(struct hdac_stream
*azx_dev
, unsigned int format
,
550 unsigned int byte_size
, struct snd_dma_buffer
*bufp
)
552 struct hdac_bus
*bus
= azx_dev
->bus
;
556 snd_hdac_dsp_lock(azx_dev
);
557 spin_lock_irq(&bus
->reg_lock
);
558 if (azx_dev
->running
|| azx_dev
->locked
) {
559 spin_unlock_irq(&bus
->reg_lock
);
563 azx_dev
->locked
= true;
564 spin_unlock_irq(&bus
->reg_lock
);
566 err
= bus
->io_ops
->dma_alloc_pages(bus
, SNDRV_DMA_TYPE_DEV_SG
,
571 azx_dev
->bufsize
= byte_size
;
572 azx_dev
->period_bytes
= byte_size
;
573 azx_dev
->format_val
= format
;
575 snd_hdac_stream_reset(azx_dev
);
577 /* reset BDL address */
578 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
579 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
582 bdl
= (u32
*)azx_dev
->bdl
.area
;
583 err
= setup_bdle(bus
, bufp
, azx_dev
, &bdl
, 0, byte_size
, 0);
587 snd_hdac_stream_setup(azx_dev
);
588 snd_hdac_dsp_unlock(azx_dev
);
589 return azx_dev
->stream_tag
;
592 bus
->io_ops
->dma_free_pages(bus
, bufp
);
594 spin_lock_irq(&bus
->reg_lock
);
595 azx_dev
->locked
= false;
596 spin_unlock_irq(&bus
->reg_lock
);
598 snd_hdac_dsp_unlock(azx_dev
);
601 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare
);
604 * snd_hdac_dsp_trigger - start / stop DSP loading
605 * @azx_dev: HD-audio core stream used for DSP loading
606 * @start: trigger start or stop
608 void snd_hdac_dsp_trigger(struct hdac_stream
*azx_dev
, bool start
)
611 snd_hdac_stream_start(azx_dev
, true);
613 snd_hdac_stream_stop(azx_dev
);
615 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger
);
618 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
619 * @azx_dev: HD-audio core stream used for DSP loading
620 * @dmab: buffer used by DSP loading
622 void snd_hdac_dsp_cleanup(struct hdac_stream
*azx_dev
,
623 struct snd_dma_buffer
*dmab
)
625 struct hdac_bus
*bus
= azx_dev
->bus
;
627 if (!dmab
->area
|| !azx_dev
->locked
)
630 snd_hdac_dsp_lock(azx_dev
);
631 /* reset BDL address */
632 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
633 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
634 snd_hdac_stream_writel(azx_dev
, SD_CTL
, 0);
635 azx_dev
->bufsize
= 0;
636 azx_dev
->period_bytes
= 0;
637 azx_dev
->format_val
= 0;
639 bus
->io_ops
->dma_free_pages(bus
, dmab
);
642 spin_lock_irq(&bus
->reg_lock
);
643 azx_dev
->locked
= false;
644 spin_unlock_irq(&bus
->reg_lock
);
645 snd_hdac_dsp_unlock(azx_dev
);
647 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup
);
648 #endif /* CONFIG_SND_HDA_DSP_LOADER */