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[mirror_ubuntu-bionic-kernel.git] / sound / oss / esssolo1.c
1 /****************************************************************************/
2
3 /*
4 * esssolo1.c -- ESS Technology Solo1 (ES1946) audio driver.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Module command line parameters:
23 * none so far
24 *
25 * Supported devices:
26 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
27 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * Revision history
31 * 10.11.1998 0.1 Initial release (without any hardware)
32 * 22.03.1999 0.2 cinfo.blocks should be reset after GETxPTR ioctl.
33 * reported by Johan Maes <joma@telindus.be>
34 * return EAGAIN instead of EBUSY when O_NONBLOCK
35 * read/write cannot be executed
36 * 07.04.1999 0.3 implemented the following ioctl's: SOUND_PCM_READ_RATE,
37 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
38 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
39 * 15.06.1999 0.4 Fix bad allocation bug.
40 * Thanks to Deti Fliegl <fliegl@in.tum.de>
41 * 28.06.1999 0.5 Add pci_set_master
42 * 12.08.1999 0.6 Fix MIDI UART crashing the driver
43 * Changed mixer semantics from OSS documented
44 * behaviour to OSS "code behaviour".
45 * Recording might actually work now.
46 * The real DDMA controller address register is at PCI config
47 * 0x60, while the register at 0x18 is used as a placeholder
48 * register for BIOS address allocation. This register
49 * is supposed to be copied into 0x60, according
50 * to the Solo1 datasheet. When I do that, I can access
51 * the DDMA registers except the mask bit, which
52 * is stuck at 1. When I copy the contents of 0x18 +0x10
53 * to the DDMA base register, everything seems to work.
54 * The fun part is that the Windows Solo1 driver doesn't
55 * seem to do these tricks.
56 * Bugs remaining: plops and clicks when starting/stopping playback
57 * 31.08.1999 0.7 add spin_lock_init
58 * replaced current->state = x with set_current_state(x)
59 * 03.09.1999 0.8 change read semantics for MIDI to match
60 * OSS more closely; remove possible wakeup race
61 * 07.10.1999 0.9 Fix initialization; complain if sequencer writes time out
62 * Revised resource grabbing for the FM synthesizer
63 * 28.10.1999 0.10 More waitqueue races fixed
64 * 09.12.1999 0.11 Work around stupid Alpha port issue (virt_to_bus(kmalloc(GFP_DMA)) > 16M)
65 * Disabling recording on Alpha
66 * 12.01.2000 0.12 Prevent some ioctl's from returning bad count values on underrun/overrun;
67 * Tim Janik's BSE (Bedevilled Sound Engine) found this
68 * Integrated (aka redid 8-)) APM support patch by Zach Brown
69 * 07.02.2000 0.13 Use pci_alloc_consistent and pci_register_driver
70 * 19.02.2000 0.14 Use pci_dma_supported to determine if recording should be disabled
71 * 13.03.2000 0.15 Reintroduce initialization of a couple of PCI config space registers
72 * 21.11.2000 0.16 Initialize dma buffers in poll, otherwise poll may return a bogus mask
73 * 12.12.2000 0.17 More dma buffer initializations, patch from
74 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
75 * 31.01.2001 0.18 Register/Unregister gameport, original patch from
76 * Nathaniel Daw <daw@cs.cmu.edu>
77 * Fix SETTRIGGER non OSS API conformity
78 * 10.03.2001 provide abs function, prevent picking up a bogus kernel macro
79 * for abs. Bug report by Andrew Morton <andrewm@uow.edu.au>
80 * 15.05.2001 pci_enable_device moved, return values in probe cleaned
81 * up. Marcus Meissner <mm@caldera.de>
82 * 22.05.2001 0.19 more cleanups, changed PM to PCI 2.4 style, got rid
83 * of global list of devices, using pci device data.
84 * Marcus Meissner <mm@caldera.de>
85 * 03.01.2003 0.20 open_mode fixes from Georg Acher <acher@in.tum.de>
86 */
87
88 /*****************************************************************************/
89
90 #include <linux/interrupt.h>
91 #include <linux/module.h>
92 #include <linux/string.h>
93 #include <linux/ioport.h>
94 #include <linux/sched.h>
95 #include <linux/delay.h>
96 #include <linux/sound.h>
97 #include <linux/slab.h>
98 #include <linux/soundcard.h>
99 #include <linux/pci.h>
100 #include <linux/bitops.h>
101 #include <linux/init.h>
102 #include <linux/poll.h>
103 #include <linux/spinlock.h>
104 #include <linux/smp_lock.h>
105 #include <linux/gameport.h>
106 #include <linux/wait.h>
107 #include <linux/dma-mapping.h>
108
109 #include <asm/io.h>
110 #include <asm/page.h>
111 #include <asm/uaccess.h>
112
113 #include "dm.h"
114
115 /* --------------------------------------------------------------------- */
116
117 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
118
119 /* --------------------------------------------------------------------- */
120
121 #ifndef PCI_VENDOR_ID_ESS
122 #define PCI_VENDOR_ID_ESS 0x125d
123 #endif
124 #ifndef PCI_DEVICE_ID_ESS_SOLO1
125 #define PCI_DEVICE_ID_ESS_SOLO1 0x1969
126 #endif
127
128 #define SOLO1_MAGIC ((PCI_VENDOR_ID_ESS<<16)|PCI_DEVICE_ID_ESS_SOLO1)
129
130 #define DDMABASE_OFFSET 0 /* chip bug workaround kludge */
131 #define DDMABASE_EXTENT 16
132
133 #define IOBASE_EXTENT 16
134 #define SBBASE_EXTENT 16
135 #define VCBASE_EXTENT (DDMABASE_EXTENT+DDMABASE_OFFSET)
136 #define MPUBASE_EXTENT 4
137 #define GPBASE_EXTENT 4
138 #define GAMEPORT_EXTENT 4
139
140 #define FMSYNTH_EXTENT 4
141
142 /* MIDI buffer sizes */
143
144 #define MIDIINBUF 256
145 #define MIDIOUTBUF 256
146
147 #define FMODE_MIDI_SHIFT 3
148 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
149 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
150
151 #define FMODE_DMFM 0x10
152
153 static struct pci_driver solo1_driver;
154
155 /* --------------------------------------------------------------------- */
156
157 struct solo1_state {
158 /* magic */
159 unsigned int magic;
160
161 /* the corresponding pci_dev structure */
162 struct pci_dev *dev;
163
164 /* soundcore stuff */
165 int dev_audio;
166 int dev_mixer;
167 int dev_midi;
168 int dev_dmfm;
169
170 /* hardware resources */
171 unsigned long iobase, sbbase, vcbase, ddmabase, mpubase; /* long for SPARC */
172 unsigned int irq;
173
174 /* mixer registers */
175 struct {
176 unsigned short vol[10];
177 unsigned int recsrc;
178 unsigned int modcnt;
179 unsigned short micpreamp;
180 } mix;
181
182 /* wave stuff */
183 unsigned fmt;
184 unsigned channels;
185 unsigned rate;
186 unsigned char clkdiv;
187 unsigned ena;
188
189 spinlock_t lock;
190 struct semaphore open_sem;
191 mode_t open_mode;
192 wait_queue_head_t open_wait;
193
194 struct dmabuf {
195 void *rawbuf;
196 dma_addr_t dmaaddr;
197 unsigned buforder;
198 unsigned numfrag;
199 unsigned fragshift;
200 unsigned hwptr, swptr;
201 unsigned total_bytes;
202 int count;
203 unsigned error; /* over/underrun */
204 wait_queue_head_t wait;
205 /* redundant, but makes calculations easier */
206 unsigned fragsize;
207 unsigned dmasize;
208 unsigned fragsamples;
209 /* OSS stuff */
210 unsigned mapped:1;
211 unsigned ready:1;
212 unsigned endcleared:1;
213 unsigned enabled:1;
214 unsigned ossfragshift;
215 int ossmaxfrags;
216 unsigned subdivision;
217 } dma_dac, dma_adc;
218
219 /* midi stuff */
220 struct {
221 unsigned ird, iwr, icnt;
222 unsigned ord, owr, ocnt;
223 wait_queue_head_t iwait;
224 wait_queue_head_t owait;
225 struct timer_list timer;
226 unsigned char ibuf[MIDIINBUF];
227 unsigned char obuf[MIDIOUTBUF];
228 } midi;
229
230 struct gameport *gameport;
231 };
232
233 /* --------------------------------------------------------------------- */
234
235 static inline void write_seq(struct solo1_state *s, unsigned char data)
236 {
237 int i;
238 unsigned long flags;
239
240 /* the local_irq_save stunt is to send the data within the command window */
241 for (i = 0; i < 0xffff; i++) {
242 local_irq_save(flags);
243 if (!(inb(s->sbbase+0xc) & 0x80)) {
244 outb(data, s->sbbase+0xc);
245 local_irq_restore(flags);
246 return;
247 }
248 local_irq_restore(flags);
249 }
250 printk(KERN_ERR "esssolo1: write_seq timeout\n");
251 outb(data, s->sbbase+0xc);
252 }
253
254 static inline int read_seq(struct solo1_state *s, unsigned char *data)
255 {
256 int i;
257
258 if (!data)
259 return 0;
260 for (i = 0; i < 0xffff; i++)
261 if (inb(s->sbbase+0xe) & 0x80) {
262 *data = inb(s->sbbase+0xa);
263 return 1;
264 }
265 printk(KERN_ERR "esssolo1: read_seq timeout\n");
266 return 0;
267 }
268
269 static inline int reset_ctrl(struct solo1_state *s)
270 {
271 int i;
272
273 outb(3, s->sbbase+6); /* clear sequencer and FIFO */
274 udelay(10);
275 outb(0, s->sbbase+6);
276 for (i = 0; i < 0xffff; i++)
277 if (inb(s->sbbase+0xe) & 0x80)
278 if (inb(s->sbbase+0xa) == 0xaa) {
279 write_seq(s, 0xc6); /* enter enhanced mode */
280 return 1;
281 }
282 return 0;
283 }
284
285 static void write_ctrl(struct solo1_state *s, unsigned char reg, unsigned char data)
286 {
287 write_seq(s, reg);
288 write_seq(s, data);
289 }
290
291 #if 0 /* unused */
292 static unsigned char read_ctrl(struct solo1_state *s, unsigned char reg)
293 {
294 unsigned char r;
295
296 write_seq(s, 0xc0);
297 write_seq(s, reg);
298 read_seq(s, &r);
299 return r;
300 }
301 #endif /* unused */
302
303 static void write_mixer(struct solo1_state *s, unsigned char reg, unsigned char data)
304 {
305 outb(reg, s->sbbase+4);
306 outb(data, s->sbbase+5);
307 }
308
309 static unsigned char read_mixer(struct solo1_state *s, unsigned char reg)
310 {
311 outb(reg, s->sbbase+4);
312 return inb(s->sbbase+5);
313 }
314
315 /* --------------------------------------------------------------------- */
316
317 static inline unsigned ld2(unsigned int x)
318 {
319 unsigned r = 0;
320
321 if (x >= 0x10000) {
322 x >>= 16;
323 r += 16;
324 }
325 if (x >= 0x100) {
326 x >>= 8;
327 r += 8;
328 }
329 if (x >= 0x10) {
330 x >>= 4;
331 r += 4;
332 }
333 if (x >= 4) {
334 x >>= 2;
335 r += 2;
336 }
337 if (x >= 2)
338 r++;
339 return r;
340 }
341
342 /* --------------------------------------------------------------------- */
343
344 static inline void stop_dac(struct solo1_state *s)
345 {
346 unsigned long flags;
347
348 spin_lock_irqsave(&s->lock, flags);
349 s->ena &= ~FMODE_WRITE;
350 write_mixer(s, 0x78, 0x10);
351 spin_unlock_irqrestore(&s->lock, flags);
352 }
353
354 static void start_dac(struct solo1_state *s)
355 {
356 unsigned long flags;
357
358 spin_lock_irqsave(&s->lock, flags);
359 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
360 s->ena |= FMODE_WRITE;
361 write_mixer(s, 0x78, 0x12);
362 udelay(10);
363 write_mixer(s, 0x78, 0x13);
364 }
365 spin_unlock_irqrestore(&s->lock, flags);
366 }
367
368 static inline void stop_adc(struct solo1_state *s)
369 {
370 unsigned long flags;
371
372 spin_lock_irqsave(&s->lock, flags);
373 s->ena &= ~FMODE_READ;
374 write_ctrl(s, 0xb8, 0xe);
375 spin_unlock_irqrestore(&s->lock, flags);
376 }
377
378 static void start_adc(struct solo1_state *s)
379 {
380 unsigned long flags;
381
382 spin_lock_irqsave(&s->lock, flags);
383 if (!(s->ena & FMODE_READ) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
384 && s->dma_adc.ready) {
385 s->ena |= FMODE_READ;
386 write_ctrl(s, 0xb8, 0xf);
387 #if 0
388 printk(KERN_DEBUG "solo1: DMAbuffer: 0x%08lx\n", (long)s->dma_adc.rawbuf);
389 printk(KERN_DEBUG "solo1: DMA: mask: 0x%02x cnt: 0x%04x addr: 0x%08x stat: 0x%02x\n",
390 inb(s->ddmabase+0xf), inw(s->ddmabase+4), inl(s->ddmabase), inb(s->ddmabase+8));
391 #endif
392 outb(0, s->ddmabase+0xd); /* master reset */
393 outb(1, s->ddmabase+0xf); /* mask */
394 outb(0x54/*0x14*/, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
395 outl(virt_to_bus(s->dma_adc.rawbuf), s->ddmabase);
396 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
397 outb(0, s->ddmabase+0xf);
398 }
399 spin_unlock_irqrestore(&s->lock, flags);
400 #if 0
401 printk(KERN_DEBUG "solo1: start DMA: reg B8: 0x%02x SBstat: 0x%02x\n"
402 KERN_DEBUG "solo1: DMA: stat: 0x%02x cnt: 0x%04x mask: 0x%02x\n",
403 read_ctrl(s, 0xb8), inb(s->sbbase+0xc),
404 inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->ddmabase+0xf));
405 printk(KERN_DEBUG "solo1: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
406 KERN_DEBUG "solo1: B1: 0x%02x B2: 0x%02x B4: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n",
407 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
408 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb4), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8),
409 read_ctrl(s, 0xb9));
410 #endif
411 }
412
413 /* --------------------------------------------------------------------- */
414
415 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
416 #define DMABUF_MINORDER 1
417
418 static inline void dealloc_dmabuf(struct solo1_state *s, struct dmabuf *db)
419 {
420 struct page *page, *pend;
421
422 if (db->rawbuf) {
423 /* undo marking the pages as reserved */
424 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
425 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
426 ClearPageReserved(page);
427 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
428 }
429 db->rawbuf = NULL;
430 db->mapped = db->ready = 0;
431 }
432
433 static int prog_dmabuf(struct solo1_state *s, struct dmabuf *db)
434 {
435 int order;
436 unsigned bytespersec;
437 unsigned bufs, sample_shift = 0;
438 struct page *page, *pend;
439
440 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
441 if (!db->rawbuf) {
442 db->ready = db->mapped = 0;
443 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
444 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
445 break;
446 if (!db->rawbuf)
447 return -ENOMEM;
448 db->buforder = order;
449 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
450 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
451 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
452 SetPageReserved(page);
453 }
454 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
455 sample_shift++;
456 if (s->channels > 1)
457 sample_shift++;
458 bytespersec = s->rate << sample_shift;
459 bufs = PAGE_SIZE << db->buforder;
460 if (db->ossfragshift) {
461 if ((1000 << db->ossfragshift) < bytespersec)
462 db->fragshift = ld2(bytespersec/1000);
463 else
464 db->fragshift = db->ossfragshift;
465 } else {
466 db->fragshift = ld2(bytespersec/100/(db->subdivision ? db->subdivision : 1));
467 if (db->fragshift < 3)
468 db->fragshift = 3;
469 }
470 db->numfrag = bufs >> db->fragshift;
471 while (db->numfrag < 4 && db->fragshift > 3) {
472 db->fragshift--;
473 db->numfrag = bufs >> db->fragshift;
474 }
475 db->fragsize = 1 << db->fragshift;
476 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
477 db->numfrag = db->ossmaxfrags;
478 db->fragsamples = db->fragsize >> sample_shift;
479 db->dmasize = db->numfrag << db->fragshift;
480 db->enabled = 1;
481 return 0;
482 }
483
484 static inline int prog_dmabuf_adc(struct solo1_state *s)
485 {
486 unsigned long va;
487 int c;
488
489 stop_adc(s);
490 /* check if PCI implementation supports 24bit busmaster DMA */
491 if (s->dev->dma_mask > 0xffffff)
492 return -EIO;
493 if ((c = prog_dmabuf(s, &s->dma_adc)))
494 return c;
495 va = s->dma_adc.dmaaddr;
496 if ((va & ~((1<<24)-1)))
497 panic("solo1: buffer above 16M boundary");
498 outb(0, s->ddmabase+0xd); /* clear */
499 outb(1, s->ddmabase+0xf); /* mask */
500 /*outb(0, s->ddmabase+8);*/ /* enable (enable is active low!) */
501 outb(0x54, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
502 outl(va, s->ddmabase);
503 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
504 c = - s->dma_adc.fragsamples;
505 write_ctrl(s, 0xa4, c);
506 write_ctrl(s, 0xa5, c >> 8);
507 outb(0, s->ddmabase+0xf);
508 s->dma_adc.ready = 1;
509 return 0;
510 }
511
512 static inline int prog_dmabuf_dac(struct solo1_state *s)
513 {
514 unsigned long va;
515 int c;
516
517 stop_dac(s);
518 if ((c = prog_dmabuf(s, &s->dma_dac)))
519 return c;
520 memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80, s->dma_dac.dmasize); /* almost correct for U16 */
521 va = s->dma_dac.dmaaddr;
522 if ((va ^ (va + s->dma_dac.dmasize - 1)) & ~((1<<20)-1))
523 panic("solo1: buffer crosses 1M boundary");
524 outl(va, s->iobase);
525 /* warning: s->dma_dac.dmasize & 0xffff must not be zero! i.e. this limits us to a 32k buffer */
526 outw(s->dma_dac.dmasize, s->iobase+4);
527 c = - s->dma_dac.fragsamples;
528 write_mixer(s, 0x74, c);
529 write_mixer(s, 0x76, c >> 8);
530 outb(0xa, s->iobase+6);
531 s->dma_dac.ready = 1;
532 return 0;
533 }
534
535 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
536 {
537 if (bptr + len > bsize) {
538 unsigned x = bsize - bptr;
539 memset(((char *)buf) + bptr, c, x);
540 bptr = 0;
541 len -= x;
542 }
543 memset(((char *)buf) + bptr, c, len);
544 }
545
546 /* call with spinlock held! */
547
548 static void solo1_update_ptr(struct solo1_state *s)
549 {
550 int diff;
551 unsigned hwptr;
552
553 /* update ADC pointer */
554 if (s->ena & FMODE_READ) {
555 hwptr = (s->dma_adc.dmasize - 1 - inw(s->ddmabase+4)) % s->dma_adc.dmasize;
556 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
557 s->dma_adc.hwptr = hwptr;
558 s->dma_adc.total_bytes += diff;
559 s->dma_adc.count += diff;
560 #if 0
561 printk(KERN_DEBUG "solo1: rd: hwptr %u swptr %u dmasize %u count %u\n",
562 s->dma_adc.hwptr, s->dma_adc.swptr, s->dma_adc.dmasize, s->dma_adc.count);
563 #endif
564 if (s->dma_adc.mapped) {
565 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
566 wake_up(&s->dma_adc.wait);
567 } else {
568 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
569 s->ena &= ~FMODE_READ;
570 write_ctrl(s, 0xb8, 0xe);
571 s->dma_adc.error++;
572 }
573 if (s->dma_adc.count > 0)
574 wake_up(&s->dma_adc.wait);
575 }
576 }
577 /* update DAC pointer */
578 if (s->ena & FMODE_WRITE) {
579 hwptr = (s->dma_dac.dmasize - inw(s->iobase+4)) % s->dma_dac.dmasize;
580 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
581 s->dma_dac.hwptr = hwptr;
582 s->dma_dac.total_bytes += diff;
583 #if 0
584 printk(KERN_DEBUG "solo1: wr: hwptr %u swptr %u dmasize %u count %u\n",
585 s->dma_dac.hwptr, s->dma_dac.swptr, s->dma_dac.dmasize, s->dma_dac.count);
586 #endif
587 if (s->dma_dac.mapped) {
588 s->dma_dac.count += diff;
589 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
590 wake_up(&s->dma_dac.wait);
591 } else {
592 s->dma_dac.count -= diff;
593 if (s->dma_dac.count <= 0) {
594 s->ena &= ~FMODE_WRITE;
595 write_mixer(s, 0x78, 0x12);
596 s->dma_dac.error++;
597 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
598 clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr,
599 s->dma_dac.fragsize, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80);
600 s->dma_dac.endcleared = 1;
601 }
602 if (s->dma_dac.count < (signed)s->dma_dac.dmasize)
603 wake_up(&s->dma_dac.wait);
604 }
605 }
606 }
607
608 /* --------------------------------------------------------------------- */
609
610 static void prog_codec(struct solo1_state *s)
611 {
612 unsigned long flags;
613 int fdiv, filter;
614 unsigned char c;
615
616 reset_ctrl(s);
617 write_seq(s, 0xd3);
618 /* program sampling rates */
619 filter = s->rate * 9 / 20; /* Set filter roll-off to 90% of rate/2 */
620 fdiv = 256 - 7160000 / (filter * 82);
621 spin_lock_irqsave(&s->lock, flags);
622 write_ctrl(s, 0xa1, s->clkdiv);
623 write_ctrl(s, 0xa2, fdiv);
624 write_mixer(s, 0x70, s->clkdiv);
625 write_mixer(s, 0x72, fdiv);
626 /* program ADC parameters */
627 write_ctrl(s, 0xb8, 0xe);
628 write_ctrl(s, 0xb9, /*0x1*/0);
629 write_ctrl(s, 0xa8, (s->channels > 1) ? 0x11 : 0x12);
630 c = 0xd0;
631 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
632 c |= 0x04;
633 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
634 c |= 0x20;
635 if (s->channels > 1)
636 c ^= 0x48;
637 write_ctrl(s, 0xb7, (c & 0x70) | 1);
638 write_ctrl(s, 0xb7, c);
639 write_ctrl(s, 0xb1, 0x50);
640 write_ctrl(s, 0xb2, 0x50);
641 /* program DAC parameters */
642 c = 0x40;
643 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
644 c |= 1;
645 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
646 c |= 4;
647 if (s->channels > 1)
648 c |= 2;
649 write_mixer(s, 0x7a, c);
650 write_mixer(s, 0x78, 0x10);
651 s->ena = 0;
652 spin_unlock_irqrestore(&s->lock, flags);
653 }
654
655 /* --------------------------------------------------------------------- */
656
657 static const char invalid_magic[] = KERN_CRIT "solo1: invalid magic value\n";
658
659 #define VALIDATE_STATE(s) \
660 ({ \
661 if (!(s) || (s)->magic != SOLO1_MAGIC) { \
662 printk(invalid_magic); \
663 return -ENXIO; \
664 } \
665 })
666
667 /* --------------------------------------------------------------------- */
668
669 static int mixer_ioctl(struct solo1_state *s, unsigned int cmd, unsigned long arg)
670 {
671 static const unsigned int mixer_src[8] = {
672 SOUND_MASK_MIC, SOUND_MASK_MIC, SOUND_MASK_CD, SOUND_MASK_VOLUME,
673 SOUND_MASK_MIC, 0, SOUND_MASK_LINE, 0
674 };
675 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
676 [SOUND_MIXER_PCM] = 1, /* voice */
677 [SOUND_MIXER_SYNTH] = 2, /* FM */
678 [SOUND_MIXER_CD] = 3, /* CD */
679 [SOUND_MIXER_LINE] = 4, /* Line */
680 [SOUND_MIXER_LINE1] = 5, /* AUX */
681 [SOUND_MIXER_MIC] = 6, /* Mic */
682 [SOUND_MIXER_LINE2] = 7, /* Mono in */
683 [SOUND_MIXER_SPEAKER] = 8, /* Speaker */
684 [SOUND_MIXER_RECLEV] = 9, /* Recording level */
685 [SOUND_MIXER_VOLUME] = 10 /* Master Volume */
686 };
687 static const unsigned char mixreg[] = {
688 0x7c, /* voice */
689 0x36, /* FM */
690 0x38, /* CD */
691 0x3e, /* Line */
692 0x3a, /* AUX */
693 0x1a, /* Mic */
694 0x6d /* Mono in */
695 };
696 unsigned char l, r, rl, rr, vidx;
697 int i, val;
698 int __user *p = (int __user *)arg;
699
700 VALIDATE_STATE(s);
701
702 if (cmd == SOUND_MIXER_PRIVATE1) {
703 /* enable/disable/query mixer preamp */
704 if (get_user(val, p))
705 return -EFAULT;
706 if (val != -1) {
707 val = val ? 0xff : 0xf7;
708 write_mixer(s, 0x7d, (read_mixer(s, 0x7d) | 0x08) & val);
709 }
710 val = (read_mixer(s, 0x7d) & 0x08) ? 1 : 0;
711 return put_user(val, p);
712 }
713 if (cmd == SOUND_MIXER_PRIVATE2) {
714 /* enable/disable/query spatializer */
715 if (get_user(val, p))
716 return -EFAULT;
717 if (val != -1) {
718 val &= 0x3f;
719 write_mixer(s, 0x52, val);
720 write_mixer(s, 0x50, val ? 0x08 : 0);
721 }
722 return put_user(read_mixer(s, 0x52), p);
723 }
724 if (cmd == SOUND_MIXER_INFO) {
725 mixer_info info;
726 strncpy(info.id, "Solo1", sizeof(info.id));
727 strncpy(info.name, "ESS Solo1", sizeof(info.name));
728 info.modify_counter = s->mix.modcnt;
729 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
730 return -EFAULT;
731 return 0;
732 }
733 if (cmd == SOUND_OLD_MIXER_INFO) {
734 _old_mixer_info info;
735 strncpy(info.id, "Solo1", sizeof(info.id));
736 strncpy(info.name, "ESS Solo1", sizeof(info.name));
737 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
738 return -EFAULT;
739 return 0;
740 }
741 if (cmd == OSS_GETVERSION)
742 return put_user(SOUND_VERSION, p);
743 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
744 return -EINVAL;
745 if (_SIOC_DIR(cmd) == _SIOC_READ) {
746 switch (_IOC_NR(cmd)) {
747 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
748 return put_user(mixer_src[read_mixer(s, 0x1c) & 7], p);
749
750 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
751 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
752 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
753 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV |
754 SOUND_MASK_SPEAKER, p);
755
756 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
757 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_VOLUME, p);
758
759 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
760 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
761 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
762 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV, p);
763
764 case SOUND_MIXER_CAPS:
765 return put_user(SOUND_CAP_EXCL_INPUT, p);
766
767 default:
768 i = _IOC_NR(cmd);
769 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
770 return -EINVAL;
771 return put_user(s->mix.vol[vidx-1], p);
772 }
773 }
774 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
775 return -EINVAL;
776 s->mix.modcnt++;
777 switch (_IOC_NR(cmd)) {
778 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
779 #if 0
780 {
781 static const unsigned char regs[] = {
782 0x1c, 0x1a, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 0x60, 0x62, 0x6d, 0x7c
783 };
784 int i;
785
786 for (i = 0; i < sizeof(regs); i++)
787 printk(KERN_DEBUG "solo1: mixer reg 0x%02x: 0x%02x\n",
788 regs[i], read_mixer(s, regs[i]));
789 printk(KERN_DEBUG "solo1: ctrl reg 0x%02x: 0x%02x\n",
790 0xb4, read_ctrl(s, 0xb4));
791 }
792 #endif
793 if (get_user(val, p))
794 return -EFAULT;
795 i = hweight32(val);
796 if (i == 0)
797 return 0;
798 else if (i > 1)
799 val &= ~mixer_src[read_mixer(s, 0x1c) & 7];
800 for (i = 0; i < 8; i++) {
801 if (mixer_src[i] & val)
802 break;
803 }
804 if (i > 7)
805 return 0;
806 write_mixer(s, 0x1c, i);
807 return 0;
808
809 case SOUND_MIXER_VOLUME:
810 if (get_user(val, p))
811 return -EFAULT;
812 l = val & 0xff;
813 if (l > 100)
814 l = 100;
815 r = (val >> 8) & 0xff;
816 if (r > 100)
817 r = 100;
818 if (l < 6) {
819 rl = 0x40;
820 l = 0;
821 } else {
822 rl = (l * 2 - 11) / 3;
823 l = (rl * 3 + 11) / 2;
824 }
825 if (r < 6) {
826 rr = 0x40;
827 r = 0;
828 } else {
829 rr = (r * 2 - 11) / 3;
830 r = (rr * 3 + 11) / 2;
831 }
832 write_mixer(s, 0x60, rl);
833 write_mixer(s, 0x62, rr);
834 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
835 s->mix.vol[9] = ((unsigned int)r << 8) | l;
836 #else
837 s->mix.vol[9] = val;
838 #endif
839 return put_user(s->mix.vol[9], p);
840
841 case SOUND_MIXER_SPEAKER:
842 if (get_user(val, p))
843 return -EFAULT;
844 l = val & 0xff;
845 if (l > 100)
846 l = 100;
847 else if (l < 2)
848 l = 2;
849 rl = (l - 2) / 14;
850 l = rl * 14 + 2;
851 write_mixer(s, 0x3c, rl);
852 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
853 s->mix.vol[7] = l * 0x101;
854 #else
855 s->mix.vol[7] = val;
856 #endif
857 return put_user(s->mix.vol[7], p);
858
859 case SOUND_MIXER_RECLEV:
860 if (get_user(val, p))
861 return -EFAULT;
862 l = (val << 1) & 0x1fe;
863 if (l > 200)
864 l = 200;
865 else if (l < 5)
866 l = 5;
867 r = (val >> 7) & 0x1fe;
868 if (r > 200)
869 r = 200;
870 else if (r < 5)
871 r = 5;
872 rl = (l - 5) / 13;
873 rr = (r - 5) / 13;
874 r = (rl * 13 + 5) / 2;
875 l = (rr * 13 + 5) / 2;
876 write_ctrl(s, 0xb4, (rl << 4) | rr);
877 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
878 s->mix.vol[8] = ((unsigned int)r << 8) | l;
879 #else
880 s->mix.vol[8] = val;
881 #endif
882 return put_user(s->mix.vol[8], p);
883
884 default:
885 i = _IOC_NR(cmd);
886 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
887 return -EINVAL;
888 if (get_user(val, p))
889 return -EFAULT;
890 l = (val << 1) & 0x1fe;
891 if (l > 200)
892 l = 200;
893 else if (l < 5)
894 l = 5;
895 r = (val >> 7) & 0x1fe;
896 if (r > 200)
897 r = 200;
898 else if (r < 5)
899 r = 5;
900 rl = (l - 5) / 13;
901 rr = (r - 5) / 13;
902 r = (rl * 13 + 5) / 2;
903 l = (rr * 13 + 5) / 2;
904 write_mixer(s, mixreg[vidx-1], (rl << 4) | rr);
905 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
906 s->mix.vol[vidx-1] = ((unsigned int)r << 8) | l;
907 #else
908 s->mix.vol[vidx-1] = val;
909 #endif
910 return put_user(s->mix.vol[vidx-1], p);
911 }
912 }
913
914 /* --------------------------------------------------------------------- */
915
916 static int solo1_open_mixdev(struct inode *inode, struct file *file)
917 {
918 unsigned int minor = iminor(inode);
919 struct solo1_state *s = NULL;
920 struct pci_dev *pci_dev = NULL;
921
922 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
923 struct pci_driver *drvr;
924 drvr = pci_dev_driver (pci_dev);
925 if (drvr != &solo1_driver)
926 continue;
927 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
928 if (!s)
929 continue;
930 if (s->dev_mixer == minor)
931 break;
932 }
933 if (!s)
934 return -ENODEV;
935 VALIDATE_STATE(s);
936 file->private_data = s;
937 return nonseekable_open(inode, file);
938 }
939
940 static int solo1_release_mixdev(struct inode *inode, struct file *file)
941 {
942 struct solo1_state *s = (struct solo1_state *)file->private_data;
943
944 VALIDATE_STATE(s);
945 return 0;
946 }
947
948 static int solo1_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
949 {
950 return mixer_ioctl((struct solo1_state *)file->private_data, cmd, arg);
951 }
952
953 static /*const*/ struct file_operations solo1_mixer_fops = {
954 .owner = THIS_MODULE,
955 .llseek = no_llseek,
956 .ioctl = solo1_ioctl_mixdev,
957 .open = solo1_open_mixdev,
958 .release = solo1_release_mixdev,
959 };
960
961 /* --------------------------------------------------------------------- */
962
963 static int drain_dac(struct solo1_state *s, int nonblock)
964 {
965 DECLARE_WAITQUEUE(wait, current);
966 unsigned long flags;
967 int count;
968 unsigned tmo;
969
970 if (s->dma_dac.mapped)
971 return 0;
972 add_wait_queue(&s->dma_dac.wait, &wait);
973 for (;;) {
974 set_current_state(TASK_INTERRUPTIBLE);
975 spin_lock_irqsave(&s->lock, flags);
976 count = s->dma_dac.count;
977 spin_unlock_irqrestore(&s->lock, flags);
978 if (count <= 0)
979 break;
980 if (signal_pending(current))
981 break;
982 if (nonblock) {
983 remove_wait_queue(&s->dma_dac.wait, &wait);
984 set_current_state(TASK_RUNNING);
985 return -EBUSY;
986 }
987 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->rate;
988 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
989 tmo >>= 1;
990 if (s->channels > 1)
991 tmo >>= 1;
992 if (!schedule_timeout(tmo + 1))
993 printk(KERN_DEBUG "solo1: dma timed out??\n");
994 }
995 remove_wait_queue(&s->dma_dac.wait, &wait);
996 set_current_state(TASK_RUNNING);
997 if (signal_pending(current))
998 return -ERESTARTSYS;
999 return 0;
1000 }
1001
1002 /* --------------------------------------------------------------------- */
1003
1004 static ssize_t solo1_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1005 {
1006 struct solo1_state *s = (struct solo1_state *)file->private_data;
1007 DECLARE_WAITQUEUE(wait, current);
1008 ssize_t ret;
1009 unsigned long flags;
1010 unsigned swptr;
1011 int cnt;
1012
1013 VALIDATE_STATE(s);
1014 if (s->dma_adc.mapped)
1015 return -ENXIO;
1016 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1017 return ret;
1018 if (!access_ok(VERIFY_WRITE, buffer, count))
1019 return -EFAULT;
1020 ret = 0;
1021 add_wait_queue(&s->dma_adc.wait, &wait);
1022 while (count > 0) {
1023 spin_lock_irqsave(&s->lock, flags);
1024 swptr = s->dma_adc.swptr;
1025 cnt = s->dma_adc.dmasize-swptr;
1026 if (s->dma_adc.count < cnt)
1027 cnt = s->dma_adc.count;
1028 if (cnt <= 0)
1029 __set_current_state(TASK_INTERRUPTIBLE);
1030 spin_unlock_irqrestore(&s->lock, flags);
1031 if (cnt > count)
1032 cnt = count;
1033 #ifdef DEBUGREC
1034 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x cnt: %u\n",
1035 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc), cnt);
1036 #endif
1037 if (cnt <= 0) {
1038 if (s->dma_adc.enabled)
1039 start_adc(s);
1040 #ifdef DEBUGREC
1041 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1042 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1043 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1044 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1045 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1046 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1047 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1048 #endif
1049 if (inb(s->ddmabase+15) & 1)
1050 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1051 if (file->f_flags & O_NONBLOCK) {
1052 if (!ret)
1053 ret = -EAGAIN;
1054 break;
1055 }
1056 schedule();
1057 #ifdef DEBUGREC
1058 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1059 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1060 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1061 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1062 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1063 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1064 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1065 #endif
1066 if (signal_pending(current)) {
1067 if (!ret)
1068 ret = -ERESTARTSYS;
1069 break;
1070 }
1071 continue;
1072 }
1073 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1074 if (!ret)
1075 ret = -EFAULT;
1076 break;
1077 }
1078 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1079 spin_lock_irqsave(&s->lock, flags);
1080 s->dma_adc.swptr = swptr;
1081 s->dma_adc.count -= cnt;
1082 spin_unlock_irqrestore(&s->lock, flags);
1083 count -= cnt;
1084 buffer += cnt;
1085 ret += cnt;
1086 if (s->dma_adc.enabled)
1087 start_adc(s);
1088 #ifdef DEBUGREC
1089 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x\n",
1090 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc));
1091 #endif
1092 }
1093 remove_wait_queue(&s->dma_adc.wait, &wait);
1094 set_current_state(TASK_RUNNING);
1095 return ret;
1096 }
1097
1098 static ssize_t solo1_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1099 {
1100 struct solo1_state *s = (struct solo1_state *)file->private_data;
1101 DECLARE_WAITQUEUE(wait, current);
1102 ssize_t ret;
1103 unsigned long flags;
1104 unsigned swptr;
1105 int cnt;
1106
1107 VALIDATE_STATE(s);
1108 if (s->dma_dac.mapped)
1109 return -ENXIO;
1110 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1111 return ret;
1112 if (!access_ok(VERIFY_READ, buffer, count))
1113 return -EFAULT;
1114 #if 0
1115 printk(KERN_DEBUG "solo1_write: reg 70: 0x%02x 71: 0x%02x 72: 0x%02x 74: 0x%02x 76: 0x%02x 78: 0x%02x 7A: 0x%02x\n"
1116 KERN_DEBUG "solo1_write: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x SBstat: 0x%02x\n",
1117 read_mixer(s, 0x70), read_mixer(s, 0x71), read_mixer(s, 0x72), read_mixer(s, 0x74), read_mixer(s, 0x76),
1118 read_mixer(s, 0x78), read_mixer(s, 0x7a), inl(s->iobase), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1119 printk(KERN_DEBUG "solo1_write: reg 78: 0x%02x reg 7A: 0x%02x DMAcnt: 0x%04x DMAstat: 0x%02x SBstat: 0x%02x\n",
1120 read_mixer(s, 0x78), read_mixer(s, 0x7a), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1121 #endif
1122 ret = 0;
1123 add_wait_queue(&s->dma_dac.wait, &wait);
1124 while (count > 0) {
1125 spin_lock_irqsave(&s->lock, flags);
1126 if (s->dma_dac.count < 0) {
1127 s->dma_dac.count = 0;
1128 s->dma_dac.swptr = s->dma_dac.hwptr;
1129 }
1130 swptr = s->dma_dac.swptr;
1131 cnt = s->dma_dac.dmasize-swptr;
1132 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1133 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1134 if (cnt <= 0)
1135 __set_current_state(TASK_INTERRUPTIBLE);
1136 spin_unlock_irqrestore(&s->lock, flags);
1137 if (cnt > count)
1138 cnt = count;
1139 if (cnt <= 0) {
1140 if (s->dma_dac.enabled)
1141 start_dac(s);
1142 if (file->f_flags & O_NONBLOCK) {
1143 if (!ret)
1144 ret = -EAGAIN;
1145 break;
1146 }
1147 schedule();
1148 if (signal_pending(current)) {
1149 if (!ret)
1150 ret = -ERESTARTSYS;
1151 break;
1152 }
1153 continue;
1154 }
1155 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1156 if (!ret)
1157 ret = -EFAULT;
1158 break;
1159 }
1160 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1161 spin_lock_irqsave(&s->lock, flags);
1162 s->dma_dac.swptr = swptr;
1163 s->dma_dac.count += cnt;
1164 s->dma_dac.endcleared = 0;
1165 spin_unlock_irqrestore(&s->lock, flags);
1166 count -= cnt;
1167 buffer += cnt;
1168 ret += cnt;
1169 if (s->dma_dac.enabled)
1170 start_dac(s);
1171 }
1172 remove_wait_queue(&s->dma_dac.wait, &wait);
1173 set_current_state(TASK_RUNNING);
1174 return ret;
1175 }
1176
1177 /* No kernel lock - we have our own spinlock */
1178 static unsigned int solo1_poll(struct file *file, struct poll_table_struct *wait)
1179 {
1180 struct solo1_state *s = (struct solo1_state *)file->private_data;
1181 unsigned long flags;
1182 unsigned int mask = 0;
1183
1184 VALIDATE_STATE(s);
1185 if (file->f_mode & FMODE_WRITE) {
1186 if (!s->dma_dac.ready && prog_dmabuf_dac(s))
1187 return 0;
1188 poll_wait(file, &s->dma_dac.wait, wait);
1189 }
1190 if (file->f_mode & FMODE_READ) {
1191 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1192 return 0;
1193 poll_wait(file, &s->dma_adc.wait, wait);
1194 }
1195 spin_lock_irqsave(&s->lock, flags);
1196 solo1_update_ptr(s);
1197 if (file->f_mode & FMODE_READ) {
1198 if (s->dma_adc.mapped) {
1199 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1200 mask |= POLLIN | POLLRDNORM;
1201 } else {
1202 if (s->dma_adc.count > 0)
1203 mask |= POLLIN | POLLRDNORM;
1204 }
1205 }
1206 if (file->f_mode & FMODE_WRITE) {
1207 if (s->dma_dac.mapped) {
1208 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1209 mask |= POLLOUT | POLLWRNORM;
1210 } else {
1211 if ((signed)s->dma_dac.dmasize > s->dma_dac.count)
1212 mask |= POLLOUT | POLLWRNORM;
1213 }
1214 }
1215 spin_unlock_irqrestore(&s->lock, flags);
1216 return mask;
1217 }
1218
1219
1220 static int solo1_mmap(struct file *file, struct vm_area_struct *vma)
1221 {
1222 struct solo1_state *s = (struct solo1_state *)file->private_data;
1223 struct dmabuf *db;
1224 int ret = -EINVAL;
1225 unsigned long size;
1226
1227 VALIDATE_STATE(s);
1228 lock_kernel();
1229 if (vma->vm_flags & VM_WRITE) {
1230 if ((ret = prog_dmabuf_dac(s)) != 0)
1231 goto out;
1232 db = &s->dma_dac;
1233 } else if (vma->vm_flags & VM_READ) {
1234 if ((ret = prog_dmabuf_adc(s)) != 0)
1235 goto out;
1236 db = &s->dma_adc;
1237 } else
1238 goto out;
1239 ret = -EINVAL;
1240 if (vma->vm_pgoff != 0)
1241 goto out;
1242 size = vma->vm_end - vma->vm_start;
1243 if (size > (PAGE_SIZE << db->buforder))
1244 goto out;
1245 ret = -EAGAIN;
1246 if (remap_pfn_range(vma, vma->vm_start,
1247 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1248 size, vma->vm_page_prot))
1249 goto out;
1250 db->mapped = 1;
1251 ret = 0;
1252 out:
1253 unlock_kernel();
1254 return ret;
1255 }
1256
1257 static int solo1_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1258 {
1259 struct solo1_state *s = (struct solo1_state *)file->private_data;
1260 unsigned long flags;
1261 audio_buf_info abinfo;
1262 count_info cinfo;
1263 int val, mapped, ret, count;
1264 int div1, div2;
1265 unsigned rate1, rate2;
1266 void __user *argp = (void __user *)arg;
1267 int __user *p = argp;
1268
1269 VALIDATE_STATE(s);
1270 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1271 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1272 switch (cmd) {
1273 case OSS_GETVERSION:
1274 return put_user(SOUND_VERSION, p);
1275
1276 case SNDCTL_DSP_SYNC:
1277 if (file->f_mode & FMODE_WRITE)
1278 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1279 return 0;
1280
1281 case SNDCTL_DSP_SETDUPLEX:
1282 return 0;
1283
1284 case SNDCTL_DSP_GETCAPS:
1285 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1286
1287 case SNDCTL_DSP_RESET:
1288 if (file->f_mode & FMODE_WRITE) {
1289 stop_dac(s);
1290 synchronize_irq(s->irq);
1291 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1292 }
1293 if (file->f_mode & FMODE_READ) {
1294 stop_adc(s);
1295 synchronize_irq(s->irq);
1296 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1297 }
1298 prog_codec(s);
1299 return 0;
1300
1301 case SNDCTL_DSP_SPEED:
1302 if (get_user(val, p))
1303 return -EFAULT;
1304 if (val >= 0) {
1305 stop_adc(s);
1306 stop_dac(s);
1307 s->dma_adc.ready = s->dma_dac.ready = 0;
1308 /* program sampling rates */
1309 if (val > 48000)
1310 val = 48000;
1311 if (val < 6300)
1312 val = 6300;
1313 div1 = (768000 + val / 2) / val;
1314 rate1 = (768000 + div1 / 2) / div1;
1315 div1 = -div1;
1316 div2 = (793800 + val / 2) / val;
1317 rate2 = (793800 + div2 / 2) / div2;
1318 div2 = (-div2) & 0x7f;
1319 if (abs(val - rate2) < abs(val - rate1)) {
1320 rate1 = rate2;
1321 div1 = div2;
1322 }
1323 s->rate = rate1;
1324 s->clkdiv = div1;
1325 prog_codec(s);
1326 }
1327 return put_user(s->rate, p);
1328
1329 case SNDCTL_DSP_STEREO:
1330 if (get_user(val, p))
1331 return -EFAULT;
1332 stop_adc(s);
1333 stop_dac(s);
1334 s->dma_adc.ready = s->dma_dac.ready = 0;
1335 /* program channels */
1336 s->channels = val ? 2 : 1;
1337 prog_codec(s);
1338 return 0;
1339
1340 case SNDCTL_DSP_CHANNELS:
1341 if (get_user(val, p))
1342 return -EFAULT;
1343 if (val != 0) {
1344 stop_adc(s);
1345 stop_dac(s);
1346 s->dma_adc.ready = s->dma_dac.ready = 0;
1347 /* program channels */
1348 s->channels = (val >= 2) ? 2 : 1;
1349 prog_codec(s);
1350 }
1351 return put_user(s->channels, p);
1352
1353 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1354 return put_user(AFMT_S16_LE|AFMT_U16_LE|AFMT_S8|AFMT_U8, p);
1355
1356 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1357 if (get_user(val, p))
1358 return -EFAULT;
1359 if (val != AFMT_QUERY) {
1360 stop_adc(s);
1361 stop_dac(s);
1362 s->dma_adc.ready = s->dma_dac.ready = 0;
1363 /* program format */
1364 if (val != AFMT_S16_LE && val != AFMT_U16_LE &&
1365 val != AFMT_S8 && val != AFMT_U8)
1366 val = AFMT_U8;
1367 s->fmt = val;
1368 prog_codec(s);
1369 }
1370 return put_user(s->fmt, p);
1371
1372 case SNDCTL_DSP_POST:
1373 return 0;
1374
1375 case SNDCTL_DSP_GETTRIGGER:
1376 val = 0;
1377 if (file->f_mode & s->ena & FMODE_READ)
1378 val |= PCM_ENABLE_INPUT;
1379 if (file->f_mode & s->ena & FMODE_WRITE)
1380 val |= PCM_ENABLE_OUTPUT;
1381 return put_user(val, p);
1382
1383 case SNDCTL_DSP_SETTRIGGER:
1384 if (get_user(val, p))
1385 return -EFAULT;
1386 if (file->f_mode & FMODE_READ) {
1387 if (val & PCM_ENABLE_INPUT) {
1388 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1389 return ret;
1390 s->dma_dac.enabled = 1;
1391 start_adc(s);
1392 if (inb(s->ddmabase+15) & 1)
1393 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1394 } else {
1395 s->dma_dac.enabled = 0;
1396 stop_adc(s);
1397 }
1398 }
1399 if (file->f_mode & FMODE_WRITE) {
1400 if (val & PCM_ENABLE_OUTPUT) {
1401 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1402 return ret;
1403 s->dma_dac.enabled = 1;
1404 start_dac(s);
1405 } else {
1406 s->dma_dac.enabled = 0;
1407 stop_dac(s);
1408 }
1409 }
1410 return 0;
1411
1412 case SNDCTL_DSP_GETOSPACE:
1413 if (!(file->f_mode & FMODE_WRITE))
1414 return -EINVAL;
1415 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1416 return val;
1417 spin_lock_irqsave(&s->lock, flags);
1418 solo1_update_ptr(s);
1419 abinfo.fragsize = s->dma_dac.fragsize;
1420 count = s->dma_dac.count;
1421 if (count < 0)
1422 count = 0;
1423 abinfo.bytes = s->dma_dac.dmasize - count;
1424 abinfo.fragstotal = s->dma_dac.numfrag;
1425 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1426 spin_unlock_irqrestore(&s->lock, flags);
1427 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1428
1429 case SNDCTL_DSP_GETISPACE:
1430 if (!(file->f_mode & FMODE_READ))
1431 return -EINVAL;
1432 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1433 return val;
1434 spin_lock_irqsave(&s->lock, flags);
1435 solo1_update_ptr(s);
1436 abinfo.fragsize = s->dma_adc.fragsize;
1437 abinfo.bytes = s->dma_adc.count;
1438 abinfo.fragstotal = s->dma_adc.numfrag;
1439 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1440 spin_unlock_irqrestore(&s->lock, flags);
1441 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1442
1443 case SNDCTL_DSP_NONBLOCK:
1444 file->f_flags |= O_NONBLOCK;
1445 return 0;
1446
1447 case SNDCTL_DSP_GETODELAY:
1448 if (!(file->f_mode & FMODE_WRITE))
1449 return -EINVAL;
1450 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1451 return val;
1452 spin_lock_irqsave(&s->lock, flags);
1453 solo1_update_ptr(s);
1454 count = s->dma_dac.count;
1455 spin_unlock_irqrestore(&s->lock, flags);
1456 if (count < 0)
1457 count = 0;
1458 return put_user(count, p);
1459
1460 case SNDCTL_DSP_GETIPTR:
1461 if (!(file->f_mode & FMODE_READ))
1462 return -EINVAL;
1463 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1464 return val;
1465 spin_lock_irqsave(&s->lock, flags);
1466 solo1_update_ptr(s);
1467 cinfo.bytes = s->dma_adc.total_bytes;
1468 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1469 cinfo.ptr = s->dma_adc.hwptr;
1470 if (s->dma_adc.mapped)
1471 s->dma_adc.count &= s->dma_adc.fragsize-1;
1472 spin_unlock_irqrestore(&s->lock, flags);
1473 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1474 return -EFAULT;
1475 return 0;
1476
1477 case SNDCTL_DSP_GETOPTR:
1478 if (!(file->f_mode & FMODE_WRITE))
1479 return -EINVAL;
1480 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1481 return val;
1482 spin_lock_irqsave(&s->lock, flags);
1483 solo1_update_ptr(s);
1484 cinfo.bytes = s->dma_dac.total_bytes;
1485 count = s->dma_dac.count;
1486 if (count < 0)
1487 count = 0;
1488 cinfo.blocks = count >> s->dma_dac.fragshift;
1489 cinfo.ptr = s->dma_dac.hwptr;
1490 if (s->dma_dac.mapped)
1491 s->dma_dac.count &= s->dma_dac.fragsize-1;
1492 spin_unlock_irqrestore(&s->lock, flags);
1493 #if 0
1494 printk(KERN_DEBUG "esssolo1: GETOPTR: bytes %u blocks %u ptr %u, buforder %u numfrag %u fragshift %u\n"
1495 KERN_DEBUG "esssolo1: swptr %u count %u fragsize %u dmasize %u fragsamples %u\n",
1496 cinfo.bytes, cinfo.blocks, cinfo.ptr, s->dma_dac.buforder, s->dma_dac.numfrag, s->dma_dac.fragshift,
1497 s->dma_dac.swptr, s->dma_dac.count, s->dma_dac.fragsize, s->dma_dac.dmasize, s->dma_dac.fragsamples);
1498 #endif
1499 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1500 return -EFAULT;
1501 return 0;
1502
1503 case SNDCTL_DSP_GETBLKSIZE:
1504 if (file->f_mode & FMODE_WRITE) {
1505 if ((val = prog_dmabuf_dac(s)))
1506 return val;
1507 return put_user(s->dma_dac.fragsize, p);
1508 }
1509 if ((val = prog_dmabuf_adc(s)))
1510 return val;
1511 return put_user(s->dma_adc.fragsize, p);
1512
1513 case SNDCTL_DSP_SETFRAGMENT:
1514 if (get_user(val, p))
1515 return -EFAULT;
1516 if (file->f_mode & FMODE_READ) {
1517 s->dma_adc.ossfragshift = val & 0xffff;
1518 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1519 if (s->dma_adc.ossfragshift < 4)
1520 s->dma_adc.ossfragshift = 4;
1521 if (s->dma_adc.ossfragshift > 15)
1522 s->dma_adc.ossfragshift = 15;
1523 if (s->dma_adc.ossmaxfrags < 4)
1524 s->dma_adc.ossmaxfrags = 4;
1525 }
1526 if (file->f_mode & FMODE_WRITE) {
1527 s->dma_dac.ossfragshift = val & 0xffff;
1528 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1529 if (s->dma_dac.ossfragshift < 4)
1530 s->dma_dac.ossfragshift = 4;
1531 if (s->dma_dac.ossfragshift > 15)
1532 s->dma_dac.ossfragshift = 15;
1533 if (s->dma_dac.ossmaxfrags < 4)
1534 s->dma_dac.ossmaxfrags = 4;
1535 }
1536 return 0;
1537
1538 case SNDCTL_DSP_SUBDIVIDE:
1539 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1540 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1541 return -EINVAL;
1542 if (get_user(val, p))
1543 return -EFAULT;
1544 if (val != 1 && val != 2 && val != 4)
1545 return -EINVAL;
1546 if (file->f_mode & FMODE_READ)
1547 s->dma_adc.subdivision = val;
1548 if (file->f_mode & FMODE_WRITE)
1549 s->dma_dac.subdivision = val;
1550 return 0;
1551
1552 case SOUND_PCM_READ_RATE:
1553 return put_user(s->rate, p);
1554
1555 case SOUND_PCM_READ_CHANNELS:
1556 return put_user(s->channels, p);
1557
1558 case SOUND_PCM_READ_BITS:
1559 return put_user((s->fmt & (AFMT_S8|AFMT_U8)) ? 8 : 16, p);
1560
1561 case SOUND_PCM_WRITE_FILTER:
1562 case SNDCTL_DSP_SETSYNCRO:
1563 case SOUND_PCM_READ_FILTER:
1564 return -EINVAL;
1565
1566 }
1567 return mixer_ioctl(s, cmd, arg);
1568 }
1569
1570 static int solo1_release(struct inode *inode, struct file *file)
1571 {
1572 struct solo1_state *s = (struct solo1_state *)file->private_data;
1573
1574 VALIDATE_STATE(s);
1575 lock_kernel();
1576 if (file->f_mode & FMODE_WRITE)
1577 drain_dac(s, file->f_flags & O_NONBLOCK);
1578 down(&s->open_sem);
1579 if (file->f_mode & FMODE_WRITE) {
1580 stop_dac(s);
1581 outb(0, s->iobase+6); /* disable DMA */
1582 dealloc_dmabuf(s, &s->dma_dac);
1583 }
1584 if (file->f_mode & FMODE_READ) {
1585 stop_adc(s);
1586 outb(1, s->ddmabase+0xf); /* mask DMA channel */
1587 outb(0, s->ddmabase+0xd); /* DMA master clear */
1588 dealloc_dmabuf(s, &s->dma_adc);
1589 }
1590 s->open_mode &= ~(FMODE_READ | FMODE_WRITE);
1591 wake_up(&s->open_wait);
1592 up(&s->open_sem);
1593 unlock_kernel();
1594 return 0;
1595 }
1596
1597 static int solo1_open(struct inode *inode, struct file *file)
1598 {
1599 unsigned int minor = iminor(inode);
1600 DECLARE_WAITQUEUE(wait, current);
1601 struct solo1_state *s = NULL;
1602 struct pci_dev *pci_dev = NULL;
1603
1604 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
1605 struct pci_driver *drvr;
1606
1607 drvr = pci_dev_driver(pci_dev);
1608 if (drvr != &solo1_driver)
1609 continue;
1610 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1611 if (!s)
1612 continue;
1613 if (!((s->dev_audio ^ minor) & ~0xf))
1614 break;
1615 }
1616 if (!s)
1617 return -ENODEV;
1618 VALIDATE_STATE(s);
1619 file->private_data = s;
1620 /* wait for device to become free */
1621 down(&s->open_sem);
1622 while (s->open_mode & (FMODE_READ | FMODE_WRITE)) {
1623 if (file->f_flags & O_NONBLOCK) {
1624 up(&s->open_sem);
1625 return -EBUSY;
1626 }
1627 add_wait_queue(&s->open_wait, &wait);
1628 __set_current_state(TASK_INTERRUPTIBLE);
1629 up(&s->open_sem);
1630 schedule();
1631 remove_wait_queue(&s->open_wait, &wait);
1632 set_current_state(TASK_RUNNING);
1633 if (signal_pending(current))
1634 return -ERESTARTSYS;
1635 down(&s->open_sem);
1636 }
1637 s->fmt = AFMT_U8;
1638 s->channels = 1;
1639 s->rate = 8000;
1640 s->clkdiv = 96 | 0x80;
1641 s->ena = 0;
1642 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1643 s->dma_adc.enabled = 1;
1644 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
1645 s->dma_dac.enabled = 1;
1646 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1647 up(&s->open_sem);
1648 prog_codec(s);
1649 return nonseekable_open(inode, file);
1650 }
1651
1652 static /*const*/ struct file_operations solo1_audio_fops = {
1653 .owner = THIS_MODULE,
1654 .llseek = no_llseek,
1655 .read = solo1_read,
1656 .write = solo1_write,
1657 .poll = solo1_poll,
1658 .ioctl = solo1_ioctl,
1659 .mmap = solo1_mmap,
1660 .open = solo1_open,
1661 .release = solo1_release,
1662 };
1663
1664 /* --------------------------------------------------------------------- */
1665
1666 /* hold spinlock for the following! */
1667 static void solo1_handle_midi(struct solo1_state *s)
1668 {
1669 unsigned char ch;
1670 int wake;
1671
1672 if (!(s->mpubase))
1673 return;
1674 wake = 0;
1675 while (!(inb(s->mpubase+1) & 0x80)) {
1676 ch = inb(s->mpubase);
1677 if (s->midi.icnt < MIDIINBUF) {
1678 s->midi.ibuf[s->midi.iwr] = ch;
1679 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1680 s->midi.icnt++;
1681 }
1682 wake = 1;
1683 }
1684 if (wake)
1685 wake_up(&s->midi.iwait);
1686 wake = 0;
1687 while (!(inb(s->mpubase+1) & 0x40) && s->midi.ocnt > 0) {
1688 outb(s->midi.obuf[s->midi.ord], s->mpubase);
1689 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1690 s->midi.ocnt--;
1691 if (s->midi.ocnt < MIDIOUTBUF-16)
1692 wake = 1;
1693 }
1694 if (wake)
1695 wake_up(&s->midi.owait);
1696 }
1697
1698 static irqreturn_t solo1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1699 {
1700 struct solo1_state *s = (struct solo1_state *)dev_id;
1701 unsigned int intsrc;
1702
1703 /* fastpath out, to ease interrupt sharing */
1704 intsrc = inb(s->iobase+7); /* get interrupt source(s) */
1705 if (!intsrc)
1706 return IRQ_NONE;
1707 (void)inb(s->sbbase+0xe); /* clear interrupt */
1708 spin_lock(&s->lock);
1709 /* clear audio interrupts first */
1710 if (intsrc & 0x20)
1711 write_mixer(s, 0x7a, read_mixer(s, 0x7a) & 0x7f);
1712 solo1_update_ptr(s);
1713 solo1_handle_midi(s);
1714 spin_unlock(&s->lock);
1715 return IRQ_HANDLED;
1716 }
1717
1718 static void solo1_midi_timer(unsigned long data)
1719 {
1720 struct solo1_state *s = (struct solo1_state *)data;
1721 unsigned long flags;
1722
1723 spin_lock_irqsave(&s->lock, flags);
1724 solo1_handle_midi(s);
1725 spin_unlock_irqrestore(&s->lock, flags);
1726 s->midi.timer.expires = jiffies+1;
1727 add_timer(&s->midi.timer);
1728 }
1729
1730 /* --------------------------------------------------------------------- */
1731
1732 static ssize_t solo1_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1733 {
1734 struct solo1_state *s = (struct solo1_state *)file->private_data;
1735 DECLARE_WAITQUEUE(wait, current);
1736 ssize_t ret;
1737 unsigned long flags;
1738 unsigned ptr;
1739 int cnt;
1740
1741 VALIDATE_STATE(s);
1742 if (!access_ok(VERIFY_WRITE, buffer, count))
1743 return -EFAULT;
1744 if (count == 0)
1745 return 0;
1746 ret = 0;
1747 add_wait_queue(&s->midi.iwait, &wait);
1748 while (count > 0) {
1749 spin_lock_irqsave(&s->lock, flags);
1750 ptr = s->midi.ird;
1751 cnt = MIDIINBUF - ptr;
1752 if (s->midi.icnt < cnt)
1753 cnt = s->midi.icnt;
1754 if (cnt <= 0)
1755 __set_current_state(TASK_INTERRUPTIBLE);
1756 spin_unlock_irqrestore(&s->lock, flags);
1757 if (cnt > count)
1758 cnt = count;
1759 if (cnt <= 0) {
1760 if (file->f_flags & O_NONBLOCK) {
1761 if (!ret)
1762 ret = -EAGAIN;
1763 break;
1764 }
1765 schedule();
1766 if (signal_pending(current)) {
1767 if (!ret)
1768 ret = -ERESTARTSYS;
1769 break;
1770 }
1771 continue;
1772 }
1773 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
1774 if (!ret)
1775 ret = -EFAULT;
1776 break;
1777 }
1778 ptr = (ptr + cnt) % MIDIINBUF;
1779 spin_lock_irqsave(&s->lock, flags);
1780 s->midi.ird = ptr;
1781 s->midi.icnt -= cnt;
1782 spin_unlock_irqrestore(&s->lock, flags);
1783 count -= cnt;
1784 buffer += cnt;
1785 ret += cnt;
1786 break;
1787 }
1788 __set_current_state(TASK_RUNNING);
1789 remove_wait_queue(&s->midi.iwait, &wait);
1790 return ret;
1791 }
1792
1793 static ssize_t solo1_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1794 {
1795 struct solo1_state *s = (struct solo1_state *)file->private_data;
1796 DECLARE_WAITQUEUE(wait, current);
1797 ssize_t ret;
1798 unsigned long flags;
1799 unsigned ptr;
1800 int cnt;
1801
1802 VALIDATE_STATE(s);
1803 if (!access_ok(VERIFY_READ, buffer, count))
1804 return -EFAULT;
1805 if (count == 0)
1806 return 0;
1807 ret = 0;
1808 add_wait_queue(&s->midi.owait, &wait);
1809 while (count > 0) {
1810 spin_lock_irqsave(&s->lock, flags);
1811 ptr = s->midi.owr;
1812 cnt = MIDIOUTBUF - ptr;
1813 if (s->midi.ocnt + cnt > MIDIOUTBUF)
1814 cnt = MIDIOUTBUF - s->midi.ocnt;
1815 if (cnt <= 0) {
1816 __set_current_state(TASK_INTERRUPTIBLE);
1817 solo1_handle_midi(s);
1818 }
1819 spin_unlock_irqrestore(&s->lock, flags);
1820 if (cnt > count)
1821 cnt = count;
1822 if (cnt <= 0) {
1823 if (file->f_flags & O_NONBLOCK) {
1824 if (!ret)
1825 ret = -EAGAIN;
1826 break;
1827 }
1828 schedule();
1829 if (signal_pending(current)) {
1830 if (!ret)
1831 ret = -ERESTARTSYS;
1832 break;
1833 }
1834 continue;
1835 }
1836 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
1837 if (!ret)
1838 ret = -EFAULT;
1839 break;
1840 }
1841 ptr = (ptr + cnt) % MIDIOUTBUF;
1842 spin_lock_irqsave(&s->lock, flags);
1843 s->midi.owr = ptr;
1844 s->midi.ocnt += cnt;
1845 spin_unlock_irqrestore(&s->lock, flags);
1846 count -= cnt;
1847 buffer += cnt;
1848 ret += cnt;
1849 spin_lock_irqsave(&s->lock, flags);
1850 solo1_handle_midi(s);
1851 spin_unlock_irqrestore(&s->lock, flags);
1852 }
1853 __set_current_state(TASK_RUNNING);
1854 remove_wait_queue(&s->midi.owait, &wait);
1855 return ret;
1856 }
1857
1858 /* No kernel lock - we have our own spinlock */
1859 static unsigned int solo1_midi_poll(struct file *file, struct poll_table_struct *wait)
1860 {
1861 struct solo1_state *s = (struct solo1_state *)file->private_data;
1862 unsigned long flags;
1863 unsigned int mask = 0;
1864
1865 VALIDATE_STATE(s);
1866 if (file->f_flags & FMODE_WRITE)
1867 poll_wait(file, &s->midi.owait, wait);
1868 if (file->f_flags & FMODE_READ)
1869 poll_wait(file, &s->midi.iwait, wait);
1870 spin_lock_irqsave(&s->lock, flags);
1871 if (file->f_flags & FMODE_READ) {
1872 if (s->midi.icnt > 0)
1873 mask |= POLLIN | POLLRDNORM;
1874 }
1875 if (file->f_flags & FMODE_WRITE) {
1876 if (s->midi.ocnt < MIDIOUTBUF)
1877 mask |= POLLOUT | POLLWRNORM;
1878 }
1879 spin_unlock_irqrestore(&s->lock, flags);
1880 return mask;
1881 }
1882
1883 static int solo1_midi_open(struct inode *inode, struct file *file)
1884 {
1885 unsigned int minor = iminor(inode);
1886 DECLARE_WAITQUEUE(wait, current);
1887 unsigned long flags;
1888 struct solo1_state *s = NULL;
1889 struct pci_dev *pci_dev = NULL;
1890
1891 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
1892 struct pci_driver *drvr;
1893
1894 drvr = pci_dev_driver(pci_dev);
1895 if (drvr != &solo1_driver)
1896 continue;
1897 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1898 if (!s)
1899 continue;
1900 if (s->dev_midi == minor)
1901 break;
1902 }
1903 if (!s)
1904 return -ENODEV;
1905 VALIDATE_STATE(s);
1906 file->private_data = s;
1907 /* wait for device to become free */
1908 down(&s->open_sem);
1909 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
1910 if (file->f_flags & O_NONBLOCK) {
1911 up(&s->open_sem);
1912 return -EBUSY;
1913 }
1914 add_wait_queue(&s->open_wait, &wait);
1915 __set_current_state(TASK_INTERRUPTIBLE);
1916 up(&s->open_sem);
1917 schedule();
1918 remove_wait_queue(&s->open_wait, &wait);
1919 set_current_state(TASK_RUNNING);
1920 if (signal_pending(current))
1921 return -ERESTARTSYS;
1922 down(&s->open_sem);
1923 }
1924 spin_lock_irqsave(&s->lock, flags);
1925 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1926 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1927 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1928 outb(0xff, s->mpubase+1); /* reset command */
1929 outb(0x3f, s->mpubase+1); /* uart command */
1930 if (!(inb(s->mpubase+1) & 0x80))
1931 inb(s->mpubase);
1932 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1933 outb(0xb0, s->iobase + 7); /* enable A1, A2, MPU irq's */
1934 init_timer(&s->midi.timer);
1935 s->midi.timer.expires = jiffies+1;
1936 s->midi.timer.data = (unsigned long)s;
1937 s->midi.timer.function = solo1_midi_timer;
1938 add_timer(&s->midi.timer);
1939 }
1940 if (file->f_mode & FMODE_READ) {
1941 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1942 }
1943 if (file->f_mode & FMODE_WRITE) {
1944 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1945 }
1946 spin_unlock_irqrestore(&s->lock, flags);
1947 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
1948 up(&s->open_sem);
1949 return nonseekable_open(inode, file);
1950 }
1951
1952 static int solo1_midi_release(struct inode *inode, struct file *file)
1953 {
1954 struct solo1_state *s = (struct solo1_state *)file->private_data;
1955 DECLARE_WAITQUEUE(wait, current);
1956 unsigned long flags;
1957 unsigned count, tmo;
1958
1959 VALIDATE_STATE(s);
1960
1961 lock_kernel();
1962 if (file->f_mode & FMODE_WRITE) {
1963 add_wait_queue(&s->midi.owait, &wait);
1964 for (;;) {
1965 __set_current_state(TASK_INTERRUPTIBLE);
1966 spin_lock_irqsave(&s->lock, flags);
1967 count = s->midi.ocnt;
1968 spin_unlock_irqrestore(&s->lock, flags);
1969 if (count <= 0)
1970 break;
1971 if (signal_pending(current))
1972 break;
1973 if (file->f_flags & O_NONBLOCK)
1974 break;
1975 tmo = (count * HZ) / 3100;
1976 if (!schedule_timeout(tmo ? : 1) && tmo)
1977 printk(KERN_DEBUG "solo1: midi timed out??\n");
1978 }
1979 remove_wait_queue(&s->midi.owait, &wait);
1980 set_current_state(TASK_RUNNING);
1981 }
1982 down(&s->open_sem);
1983 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
1984 spin_lock_irqsave(&s->lock, flags);
1985 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1986 outb(0x30, s->iobase + 7); /* enable A1, A2 irq's */
1987 del_timer(&s->midi.timer);
1988 }
1989 spin_unlock_irqrestore(&s->lock, flags);
1990 wake_up(&s->open_wait);
1991 up(&s->open_sem);
1992 unlock_kernel();
1993 return 0;
1994 }
1995
1996 static /*const*/ struct file_operations solo1_midi_fops = {
1997 .owner = THIS_MODULE,
1998 .llseek = no_llseek,
1999 .read = solo1_midi_read,
2000 .write = solo1_midi_write,
2001 .poll = solo1_midi_poll,
2002 .open = solo1_midi_open,
2003 .release = solo1_midi_release,
2004 };
2005
2006 /* --------------------------------------------------------------------- */
2007
2008 static int solo1_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2009 {
2010 static const unsigned char op_offset[18] = {
2011 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
2012 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
2013 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
2014 };
2015 struct solo1_state *s = (struct solo1_state *)file->private_data;
2016 struct dm_fm_voice v;
2017 struct dm_fm_note n;
2018 struct dm_fm_params p;
2019 unsigned int io;
2020 unsigned int regb;
2021
2022 switch (cmd) {
2023 case FM_IOCTL_RESET:
2024 for (regb = 0xb0; regb < 0xb9; regb++) {
2025 outb(regb, s->sbbase);
2026 outb(0, s->sbbase+1);
2027 outb(regb, s->sbbase+2);
2028 outb(0, s->sbbase+3);
2029 }
2030 return 0;
2031
2032 case FM_IOCTL_PLAY_NOTE:
2033 if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
2034 return -EFAULT;
2035 if (n.voice >= 18)
2036 return -EINVAL;
2037 if (n.voice >= 9) {
2038 regb = n.voice - 9;
2039 io = s->sbbase+2;
2040 } else {
2041 regb = n.voice;
2042 io = s->sbbase;
2043 }
2044 outb(0xa0 + regb, io);
2045 outb(n.fnum & 0xff, io+1);
2046 outb(0xb0 + regb, io);
2047 outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
2048 return 0;
2049
2050 case FM_IOCTL_SET_VOICE:
2051 if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
2052 return -EFAULT;
2053 if (v.voice >= 18)
2054 return -EINVAL;
2055 regb = op_offset[v.voice];
2056 io = s->sbbase + ((v.op & 1) << 1);
2057 outb(0x20 + regb, io);
2058 outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
2059 ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
2060 outb(0x40 + regb, io);
2061 outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
2062 outb(0x60 + regb, io);
2063 outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
2064 outb(0x80 + regb, io);
2065 outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
2066 outb(0xe0 + regb, io);
2067 outb(v.waveform & 0x7, io+1);
2068 if (n.voice >= 9) {
2069 regb = n.voice - 9;
2070 io = s->sbbase+2;
2071 } else {
2072 regb = n.voice;
2073 io = s->sbbase;
2074 }
2075 outb(0xc0 + regb, io);
2076 outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
2077 (v.connection & 1), io+1);
2078 return 0;
2079
2080 case FM_IOCTL_SET_PARAMS:
2081 if (copy_from_user(&p, (void __user *)arg, sizeof(p)))
2082 return -EFAULT;
2083 outb(0x08, s->sbbase);
2084 outb((p.kbd_split & 1) << 6, s->sbbase+1);
2085 outb(0xbd, s->sbbase);
2086 outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
2087 ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->sbbase+1);
2088 return 0;
2089
2090 case FM_IOCTL_SET_OPL:
2091 outb(4, s->sbbase+2);
2092 outb(arg, s->sbbase+3);
2093 return 0;
2094
2095 case FM_IOCTL_SET_MODE:
2096 outb(5, s->sbbase+2);
2097 outb(arg & 1, s->sbbase+3);
2098 return 0;
2099
2100 default:
2101 return -EINVAL;
2102 }
2103 }
2104
2105 static int solo1_dmfm_open(struct inode *inode, struct file *file)
2106 {
2107 unsigned int minor = iminor(inode);
2108 DECLARE_WAITQUEUE(wait, current);
2109 struct solo1_state *s = NULL;
2110 struct pci_dev *pci_dev = NULL;
2111
2112 while ((pci_dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL) {
2113 struct pci_driver *drvr;
2114
2115 drvr = pci_dev_driver(pci_dev);
2116 if (drvr != &solo1_driver)
2117 continue;
2118 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2119 if (!s)
2120 continue;
2121 if (s->dev_dmfm == minor)
2122 break;
2123 }
2124 if (!s)
2125 return -ENODEV;
2126 VALIDATE_STATE(s);
2127 file->private_data = s;
2128 /* wait for device to become free */
2129 down(&s->open_sem);
2130 while (s->open_mode & FMODE_DMFM) {
2131 if (file->f_flags & O_NONBLOCK) {
2132 up(&s->open_sem);
2133 return -EBUSY;
2134 }
2135 add_wait_queue(&s->open_wait, &wait);
2136 __set_current_state(TASK_INTERRUPTIBLE);
2137 up(&s->open_sem);
2138 schedule();
2139 remove_wait_queue(&s->open_wait, &wait);
2140 set_current_state(TASK_RUNNING);
2141 if (signal_pending(current))
2142 return -ERESTARTSYS;
2143 down(&s->open_sem);
2144 }
2145 if (!request_region(s->sbbase, FMSYNTH_EXTENT, "ESS Solo1")) {
2146 up(&s->open_sem);
2147 printk(KERN_ERR "solo1: FM synth io ports in use, opl3 loaded?\n");
2148 return -EBUSY;
2149 }
2150 /* init the stuff */
2151 outb(1, s->sbbase);
2152 outb(0x20, s->sbbase+1); /* enable waveforms */
2153 outb(4, s->sbbase+2);
2154 outb(0, s->sbbase+3); /* no 4op enabled */
2155 outb(5, s->sbbase+2);
2156 outb(1, s->sbbase+3); /* enable OPL3 */
2157 s->open_mode |= FMODE_DMFM;
2158 up(&s->open_sem);
2159 return nonseekable_open(inode, file);
2160 }
2161
2162 static int solo1_dmfm_release(struct inode *inode, struct file *file)
2163 {
2164 struct solo1_state *s = (struct solo1_state *)file->private_data;
2165 unsigned int regb;
2166
2167 VALIDATE_STATE(s);
2168 lock_kernel();
2169 down(&s->open_sem);
2170 s->open_mode &= ~FMODE_DMFM;
2171 for (regb = 0xb0; regb < 0xb9; regb++) {
2172 outb(regb, s->sbbase);
2173 outb(0, s->sbbase+1);
2174 outb(regb, s->sbbase+2);
2175 outb(0, s->sbbase+3);
2176 }
2177 release_region(s->sbbase, FMSYNTH_EXTENT);
2178 wake_up(&s->open_wait);
2179 up(&s->open_sem);
2180 unlock_kernel();
2181 return 0;
2182 }
2183
2184 static /*const*/ struct file_operations solo1_dmfm_fops = {
2185 .owner = THIS_MODULE,
2186 .llseek = no_llseek,
2187 .ioctl = solo1_dmfm_ioctl,
2188 .open = solo1_dmfm_open,
2189 .release = solo1_dmfm_release,
2190 };
2191
2192 /* --------------------------------------------------------------------- */
2193
2194 static struct initvol {
2195 int mixch;
2196 int vol;
2197 } initvol[] __devinitdata = {
2198 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2199 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2200 { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
2201 { SOUND_MIXER_WRITE_CD, 0x4040 },
2202 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2203 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2204 { SOUND_MIXER_WRITE_LINE2, 0x4040 },
2205 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2206 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2207 { SOUND_MIXER_WRITE_MIC, 0x4040 }
2208 };
2209
2210 static int setup_solo1(struct solo1_state *s)
2211 {
2212 struct pci_dev *pcidev = s->dev;
2213 mm_segment_t fs;
2214 int i, val;
2215
2216 /* initialize DDMA base address */
2217 printk(KERN_DEBUG "solo1: ddma base address: 0x%lx\n", s->ddmabase);
2218 pci_write_config_word(pcidev, 0x60, (s->ddmabase & (~0xf)) | 1);
2219 /* set DMA policy to DDMA, IRQ emulation off (CLKRUN disabled for now) */
2220 pci_write_config_dword(pcidev, 0x50, 0);
2221 /* disable legacy audio address decode */
2222 pci_write_config_word(pcidev, 0x40, 0x907f);
2223
2224 /* initialize the chips */
2225 if (!reset_ctrl(s)) {
2226 printk(KERN_ERR "esssolo1: cannot reset controller\n");
2227 return -1;
2228 }
2229 outb(0xb0, s->iobase+7); /* enable A1, A2, MPU irq's */
2230
2231 /* initialize mixer regs */
2232 write_mixer(s, 0x7f, 0); /* disable music digital recording */
2233 write_mixer(s, 0x7d, 0x0c); /* enable mic preamp, MONO_OUT is 2nd DAC right channel */
2234 write_mixer(s, 0x64, 0x45); /* volume control */
2235 write_mixer(s, 0x48, 0x10); /* enable music DAC/ES6xx interface */
2236 write_mixer(s, 0x50, 0); /* disable spatializer */
2237 write_mixer(s, 0x52, 0);
2238 write_mixer(s, 0x14, 0); /* DAC1 minimum volume */
2239 write_mixer(s, 0x71, 0x20); /* enable new 0xA1 reg format */
2240 outb(0, s->ddmabase+0xd); /* DMA master clear */
2241 outb(1, s->ddmabase+0xf); /* mask channel */
2242 /*outb(0, s->ddmabase+0x8);*/ /* enable controller (enable is low active!!) */
2243
2244 pci_set_master(pcidev); /* enable bus mastering */
2245
2246 fs = get_fs();
2247 set_fs(KERNEL_DS);
2248 val = SOUND_MASK_LINE;
2249 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2250 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2251 val = initvol[i].vol;
2252 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2253 }
2254 val = 1; /* enable mic preamp */
2255 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long)&val);
2256 set_fs(fs);
2257 return 0;
2258 }
2259
2260 static int
2261 solo1_suspend(struct pci_dev *pci_dev, pm_message_t state) {
2262 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2263 if (!s)
2264 return 1;
2265 outb(0, s->iobase+6);
2266 /* DMA master clear */
2267 outb(0, s->ddmabase+0xd);
2268 /* reset sequencer and FIFO */
2269 outb(3, s->sbbase+6);
2270 /* turn off DDMA controller address space */
2271 pci_write_config_word(s->dev, 0x60, 0);
2272 return 0;
2273 }
2274
2275 static int
2276 solo1_resume(struct pci_dev *pci_dev) {
2277 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2278 if (!s)
2279 return 1;
2280 setup_solo1(s);
2281 return 0;
2282 }
2283
2284 static int __devinit solo1_register_gameport(struct solo1_state *s, int io_port)
2285 {
2286 struct gameport *gp;
2287
2288 if (!request_region(io_port, GAMEPORT_EXTENT, "ESS Solo1")) {
2289 printk(KERN_ERR "solo1: gameport io ports are in use\n");
2290 return -EBUSY;
2291 }
2292
2293 s->gameport = gp = gameport_allocate_port();
2294 if (!gp) {
2295 printk(KERN_ERR "solo1: can not allocate memory for gameport\n");
2296 release_region(io_port, GAMEPORT_EXTENT);
2297 return -ENOMEM;
2298 }
2299
2300 gameport_set_name(gp, "ESS Solo1 Gameport");
2301 gameport_set_phys(gp, "isa%04x/gameport0", io_port);
2302 gp->dev.parent = &s->dev->dev;
2303 gp->io = io_port;
2304
2305 gameport_register_port(gp);
2306
2307 return 0;
2308 }
2309
2310 static int __devinit solo1_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2311 {
2312 struct solo1_state *s;
2313 int gpio;
2314 int ret;
2315
2316 if ((ret=pci_enable_device(pcidev)))
2317 return ret;
2318 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO) ||
2319 !(pci_resource_flags(pcidev, 1) & IORESOURCE_IO) ||
2320 !(pci_resource_flags(pcidev, 2) & IORESOURCE_IO) ||
2321 !(pci_resource_flags(pcidev, 3) & IORESOURCE_IO))
2322 return -ENODEV;
2323 if (pcidev->irq == 0)
2324 return -ENODEV;
2325
2326 /* Recording requires 24-bit DMA, so attempt to set dma mask
2327 * to 24 bits first, then 32 bits (playback only) if that fails.
2328 */
2329 if (pci_set_dma_mask(pcidev, 0x00ffffff) &&
2330 pci_set_dma_mask(pcidev, DMA_32BIT_MASK)) {
2331 printk(KERN_WARNING "solo1: architecture does not support 24bit or 32bit PCI busmaster DMA\n");
2332 return -ENODEV;
2333 }
2334
2335 if (!(s = kmalloc(sizeof(struct solo1_state), GFP_KERNEL))) {
2336 printk(KERN_WARNING "solo1: out of memory\n");
2337 return -ENOMEM;
2338 }
2339 memset(s, 0, sizeof(struct solo1_state));
2340 init_waitqueue_head(&s->dma_adc.wait);
2341 init_waitqueue_head(&s->dma_dac.wait);
2342 init_waitqueue_head(&s->open_wait);
2343 init_waitqueue_head(&s->midi.iwait);
2344 init_waitqueue_head(&s->midi.owait);
2345 init_MUTEX(&s->open_sem);
2346 spin_lock_init(&s->lock);
2347 s->magic = SOLO1_MAGIC;
2348 s->dev = pcidev;
2349 s->iobase = pci_resource_start(pcidev, 0);
2350 s->sbbase = pci_resource_start(pcidev, 1);
2351 s->vcbase = pci_resource_start(pcidev, 2);
2352 s->ddmabase = s->vcbase + DDMABASE_OFFSET;
2353 s->mpubase = pci_resource_start(pcidev, 3);
2354 gpio = pci_resource_start(pcidev, 4);
2355 s->irq = pcidev->irq;
2356 ret = -EBUSY;
2357 if (!request_region(s->iobase, IOBASE_EXTENT, "ESS Solo1")) {
2358 printk(KERN_ERR "solo1: io ports in use\n");
2359 goto err_region1;
2360 }
2361 if (!request_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT, "ESS Solo1")) {
2362 printk(KERN_ERR "solo1: io ports in use\n");
2363 goto err_region2;
2364 }
2365 if (!request_region(s->ddmabase, DDMABASE_EXTENT, "ESS Solo1")) {
2366 printk(KERN_ERR "solo1: io ports in use\n");
2367 goto err_region3;
2368 }
2369 if (!request_region(s->mpubase, MPUBASE_EXTENT, "ESS Solo1")) {
2370 printk(KERN_ERR "solo1: io ports in use\n");
2371 goto err_region4;
2372 }
2373 if ((ret=request_irq(s->irq,solo1_interrupt,SA_SHIRQ,"ESS Solo1",s))) {
2374 printk(KERN_ERR "solo1: irq %u in use\n", s->irq);
2375 goto err_irq;
2376 }
2377 /* register devices */
2378 if ((s->dev_audio = register_sound_dsp(&solo1_audio_fops, -1)) < 0) {
2379 ret = s->dev_audio;
2380 goto err_dev1;
2381 }
2382 if ((s->dev_mixer = register_sound_mixer(&solo1_mixer_fops, -1)) < 0) {
2383 ret = s->dev_mixer;
2384 goto err_dev2;
2385 }
2386 if ((s->dev_midi = register_sound_midi(&solo1_midi_fops, -1)) < 0) {
2387 ret = s->dev_midi;
2388 goto err_dev3;
2389 }
2390 if ((s->dev_dmfm = register_sound_special(&solo1_dmfm_fops, 15 /* ?? */)) < 0) {
2391 ret = s->dev_dmfm;
2392 goto err_dev4;
2393 }
2394 if (setup_solo1(s)) {
2395 ret = -EIO;
2396 goto err;
2397 }
2398 /* register gameport */
2399 solo1_register_gameport(s, gpio);
2400 /* store it in the driver field */
2401 pci_set_drvdata(pcidev, s);
2402 return 0;
2403
2404 err:
2405 unregister_sound_special(s->dev_dmfm);
2406 err_dev4:
2407 unregister_sound_midi(s->dev_midi);
2408 err_dev3:
2409 unregister_sound_mixer(s->dev_mixer);
2410 err_dev2:
2411 unregister_sound_dsp(s->dev_audio);
2412 err_dev1:
2413 printk(KERN_ERR "solo1: initialisation error\n");
2414 free_irq(s->irq, s);
2415 err_irq:
2416 release_region(s->mpubase, MPUBASE_EXTENT);
2417 err_region4:
2418 release_region(s->ddmabase, DDMABASE_EXTENT);
2419 err_region3:
2420 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2421 err_region2:
2422 release_region(s->iobase, IOBASE_EXTENT);
2423 err_region1:
2424 kfree(s);
2425 return ret;
2426 }
2427
2428 static void __devexit solo1_remove(struct pci_dev *dev)
2429 {
2430 struct solo1_state *s = pci_get_drvdata(dev);
2431
2432 if (!s)
2433 return;
2434 /* stop DMA controller */
2435 outb(0, s->iobase+6);
2436 outb(0, s->ddmabase+0xd); /* DMA master clear */
2437 outb(3, s->sbbase+6); /* reset sequencer and FIFO */
2438 synchronize_irq(s->irq);
2439 pci_write_config_word(s->dev, 0x60, 0); /* turn off DDMA controller address space */
2440 free_irq(s->irq, s);
2441 if (s->gameport) {
2442 int gpio = s->gameport->io;
2443 gameport_unregister_port(s->gameport);
2444 release_region(gpio, GAMEPORT_EXTENT);
2445 }
2446 release_region(s->iobase, IOBASE_EXTENT);
2447 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2448 release_region(s->ddmabase, DDMABASE_EXTENT);
2449 release_region(s->mpubase, MPUBASE_EXTENT);
2450 unregister_sound_dsp(s->dev_audio);
2451 unregister_sound_mixer(s->dev_mixer);
2452 unregister_sound_midi(s->dev_midi);
2453 unregister_sound_special(s->dev_dmfm);
2454 kfree(s);
2455 pci_set_drvdata(dev, NULL);
2456 }
2457
2458 static struct pci_device_id id_table[] = {
2459 { PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_SOLO1, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2460 { 0, }
2461 };
2462
2463 MODULE_DEVICE_TABLE(pci, id_table);
2464
2465 static struct pci_driver solo1_driver = {
2466 .name = "ESS Solo1",
2467 .id_table = id_table,
2468 .probe = solo1_probe,
2469 .remove = __devexit_p(solo1_remove),
2470 .suspend = solo1_suspend,
2471 .resume = solo1_resume,
2472 };
2473
2474
2475 static int __init init_solo1(void)
2476 {
2477 printk(KERN_INFO "solo1: version v0.20 time " __TIME__ " " __DATE__ "\n");
2478 return pci_register_driver(&solo1_driver);
2479 }
2480
2481 /* --------------------------------------------------------------------- */
2482
2483 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2484 MODULE_DESCRIPTION("ESS Solo1 Driver");
2485 MODULE_LICENSE("GPL");
2486
2487
2488 static void __exit cleanup_solo1(void)
2489 {
2490 printk(KERN_INFO "solo1: unloading\n");
2491 pci_unregister_driver(&solo1_driver);
2492 }
2493
2494 /* --------------------------------------------------------------------- */
2495
2496 module_init(init_solo1);
2497 module_exit(cleanup_solo1);
2498
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