2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
23 #include <sound/driver.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
50 "{C-Media,CMI8338B}}");
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
56 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
57 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
58 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable switches */
59 static long mpu_port
[SNDRV_CARDS
];
60 static long fm_port
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)]=1};
61 static int soft_ac3
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port
[SNDRV_CARDS
];
66 module_param_array(index
, int, NULL
, 0444);
67 MODULE_PARM_DESC(index
, "Index value for C-Media PCI soundcard.");
68 module_param_array(id
, charp
, NULL
, 0444);
69 MODULE_PARM_DESC(id
, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable
, bool, NULL
, 0444);
71 MODULE_PARM_DESC(enable
, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port
, long, NULL
, 0444);
73 MODULE_PARM_DESC(mpu_port
, "MPU-401 port.");
74 module_param_array(fm_port
, long, NULL
, 0444);
75 MODULE_PARM_DESC(fm_port
, "FM port.");
76 module_param_array(soft_ac3
, bool, NULL
, 0444);
77 MODULE_PARM_DESC(soft_ac3
, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port
, int, NULL
, 0444);
80 MODULE_PARM_DESC(joystick_port
, "Joystick port address.");
84 * CM8x38 registers definition
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99 #define CM_DSFC_SHIFT 13
100 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101 #define CM_ASFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* legacy UART */
110 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111 #define CM_ZVPORT 0x00000001 /* ZVPORT */
113 #define CM_REG_CHFORMAT 0x08
115 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
117 #define CM_CHB3D 0x20000000 /* 4 channels */
119 #define CM_CHIP_MASK1 0x1f000000
120 #define CM_CHIP_037 0x01000000
121 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
122 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
124 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
126 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
127 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
129 #define CM_ADCBITLEN_MASK 0x0000C000
130 #define CM_ADCBITLEN_16 0x00000000
131 #define CM_ADCBITLEN_15 0x00004000
132 #define CM_ADCBITLEN_14 0x00008000
133 #define CM_ADCBITLEN_13 0x0000C000
135 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
136 #define CM_ADCDACLEN_060 0x00000000
137 #define CM_ADCDACLEN_066 0x00001000
138 #define CM_ADCDACLEN_130 0x00002000
139 #define CM_ADCDACLEN_280 0x00003000
141 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142 #define CM_ADCDLEN_ORIGINAL 0x00000000
143 #define CM_ADCDLEN_EXTRA 0x00001000
144 #define CM_ADCDLEN_24K 0x00002000
145 #define CM_ADCDLEN_WEIGHT 0x00003000
147 #define CM_CH1_SRATE_176K 0x00000800
148 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
149 #define CM_CH1_SRATE_88K 0x00000400
150 #define CM_CH0_SRATE_176K 0x00000200
151 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
152 #define CM_CH0_SRATE_88K 0x00000100
153 #define CM_CH0_SRATE_128K 0x00000300
154 #define CM_CH0_SRATE_MASK 0x00000300
156 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
157 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
158 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
159 #define CM_SPDLOCKED 0x00000010
161 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
162 #define CM_CH1FMT_SHIFT 2
163 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
164 #define CM_CH0FMT_SHIFT 0
166 #define CM_REG_INT_HLDCLR 0x0C
167 #define CM_CHIP_MASK2 0xff000000
168 #define CM_CHIP_8768 0x20000000
169 #define CM_CHIP_055 0x08000000
170 #define CM_CHIP_039 0x04000000
171 #define CM_CHIP_039_6CH 0x01000000
172 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
173 #define CM_TDMA_INT_EN 0x00040000
174 #define CM_CH1_INT_EN 0x00020000
175 #define CM_CH0_INT_EN 0x00010000
177 #define CM_REG_INT_STATUS 0x10
178 #define CM_INTR 0x80000000
179 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
180 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
181 #define CM_UARTINT 0x00010000
182 #define CM_LTDMAINT 0x00008000
183 #define CM_HTDMAINT 0x00004000
184 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
185 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
186 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
187 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
188 #define CM_CH1BUSY 0x00000008
189 #define CM_CH0BUSY 0x00000004
190 #define CM_CHINT1 0x00000002
191 #define CM_CHINT0 0x00000001
193 #define CM_REG_LEGACY_CTRL 0x14
194 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
195 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
196 #define CM_VMPU_330 0x00000000
197 #define CM_VMPU_320 0x20000000
198 #define CM_VMPU_310 0x40000000
199 #define CM_VMPU_300 0x60000000
200 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
201 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
202 #define CM_VSBSEL_220 0x00000000
203 #define CM_VSBSEL_240 0x04000000
204 #define CM_VSBSEL_260 0x08000000
205 #define CM_VSBSEL_280 0x0C000000
206 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
207 #define CM_FMSEL_388 0x00000000
208 #define CM_FMSEL_3C8 0x01000000
209 #define CM_FMSEL_3E0 0x02000000
210 #define CM_FMSEL_3E8 0x03000000
211 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
212 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
213 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
214 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
215 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
216 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
217 #define CM_C_EECS 0x00040000
218 #define CM_C_EEDI46 0x00020000
219 #define CM_C_EECK46 0x00010000
220 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
221 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
222 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
223 #define CM_EXBASEN 0x00001000 /* external bass input enable */
225 #define CM_REG_MISC_CTRL 0x18
226 #define CM_PWD 0x80000000 /* power down */
227 #define CM_RESET 0x40000000
228 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
229 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
230 #define CM_TXVX 0x08000000 /* model 037? */
231 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
232 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
233 #define CM_SPDIF48K 0x01000000 /* write */
234 #define CM_SPATUS48K 0x01000000 /* read */
235 #define CM_ENDBDAC 0x00800000 /* enable double dac */
236 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
237 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
238 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
239 #define CM_FM_EN 0x00080000 /* enable legacy FM */
240 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
241 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
242 #define CM_VIDWPDSB 0x00010000 /* model 037? */
243 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
244 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
245 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
246 #define CM_VIDWPPRT 0x00002000 /* model 037? */
247 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
248 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
249 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
250 #define CM_ENCENTER 0x00000080
251 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
252 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
253 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
254 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
255 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
256 #define CM_UPDDMA_2048 0x00000000
257 #define CM_UPDDMA_1024 0x00000004
258 #define CM_UPDDMA_512 0x00000008
259 #define CM_UPDDMA_256 0x0000000C
260 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
261 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
262 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
264 #define CM_REG_TDMA_POSITION 0x1C
265 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
266 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
269 #define CM_REG_MIXER0 0x20
270 #define CM_REG_SBVR 0x20 /* write: sb16 version */
271 #define CM_REG_DEV 0x20 /* read: hardware device version */
273 #define CM_REG_MIXER21 0x21
274 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
275 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
276 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
277 #define CM_X_SB16 0x01 /* SB16 compatible */
279 #define CM_REG_SB16_DATA 0x22
280 #define CM_REG_SB16_ADDR 0x23
282 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
283 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
284 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
285 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
287 #define CM_REG_MIXER1 0x24
288 #define CM_FMMUTE 0x80 /* mute FM */
289 #define CM_FMMUTE_SHIFT 7
290 #define CM_WSMUTE 0x40 /* mute PCM */
291 #define CM_WSMUTE_SHIFT 6
292 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
293 #define CM_REAR2LIN_SHIFT 5
294 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
295 #define CM_REAR2FRONT_SHIFT 4
296 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
297 #define CM_WAVEINL_SHIFT 3
298 #define CM_WAVEINR 0x04 /* digical wave rec. right */
299 #define CM_WAVEINR_SHIFT 2
300 #define CM_X3DEN 0x02 /* 3D surround enable */
301 #define CM_X3DEN_SHIFT 1
302 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
303 #define CM_CDPLAY_SHIFT 0
305 #define CM_REG_MIXER2 0x25
306 #define CM_RAUXREN 0x80 /* AUX right capture */
307 #define CM_RAUXREN_SHIFT 7
308 #define CM_RAUXLEN 0x40 /* AUX left capture */
309 #define CM_RAUXLEN_SHIFT 6
310 #define CM_VAUXRM 0x20 /* AUX right mute */
311 #define CM_VAUXRM_SHIFT 5
312 #define CM_VAUXLM 0x10 /* AUX left mute */
313 #define CM_VAUXLM_SHIFT 4
314 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
315 #define CM_VADMIC_SHIFT 1
316 #define CM_MICGAINZ 0x01 /* mic boost */
317 #define CM_MICGAINZ_SHIFT 0
319 #define CM_REG_MIXER3 0x24
320 #define CM_REG_AUX_VOL 0x26
321 #define CM_VAUXL_MASK 0xf0
322 #define CM_VAUXR_MASK 0x0f
324 #define CM_REG_MISC 0x27
325 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
326 #define CM_XGPO1 0x20
327 // #define CM_XGPBIO 0x04
328 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
329 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
330 #define CM_SPDVALID 0x02 /* spdif input valid check */
331 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
333 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
335 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
336 * or identical with AC97 codec?
338 #define CM_REG_EXTERN_CODEC CM_REG_AC97
341 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
343 #define CM_REG_MPU_PCI 0x40
346 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
348 #define CM_REG_FM_PCI 0x50
351 * access from SB-mixer port
353 #define CM_REG_EXTENT_IND 0xf0
354 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
355 #define CM_VPHONE_SHIFT 5
356 #define CM_VPHOM 0x10 /* Phone mute control */
357 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
358 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
359 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
360 #define CM_VADMIC3 0x01 /* Mic record boost */
363 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
364 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
367 #define CM_REG_PLL 0xf8
372 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
373 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
374 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
375 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
377 #define CM_REG_EXT_MISC 0x90
378 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
379 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
380 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
381 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
382 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
383 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
384 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
385 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
390 #define CM_EXTENT_CODEC 0x100
391 #define CM_EXTENT_MIDI 0x2
392 #define CM_EXTENT_SYNTH 0x4
396 * channels for playback / capture
402 * flags to check device open/close
404 #define CM_OPEN_NONE 0
405 #define CM_OPEN_CH_MASK 0x01
406 #define CM_OPEN_DAC 0x10
407 #define CM_OPEN_ADC 0x20
408 #define CM_OPEN_SPDIF 0x40
409 #define CM_OPEN_MCHAN 0x80
410 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
411 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
412 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
413 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
414 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
415 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
419 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
420 #define CM_PLAYBACK_SPDF CM_SPDF_1
421 #define CM_CAPTURE_SPDF CM_SPDF_0
423 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
424 #define CM_PLAYBACK_SPDF CM_SPDF_0
425 #define CM_CAPTURE_SPDF CM_SPDF_1
434 struct snd_pcm_substream
*substream
;
435 u8 running
; /* dac/adc running? */
436 u8 fmt
; /* format bits */
439 unsigned int dma_size
; /* in frames */
441 unsigned int ch
; /* channel (0/1) */
442 unsigned int offset
; /* physical address of the buffer */
445 /* mixer elements toggled/resumed during ac3 playback */
446 struct cmipci_mixer_auto_switches
{
447 const char *name
; /* switch to toggle */
448 int toggle_on
; /* value to change when ac3 mode */
450 static const struct cmipci_mixer_auto_switches cm_saved_mixer
[] = {
451 {"PCM Playback Switch", 0},
452 {"IEC958 Output Switch", 1},
453 {"IEC958 Mix Analog", 0},
454 // {"IEC958 Out To DAC", 1}, // no longer used
457 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
460 struct snd_card
*card
;
463 unsigned int device
; /* device ID */
466 unsigned long iobase
;
467 unsigned int ctrl
; /* FUNCTRL0 current value */
469 struct snd_pcm
*pcm
; /* DAC/ADC PCM */
470 struct snd_pcm
*pcm2
; /* 2nd DAC */
471 struct snd_pcm
*pcm_spdif
; /* SPDIF */
475 unsigned int can_ac3_sw
: 1;
476 unsigned int can_ac3_hw
: 1;
477 unsigned int can_multi_ch
: 1;
478 unsigned int can_96k
: 1; /* samplerate above 48k */
479 unsigned int do_soft_ac3
: 1;
481 unsigned int spdif_playback_avail
: 1; /* spdif ready? */
482 unsigned int spdif_playback_enabled
: 1; /* spdif switch enabled? */
483 int spdif_counter
; /* for software AC3 */
485 unsigned int dig_status
;
486 unsigned int dig_pcm_status
;
488 struct snd_pcm_hardware
*hw_info
[3]; /* for playbacks */
490 int opened
[2]; /* open mode */
491 struct mutex open_mutex
;
493 unsigned int mixer_insensitive
: 1;
494 struct snd_kcontrol
*mixer_res_ctl
[CM_SAVED_MIXERS
];
495 int mixer_res_status
[CM_SAVED_MIXERS
];
497 struct cmipci_pcm channel
[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
500 struct snd_rawmidi
*rmidi
;
502 #ifdef SUPPORT_JOYSTICK
503 struct gameport
*gameport
;
509 unsigned int saved_regs
[0x20];
510 unsigned char saved_mixers
[0x20];
515 /* read/write operations for dword register */
516 static inline void snd_cmipci_write(struct cmipci
*cm
, unsigned int cmd
, unsigned int data
)
518 outl(data
, cm
->iobase
+ cmd
);
521 static inline unsigned int snd_cmipci_read(struct cmipci
*cm
, unsigned int cmd
)
523 return inl(cm
->iobase
+ cmd
);
526 /* read/write operations for word register */
527 static inline void snd_cmipci_write_w(struct cmipci
*cm
, unsigned int cmd
, unsigned short data
)
529 outw(data
, cm
->iobase
+ cmd
);
532 static inline unsigned short snd_cmipci_read_w(struct cmipci
*cm
, unsigned int cmd
)
534 return inw(cm
->iobase
+ cmd
);
537 /* read/write operations for byte register */
538 static inline void snd_cmipci_write_b(struct cmipci
*cm
, unsigned int cmd
, unsigned char data
)
540 outb(data
, cm
->iobase
+ cmd
);
543 static inline unsigned char snd_cmipci_read_b(struct cmipci
*cm
, unsigned int cmd
)
545 return inb(cm
->iobase
+ cmd
);
548 /* bit operations for dword register */
549 static int snd_cmipci_set_bit(struct cmipci
*cm
, unsigned int cmd
, unsigned int flag
)
551 unsigned int val
, oval
;
552 val
= oval
= inl(cm
->iobase
+ cmd
);
556 outl(val
, cm
->iobase
+ cmd
);
560 static int snd_cmipci_clear_bit(struct cmipci
*cm
, unsigned int cmd
, unsigned int flag
)
562 unsigned int val
, oval
;
563 val
= oval
= inl(cm
->iobase
+ cmd
);
567 outl(val
, cm
->iobase
+ cmd
);
571 /* bit operations for byte register */
572 static int snd_cmipci_set_bit_b(struct cmipci
*cm
, unsigned int cmd
, unsigned char flag
)
574 unsigned char val
, oval
;
575 val
= oval
= inb(cm
->iobase
+ cmd
);
579 outb(val
, cm
->iobase
+ cmd
);
583 static int snd_cmipci_clear_bit_b(struct cmipci
*cm
, unsigned int cmd
, unsigned char flag
)
585 unsigned char val
, oval
;
586 val
= oval
= inb(cm
->iobase
+ cmd
);
590 outb(val
, cm
->iobase
+ cmd
);
600 * calculate frequency
603 static unsigned int rates
[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
605 static unsigned int snd_cmipci_rate_freq(unsigned int rate
)
609 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
610 if (rates
[i
] == rate
)
617 #ifdef USE_VAR48KRATE
619 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
620 * does it this way .. maybe not. Never get any information from C-Media about
621 * that <werner@suse.de>.
623 static int snd_cmipci_pll_rmn(unsigned int rate
, unsigned int adcmult
, int *r
, int *m
, int *n
)
625 unsigned int delta
, tolerance
;
628 for (*r
= 0; rate
< CM_MAXIMUM_RATE
/adcmult
; *r
+= (1<<5))
633 tolerance
= rate
*CM_TOLERANCE_RATE
;
635 for (xn
= (1+2); xn
< (0x1f+2); xn
++) {
636 for (xm
= (1+2); xm
< (0xff+2); xm
++) {
637 xr
= ((CM_REFFREQ_XIN
/adcmult
) * xm
) / xn
;
645 * If we found one, remember this,
646 * and try to find a closer one
648 if (delta
< tolerance
) {
660 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
661 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
662 * at the register CM_REG_FUNCTRL1 (0x04).
663 * Problem: other ways are also possible (any information about that?)
665 static void snd_cmipci_set_pll(struct cmipci
*cm
, unsigned int rate
, unsigned int slot
)
667 unsigned int reg
= CM_REG_PLL
+ slot
;
669 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
670 * for DSFC/ASFC (000 upto 111).
673 /* FIXME: Init (Do we've to set an other register first before programming?) */
675 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
676 snd_cmipci_write_b(cm
, reg
, rate
>>8);
677 snd_cmipci_write_b(cm
, reg
, rate
&0xff);
679 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
681 #endif /* USE_VAR48KRATE */
683 static int snd_cmipci_hw_params(struct snd_pcm_substream
*substream
,
684 struct snd_pcm_hw_params
*hw_params
)
686 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
689 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream
*substream
,
690 struct snd_pcm_hw_params
*hw_params
)
692 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
693 if (params_channels(hw_params
) > 2) {
694 mutex_lock(&cm
->open_mutex
);
695 if (cm
->opened
[CM_CH_PLAY
]) {
696 mutex_unlock(&cm
->open_mutex
);
699 /* reserve the channel A */
700 cm
->opened
[CM_CH_PLAY
] = CM_OPEN_PLAYBACK_MULTI
;
701 mutex_unlock(&cm
->open_mutex
);
703 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
706 static void snd_cmipci_ch_reset(struct cmipci
*cm
, int ch
)
708 int reset
= CM_RST_CH0
<< (cm
->channel
[ch
].ch
);
709 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| reset
);
710 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~reset
);
714 static int snd_cmipci_hw_free(struct snd_pcm_substream
*substream
)
716 return snd_pcm_lib_free_pages(substream
);
723 static unsigned int hw_channels
[] = {1, 2, 4, 6, 8};
724 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4
= {
729 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6
= {
734 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8
= {
740 static int set_dac_channels(struct cmipci
*cm
, struct cmipci_pcm
*rec
, int channels
)
743 if (!cm
->can_multi_ch
|| !rec
->ch
)
745 if (rec
->fmt
!= 0x03) /* stereo 16bit only */
749 if (cm
->can_multi_ch
) {
750 spin_lock_irq(&cm
->reg_lock
);
752 snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_NXCHG
);
753 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
755 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_NXCHG
);
756 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
759 snd_cmipci_set_bit(cm
, CM_REG_EXT_MISC
, CM_CHB3D8C
);
761 snd_cmipci_clear_bit(cm
, CM_REG_EXT_MISC
, CM_CHB3D8C
);
763 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
764 snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
766 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
767 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
770 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
772 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
773 spin_unlock_irq(&cm
->reg_lock
);
780 * prepare playback/capture channel
781 * channel to be used must have been set in rec->ch.
783 static int snd_cmipci_pcm_prepare(struct cmipci
*cm
, struct cmipci_pcm
*rec
,
784 struct snd_pcm_substream
*substream
)
786 unsigned int reg
, freq
, freq_ext
, val
;
787 unsigned int period_size
;
788 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
792 if (snd_pcm_format_width(runtime
->format
) >= 16) {
794 if (snd_pcm_format_width(runtime
->format
) > 16)
795 rec
->shift
++; /* 24/32bit */
797 if (runtime
->channels
> 1)
799 if (rec
->is_dac
&& set_dac_channels(cm
, rec
, runtime
->channels
) < 0) {
800 snd_printd("cannot set dac channels\n");
804 rec
->offset
= runtime
->dma_addr
;
805 /* buffer and period sizes in frame */
806 rec
->dma_size
= runtime
->buffer_size
<< rec
->shift
;
807 period_size
= runtime
->period_size
<< rec
->shift
;
808 if (runtime
->channels
> 2) {
810 rec
->dma_size
= (rec
->dma_size
* runtime
->channels
) / 2;
811 period_size
= (period_size
* runtime
->channels
) / 2;
814 spin_lock_irq(&cm
->reg_lock
);
816 /* set buffer address */
817 reg
= rec
->ch
? CM_REG_CH1_FRAME1
: CM_REG_CH0_FRAME1
;
818 snd_cmipci_write(cm
, reg
, rec
->offset
);
819 /* program sample counts */
820 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
821 snd_cmipci_write_w(cm
, reg
, rec
->dma_size
- 1);
822 snd_cmipci_write_w(cm
, reg
+ 2, period_size
- 1);
824 /* set adc/dac flag */
825 val
= rec
->ch
? CM_CHADC1
: CM_CHADC0
;
830 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
831 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
833 /* set sample rate */
836 if (runtime
->rate
> 48000)
837 switch (runtime
->rate
) {
838 case 88200: freq_ext
= CM_CH0_SRATE_88K
; break;
839 case 96000: freq_ext
= CM_CH0_SRATE_96K
; break;
840 case 128000: freq_ext
= CM_CH0_SRATE_128K
; break;
841 default: snd_BUG(); break;
844 freq
= snd_cmipci_rate_freq(runtime
->rate
);
845 val
= snd_cmipci_read(cm
, CM_REG_FUNCTRL1
);
847 val
&= ~CM_DSFC_MASK
;
848 val
|= (freq
<< CM_DSFC_SHIFT
) & CM_DSFC_MASK
;
850 val
&= ~CM_ASFC_MASK
;
851 val
|= (freq
<< CM_ASFC_SHIFT
) & CM_ASFC_MASK
;
853 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, val
);
854 //snd_printd("cmipci: functrl1 = %08x\n", val);
857 val
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
);
859 val
&= ~CM_CH1FMT_MASK
;
860 val
|= rec
->fmt
<< CM_CH1FMT_SHIFT
;
862 val
&= ~CM_CH0FMT_MASK
;
863 val
|= rec
->fmt
<< CM_CH0FMT_SHIFT
;
866 val
&= ~(CM_CH0_SRATE_MASK
<< (rec
->ch
* 2));
867 val
|= freq_ext
<< (rec
->ch
* 2);
869 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, val
);
870 //snd_printd("cmipci: chformat = %08x\n", val);
872 if (!rec
->is_dac
&& cm
->chip_version
) {
873 if (runtime
->rate
> 44100)
874 snd_cmipci_set_bit(cm
, CM_REG_EXT_MISC
, CM_ADC48K44K
);
876 snd_cmipci_clear_bit(cm
, CM_REG_EXT_MISC
, CM_ADC48K44K
);
880 spin_unlock_irq(&cm
->reg_lock
);
888 static int snd_cmipci_pcm_trigger(struct cmipci
*cm
, struct cmipci_pcm
*rec
,
891 unsigned int inthld
, chen
, reset
, pause
;
894 inthld
= CM_CH0_INT_EN
<< rec
->ch
;
895 chen
= CM_CHEN0
<< rec
->ch
;
896 reset
= CM_RST_CH0
<< rec
->ch
;
897 pause
= CM_PAUSE0
<< rec
->ch
;
899 spin_lock(&cm
->reg_lock
);
901 case SNDRV_PCM_TRIGGER_START
:
904 snd_cmipci_set_bit(cm
, CM_REG_INT_HLDCLR
, inthld
);
907 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
908 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
910 case SNDRV_PCM_TRIGGER_STOP
:
912 /* disable interrupt */
913 snd_cmipci_clear_bit(cm
, CM_REG_INT_HLDCLR
, inthld
);
916 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| reset
);
917 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~reset
);
918 rec
->needs_silencing
= rec
->is_dac
;
920 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
921 case SNDRV_PCM_TRIGGER_SUSPEND
:
923 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
925 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
926 case SNDRV_PCM_TRIGGER_RESUME
:
928 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
934 spin_unlock(&cm
->reg_lock
);
939 * return the current pointer
941 static snd_pcm_uframes_t
snd_cmipci_pcm_pointer(struct cmipci
*cm
, struct cmipci_pcm
*rec
,
942 struct snd_pcm_substream
*substream
)
948 #if 1 // this seems better..
949 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
950 ptr
= rec
->dma_size
- (snd_cmipci_read_w(cm
, reg
) + 1);
953 reg
= rec
->ch
? CM_REG_CH1_FRAME1
: CM_REG_CH0_FRAME1
;
954 ptr
= snd_cmipci_read(cm
, reg
) - rec
->offset
;
955 ptr
= bytes_to_frames(substream
->runtime
, ptr
);
957 if (substream
->runtime
->channels
> 2)
958 ptr
= (ptr
* 2) / substream
->runtime
->channels
;
966 static int snd_cmipci_playback_trigger(struct snd_pcm_substream
*substream
,
969 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
970 return snd_cmipci_pcm_trigger(cm
, &cm
->channel
[CM_CH_PLAY
], cmd
);
973 static snd_pcm_uframes_t
snd_cmipci_playback_pointer(struct snd_pcm_substream
*substream
)
975 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
976 return snd_cmipci_pcm_pointer(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
985 static int snd_cmipci_capture_trigger(struct snd_pcm_substream
*substream
,
988 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
989 return snd_cmipci_pcm_trigger(cm
, &cm
->channel
[CM_CH_CAPT
], cmd
);
992 static snd_pcm_uframes_t
snd_cmipci_capture_pointer(struct snd_pcm_substream
*substream
)
994 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
995 return snd_cmipci_pcm_pointer(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1000 * hw preparation for spdif
1003 static int snd_cmipci_spdif_default_info(struct snd_kcontrol
*kcontrol
,
1004 struct snd_ctl_elem_info
*uinfo
)
1006 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1011 static int snd_cmipci_spdif_default_get(struct snd_kcontrol
*kcontrol
,
1012 struct snd_ctl_elem_value
*ucontrol
)
1014 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1017 spin_lock_irq(&chip
->reg_lock
);
1018 for (i
= 0; i
< 4; i
++)
1019 ucontrol
->value
.iec958
.status
[i
] = (chip
->dig_status
>> (i
* 8)) & 0xff;
1020 spin_unlock_irq(&chip
->reg_lock
);
1024 static int snd_cmipci_spdif_default_put(struct snd_kcontrol
*kcontrol
,
1025 struct snd_ctl_elem_value
*ucontrol
)
1027 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1032 spin_lock_irq(&chip
->reg_lock
);
1033 for (i
= 0; i
< 4; i
++)
1034 val
|= (unsigned int)ucontrol
->value
.iec958
.status
[i
] << (i
* 8);
1035 change
= val
!= chip
->dig_status
;
1036 chip
->dig_status
= val
;
1037 spin_unlock_irq(&chip
->reg_lock
);
1041 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata
=
1043 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1044 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
1045 .info
= snd_cmipci_spdif_default_info
,
1046 .get
= snd_cmipci_spdif_default_get
,
1047 .put
= snd_cmipci_spdif_default_put
1050 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol
*kcontrol
,
1051 struct snd_ctl_elem_info
*uinfo
)
1053 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1058 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol
*kcontrol
,
1059 struct snd_ctl_elem_value
*ucontrol
)
1061 ucontrol
->value
.iec958
.status
[0] = 0xff;
1062 ucontrol
->value
.iec958
.status
[1] = 0xff;
1063 ucontrol
->value
.iec958
.status
[2] = 0xff;
1064 ucontrol
->value
.iec958
.status
[3] = 0xff;
1068 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata
=
1070 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
1071 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1072 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
1073 .info
= snd_cmipci_spdif_mask_info
,
1074 .get
= snd_cmipci_spdif_mask_get
,
1077 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol
*kcontrol
,
1078 struct snd_ctl_elem_info
*uinfo
)
1080 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1085 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol
*kcontrol
,
1086 struct snd_ctl_elem_value
*ucontrol
)
1088 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1091 spin_lock_irq(&chip
->reg_lock
);
1092 for (i
= 0; i
< 4; i
++)
1093 ucontrol
->value
.iec958
.status
[i
] = (chip
->dig_pcm_status
>> (i
* 8)) & 0xff;
1094 spin_unlock_irq(&chip
->reg_lock
);
1098 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol
*kcontrol
,
1099 struct snd_ctl_elem_value
*ucontrol
)
1101 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
1106 spin_lock_irq(&chip
->reg_lock
);
1107 for (i
= 0; i
< 4; i
++)
1108 val
|= (unsigned int)ucontrol
->value
.iec958
.status
[i
] << (i
* 8);
1109 change
= val
!= chip
->dig_pcm_status
;
1110 chip
->dig_pcm_status
= val
;
1111 spin_unlock_irq(&chip
->reg_lock
);
1115 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata
=
1117 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
1118 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1119 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
1120 .info
= snd_cmipci_spdif_stream_info
,
1121 .get
= snd_cmipci_spdif_stream_get
,
1122 .put
= snd_cmipci_spdif_stream_put
1128 /* save mixer setting and mute for AC3 playback */
1129 static int save_mixer_state(struct cmipci
*cm
)
1131 if (! cm
->mixer_insensitive
) {
1132 struct snd_ctl_elem_value
*val
;
1135 val
= kmalloc(sizeof(*val
), GFP_ATOMIC
);
1138 for (i
= 0; i
< CM_SAVED_MIXERS
; i
++) {
1139 struct snd_kcontrol
*ctl
= cm
->mixer_res_ctl
[i
];
1142 memset(val
, 0, sizeof(*val
));
1144 cm
->mixer_res_status
[i
] = val
->value
.integer
.value
[0];
1145 val
->value
.integer
.value
[0] = cm_saved_mixer
[i
].toggle_on
;
1146 event
= SNDRV_CTL_EVENT_MASK_INFO
;
1147 if (cm
->mixer_res_status
[i
] != val
->value
.integer
.value
[0]) {
1148 ctl
->put(ctl
, val
); /* toggle */
1149 event
|= SNDRV_CTL_EVENT_MASK_VALUE
;
1151 ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1152 snd_ctl_notify(cm
->card
, event
, &ctl
->id
);
1156 cm
->mixer_insensitive
= 1;
1162 /* restore the previously saved mixer status */
1163 static void restore_mixer_state(struct cmipci
*cm
)
1165 if (cm
->mixer_insensitive
) {
1166 struct snd_ctl_elem_value
*val
;
1169 val
= kmalloc(sizeof(*val
), GFP_KERNEL
);
1172 cm
->mixer_insensitive
= 0; /* at first clear this;
1173 otherwise the changes will be ignored */
1174 for (i
= 0; i
< CM_SAVED_MIXERS
; i
++) {
1175 struct snd_kcontrol
*ctl
= cm
->mixer_res_ctl
[i
];
1179 memset(val
, 0, sizeof(*val
));
1180 ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1182 event
= SNDRV_CTL_EVENT_MASK_INFO
;
1183 if (val
->value
.integer
.value
[0] != cm
->mixer_res_status
[i
]) {
1184 val
->value
.integer
.value
[0] = cm
->mixer_res_status
[i
];
1186 event
|= SNDRV_CTL_EVENT_MASK_VALUE
;
1188 snd_ctl_notify(cm
->card
, event
, &ctl
->id
);
1195 /* spinlock held! */
1196 static void setup_ac3(struct cmipci
*cm
, struct snd_pcm_substream
*subs
, int do_ac3
, int rate
)
1200 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_AC3EN1
);
1202 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_AC3EN2
);
1204 if (cm
->can_ac3_hw
) {
1205 /* SPD24SEL for 037, 0x02 */
1206 /* SPD24SEL for 039, 0x20, but cannot be set */
1207 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1208 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1209 } else { /* can_ac3_sw */
1210 /* SPD32SEL for 037 & 039, 0x20 */
1211 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1212 /* set 176K sample rate to fix 033 HW bug */
1213 if (cm
->chip_version
== 33) {
1214 if (rate
>= 48000) {
1215 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1217 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1223 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_AC3EN1
);
1224 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_AC3EN2
);
1226 if (cm
->can_ac3_hw
) {
1227 /* chip model >= 37 */
1228 if (snd_pcm_format_width(subs
->runtime
->format
) > 16) {
1229 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1230 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1232 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1233 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1236 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1237 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1238 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1243 static int setup_spdif_playback(struct cmipci
*cm
, struct snd_pcm_substream
*subs
, int up
, int do_ac3
)
1247 rate
= subs
->runtime
->rate
;
1250 if ((err
= save_mixer_state(cm
)) < 0)
1253 spin_lock_irq(&cm
->reg_lock
);
1254 cm
->spdif_playback_avail
= up
;
1256 /* they are controlled via "IEC958 Output Switch" */
1257 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1258 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1259 if (cm
->spdif_playback_enabled
)
1260 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
1261 setup_ac3(cm
, subs
, do_ac3
, rate
);
1263 if (rate
== 48000 || rate
== 96000)
1264 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
| CM_SPDF_AC97
);
1266 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
| CM_SPDF_AC97
);
1268 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1270 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1272 /* they are controlled via "IEC958 Output Switch" */
1273 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1274 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1275 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1276 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
1277 setup_ac3(cm
, subs
, 0, 0);
1279 spin_unlock_irq(&cm
->reg_lock
);
1288 /* playback - enable spdif only on the certain condition */
1289 static int snd_cmipci_playback_prepare(struct snd_pcm_substream
*substream
)
1291 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1292 int rate
= substream
->runtime
->rate
;
1293 int err
, do_spdif
, do_ac3
= 0;
1295 do_spdif
= (rate
>= 44100 && rate
<= 96000 &&
1296 substream
->runtime
->format
== SNDRV_PCM_FORMAT_S16_LE
&&
1297 substream
->runtime
->channels
== 2);
1298 if (do_spdif
&& cm
->can_ac3_hw
)
1299 do_ac3
= cm
->dig_pcm_status
& IEC958_AES0_NONAUDIO
;
1300 if ((err
= setup_spdif_playback(cm
, substream
, do_spdif
, do_ac3
)) < 0)
1302 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
1305 /* playback (via device #2) - enable spdif always */
1306 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream
*substream
)
1308 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1312 do_ac3
= cm
->dig_pcm_status
& IEC958_AES0_NONAUDIO
;
1314 do_ac3
= 1; /* doesn't matter */
1315 if ((err
= setup_spdif_playback(cm
, substream
, 1, do_ac3
)) < 0)
1317 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
1321 * Apparently, the samples last played on channel A stay in some buffer, even
1322 * after the channel is reset, and get added to the data for the rear DACs when
1323 * playing a multichannel stream on channel B. This is likely to generate
1324 * wraparounds and thus distortions.
1325 * To avoid this, we play at least one zero sample after the actual stream has
1328 static void snd_cmipci_silence_hack(struct cmipci
*cm
, struct cmipci_pcm
*rec
)
1330 struct snd_pcm_runtime
*runtime
= rec
->substream
->runtime
;
1331 unsigned int reg
, val
;
1333 if (rec
->needs_silencing
&& runtime
&& runtime
->dma_area
) {
1334 /* set up a small silence buffer */
1335 memset(runtime
->dma_area
, 0, PAGE_SIZE
);
1336 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
1337 val
= ((PAGE_SIZE
/ 4) - 1) | (((PAGE_SIZE
/ 4) / 2 - 1) << 16);
1338 snd_cmipci_write(cm
, reg
, val
);
1340 /* configure for 16 bits, 2 channels, 8 kHz */
1341 if (runtime
->channels
> 2)
1342 set_dac_channels(cm
, rec
, 2);
1343 spin_lock_irq(&cm
->reg_lock
);
1344 val
= snd_cmipci_read(cm
, CM_REG_FUNCTRL1
);
1345 val
&= ~(CM_ASFC_MASK
<< (rec
->ch
* 3));
1346 val
|= (4 << CM_ASFC_SHIFT
) << (rec
->ch
* 3);
1347 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, val
);
1348 val
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
);
1349 val
&= ~(CM_CH0FMT_MASK
<< (rec
->ch
* 2));
1350 val
|= (3 << CM_CH0FMT_SHIFT
) << (rec
->ch
* 2);
1352 val
&= ~(CM_CH0_SRATE_MASK
<< (rec
->ch
* 2));
1353 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, val
);
1355 /* start stream (we don't need interrupts) */
1356 cm
->ctrl
|= CM_CHEN0
<< rec
->ch
;
1357 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
1358 spin_unlock_irq(&cm
->reg_lock
);
1362 /* stop and reset stream */
1363 spin_lock_irq(&cm
->reg_lock
);
1364 cm
->ctrl
&= ~(CM_CHEN0
<< rec
->ch
);
1365 val
= CM_RST_CH0
<< rec
->ch
;
1366 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| val
);
1367 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~val
);
1368 spin_unlock_irq(&cm
->reg_lock
);
1370 rec
->needs_silencing
= 0;
1374 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream
*substream
)
1376 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1377 setup_spdif_playback(cm
, substream
, 0, 0);
1378 restore_mixer_state(cm
);
1379 snd_cmipci_silence_hack(cm
, &cm
->channel
[0]);
1380 return snd_cmipci_hw_free(substream
);
1383 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream
*substream
)
1385 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1386 snd_cmipci_silence_hack(cm
, &cm
->channel
[1]);
1387 return snd_cmipci_hw_free(substream
);
1391 static int snd_cmipci_capture_prepare(struct snd_pcm_substream
*substream
)
1393 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1394 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1397 /* capture with spdif (via device #2) */
1398 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream
*substream
)
1400 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1402 spin_lock_irq(&cm
->reg_lock
);
1403 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_CAPTURE_SPDF
);
1405 if (substream
->runtime
->rate
> 48000)
1406 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1408 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_DBLSPDS
);
1410 if (snd_pcm_format_width(substream
->runtime
->format
) > 16)
1411 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1413 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1415 spin_unlock_irq(&cm
->reg_lock
);
1417 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1420 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream
*subs
)
1422 struct cmipci
*cm
= snd_pcm_substream_chip(subs
);
1424 spin_lock_irq(&cm
->reg_lock
);
1425 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_CAPTURE_SPDF
);
1426 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1427 spin_unlock_irq(&cm
->reg_lock
);
1429 return snd_cmipci_hw_free(subs
);
1436 static irqreturn_t
snd_cmipci_interrupt(int irq
, void *dev_id
)
1438 struct cmipci
*cm
= dev_id
;
1439 unsigned int status
, mask
= 0;
1441 /* fastpath out, to ease interrupt sharing */
1442 status
= snd_cmipci_read(cm
, CM_REG_INT_STATUS
);
1443 if (!(status
& CM_INTR
))
1446 /* acknowledge interrupt */
1447 spin_lock(&cm
->reg_lock
);
1448 if (status
& CM_CHINT0
)
1449 mask
|= CM_CH0_INT_EN
;
1450 if (status
& CM_CHINT1
)
1451 mask
|= CM_CH1_INT_EN
;
1452 snd_cmipci_clear_bit(cm
, CM_REG_INT_HLDCLR
, mask
);
1453 snd_cmipci_set_bit(cm
, CM_REG_INT_HLDCLR
, mask
);
1454 spin_unlock(&cm
->reg_lock
);
1456 if (cm
->rmidi
&& (status
& CM_UARTINT
))
1457 snd_mpu401_uart_interrupt(irq
, cm
->rmidi
->private_data
);
1460 if ((status
& CM_CHINT0
) && cm
->channel
[0].running
)
1461 snd_pcm_period_elapsed(cm
->channel
[0].substream
);
1462 if ((status
& CM_CHINT1
) && cm
->channel
[1].running
)
1463 snd_pcm_period_elapsed(cm
->channel
[1].substream
);
1472 /* playback on channel A */
1473 static struct snd_pcm_hardware snd_cmipci_playback
=
1475 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1476 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1477 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1478 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1479 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1484 .buffer_bytes_max
= (128*1024),
1485 .period_bytes_min
= 64,
1486 .period_bytes_max
= (128*1024),
1488 .periods_max
= 1024,
1492 /* capture on channel B */
1493 static struct snd_pcm_hardware snd_cmipci_capture
=
1495 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1496 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1497 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1498 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1499 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1504 .buffer_bytes_max
= (128*1024),
1505 .period_bytes_min
= 64,
1506 .period_bytes_max
= (128*1024),
1508 .periods_max
= 1024,
1512 /* playback on channel B - stereo 16bit only? */
1513 static struct snd_pcm_hardware snd_cmipci_playback2
=
1515 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1516 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1517 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1518 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1519 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1524 .buffer_bytes_max
= (128*1024),
1525 .period_bytes_min
= 64,
1526 .period_bytes_max
= (128*1024),
1528 .periods_max
= 1024,
1532 /* spdif playback on channel A */
1533 static struct snd_pcm_hardware snd_cmipci_playback_spdif
=
1535 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1536 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1537 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1538 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1539 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1544 .buffer_bytes_max
= (128*1024),
1545 .period_bytes_min
= 64,
1546 .period_bytes_max
= (128*1024),
1548 .periods_max
= 1024,
1552 /* spdif playback on channel A (32bit, IEC958 subframes) */
1553 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe
=
1555 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1556 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1557 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1558 .formats
= SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
,
1559 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1564 .buffer_bytes_max
= (128*1024),
1565 .period_bytes_min
= 64,
1566 .period_bytes_max
= (128*1024),
1568 .periods_max
= 1024,
1572 /* spdif capture on channel B */
1573 static struct snd_pcm_hardware snd_cmipci_capture_spdif
=
1575 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1576 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1577 SNDRV_PCM_INFO_RESUME
| SNDRV_PCM_INFO_MMAP_VALID
),
1578 .formats
= SNDRV_PCM_FMTBIT_S16_LE
|
1579 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
,
1580 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1585 .buffer_bytes_max
= (128*1024),
1586 .period_bytes_min
= 64,
1587 .period_bytes_max
= (128*1024),
1589 .periods_max
= 1024,
1593 static unsigned int rate_constraints
[] = { 5512, 8000, 11025, 16000, 22050,
1594 32000, 44100, 48000, 88200, 96000, 128000 };
1595 static struct snd_pcm_hw_constraint_list hw_constraints_rates
= {
1596 .count
= ARRAY_SIZE(rate_constraints
),
1597 .list
= rate_constraints
,
1602 * check device open/close
1604 static int open_device_check(struct cmipci
*cm
, int mode
, struct snd_pcm_substream
*subs
)
1606 int ch
= mode
& CM_OPEN_CH_MASK
;
1608 /* FIXME: a file should wait until the device becomes free
1609 * when it's opened on blocking mode. however, since the current
1610 * pcm framework doesn't pass file pointer before actually opened,
1611 * we can't know whether blocking mode or not in open callback..
1613 mutex_lock(&cm
->open_mutex
);
1614 if (cm
->opened
[ch
]) {
1615 mutex_unlock(&cm
->open_mutex
);
1618 cm
->opened
[ch
] = mode
;
1619 cm
->channel
[ch
].substream
= subs
;
1620 if (! (mode
& CM_OPEN_DAC
)) {
1621 /* disable dual DAC mode */
1622 cm
->channel
[ch
].is_dac
= 0;
1623 spin_lock_irq(&cm
->reg_lock
);
1624 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
);
1625 spin_unlock_irq(&cm
->reg_lock
);
1627 mutex_unlock(&cm
->open_mutex
);
1631 static void close_device_check(struct cmipci
*cm
, int mode
)
1633 int ch
= mode
& CM_OPEN_CH_MASK
;
1635 mutex_lock(&cm
->open_mutex
);
1636 if (cm
->opened
[ch
] == mode
) {
1637 if (cm
->channel
[ch
].substream
) {
1638 snd_cmipci_ch_reset(cm
, ch
);
1639 cm
->channel
[ch
].running
= 0;
1640 cm
->channel
[ch
].substream
= NULL
;
1643 if (! cm
->channel
[ch
].is_dac
) {
1644 /* enable dual DAC mode again */
1645 cm
->channel
[ch
].is_dac
= 1;
1646 spin_lock_irq(&cm
->reg_lock
);
1647 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
);
1648 spin_unlock_irq(&cm
->reg_lock
);
1651 mutex_unlock(&cm
->open_mutex
);
1657 static int snd_cmipci_playback_open(struct snd_pcm_substream
*substream
)
1659 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1660 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1663 if ((err
= open_device_check(cm
, CM_OPEN_PLAYBACK
, substream
)) < 0)
1665 runtime
->hw
= snd_cmipci_playback
;
1666 if (cm
->chip_version
== 68) {
1667 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1668 SNDRV_PCM_RATE_96000
;
1669 runtime
->hw
.rate_max
= 96000;
1670 } else if (cm
->chip_version
== 55) {
1671 err
= snd_pcm_hw_constraint_list(runtime
, 0,
1672 SNDRV_PCM_HW_PARAM_RATE
, &hw_constraints_rates
);
1675 runtime
->hw
.rates
|= SNDRV_PCM_RATE_KNOT
;
1676 runtime
->hw
.rate_max
= 128000;
1678 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1679 cm
->dig_pcm_status
= cm
->dig_status
;
1683 static int snd_cmipci_capture_open(struct snd_pcm_substream
*substream
)
1685 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1686 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1689 if ((err
= open_device_check(cm
, CM_OPEN_CAPTURE
, substream
)) < 0)
1691 runtime
->hw
= snd_cmipci_capture
;
1692 if (cm
->chip_version
== 68) { // 8768 only supports 44k/48k recording
1693 runtime
->hw
.rate_min
= 41000;
1694 runtime
->hw
.rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
;
1695 } else if (cm
->chip_version
== 55) {
1696 err
= snd_pcm_hw_constraint_list(runtime
, 0,
1697 SNDRV_PCM_HW_PARAM_RATE
, &hw_constraints_rates
);
1700 runtime
->hw
.rates
|= SNDRV_PCM_RATE_KNOT
;
1701 runtime
->hw
.rate_max
= 128000;
1703 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1707 static int snd_cmipci_playback2_open(struct snd_pcm_substream
*substream
)
1709 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1710 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1713 if ((err
= open_device_check(cm
, CM_OPEN_PLAYBACK2
, substream
)) < 0) /* use channel B */
1715 runtime
->hw
= snd_cmipci_playback2
;
1716 mutex_lock(&cm
->open_mutex
);
1717 if (! cm
->opened
[CM_CH_PLAY
]) {
1718 if (cm
->can_multi_ch
) {
1719 runtime
->hw
.channels_max
= cm
->max_channels
;
1720 if (cm
->max_channels
== 4)
1721 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_4
);
1722 else if (cm
->max_channels
== 6)
1723 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_6
);
1724 else if (cm
->max_channels
== 8)
1725 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_8
);
1728 mutex_unlock(&cm
->open_mutex
);
1729 if (cm
->chip_version
== 68) {
1730 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1731 SNDRV_PCM_RATE_96000
;
1732 runtime
->hw
.rate_max
= 96000;
1733 } else if (cm
->chip_version
== 55) {
1734 err
= snd_pcm_hw_constraint_list(runtime
, 0,
1735 SNDRV_PCM_HW_PARAM_RATE
, &hw_constraints_rates
);
1738 runtime
->hw
.rates
|= SNDRV_PCM_RATE_KNOT
;
1739 runtime
->hw
.rate_max
= 128000;
1741 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1745 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream
*substream
)
1747 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1748 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1751 if ((err
= open_device_check(cm
, CM_OPEN_SPDIF_PLAYBACK
, substream
)) < 0) /* use channel A */
1753 if (cm
->can_ac3_hw
) {
1754 runtime
->hw
= snd_cmipci_playback_spdif
;
1755 if (cm
->chip_version
>= 37) {
1756 runtime
->hw
.formats
|= SNDRV_PCM_FMTBIT_S32_LE
;
1757 snd_pcm_hw_constraint_msbits(runtime
, 0, 32, 24);
1760 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1761 SNDRV_PCM_RATE_96000
;
1762 runtime
->hw
.rate_max
= 96000;
1765 runtime
->hw
= snd_cmipci_playback_iec958_subframe
;
1767 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x40000);
1768 cm
->dig_pcm_status
= cm
->dig_status
;
1772 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream
*substream
)
1774 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1775 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1778 if ((err
= open_device_check(cm
, CM_OPEN_SPDIF_CAPTURE
, substream
)) < 0) /* use channel B */
1780 runtime
->hw
= snd_cmipci_capture_spdif
;
1781 if (cm
->can_96k
&& !(cm
->chip_version
== 68)) {
1782 runtime
->hw
.rates
|= SNDRV_PCM_RATE_88200
|
1783 SNDRV_PCM_RATE_96000
;
1784 runtime
->hw
.rate_max
= 96000;
1786 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x40000);
1794 static int snd_cmipci_playback_close(struct snd_pcm_substream
*substream
)
1796 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1797 close_device_check(cm
, CM_OPEN_PLAYBACK
);
1801 static int snd_cmipci_capture_close(struct snd_pcm_substream
*substream
)
1803 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1804 close_device_check(cm
, CM_OPEN_CAPTURE
);
1808 static int snd_cmipci_playback2_close(struct snd_pcm_substream
*substream
)
1810 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1811 close_device_check(cm
, CM_OPEN_PLAYBACK2
);
1812 close_device_check(cm
, CM_OPEN_PLAYBACK_MULTI
);
1816 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream
*substream
)
1818 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1819 close_device_check(cm
, CM_OPEN_SPDIF_PLAYBACK
);
1823 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream
*substream
)
1825 struct cmipci
*cm
= snd_pcm_substream_chip(substream
);
1826 close_device_check(cm
, CM_OPEN_SPDIF_CAPTURE
);
1834 static struct snd_pcm_ops snd_cmipci_playback_ops
= {
1835 .open
= snd_cmipci_playback_open
,
1836 .close
= snd_cmipci_playback_close
,
1837 .ioctl
= snd_pcm_lib_ioctl
,
1838 .hw_params
= snd_cmipci_hw_params
,
1839 .hw_free
= snd_cmipci_playback_hw_free
,
1840 .prepare
= snd_cmipci_playback_prepare
,
1841 .trigger
= snd_cmipci_playback_trigger
,
1842 .pointer
= snd_cmipci_playback_pointer
,
1845 static struct snd_pcm_ops snd_cmipci_capture_ops
= {
1846 .open
= snd_cmipci_capture_open
,
1847 .close
= snd_cmipci_capture_close
,
1848 .ioctl
= snd_pcm_lib_ioctl
,
1849 .hw_params
= snd_cmipci_hw_params
,
1850 .hw_free
= snd_cmipci_hw_free
,
1851 .prepare
= snd_cmipci_capture_prepare
,
1852 .trigger
= snd_cmipci_capture_trigger
,
1853 .pointer
= snd_cmipci_capture_pointer
,
1856 static struct snd_pcm_ops snd_cmipci_playback2_ops
= {
1857 .open
= snd_cmipci_playback2_open
,
1858 .close
= snd_cmipci_playback2_close
,
1859 .ioctl
= snd_pcm_lib_ioctl
,
1860 .hw_params
= snd_cmipci_playback2_hw_params
,
1861 .hw_free
= snd_cmipci_playback2_hw_free
,
1862 .prepare
= snd_cmipci_capture_prepare
, /* channel B */
1863 .trigger
= snd_cmipci_capture_trigger
, /* channel B */
1864 .pointer
= snd_cmipci_capture_pointer
, /* channel B */
1867 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops
= {
1868 .open
= snd_cmipci_playback_spdif_open
,
1869 .close
= snd_cmipci_playback_spdif_close
,
1870 .ioctl
= snd_pcm_lib_ioctl
,
1871 .hw_params
= snd_cmipci_hw_params
,
1872 .hw_free
= snd_cmipci_playback_hw_free
,
1873 .prepare
= snd_cmipci_playback_spdif_prepare
, /* set up rate */
1874 .trigger
= snd_cmipci_playback_trigger
,
1875 .pointer
= snd_cmipci_playback_pointer
,
1878 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops
= {
1879 .open
= snd_cmipci_capture_spdif_open
,
1880 .close
= snd_cmipci_capture_spdif_close
,
1881 .ioctl
= snd_pcm_lib_ioctl
,
1882 .hw_params
= snd_cmipci_hw_params
,
1883 .hw_free
= snd_cmipci_capture_spdif_hw_free
,
1884 .prepare
= snd_cmipci_capture_spdif_prepare
,
1885 .trigger
= snd_cmipci_capture_trigger
,
1886 .pointer
= snd_cmipci_capture_pointer
,
1893 static int __devinit
snd_cmipci_pcm_new(struct cmipci
*cm
, int device
)
1895 struct snd_pcm
*pcm
;
1898 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 1, &pcm
);
1902 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback_ops
);
1903 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cmipci_capture_ops
);
1905 pcm
->private_data
= cm
;
1906 pcm
->info_flags
= 0;
1907 strcpy(pcm
->name
, "C-Media PCI DAC/ADC");
1910 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1911 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1916 static int __devinit
snd_cmipci_pcm2_new(struct cmipci
*cm
, int device
)
1918 struct snd_pcm
*pcm
;
1921 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 0, &pcm
);
1925 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback2_ops
);
1927 pcm
->private_data
= cm
;
1928 pcm
->info_flags
= 0;
1929 strcpy(pcm
->name
, "C-Media PCI 2nd DAC");
1932 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1933 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1938 static int __devinit
snd_cmipci_pcm_spdif_new(struct cmipci
*cm
, int device
)
1940 struct snd_pcm
*pcm
;
1943 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 1, &pcm
);
1947 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback_spdif_ops
);
1948 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cmipci_capture_spdif_ops
);
1950 pcm
->private_data
= cm
;
1951 pcm
->info_flags
= 0;
1952 strcpy(pcm
->name
, "C-Media PCI IEC958");
1953 cm
->pcm_spdif
= pcm
;
1955 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1956 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1963 * - CM8338/8738 has a compatible mixer interface with SB16, but
1964 * lack of some elements like tone control, i/o gain and AGC.
1965 * - Access to native registers:
1967 * - Output mute switches
1970 static void snd_cmipci_mixer_write(struct cmipci
*s
, unsigned char idx
, unsigned char data
)
1972 outb(idx
, s
->iobase
+ CM_REG_SB16_ADDR
);
1973 outb(data
, s
->iobase
+ CM_REG_SB16_DATA
);
1976 static unsigned char snd_cmipci_mixer_read(struct cmipci
*s
, unsigned char idx
)
1980 outb(idx
, s
->iobase
+ CM_REG_SB16_ADDR
);
1981 v
= inb(s
->iobase
+ CM_REG_SB16_DATA
);
1986 * general mixer element
1988 struct cmipci_sb_reg
{
1989 unsigned int left_reg
, right_reg
;
1990 unsigned int left_shift
, right_shift
;
1992 unsigned int invert
: 1;
1993 unsigned int stereo
: 1;
1996 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1997 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1999 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2000 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2001 .info = snd_cmipci_info_volume, \
2002 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2003 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2006 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2007 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2008 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2009 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2011 static void cmipci_sb_reg_decode(struct cmipci_sb_reg
*r
, unsigned long val
)
2013 r
->left_reg
= val
& 0xff;
2014 r
->right_reg
= (val
>> 8) & 0xff;
2015 r
->left_shift
= (val
>> 16) & 0x07;
2016 r
->right_shift
= (val
>> 19) & 0x07;
2017 r
->invert
= (val
>> 22) & 1;
2018 r
->stereo
= (val
>> 23) & 1;
2019 r
->mask
= (val
>> 24) & 0xff;
2022 static int snd_cmipci_info_volume(struct snd_kcontrol
*kcontrol
,
2023 struct snd_ctl_elem_info
*uinfo
)
2025 struct cmipci_sb_reg reg
;
2027 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2028 uinfo
->type
= reg
.mask
== 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
2029 uinfo
->count
= reg
.stereo
+ 1;
2030 uinfo
->value
.integer
.min
= 0;
2031 uinfo
->value
.integer
.max
= reg
.mask
;
2035 static int snd_cmipci_get_volume(struct snd_kcontrol
*kcontrol
,
2036 struct snd_ctl_elem_value
*ucontrol
)
2038 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2039 struct cmipci_sb_reg reg
;
2042 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2043 spin_lock_irq(&cm
->reg_lock
);
2044 val
= (snd_cmipci_mixer_read(cm
, reg
.left_reg
) >> reg
.left_shift
) & reg
.mask
;
2046 val
= reg
.mask
- val
;
2047 ucontrol
->value
.integer
.value
[0] = val
;
2049 val
= (snd_cmipci_mixer_read(cm
, reg
.right_reg
) >> reg
.right_shift
) & reg
.mask
;
2051 val
= reg
.mask
- val
;
2052 ucontrol
->value
.integer
.value
[1] = val
;
2054 spin_unlock_irq(&cm
->reg_lock
);
2058 static int snd_cmipci_put_volume(struct snd_kcontrol
*kcontrol
,
2059 struct snd_ctl_elem_value
*ucontrol
)
2061 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2062 struct cmipci_sb_reg reg
;
2064 int left
, right
, oleft
, oright
;
2066 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2067 left
= ucontrol
->value
.integer
.value
[0] & reg
.mask
;
2069 left
= reg
.mask
- left
;
2070 left
<<= reg
.left_shift
;
2072 right
= ucontrol
->value
.integer
.value
[1] & reg
.mask
;
2074 right
= reg
.mask
- right
;
2075 right
<<= reg
.right_shift
;
2078 spin_lock_irq(&cm
->reg_lock
);
2079 oleft
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
2080 left
|= oleft
& ~(reg
.mask
<< reg
.left_shift
);
2081 change
= left
!= oleft
;
2083 if (reg
.left_reg
!= reg
.right_reg
) {
2084 snd_cmipci_mixer_write(cm
, reg
.left_reg
, left
);
2085 oright
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
2088 right
|= oright
& ~(reg
.mask
<< reg
.right_shift
);
2089 change
|= right
!= oright
;
2090 snd_cmipci_mixer_write(cm
, reg
.right_reg
, right
);
2092 snd_cmipci_mixer_write(cm
, reg
.left_reg
, left
);
2093 spin_unlock_irq(&cm
->reg_lock
);
2098 * input route (left,right) -> (left,right)
2100 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2102 .info = snd_cmipci_info_input_sw, \
2103 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2104 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2107 static int snd_cmipci_info_input_sw(struct snd_kcontrol
*kcontrol
,
2108 struct snd_ctl_elem_info
*uinfo
)
2110 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
2112 uinfo
->value
.integer
.min
= 0;
2113 uinfo
->value
.integer
.max
= 1;
2117 static int snd_cmipci_get_input_sw(struct snd_kcontrol
*kcontrol
,
2118 struct snd_ctl_elem_value
*ucontrol
)
2120 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2121 struct cmipci_sb_reg reg
;
2124 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2125 spin_lock_irq(&cm
->reg_lock
);
2126 val1
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
2127 val2
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
2128 spin_unlock_irq(&cm
->reg_lock
);
2129 ucontrol
->value
.integer
.value
[0] = (val1
>> reg
.left_shift
) & 1;
2130 ucontrol
->value
.integer
.value
[1] = (val2
>> reg
.left_shift
) & 1;
2131 ucontrol
->value
.integer
.value
[2] = (val1
>> reg
.right_shift
) & 1;
2132 ucontrol
->value
.integer
.value
[3] = (val2
>> reg
.right_shift
) & 1;
2136 static int snd_cmipci_put_input_sw(struct snd_kcontrol
*kcontrol
,
2137 struct snd_ctl_elem_value
*ucontrol
)
2139 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2140 struct cmipci_sb_reg reg
;
2142 int val1
, val2
, oval1
, oval2
;
2144 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2145 spin_lock_irq(&cm
->reg_lock
);
2146 oval1
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
2147 oval2
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
2148 val1
= oval1
& ~((1 << reg
.left_shift
) | (1 << reg
.right_shift
));
2149 val2
= oval2
& ~((1 << reg
.left_shift
) | (1 << reg
.right_shift
));
2150 val1
|= (ucontrol
->value
.integer
.value
[0] & 1) << reg
.left_shift
;
2151 val2
|= (ucontrol
->value
.integer
.value
[1] & 1) << reg
.left_shift
;
2152 val1
|= (ucontrol
->value
.integer
.value
[2] & 1) << reg
.right_shift
;
2153 val2
|= (ucontrol
->value
.integer
.value
[3] & 1) << reg
.right_shift
;
2154 change
= val1
!= oval1
|| val2
!= oval2
;
2155 snd_cmipci_mixer_write(cm
, reg
.left_reg
, val1
);
2156 snd_cmipci_mixer_write(cm
, reg
.right_reg
, val2
);
2157 spin_unlock_irq(&cm
->reg_lock
);
2162 * native mixer switches/volumes
2165 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2166 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167 .info = snd_cmipci_info_native_mixer, \
2168 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2172 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2173 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2174 .info = snd_cmipci_info_native_mixer, \
2175 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2176 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2179 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2180 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2181 .info = snd_cmipci_info_native_mixer, \
2182 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2183 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2186 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2187 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2188 .info = snd_cmipci_info_native_mixer, \
2189 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2190 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2193 static int snd_cmipci_info_native_mixer(struct snd_kcontrol
*kcontrol
,
2194 struct snd_ctl_elem_info
*uinfo
)
2196 struct cmipci_sb_reg reg
;
2198 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2199 uinfo
->type
= reg
.mask
== 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
2200 uinfo
->count
= reg
.stereo
+ 1;
2201 uinfo
->value
.integer
.min
= 0;
2202 uinfo
->value
.integer
.max
= reg
.mask
;
2207 static int snd_cmipci_get_native_mixer(struct snd_kcontrol
*kcontrol
,
2208 struct snd_ctl_elem_value
*ucontrol
)
2210 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2211 struct cmipci_sb_reg reg
;
2212 unsigned char oreg
, val
;
2214 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2215 spin_lock_irq(&cm
->reg_lock
);
2216 oreg
= inb(cm
->iobase
+ reg
.left_reg
);
2217 val
= (oreg
>> reg
.left_shift
) & reg
.mask
;
2219 val
= reg
.mask
- val
;
2220 ucontrol
->value
.integer
.value
[0] = val
;
2222 val
= (oreg
>> reg
.right_shift
) & reg
.mask
;
2224 val
= reg
.mask
- val
;
2225 ucontrol
->value
.integer
.value
[1] = val
;
2227 spin_unlock_irq(&cm
->reg_lock
);
2231 static int snd_cmipci_put_native_mixer(struct snd_kcontrol
*kcontrol
,
2232 struct snd_ctl_elem_value
*ucontrol
)
2234 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2235 struct cmipci_sb_reg reg
;
2236 unsigned char oreg
, nreg
, val
;
2238 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2239 spin_lock_irq(&cm
->reg_lock
);
2240 oreg
= inb(cm
->iobase
+ reg
.left_reg
);
2241 val
= ucontrol
->value
.integer
.value
[0] & reg
.mask
;
2243 val
= reg
.mask
- val
;
2244 nreg
= oreg
& ~(reg
.mask
<< reg
.left_shift
);
2245 nreg
|= (val
<< reg
.left_shift
);
2247 val
= ucontrol
->value
.integer
.value
[1] & reg
.mask
;
2249 val
= reg
.mask
- val
;
2250 nreg
&= ~(reg
.mask
<< reg
.right_shift
);
2251 nreg
|= (val
<< reg
.right_shift
);
2253 outb(nreg
, cm
->iobase
+ reg
.left_reg
);
2254 spin_unlock_irq(&cm
->reg_lock
);
2255 return (nreg
!= oreg
);
2259 * special case - check mixer sensitivity
2261 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol
*kcontrol
,
2262 struct snd_ctl_elem_value
*ucontrol
)
2264 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2265 return snd_cmipci_get_native_mixer(kcontrol
, ucontrol
);
2268 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol
*kcontrol
,
2269 struct snd_ctl_elem_value
*ucontrol
)
2271 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2272 if (cm
->mixer_insensitive
) {
2276 return snd_cmipci_put_native_mixer(kcontrol
, ucontrol
);
2280 static struct snd_kcontrol_new snd_cmipci_mixers
[] __devinitdata
= {
2281 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV
, 3, 31),
2282 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1
, CM_X3DEN_SHIFT
, 0),
2283 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV
, 3, 31),
2284 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2285 { /* switch with sensitivity */
2286 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2287 .name
= "PCM Playback Switch",
2288 .info
= snd_cmipci_info_native_mixer
,
2289 .get
= snd_cmipci_get_native_mixer_sensitive
,
2290 .put
= snd_cmipci_put_native_mixer_sensitive
,
2291 .private_value
= COMPOSE_SB_REG(CM_REG_MIXER1
, CM_REG_MIXER1
, CM_WSMUTE_SHIFT
, CM_WSMUTE_SHIFT
, 1, 1, 0),
2293 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1
, CM_WAVEINL_SHIFT
, CM_WAVEINR_SHIFT
, 0),
2294 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV
, 3, 31),
2295 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1
, CM_FMMUTE_SHIFT
, 1),
2296 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2297 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV
, 3, 31),
2298 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2299 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2300 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV
, 3, 31),
2301 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2302 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2303 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV
, 3, 31),
2304 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2305 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT
, SB_DSP4_INPUT_RIGHT
, 0, 0, 1, 0, 0),
2306 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV
, 6, 3),
2307 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL
, 4, 0, 15),
2308 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2
, CM_VAUXLM_SHIFT
, CM_VAUXRM_SHIFT
, 0),
2309 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2
, CM_RAUXLEN_SHIFT
, CM_RAUXREN_SHIFT
, 0),
2310 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2
, CM_MICGAINZ_SHIFT
, 1),
2311 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2
, CM_VADMIC_SHIFT
, 7),
2312 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND
, 5, 7),
2313 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 4, 4, 1, 0, 0),
2314 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 3, 3, 1, 0, 0),
2315 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 0, 0, 1, 0, 0),
2322 struct cmipci_switch_args
{
2323 int reg
; /* register index */
2324 unsigned int mask
; /* mask bits */
2325 unsigned int mask_on
; /* mask bits to turn on */
2326 unsigned int is_byte
: 1; /* byte access? */
2327 unsigned int ac3_sensitive
: 1; /* access forbidden during
2328 * non-audio operation?
2332 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2334 static int _snd_cmipci_uswitch_get(struct snd_kcontrol
*kcontrol
,
2335 struct snd_ctl_elem_value
*ucontrol
,
2336 struct cmipci_switch_args
*args
)
2339 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2341 spin_lock_irq(&cm
->reg_lock
);
2342 if (args
->ac3_sensitive
&& cm
->mixer_insensitive
) {
2343 ucontrol
->value
.integer
.value
[0] = 0;
2344 spin_unlock_irq(&cm
->reg_lock
);
2348 val
= inb(cm
->iobase
+ args
->reg
);
2350 val
= snd_cmipci_read(cm
, args
->reg
);
2351 ucontrol
->value
.integer
.value
[0] = ((val
& args
->mask
) == args
->mask_on
) ? 1 : 0;
2352 spin_unlock_irq(&cm
->reg_lock
);
2356 static int snd_cmipci_uswitch_get(struct snd_kcontrol
*kcontrol
,
2357 struct snd_ctl_elem_value
*ucontrol
)
2359 struct cmipci_switch_args
*args
;
2360 args
= (struct cmipci_switch_args
*)kcontrol
->private_value
;
2361 snd_assert(args
!= NULL
, return -EINVAL
);
2362 return _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, args
);
2365 static int _snd_cmipci_uswitch_put(struct snd_kcontrol
*kcontrol
,
2366 struct snd_ctl_elem_value
*ucontrol
,
2367 struct cmipci_switch_args
*args
)
2371 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2373 spin_lock_irq(&cm
->reg_lock
);
2374 if (args
->ac3_sensitive
&& cm
->mixer_insensitive
) {
2376 spin_unlock_irq(&cm
->reg_lock
);
2380 val
= inb(cm
->iobase
+ args
->reg
);
2382 val
= snd_cmipci_read(cm
, args
->reg
);
2383 change
= (val
& args
->mask
) != (ucontrol
->value
.integer
.value
[0] ?
2384 args
->mask_on
: (args
->mask
& ~args
->mask_on
));
2387 if (ucontrol
->value
.integer
.value
[0])
2388 val
|= args
->mask_on
;
2390 val
|= (args
->mask
& ~args
->mask_on
);
2392 outb((unsigned char)val
, cm
->iobase
+ args
->reg
);
2394 snd_cmipci_write(cm
, args
->reg
, val
);
2396 spin_unlock_irq(&cm
->reg_lock
);
2400 static int snd_cmipci_uswitch_put(struct snd_kcontrol
*kcontrol
,
2401 struct snd_ctl_elem_value
*ucontrol
)
2403 struct cmipci_switch_args
*args
;
2404 args
= (struct cmipci_switch_args
*)kcontrol
->private_value
;
2405 snd_assert(args
!= NULL
, return -EINVAL
);
2406 return _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, args
);
2409 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2410 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2413 .mask_on = xmask_on, \
2414 .is_byte = xis_byte, \
2415 .ac3_sensitive = xac3, \
2418 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2419 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2421 #if 0 /* these will be controlled in pcm device */
2422 DEFINE_BIT_SWITCH_ARG(spdif_in
, CM_REG_FUNCTRL1
, CM_SPDF_1
, 0, 0);
2423 DEFINE_BIT_SWITCH_ARG(spdif_out
, CM_REG_FUNCTRL1
, CM_SPDF_0
, 0, 0);
2425 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1
, CM_REG_CHFORMAT
, CM_SPDIF_SELECT1
, 0, 0);
2426 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2
, CM_REG_MISC_CTRL
, CM_SPDIF_SELECT2
, 0, 0);
2427 DEFINE_BIT_SWITCH_ARG(spdif_enable
, CM_REG_LEGACY_CTRL
, CM_ENSPDOUT
, 0, 0);
2428 DEFINE_BIT_SWITCH_ARG(spdo2dac
, CM_REG_FUNCTRL1
, CM_SPDO2DAC
, 0, 1);
2429 DEFINE_BIT_SWITCH_ARG(spdi_valid
, CM_REG_MISC
, CM_SPDVALID
, 1, 0);
2430 DEFINE_BIT_SWITCH_ARG(spdif_copyright
, CM_REG_LEGACY_CTRL
, CM_SPDCOPYRHT
, 0, 0);
2431 DEFINE_BIT_SWITCH_ARG(spdif_dac_out
, CM_REG_LEGACY_CTRL
, CM_DAC2SPDO
, 0, 1);
2432 DEFINE_SWITCH_ARG(spdo_5v
, CM_REG_MISC_CTRL
, CM_SPDO5V
, 0, 0, 0); /* inverse: 0 = 5V */
2433 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2434 DEFINE_BIT_SWITCH_ARG(spdif_loop
, CM_REG_FUNCTRL1
, CM_SPDFLOOP
, 0, 1);
2435 DEFINE_BIT_SWITCH_ARG(spdi_monitor
, CM_REG_MIXER1
, CM_CDPLAY
, 1, 0);
2436 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2437 DEFINE_BIT_SWITCH_ARG(spdi_phase
, CM_REG_MISC
, CM_SPDIF_INVERSE
, 1, 0);
2438 DEFINE_BIT_SWITCH_ARG(spdi_phase2
, CM_REG_CHFORMAT
, CM_SPDIF_INVERSE2
, 0, 0);
2440 DEFINE_SWITCH_ARG(exchange_dac
, CM_REG_MISC_CTRL
, CM_XCHGDAC
, 0, 0, 0); /* reversed */
2442 DEFINE_SWITCH_ARG(exchange_dac
, CM_REG_MISC_CTRL
, CM_XCHGDAC
, CM_XCHGDAC
, 0, 0);
2444 DEFINE_BIT_SWITCH_ARG(fourch
, CM_REG_MISC_CTRL
, CM_N4SPK3D
, 0, 0);
2445 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2446 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2447 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2448 DEFINE_SWITCH_ARG(modem
, CM_REG_MISC_CTRL
, CM_FLINKON
|CM_FLINKOFF
, CM_FLINKON
, 0, 0);
2450 #define DEFINE_SWITCH(sname, stype, sarg) \
2453 .info = snd_cmipci_uswitch_info, \
2454 .get = snd_cmipci_uswitch_get, \
2455 .put = snd_cmipci_uswitch_put, \
2456 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2459 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2460 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2464 * callbacks for spdif output switch
2465 * needs toggle two registers..
2467 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol
*kcontrol
,
2468 struct snd_ctl_elem_value
*ucontrol
)
2471 changed
= _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, &cmipci_switch_arg_spdif_enable
);
2472 changed
|= _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, &cmipci_switch_arg_spdo2dac
);
2476 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol
*kcontrol
,
2477 struct snd_ctl_elem_value
*ucontrol
)
2479 struct cmipci
*chip
= snd_kcontrol_chip(kcontrol
);
2481 changed
= _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, &cmipci_switch_arg_spdif_enable
);
2482 changed
|= _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, &cmipci_switch_arg_spdo2dac
);
2484 if (ucontrol
->value
.integer
.value
[0]) {
2485 if (chip
->spdif_playback_avail
)
2486 snd_cmipci_set_bit(chip
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
2488 if (chip
->spdif_playback_avail
)
2489 snd_cmipci_clear_bit(chip
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
2492 chip
->spdif_playback_enabled
= ucontrol
->value
.integer
.value
[0];
2497 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol
*kcontrol
,
2498 struct snd_ctl_elem_info
*uinfo
)
2500 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2501 static char *texts
[3] = { "Line-In", "Rear Output", "Bass Output" };
2502 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2504 uinfo
->value
.enumerated
.items
= cm
->chip_version
>= 39 ? 3 : 2;
2505 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2506 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
2507 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2511 static inline unsigned int get_line_in_mode(struct cmipci
*cm
)
2514 if (cm
->chip_version
>= 39) {
2515 val
= snd_cmipci_read(cm
, CM_REG_LEGACY_CTRL
);
2516 if (val
& (CM_CENTR2LIN
| CM_BASE2LIN
))
2519 val
= snd_cmipci_read_b(cm
, CM_REG_MIXER1
);
2520 if (val
& CM_REAR2LIN
)
2525 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol
*kcontrol
,
2526 struct snd_ctl_elem_value
*ucontrol
)
2528 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2530 spin_lock_irq(&cm
->reg_lock
);
2531 ucontrol
->value
.enumerated
.item
[0] = get_line_in_mode(cm
);
2532 spin_unlock_irq(&cm
->reg_lock
);
2536 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol
*kcontrol
,
2537 struct snd_ctl_elem_value
*ucontrol
)
2539 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2542 spin_lock_irq(&cm
->reg_lock
);
2543 if (ucontrol
->value
.enumerated
.item
[0] == 2)
2544 change
= snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CENTR2LIN
| CM_BASE2LIN
);
2546 change
= snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CENTR2LIN
| CM_BASE2LIN
);
2547 if (ucontrol
->value
.enumerated
.item
[0] == 1)
2548 change
|= snd_cmipci_set_bit_b(cm
, CM_REG_MIXER1
, CM_REAR2LIN
);
2550 change
|= snd_cmipci_clear_bit_b(cm
, CM_REG_MIXER1
, CM_REAR2LIN
);
2551 spin_unlock_irq(&cm
->reg_lock
);
2555 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol
*kcontrol
,
2556 struct snd_ctl_elem_info
*uinfo
)
2558 static char *texts
[2] = { "Mic-In", "Center/LFE Output" };
2559 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2561 uinfo
->value
.enumerated
.items
= 2;
2562 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2563 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
2564 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2568 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol
*kcontrol
,
2569 struct snd_ctl_elem_value
*ucontrol
)
2571 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2572 /* same bit as spdi_phase */
2573 spin_lock_irq(&cm
->reg_lock
);
2574 ucontrol
->value
.enumerated
.item
[0] =
2575 (snd_cmipci_read_b(cm
, CM_REG_MISC
) & CM_SPDIF_INVERSE
) ? 1 : 0;
2576 spin_unlock_irq(&cm
->reg_lock
);
2580 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol
*kcontrol
,
2581 struct snd_ctl_elem_value
*ucontrol
)
2583 struct cmipci
*cm
= snd_kcontrol_chip(kcontrol
);
2586 spin_lock_irq(&cm
->reg_lock
);
2587 if (ucontrol
->value
.enumerated
.item
[0])
2588 change
= snd_cmipci_set_bit_b(cm
, CM_REG_MISC
, CM_SPDIF_INVERSE
);
2590 change
= snd_cmipci_clear_bit_b(cm
, CM_REG_MISC
, CM_SPDIF_INVERSE
);
2591 spin_unlock_irq(&cm
->reg_lock
);
2595 /* both for CM8338/8738 */
2596 static struct snd_kcontrol_new snd_cmipci_mixer_switches
[] __devinitdata
= {
2597 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch
),
2599 .name
= "Line-In Mode",
2600 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2601 .info
= snd_cmipci_line_in_mode_info
,
2602 .get
= snd_cmipci_line_in_mode_get
,
2603 .put
= snd_cmipci_line_in_mode_put
,
2607 /* for non-multichannel chips */
2608 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata
=
2609 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac
);
2611 /* only for CM8738 */
2612 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches
[] __devinitdata
= {
2613 #if 0 /* controlled in pcm device */
2614 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in
),
2615 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out
),
2616 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac
),
2618 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2619 { .name
= "IEC958 Output Switch",
2620 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2621 .info
= snd_cmipci_uswitch_info
,
2622 .get
= snd_cmipci_spdout_enable_get
,
2623 .put
= snd_cmipci_spdout_enable_put
,
2625 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid
),
2626 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright
),
2627 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v
),
2628 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2629 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop
),
2630 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor
),
2633 /* only for model 033/037 */
2634 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches
[] __devinitdata
= {
2635 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out
),
2636 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase
),
2637 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1
),
2640 /* only for model 039 or later */
2641 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches
[] __devinitdata
= {
2642 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2
),
2643 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2
),
2645 .name
= "Mic-In Mode",
2646 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2647 .info
= snd_cmipci_mic_in_mode_info
,
2648 .get
= snd_cmipci_mic_in_mode_get
,
2649 .put
= snd_cmipci_mic_in_mode_put
,
2653 /* card control switches */
2654 static struct snd_kcontrol_new snd_cmipci_modem_switch __devinitdata
=
2655 DEFINE_CARD_SWITCH("Modem", modem
);
2658 static int __devinit
snd_cmipci_mixer_new(struct cmipci
*cm
, int pcm_spdif_device
)
2660 struct snd_card
*card
;
2661 struct snd_kcontrol_new
*sw
;
2662 struct snd_kcontrol
*kctl
;
2666 snd_assert(cm
!= NULL
&& cm
->card
!= NULL
, return -EINVAL
);
2670 strcpy(card
->mixername
, "CMedia PCI");
2672 spin_lock_irq(&cm
->reg_lock
);
2673 snd_cmipci_mixer_write(cm
, 0x00, 0x00); /* mixer reset */
2674 spin_unlock_irq(&cm
->reg_lock
);
2676 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_mixers
); idx
++) {
2677 if (cm
->chip_version
== 68) { // 8768 has no PCM volume
2678 if (!strcmp(snd_cmipci_mixers
[idx
].name
,
2679 "PCM Playback Volume"))
2682 if ((err
= snd_ctl_add(card
, snd_ctl_new1(&snd_cmipci_mixers
[idx
], cm
))) < 0)
2686 /* mixer switches */
2687 sw
= snd_cmipci_mixer_switches
;
2688 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_mixer_switches
); idx
++, sw
++) {
2689 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2693 if (! cm
->can_multi_ch
) {
2694 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(&snd_cmipci_nomulti_switch
, cm
));
2698 if (cm
->device
== PCI_DEVICE_ID_CMEDIA_CM8738
||
2699 cm
->device
== PCI_DEVICE_ID_CMEDIA_CM8738B
) {
2700 sw
= snd_cmipci_8738_mixer_switches
;
2701 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_8738_mixer_switches
); idx
++, sw
++) {
2702 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2706 if (cm
->can_ac3_hw
) {
2707 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_default
, cm
))) < 0)
2709 kctl
->id
.device
= pcm_spdif_device
;
2710 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_mask
, cm
))) < 0)
2712 kctl
->id
.device
= pcm_spdif_device
;
2713 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_stream
, cm
))) < 0)
2715 kctl
->id
.device
= pcm_spdif_device
;
2717 if (cm
->chip_version
<= 37) {
2718 sw
= snd_cmipci_old_mixer_switches
;
2719 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_old_mixer_switches
); idx
++, sw
++) {
2720 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2726 if (cm
->chip_version
>= 39) {
2727 sw
= snd_cmipci_extra_mixer_switches
;
2728 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_extra_mixer_switches
); idx
++, sw
++) {
2729 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2736 if (cm
->chip_version
< 39) {
2737 err
= snd_ctl_add(cm
->card
,
2738 snd_ctl_new1(&snd_cmipci_modem_switch
, cm
));
2743 for (idx
= 0; idx
< CM_SAVED_MIXERS
; idx
++) {
2744 struct snd_ctl_elem_id id
;
2745 struct snd_kcontrol
*ctl
;
2746 memset(&id
, 0, sizeof(id
));
2747 id
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
2748 strcpy(id
.name
, cm_saved_mixer
[idx
].name
);
2749 if ((ctl
= snd_ctl_find_id(cm
->card
, &id
)) != NULL
)
2750 cm
->mixer_res_ctl
[idx
] = ctl
;
2761 #ifdef CONFIG_PROC_FS
2762 static void snd_cmipci_proc_read(struct snd_info_entry
*entry
,
2763 struct snd_info_buffer
*buffer
)
2765 struct cmipci
*cm
= entry
->private_data
;
2768 snd_iprintf(buffer
, "%s\n", cm
->card
->longname
);
2769 for (i
= 0; i
< 0x94; i
++) {
2772 v
= inb(cm
->iobase
+ i
);
2774 snd_iprintf(buffer
, "\n%02x:", i
);
2775 snd_iprintf(buffer
, " %02x", v
);
2777 snd_iprintf(buffer
, "\n");
2780 static void __devinit
snd_cmipci_proc_init(struct cmipci
*cm
)
2782 struct snd_info_entry
*entry
;
2784 if (! snd_card_proc_new(cm
->card
, "cmipci", &entry
))
2785 snd_info_set_text_ops(entry
, cm
, snd_cmipci_proc_read
);
2787 #else /* !CONFIG_PROC_FS */
2788 static inline void snd_cmipci_proc_init(struct cmipci
*cm
) {}
2792 static struct pci_device_id snd_cmipci_ids
[] = {
2793 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8338A
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2794 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8338B
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2795 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8738
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2796 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8738B
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2797 {PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_CMEDIA_CM8738
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2803 * check chip version and capabilities
2804 * driver name is modified according to the chip model
2806 static void __devinit
query_chip(struct cmipci
*cm
)
2808 unsigned int detect
;
2810 /* check reg 0Ch, bit 24-31 */
2811 detect
= snd_cmipci_read(cm
, CM_REG_INT_HLDCLR
) & CM_CHIP_MASK2
;
2813 /* check reg 08h, bit 24-28 */
2814 detect
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
) & CM_CHIP_MASK1
;
2817 cm
->chip_version
= 33;
2818 if (cm
->do_soft_ac3
)
2824 cm
->chip_version
= 37;
2828 cm
->chip_version
= 39;
2832 cm
->max_channels
= 2;
2834 if (detect
& CM_CHIP_039
) {
2835 cm
->chip_version
= 39;
2836 if (detect
& CM_CHIP_039_6CH
) /* 4 or 6 channels */
2837 cm
->max_channels
= 6;
2839 cm
->max_channels
= 4;
2840 } else if (detect
& CM_CHIP_8768
) {
2841 cm
->chip_version
= 68;
2842 cm
->max_channels
= 8;
2845 cm
->chip_version
= 55;
2846 cm
->max_channels
= 6;
2850 cm
->can_multi_ch
= 1;
2854 #ifdef SUPPORT_JOYSTICK
2855 static int __devinit
snd_cmipci_create_gameport(struct cmipci
*cm
, int dev
)
2857 static int ports
[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2858 struct gameport
*gp
;
2859 struct resource
*r
= NULL
;
2862 if (joystick_port
[dev
] == 0)
2865 if (joystick_port
[dev
] == 1) { /* auto-detect */
2866 for (i
= 0; ports
[i
]; i
++) {
2868 r
= request_region(io_port
, 1, "CMIPCI gameport");
2873 io_port
= joystick_port
[dev
];
2874 r
= request_region(io_port
, 1, "CMIPCI gameport");
2878 printk(KERN_WARNING
"cmipci: cannot reserve joystick ports\n");
2882 cm
->gameport
= gp
= gameport_allocate_port();
2884 printk(KERN_ERR
"cmipci: cannot allocate memory for gameport\n");
2885 release_and_free_resource(r
);
2888 gameport_set_name(gp
, "C-Media Gameport");
2889 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(cm
->pci
));
2890 gameport_set_dev_parent(gp
, &cm
->pci
->dev
);
2892 gameport_set_port_data(gp
, r
);
2894 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2896 gameport_register_port(cm
->gameport
);
2901 static void snd_cmipci_free_gameport(struct cmipci
*cm
)
2904 struct resource
*r
= gameport_get_port_data(cm
->gameport
);
2906 gameport_unregister_port(cm
->gameport
);
2907 cm
->gameport
= NULL
;
2909 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2910 release_and_free_resource(r
);
2914 static inline int snd_cmipci_create_gameport(struct cmipci
*cm
, int dev
) { return -ENOSYS
; }
2915 static inline void snd_cmipci_free_gameport(struct cmipci
*cm
) { }
2918 static int snd_cmipci_free(struct cmipci
*cm
)
2921 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2922 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_ENSPDOUT
);
2923 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0); /* disable ints */
2924 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
2925 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
2926 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, 0); /* disable channels */
2927 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, 0);
2930 snd_cmipci_mixer_write(cm
, 0, 0);
2932 synchronize_irq(cm
->irq
);
2934 free_irq(cm
->irq
, cm
);
2937 snd_cmipci_free_gameport(cm
);
2938 pci_release_regions(cm
->pci
);
2939 pci_disable_device(cm
->pci
);
2944 static int snd_cmipci_dev_free(struct snd_device
*device
)
2946 struct cmipci
*cm
= device
->device_data
;
2947 return snd_cmipci_free(cm
);
2950 static int __devinit
snd_cmipci_create_fm(struct cmipci
*cm
, long fm_port
)
2954 struct snd_opl3
*opl3
;
2960 if (cm
->chip_version
>= 39) {
2961 /* first try FM regs in PCI port range */
2962 iosynth
= cm
->iobase
+ CM_REG_FM_PCI
;
2963 err
= snd_opl3_create(cm
->card
, iosynth
, iosynth
+ 2,
2964 OPL3_HW_OPL3
, 1, &opl3
);
2969 /* then try legacy ports */
2970 val
= snd_cmipci_read(cm
, CM_REG_LEGACY_CTRL
) & ~CM_FMSEL_MASK
;
2973 case 0x3E8: val
|= CM_FMSEL_3E8
; break;
2974 case 0x3E0: val
|= CM_FMSEL_3E0
; break;
2975 case 0x3C8: val
|= CM_FMSEL_3C8
; break;
2976 case 0x388: val
|= CM_FMSEL_388
; break;
2980 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
, val
);
2982 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2984 if (snd_opl3_create(cm
->card
, iosynth
, iosynth
+ 2,
2985 OPL3_HW_OPL3
, 0, &opl3
) < 0) {
2986 printk(KERN_ERR
"cmipci: no OPL device at %#lx, "
2987 "skipping...\n", iosynth
);
2991 if ((err
= snd_opl3_hwdep_new(opl3
, 0, 1, NULL
)) < 0) {
2992 printk(KERN_ERR
"cmipci: cannot create OPL3 hwdep\n");
2998 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_FMSEL_MASK
);
2999 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
3003 static int __devinit
snd_cmipci_create(struct snd_card
*card
, struct pci_dev
*pci
,
3004 int dev
, struct cmipci
**rcmipci
)
3008 static struct snd_device_ops ops
= {
3009 .dev_free
= snd_cmipci_dev_free
,
3013 int integrated_midi
= 0;
3015 int pcm_index
, pcm_spdif_index
;
3016 static struct pci_device_id intel_82437vx
[] = {
3017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
) },
3023 if ((err
= pci_enable_device(pci
)) < 0)
3026 cm
= kzalloc(sizeof(*cm
), GFP_KERNEL
);
3028 pci_disable_device(pci
);
3032 spin_lock_init(&cm
->reg_lock
);
3033 mutex_init(&cm
->open_mutex
);
3034 cm
->device
= pci
->device
;
3038 cm
->channel
[0].ch
= 0;
3039 cm
->channel
[1].ch
= 1;
3040 cm
->channel
[0].is_dac
= cm
->channel
[1].is_dac
= 1; /* dual DAC mode */
3042 if ((err
= pci_request_regions(pci
, card
->driver
)) < 0) {
3044 pci_disable_device(pci
);
3047 cm
->iobase
= pci_resource_start(pci
, 0);
3049 if (request_irq(pci
->irq
, snd_cmipci_interrupt
,
3050 IRQF_SHARED
, card
->driver
, cm
)) {
3051 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
3052 snd_cmipci_free(cm
);
3057 pci_set_master(cm
->pci
);
3060 * check chip version, max channels and capabilities
3063 cm
->chip_version
= 0;
3064 cm
->max_channels
= 2;
3065 cm
->do_soft_ac3
= soft_ac3
[dev
];
3067 if (pci
->device
!= PCI_DEVICE_ID_CMEDIA_CM8338A
&&
3068 pci
->device
!= PCI_DEVICE_ID_CMEDIA_CM8338B
)
3070 /* added -MCx suffix for chip supporting multi-channels */
3071 if (cm
->can_multi_ch
)
3072 sprintf(cm
->card
->driver
+ strlen(cm
->card
->driver
),
3073 "-MC%d", cm
->max_channels
);
3074 else if (cm
->can_ac3_sw
)
3075 strcpy(cm
->card
->driver
+ strlen(cm
->card
->driver
), "-SWIEC");
3077 cm
->dig_status
= SNDRV_PCM_DEFAULT_CON_SPDIF
;
3078 cm
->dig_pcm_status
= SNDRV_PCM_DEFAULT_CON_SPDIF
;
3081 cm
->ctrl
= CM_CHADC0
; /* default FUNCNTRL0 */
3083 cm
->ctrl
= CM_CHADC1
; /* default FUNCNTRL0 */
3086 /* initialize codec registers */
3087 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_RESET
);
3088 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_RESET
);
3089 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0); /* disable ints */
3090 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
3091 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
3092 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, 0); /* disable channels */
3093 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, 0);
3095 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, 0);
3096 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
|CM_N4SPK3D
);
3098 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
3100 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
3102 if (cm
->chip_version
) {
3103 snd_cmipci_write_b(cm
, CM_REG_EXT_MISC
, 0x20); /* magic */
3104 snd_cmipci_write_b(cm
, CM_REG_EXT_MISC
+ 1, 0x09); /* more magic */
3106 /* Set Bus Master Request */
3107 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_BREQ
);
3109 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3110 switch (pci
->device
) {
3111 case PCI_DEVICE_ID_CMEDIA_CM8738
:
3112 case PCI_DEVICE_ID_CMEDIA_CM8738B
:
3113 if (!pci_dev_present(intel_82437vx
))
3114 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_TXVX
);
3120 if (cm
->chip_version
< 68) {
3121 val
= pci
->device
< 0x110 ? 8338 : 8738;
3123 switch (snd_cmipci_read_b(cm
, CM_REG_INT_HLDCLR
+ 3) & 0x03) {
3131 switch ((pci
->subsystem_vendor
<< 16) |
3132 pci
->subsystem_device
) {
3147 sprintf(card
->shortname
, "C-Media CMI%d", val
);
3148 if (cm
->chip_version
< 68)
3149 sprintf(modelstr
, " (model %d)", cm
->chip_version
);
3152 sprintf(card
->longname
, "%s%s at %#lx, irq %i",
3153 card
->shortname
, modelstr
, cm
->iobase
, cm
->irq
);
3155 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, cm
, &ops
)) < 0) {
3156 snd_cmipci_free(cm
);
3160 if (cm
->chip_version
>= 39) {
3161 val
= snd_cmipci_read_b(cm
, CM_REG_MPU_PCI
+ 1);
3162 if (val
!= 0x00 && val
!= 0xff) {
3163 iomidi
= cm
->iobase
+ CM_REG_MPU_PCI
;
3164 integrated_midi
= 1;
3167 if (!integrated_midi
) {
3169 iomidi
= mpu_port
[dev
];
3171 case 0x320: val
= CM_VMPU_320
; break;
3172 case 0x310: val
= CM_VMPU_310
; break;
3173 case 0x300: val
= CM_VMPU_300
; break;
3174 case 0x330: val
= CM_VMPU_330
; break;
3179 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
, val
);
3181 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_UART_EN
);
3182 if (inb(iomidi
+ 1) == 0xff) {
3183 snd_printk(KERN_ERR
"cannot enable MPU-401 port"
3184 " at %#lx\n", iomidi
);
3185 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
,
3192 if (cm
->chip_version
< 68) {
3193 err
= snd_cmipci_create_fm(cm
, fm_port
[dev
]);
3199 snd_cmipci_mixer_write(cm
, 0, 0);
3201 snd_cmipci_proc_init(cm
);
3203 /* create pcm devices */
3204 pcm_index
= pcm_spdif_index
= 0;
3205 if ((err
= snd_cmipci_pcm_new(cm
, pcm_index
)) < 0)
3208 if ((err
= snd_cmipci_pcm2_new(cm
, pcm_index
)) < 0)
3211 if (cm
->can_ac3_hw
|| cm
->can_ac3_sw
) {
3212 pcm_spdif_index
= pcm_index
;
3213 if ((err
= snd_cmipci_pcm_spdif_new(cm
, pcm_index
)) < 0)
3217 /* create mixer interface & switches */
3218 if ((err
= snd_cmipci_mixer_new(cm
, pcm_spdif_index
)) < 0)
3222 if ((err
= snd_mpu401_uart_new(card
, 0, MPU401_HW_CMIPCI
,
3225 MPU401_INFO_INTEGRATED
: 0),
3226 cm
->irq
, 0, &cm
->rmidi
)) < 0) {
3227 printk(KERN_ERR
"cmipci: no UART401 device at 0x%lx\n", iomidi
);
3231 #ifdef USE_VAR48KRATE
3232 for (val
= 0; val
< ARRAY_SIZE(rates
); val
++)
3233 snd_cmipci_set_pll(cm
, rates
[val
], val
);
3236 * (Re-)Enable external switch spdo_48k
3238 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
|CM_SPDF_AC97
);
3239 #endif /* USE_VAR48KRATE */
3241 if (snd_cmipci_create_gameport(cm
, dev
) < 0)
3242 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
3244 snd_card_set_dev(card
, &pci
->dev
);
3253 MODULE_DEVICE_TABLE(pci
, snd_cmipci_ids
);
3255 static int __devinit
snd_cmipci_probe(struct pci_dev
*pci
,
3256 const struct pci_device_id
*pci_id
)
3259 struct snd_card
*card
;
3263 if (dev
>= SNDRV_CARDS
)
3265 if (! enable
[dev
]) {
3270 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
3274 switch (pci
->device
) {
3275 case PCI_DEVICE_ID_CMEDIA_CM8738
:
3276 case PCI_DEVICE_ID_CMEDIA_CM8738B
:
3277 strcpy(card
->driver
, "CMI8738");
3279 case PCI_DEVICE_ID_CMEDIA_CM8338A
:
3280 case PCI_DEVICE_ID_CMEDIA_CM8338B
:
3281 strcpy(card
->driver
, "CMI8338");
3284 strcpy(card
->driver
, "CMIPCI");
3288 if ((err
= snd_cmipci_create(card
, pci
, dev
, &cm
)) < 0) {
3289 snd_card_free(card
);
3292 card
->private_data
= cm
;
3294 if ((err
= snd_card_register(card
)) < 0) {
3295 snd_card_free(card
);
3298 pci_set_drvdata(pci
, card
);
3304 static void __devexit
snd_cmipci_remove(struct pci_dev
*pci
)
3306 snd_card_free(pci_get_drvdata(pci
));
3307 pci_set_drvdata(pci
, NULL
);
3315 static unsigned char saved_regs
[] = {
3316 CM_REG_FUNCTRL1
, CM_REG_CHFORMAT
, CM_REG_LEGACY_CTRL
, CM_REG_MISC_CTRL
,
3317 CM_REG_MIXER0
, CM_REG_MIXER1
, CM_REG_MIXER2
, CM_REG_MIXER3
, CM_REG_PLL
,
3318 CM_REG_CH0_FRAME1
, CM_REG_CH0_FRAME2
,
3319 CM_REG_CH1_FRAME1
, CM_REG_CH1_FRAME2
, CM_REG_EXT_MISC
,
3320 CM_REG_INT_STATUS
, CM_REG_INT_HLDCLR
, CM_REG_FUNCTRL0
,
3323 static unsigned char saved_mixers
[] = {
3324 SB_DSP4_MASTER_DEV
, SB_DSP4_MASTER_DEV
+ 1,
3325 SB_DSP4_PCM_DEV
, SB_DSP4_PCM_DEV
+ 1,
3326 SB_DSP4_SYNTH_DEV
, SB_DSP4_SYNTH_DEV
+ 1,
3327 SB_DSP4_CD_DEV
, SB_DSP4_CD_DEV
+ 1,
3328 SB_DSP4_LINE_DEV
, SB_DSP4_LINE_DEV
+ 1,
3329 SB_DSP4_MIC_DEV
, SB_DSP4_SPEAKER_DEV
,
3330 CM_REG_EXTENT_IND
, SB_DSP4_OUTPUT_SW
,
3331 SB_DSP4_INPUT_LEFT
, SB_DSP4_INPUT_RIGHT
,
3334 static int snd_cmipci_suspend(struct pci_dev
*pci
, pm_message_t state
)
3336 struct snd_card
*card
= pci_get_drvdata(pci
);
3337 struct cmipci
*cm
= card
->private_data
;
3340 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
3342 snd_pcm_suspend_all(cm
->pcm
);
3343 snd_pcm_suspend_all(cm
->pcm2
);
3344 snd_pcm_suspend_all(cm
->pcm_spdif
);
3346 /* save registers */
3347 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3348 cm
->saved_regs
[i
] = snd_cmipci_read(cm
, saved_regs
[i
]);
3349 for (i
= 0; i
< ARRAY_SIZE(saved_mixers
); i
++)
3350 cm
->saved_mixers
[i
] = snd_cmipci_mixer_read(cm
, saved_mixers
[i
]);
3353 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0);
3355 pci_disable_device(pci
);
3356 pci_save_state(pci
);
3357 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
3361 static int snd_cmipci_resume(struct pci_dev
*pci
)
3363 struct snd_card
*card
= pci_get_drvdata(pci
);
3364 struct cmipci
*cm
= card
->private_data
;
3367 pci_set_power_state(pci
, PCI_D0
);
3368 pci_restore_state(pci
);
3369 if (pci_enable_device(pci
) < 0) {
3370 printk(KERN_ERR
"cmipci: pci_enable_device failed, "
3371 "disabling device\n");
3372 snd_card_disconnect(card
);
3375 pci_set_master(pci
);
3377 /* reset / initialize to a sane state */
3378 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0);
3379 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
3380 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
3381 snd_cmipci_mixer_write(cm
, 0, 0);
3383 /* restore registers */
3384 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3385 snd_cmipci_write(cm
, saved_regs
[i
], cm
->saved_regs
[i
]);
3386 for (i
= 0; i
< ARRAY_SIZE(saved_mixers
); i
++)
3387 snd_cmipci_mixer_write(cm
, saved_mixers
[i
], cm
->saved_mixers
[i
]);
3389 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
3392 #endif /* CONFIG_PM */
3394 static struct pci_driver driver
= {
3395 .name
= "C-Media PCI",
3396 .id_table
= snd_cmipci_ids
,
3397 .probe
= snd_cmipci_probe
,
3398 .remove
= __devexit_p(snd_cmipci_remove
),
3400 .suspend
= snd_cmipci_suspend
,
3401 .resume
= snd_cmipci_resume
,
3405 static int __init
alsa_card_cmipci_init(void)
3407 return pci_register_driver(&driver
);
3410 static void __exit
alsa_card_cmipci_exit(void)
3412 pci_unregister_driver(&driver
);
3415 module_init(alsa_card_cmipci_init
)
3416 module_exit(alsa_card_cmipci_exit
)