]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - sound/pci/emu10k1/emufx.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ALSA: emu10k1: Get rid of set_fs() usage
[mirror_ubuntu-artful-kernel.git] / sound / pci / emu10k1 / emufx.c
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Creative Labs, Inc.
4 * Routines for effect processor FX8010
5 *
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added EMU 1010 support.
8 *
9 * BUGS:
10 * --
11 *
12 * TODO:
13 * --
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 *
29 */
30
31 #include <linux/pci.h>
32 #include <linux/capability.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/init.h>
37 #include <linux/mutex.h>
38 #include <linux/moduleparam.h>
39
40 #include <sound/core.h>
41 #include <sound/tlv.h>
42 #include <sound/emu10k1.h>
43
44 #if 0 /* for testing purposes - digital out -> capture */
45 #define EMU10K1_CAPTURE_DIGITAL_OUT
46 #endif
47 #if 0 /* for testing purposes - set S/PDIF to AC3 output */
48 #define EMU10K1_SET_AC3_IEC958
49 #endif
50 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
51 #define EMU10K1_CENTER_LFE_FROM_FRONT
52 #endif
53
54 static bool high_res_gpr_volume;
55 module_param(high_res_gpr_volume, bool, 0444);
56 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
57
58 /*
59 * Tables
60 */
61
62 static char *fxbuses[16] = {
63 /* 0x00 */ "PCM Left",
64 /* 0x01 */ "PCM Right",
65 /* 0x02 */ "PCM Surround Left",
66 /* 0x03 */ "PCM Surround Right",
67 /* 0x04 */ "MIDI Left",
68 /* 0x05 */ "MIDI Right",
69 /* 0x06 */ "Center",
70 /* 0x07 */ "LFE",
71 /* 0x08 */ NULL,
72 /* 0x09 */ NULL,
73 /* 0x0a */ NULL,
74 /* 0x0b */ NULL,
75 /* 0x0c */ "MIDI Reverb",
76 /* 0x0d */ "MIDI Chorus",
77 /* 0x0e */ NULL,
78 /* 0x0f */ NULL
79 };
80
81 static char *creative_ins[16] = {
82 /* 0x00 */ "AC97 Left",
83 /* 0x01 */ "AC97 Right",
84 /* 0x02 */ "TTL IEC958 Left",
85 /* 0x03 */ "TTL IEC958 Right",
86 /* 0x04 */ "Zoom Video Left",
87 /* 0x05 */ "Zoom Video Right",
88 /* 0x06 */ "Optical IEC958 Left",
89 /* 0x07 */ "Optical IEC958 Right",
90 /* 0x08 */ "Line/Mic 1 Left",
91 /* 0x09 */ "Line/Mic 1 Right",
92 /* 0x0a */ "Coaxial IEC958 Left",
93 /* 0x0b */ "Coaxial IEC958 Right",
94 /* 0x0c */ "Line/Mic 2 Left",
95 /* 0x0d */ "Line/Mic 2 Right",
96 /* 0x0e */ NULL,
97 /* 0x0f */ NULL
98 };
99
100 static char *audigy_ins[16] = {
101 /* 0x00 */ "AC97 Left",
102 /* 0x01 */ "AC97 Right",
103 /* 0x02 */ "Audigy CD Left",
104 /* 0x03 */ "Audigy CD Right",
105 /* 0x04 */ "Optical IEC958 Left",
106 /* 0x05 */ "Optical IEC958 Right",
107 /* 0x06 */ NULL,
108 /* 0x07 */ NULL,
109 /* 0x08 */ "Line/Mic 2 Left",
110 /* 0x09 */ "Line/Mic 2 Right",
111 /* 0x0a */ "SPDIF Left",
112 /* 0x0b */ "SPDIF Right",
113 /* 0x0c */ "Aux2 Left",
114 /* 0x0d */ "Aux2 Right",
115 /* 0x0e */ NULL,
116 /* 0x0f */ NULL
117 };
118
119 static char *creative_outs[32] = {
120 /* 0x00 */ "AC97 Left",
121 /* 0x01 */ "AC97 Right",
122 /* 0x02 */ "Optical IEC958 Left",
123 /* 0x03 */ "Optical IEC958 Right",
124 /* 0x04 */ "Center",
125 /* 0x05 */ "LFE",
126 /* 0x06 */ "Headphone Left",
127 /* 0x07 */ "Headphone Right",
128 /* 0x08 */ "Surround Left",
129 /* 0x09 */ "Surround Right",
130 /* 0x0a */ "PCM Capture Left",
131 /* 0x0b */ "PCM Capture Right",
132 /* 0x0c */ "MIC Capture",
133 /* 0x0d */ "AC97 Surround Left",
134 /* 0x0e */ "AC97 Surround Right",
135 /* 0x0f */ NULL,
136 /* 0x10 */ NULL,
137 /* 0x11 */ "Analog Center",
138 /* 0x12 */ "Analog LFE",
139 /* 0x13 */ NULL,
140 /* 0x14 */ NULL,
141 /* 0x15 */ NULL,
142 /* 0x16 */ NULL,
143 /* 0x17 */ NULL,
144 /* 0x18 */ NULL,
145 /* 0x19 */ NULL,
146 /* 0x1a */ NULL,
147 /* 0x1b */ NULL,
148 /* 0x1c */ NULL,
149 /* 0x1d */ NULL,
150 /* 0x1e */ NULL,
151 /* 0x1f */ NULL,
152 };
153
154 static char *audigy_outs[32] = {
155 /* 0x00 */ "Digital Front Left",
156 /* 0x01 */ "Digital Front Right",
157 /* 0x02 */ "Digital Center",
158 /* 0x03 */ "Digital LEF",
159 /* 0x04 */ "Headphone Left",
160 /* 0x05 */ "Headphone Right",
161 /* 0x06 */ "Digital Rear Left",
162 /* 0x07 */ "Digital Rear Right",
163 /* 0x08 */ "Front Left",
164 /* 0x09 */ "Front Right",
165 /* 0x0a */ "Center",
166 /* 0x0b */ "LFE",
167 /* 0x0c */ NULL,
168 /* 0x0d */ NULL,
169 /* 0x0e */ "Rear Left",
170 /* 0x0f */ "Rear Right",
171 /* 0x10 */ "AC97 Front Left",
172 /* 0x11 */ "AC97 Front Right",
173 /* 0x12 */ "ADC Caputre Left",
174 /* 0x13 */ "ADC Capture Right",
175 /* 0x14 */ NULL,
176 /* 0x15 */ NULL,
177 /* 0x16 */ NULL,
178 /* 0x17 */ NULL,
179 /* 0x18 */ NULL,
180 /* 0x19 */ NULL,
181 /* 0x1a */ NULL,
182 /* 0x1b */ NULL,
183 /* 0x1c */ NULL,
184 /* 0x1d */ NULL,
185 /* 0x1e */ NULL,
186 /* 0x1f */ NULL,
187 };
188
189 static const u32 bass_table[41][5] = {
190 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
191 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
192 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
193 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
194 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
195 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
196 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
197 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
198 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
199 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
200 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
201 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
202 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
203 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
204 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
205 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
206 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
207 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
208 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
209 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
210 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
211 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
212 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
213 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
214 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
215 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
216 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
217 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
218 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
219 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
220 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
221 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
222 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
223 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
224 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
225 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
226 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
227 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
228 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
229 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
230 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
231 };
232
233 static const u32 treble_table[41][5] = {
234 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
235 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
236 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
237 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
238 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
239 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
240 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
241 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
242 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
243 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
244 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
245 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
246 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
247 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
248 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
249 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
250 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
251 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
252 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
253 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
254 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
255 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
256 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
257 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
258 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
259 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
260 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
261 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
262 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
263 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
264 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
265 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
266 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
267 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
268 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
269 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
270 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
271 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
272 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
273 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
274 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
275 };
276
277 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
278 static const u32 db_table[101] = {
279 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
280 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
281 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
282 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
283 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
284 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
285 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
286 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
287 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
288 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
289 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
290 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
291 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
292 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
293 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
294 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
295 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
296 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
297 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
298 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
299 0x7fffffff,
300 };
301
302 /* EMU10k1/EMU10k2 DSP control db gain */
303 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
304 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
305
306 /* EMU10K1 bass/treble db gain */
307 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
308
309 static const u32 onoff_table[2] = {
310 0x00000000, 0x00000001
311 };
312
313 /*
314 * controls
315 */
316
317 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
318 {
319 struct snd_emu10k1_fx8010_ctl *ctl =
320 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
321
322 if (ctl->min == 0 && ctl->max == 1)
323 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
324 else
325 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
326 uinfo->count = ctl->vcount;
327 uinfo->value.integer.min = ctl->min;
328 uinfo->value.integer.max = ctl->max;
329 return 0;
330 }
331
332 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
333 {
334 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
335 struct snd_emu10k1_fx8010_ctl *ctl =
336 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
337 unsigned long flags;
338 unsigned int i;
339
340 spin_lock_irqsave(&emu->reg_lock, flags);
341 for (i = 0; i < ctl->vcount; i++)
342 ucontrol->value.integer.value[i] = ctl->value[i];
343 spin_unlock_irqrestore(&emu->reg_lock, flags);
344 return 0;
345 }
346
347 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
348 {
349 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
350 struct snd_emu10k1_fx8010_ctl *ctl =
351 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
352 unsigned long flags;
353 unsigned int nval, val;
354 unsigned int i, j;
355 int change = 0;
356
357 spin_lock_irqsave(&emu->reg_lock, flags);
358 for (i = 0; i < ctl->vcount; i++) {
359 nval = ucontrol->value.integer.value[i];
360 if (nval < ctl->min)
361 nval = ctl->min;
362 if (nval > ctl->max)
363 nval = ctl->max;
364 if (nval != ctl->value[i])
365 change = 1;
366 val = ctl->value[i] = nval;
367 switch (ctl->translation) {
368 case EMU10K1_GPR_TRANSLATION_NONE:
369 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
370 break;
371 case EMU10K1_GPR_TRANSLATION_TABLE100:
372 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
373 break;
374 case EMU10K1_GPR_TRANSLATION_BASS:
375 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
376 change = -EIO;
377 goto __error;
378 }
379 for (j = 0; j < 5; j++)
380 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
381 break;
382 case EMU10K1_GPR_TRANSLATION_TREBLE:
383 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
384 change = -EIO;
385 goto __error;
386 }
387 for (j = 0; j < 5; j++)
388 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
389 break;
390 case EMU10K1_GPR_TRANSLATION_ONOFF:
391 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
392 break;
393 }
394 }
395 __error:
396 spin_unlock_irqrestore(&emu->reg_lock, flags);
397 return change;
398 }
399
400 /*
401 * Interrupt handler
402 */
403
404 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
405 {
406 struct snd_emu10k1_fx8010_irq *irq, *nirq;
407
408 irq = emu->fx8010.irq_handlers;
409 while (irq) {
410 nirq = irq->next; /* irq ptr can be removed from list */
411 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
412 if (irq->handler)
413 irq->handler(emu, irq->private_data);
414 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
415 }
416 irq = nirq;
417 }
418 }
419
420 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
421 snd_fx8010_irq_handler_t *handler,
422 unsigned char gpr_running,
423 void *private_data,
424 struct snd_emu10k1_fx8010_irq **r_irq)
425 {
426 struct snd_emu10k1_fx8010_irq *irq;
427 unsigned long flags;
428
429 irq = kmalloc(sizeof(*irq), GFP_ATOMIC);
430 if (irq == NULL)
431 return -ENOMEM;
432 irq->handler = handler;
433 irq->gpr_running = gpr_running;
434 irq->private_data = private_data;
435 irq->next = NULL;
436 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
437 if (emu->fx8010.irq_handlers == NULL) {
438 emu->fx8010.irq_handlers = irq;
439 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
440 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
441 } else {
442 irq->next = emu->fx8010.irq_handlers;
443 emu->fx8010.irq_handlers = irq;
444 }
445 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
446 if (r_irq)
447 *r_irq = irq;
448 return 0;
449 }
450
451 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
452 struct snd_emu10k1_fx8010_irq *irq)
453 {
454 struct snd_emu10k1_fx8010_irq *tmp;
455 unsigned long flags;
456
457 spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
458 if ((tmp = emu->fx8010.irq_handlers) == irq) {
459 emu->fx8010.irq_handlers = tmp->next;
460 if (emu->fx8010.irq_handlers == NULL) {
461 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
462 emu->dsp_interrupt = NULL;
463 }
464 } else {
465 while (tmp && tmp->next != irq)
466 tmp = tmp->next;
467 if (tmp)
468 tmp->next = tmp->next->next;
469 }
470 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
471 kfree(irq);
472 return 0;
473 }
474
475 /*************************************************************************
476 * EMU10K1 effect manager
477 *************************************************************************/
478
479 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
480 unsigned int *ptr,
481 u32 op, u32 r, u32 a, u32 x, u32 y)
482 {
483 u_int32_t *code;
484 if (snd_BUG_ON(*ptr >= 512))
485 return;
486 code = (u_int32_t __force *)icode->code + (*ptr) * 2;
487 set_bit(*ptr, icode->code_valid);
488 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
489 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
490 (*ptr)++;
491 }
492
493 #define OP(icode, ptr, op, r, a, x, y) \
494 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
495
496 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
497 unsigned int *ptr,
498 u32 op, u32 r, u32 a, u32 x, u32 y)
499 {
500 u_int32_t *code;
501 if (snd_BUG_ON(*ptr >= 1024))
502 return;
503 code = (u_int32_t __force *)icode->code + (*ptr) * 2;
504 set_bit(*ptr, icode->code_valid);
505 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
506 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
507 (*ptr)++;
508 }
509
510 #define A_OP(icode, ptr, op, r, a, x, y) \
511 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
512
513 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
514 {
515 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
516 snd_emu10k1_ptr_write(emu, pc, 0, data);
517 }
518
519 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
520 {
521 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
522 return snd_emu10k1_ptr_read(emu, pc, 0);
523 }
524
525 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
526 struct snd_emu10k1_fx8010_code *icode,
527 bool in_kernel)
528 {
529 int gpr;
530 u32 val;
531
532 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
533 if (!test_bit(gpr, icode->gpr_valid))
534 continue;
535 if (in_kernel)
536 val = *(u32 *)&icode->gpr_map[gpr];
537 else if (get_user(val, &icode->gpr_map[gpr]))
538 return -EFAULT;
539 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
540 }
541 return 0;
542 }
543
544 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
545 struct snd_emu10k1_fx8010_code *icode)
546 {
547 int gpr;
548 u32 val;
549
550 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
551 set_bit(gpr, icode->gpr_valid);
552 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
553 if (put_user(val, &icode->gpr_map[gpr]))
554 return -EFAULT;
555 }
556 return 0;
557 }
558
559 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
560 struct snd_emu10k1_fx8010_code *icode,
561 bool in_kernel)
562 {
563 int tram;
564 u32 addr, val;
565
566 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
567 if (!test_bit(tram, icode->tram_valid))
568 continue;
569 if (in_kernel) {
570 val = *(u32 *)&icode->tram_data_map[tram];
571 addr = *(u32 *)&icode->tram_addr_map[tram];
572 } else {
573 if (get_user(val, &icode->tram_data_map[tram]) ||
574 get_user(addr, &icode->tram_addr_map[tram]))
575 return -EFAULT;
576 }
577 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
578 if (!emu->audigy) {
579 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
580 } else {
581 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
582 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
583 }
584 }
585 return 0;
586 }
587
588 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
589 struct snd_emu10k1_fx8010_code *icode)
590 {
591 int tram;
592 u32 val, addr;
593
594 memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
595 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
596 set_bit(tram, icode->tram_valid);
597 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
598 if (!emu->audigy) {
599 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
600 } else {
601 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
602 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
603 }
604 if (put_user(val, &icode->tram_data_map[tram]) ||
605 put_user(addr, &icode->tram_addr_map[tram]))
606 return -EFAULT;
607 }
608 return 0;
609 }
610
611 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
612 struct snd_emu10k1_fx8010_code *icode,
613 bool in_kernel)
614 {
615 u32 pc, lo, hi;
616
617 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
618 if (!test_bit(pc / 2, icode->code_valid))
619 continue;
620 if (in_kernel) {
621 lo = *(u32 *)&icode->code[pc + 0];
622 hi = *(u32 *)&icode->code[pc + 1];
623 } else {
624 if (get_user(lo, &icode->code[pc + 0]) ||
625 get_user(hi, &icode->code[pc + 1]))
626 return -EFAULT;
627 }
628 snd_emu10k1_efx_write(emu, pc + 0, lo);
629 snd_emu10k1_efx_write(emu, pc + 1, hi);
630 }
631 return 0;
632 }
633
634 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
635 struct snd_emu10k1_fx8010_code *icode)
636 {
637 u32 pc;
638
639 memset(icode->code_valid, 0, sizeof(icode->code_valid));
640 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
641 set_bit(pc / 2, icode->code_valid);
642 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
643 return -EFAULT;
644 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
645 return -EFAULT;
646 }
647 return 0;
648 }
649
650 static struct snd_emu10k1_fx8010_ctl *
651 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
652 {
653 struct snd_emu10k1_fx8010_ctl *ctl;
654 struct snd_kcontrol *kcontrol;
655
656 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
657 kcontrol = ctl->kcontrol;
658 if (kcontrol->id.iface == id->iface &&
659 !strcmp(kcontrol->id.name, id->name) &&
660 kcontrol->id.index == id->index)
661 return ctl;
662 }
663 return NULL;
664 }
665
666 #define MAX_TLV_SIZE 256
667
668 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
669 {
670 unsigned int data[2];
671 unsigned int *tlv;
672
673 if (!_tlv)
674 return NULL;
675 if (in_kernel)
676 memcpy(data, (void *)_tlv, sizeof(data));
677 else if (copy_from_user(data, _tlv, sizeof(data)))
678 return NULL;
679 if (data[1] >= MAX_TLV_SIZE)
680 return NULL;
681 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
682 if (!tlv)
683 return NULL;
684 memcpy(tlv, data, sizeof(data));
685 if (in_kernel) {
686 memcpy(tlv + 2, (void *)(_tlv + 2), data[1]);
687 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
688 kfree(tlv);
689 return NULL;
690 }
691 return tlv;
692 }
693
694 static int copy_gctl(struct snd_emu10k1 *emu,
695 struct snd_emu10k1_fx8010_control_gpr *gctl,
696 struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
697 int idx, bool in_kernel)
698 {
699 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
700
701 if (emu->support_tlv)
702 return copy_from_user(gctl, &_gctl[idx], sizeof(*gctl));
703 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
704 if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
705 return -EFAULT;
706 gctl->tlv = NULL;
707 return 0;
708 }
709
710 static int copy_gctl_to_user(struct snd_emu10k1 *emu,
711 struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
712 struct snd_emu10k1_fx8010_control_gpr *gctl,
713 int idx)
714 {
715 struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
716
717 if (emu->support_tlv)
718 return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
719
720 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
721 return copy_to_user(&octl[idx], gctl, sizeof(*octl));
722 }
723
724 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
725 struct snd_emu10k1_fx8010_code *icode,
726 bool in_kernel)
727 {
728 unsigned int i;
729 struct snd_ctl_elem_id __user *_id;
730 struct snd_ctl_elem_id id;
731 struct snd_emu10k1_fx8010_control_gpr *gctl;
732 int err;
733
734 for (i = 0, _id = icode->gpr_del_controls;
735 i < icode->gpr_del_control_count; i++, _id++) {
736 if (in_kernel)
737 id = *(struct snd_ctl_elem_id *)_id;
738 else if (copy_from_user(&id, _id, sizeof(id)))
739 return -EFAULT;
740 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
741 return -ENOENT;
742 }
743 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
744 if (! gctl)
745 return -ENOMEM;
746 err = 0;
747 for (i = 0; i < icode->gpr_add_control_count; i++) {
748 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
749 in_kernel)) {
750 err = -EFAULT;
751 goto __error;
752 }
753 if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
754 continue;
755 down_read(&emu->card->controls_rwsem);
756 if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
757 up_read(&emu->card->controls_rwsem);
758 err = -EEXIST;
759 goto __error;
760 }
761 up_read(&emu->card->controls_rwsem);
762 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
763 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
764 err = -EINVAL;
765 goto __error;
766 }
767 }
768 for (i = 0; i < icode->gpr_list_control_count; i++) {
769 /* FIXME: we need to check the WRITE access */
770 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
771 in_kernel)) {
772 err = -EFAULT;
773 goto __error;
774 }
775 }
776 __error:
777 kfree(gctl);
778 return err;
779 }
780
781 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
782 {
783 struct snd_emu10k1_fx8010_ctl *ctl;
784
785 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
786 kctl->private_value = 0;
787 list_del(&ctl->list);
788 kfree(ctl);
789 kfree(kctl->tlv.p);
790 }
791
792 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
793 struct snd_emu10k1_fx8010_code *icode,
794 bool in_kernel)
795 {
796 unsigned int i, j;
797 struct snd_emu10k1_fx8010_control_gpr *gctl;
798 struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
799 struct snd_kcontrol_new knew;
800 struct snd_kcontrol *kctl;
801 struct snd_ctl_elem_value *val;
802 int err = 0;
803
804 val = kmalloc(sizeof(*val), GFP_KERNEL);
805 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
806 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
807 if (!val || !gctl || !nctl) {
808 err = -ENOMEM;
809 goto __error;
810 }
811
812 for (i = 0; i < icode->gpr_add_control_count; i++) {
813 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
814 in_kernel)) {
815 err = -EFAULT;
816 goto __error;
817 }
818 if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
819 gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
820 err = -EINVAL;
821 goto __error;
822 }
823 if (! gctl->id.name[0]) {
824 err = -EINVAL;
825 goto __error;
826 }
827 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
828 memset(&knew, 0, sizeof(knew));
829 knew.iface = gctl->id.iface;
830 knew.name = gctl->id.name;
831 knew.index = gctl->id.index;
832 knew.device = gctl->id.device;
833 knew.subdevice = gctl->id.subdevice;
834 knew.info = snd_emu10k1_gpr_ctl_info;
835 knew.tlv.p = copy_tlv(gctl->tlv, in_kernel);
836 if (knew.tlv.p)
837 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
838 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
839 knew.get = snd_emu10k1_gpr_ctl_get;
840 knew.put = snd_emu10k1_gpr_ctl_put;
841 memset(nctl, 0, sizeof(*nctl));
842 nctl->vcount = gctl->vcount;
843 nctl->count = gctl->count;
844 for (j = 0; j < 32; j++) {
845 nctl->gpr[j] = gctl->gpr[j];
846 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
847 val->value.integer.value[j] = gctl->value[j];
848 }
849 nctl->min = gctl->min;
850 nctl->max = gctl->max;
851 nctl->translation = gctl->translation;
852 if (ctl == NULL) {
853 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
854 if (ctl == NULL) {
855 err = -ENOMEM;
856 kfree(knew.tlv.p);
857 goto __error;
858 }
859 knew.private_value = (unsigned long)ctl;
860 *ctl = *nctl;
861 if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
862 kfree(ctl);
863 kfree(knew.tlv.p);
864 goto __error;
865 }
866 kctl->private_free = snd_emu10k1_ctl_private_free;
867 ctl->kcontrol = kctl;
868 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
869 } else {
870 /* overwrite */
871 nctl->list = ctl->list;
872 nctl->kcontrol = ctl->kcontrol;
873 *ctl = *nctl;
874 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
875 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
876 }
877 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
878 }
879 __error:
880 kfree(nctl);
881 kfree(gctl);
882 kfree(val);
883 return err;
884 }
885
886 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
887 struct snd_emu10k1_fx8010_code *icode,
888 bool in_kernel)
889 {
890 unsigned int i;
891 struct snd_ctl_elem_id id;
892 struct snd_ctl_elem_id __user *_id;
893 struct snd_emu10k1_fx8010_ctl *ctl;
894 struct snd_card *card = emu->card;
895
896 for (i = 0, _id = icode->gpr_del_controls;
897 i < icode->gpr_del_control_count; i++, _id++) {
898 if (in_kernel)
899 id = *(struct snd_ctl_elem_id *)_id;
900 else if (copy_from_user(&id, _id, sizeof(id)))
901 return -EFAULT;
902 down_write(&card->controls_rwsem);
903 ctl = snd_emu10k1_look_for_ctl(emu, &id);
904 if (ctl)
905 snd_ctl_remove(card, ctl->kcontrol);
906 up_write(&card->controls_rwsem);
907 }
908 return 0;
909 }
910
911 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
912 struct snd_emu10k1_fx8010_code *icode)
913 {
914 unsigned int i = 0, j;
915 unsigned int total = 0;
916 struct snd_emu10k1_fx8010_control_gpr *gctl;
917 struct snd_emu10k1_fx8010_ctl *ctl;
918 struct snd_ctl_elem_id *id;
919
920 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
921 if (! gctl)
922 return -ENOMEM;
923
924 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
925 total++;
926 if (icode->gpr_list_controls &&
927 i < icode->gpr_list_control_count) {
928 memset(gctl, 0, sizeof(*gctl));
929 id = &ctl->kcontrol->id;
930 gctl->id.iface = id->iface;
931 strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
932 gctl->id.index = id->index;
933 gctl->id.device = id->device;
934 gctl->id.subdevice = id->subdevice;
935 gctl->vcount = ctl->vcount;
936 gctl->count = ctl->count;
937 for (j = 0; j < 32; j++) {
938 gctl->gpr[j] = ctl->gpr[j];
939 gctl->value[j] = ctl->value[j];
940 }
941 gctl->min = ctl->min;
942 gctl->max = ctl->max;
943 gctl->translation = ctl->translation;
944 if (copy_gctl_to_user(emu, icode->gpr_list_controls,
945 gctl, i)) {
946 kfree(gctl);
947 return -EFAULT;
948 }
949 i++;
950 }
951 }
952 icode->gpr_list_control_total = total;
953 kfree(gctl);
954 return 0;
955 }
956
957 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
958 struct snd_emu10k1_fx8010_code *icode,
959 bool in_kernel)
960 {
961 int err = 0;
962
963 mutex_lock(&emu->fx8010.lock);
964 err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
965 if (err < 0)
966 goto __error;
967 strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
968 /* stop FX processor - this may be dangerous, but it's better to miss
969 some samples than generate wrong ones - [jk] */
970 if (emu->audigy)
971 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
972 else
973 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
974 /* ok, do the main job */
975 err = snd_emu10k1_del_controls(emu, icode, in_kernel);
976 if (err < 0)
977 goto __error;
978 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
979 if (err < 0)
980 goto __error;
981 err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
982 if (err < 0)
983 goto __error;
984 err = snd_emu10k1_code_poke(emu, icode, in_kernel);
985 if (err < 0)
986 goto __error;
987 err = snd_emu10k1_add_controls(emu, icode, in_kernel);
988 if (err < 0)
989 goto __error;
990 /* start FX processor when the DSP code is updated */
991 if (emu->audigy)
992 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
993 else
994 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
995 __error:
996 mutex_unlock(&emu->fx8010.lock);
997 return err;
998 }
999
1000 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
1001 struct snd_emu10k1_fx8010_code *icode)
1002 {
1003 int err;
1004
1005 mutex_lock(&emu->fx8010.lock);
1006 strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
1007 /* ok, do the main job */
1008 err = snd_emu10k1_gpr_peek(emu, icode);
1009 if (err >= 0)
1010 err = snd_emu10k1_tram_peek(emu, icode);
1011 if (err >= 0)
1012 err = snd_emu10k1_code_peek(emu, icode);
1013 if (err >= 0)
1014 err = snd_emu10k1_list_controls(emu, icode);
1015 mutex_unlock(&emu->fx8010.lock);
1016 return err;
1017 }
1018
1019 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
1020 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1021 {
1022 unsigned int i;
1023 int err = 0;
1024 struct snd_emu10k1_fx8010_pcm *pcm;
1025
1026 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1027 return -EINVAL;
1028 if (ipcm->channels > 32)
1029 return -EINVAL;
1030 pcm = &emu->fx8010.pcm[ipcm->substream];
1031 mutex_lock(&emu->fx8010.lock);
1032 spin_lock_irq(&emu->reg_lock);
1033 if (pcm->opened) {
1034 err = -EBUSY;
1035 goto __error;
1036 }
1037 if (ipcm->channels == 0) { /* remove */
1038 pcm->valid = 0;
1039 } else {
1040 /* FIXME: we need to add universal code to the PCM transfer routine */
1041 if (ipcm->channels != 2) {
1042 err = -EINVAL;
1043 goto __error;
1044 }
1045 pcm->valid = 1;
1046 pcm->opened = 0;
1047 pcm->channels = ipcm->channels;
1048 pcm->tram_start = ipcm->tram_start;
1049 pcm->buffer_size = ipcm->buffer_size;
1050 pcm->gpr_size = ipcm->gpr_size;
1051 pcm->gpr_count = ipcm->gpr_count;
1052 pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
1053 pcm->gpr_ptr = ipcm->gpr_ptr;
1054 pcm->gpr_trigger = ipcm->gpr_trigger;
1055 pcm->gpr_running = ipcm->gpr_running;
1056 for (i = 0; i < pcm->channels; i++)
1057 pcm->etram[i] = ipcm->etram[i];
1058 }
1059 __error:
1060 spin_unlock_irq(&emu->reg_lock);
1061 mutex_unlock(&emu->fx8010.lock);
1062 return err;
1063 }
1064
1065 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
1066 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1067 {
1068 unsigned int i;
1069 int err = 0;
1070 struct snd_emu10k1_fx8010_pcm *pcm;
1071
1072 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1073 return -EINVAL;
1074 pcm = &emu->fx8010.pcm[ipcm->substream];
1075 mutex_lock(&emu->fx8010.lock);
1076 spin_lock_irq(&emu->reg_lock);
1077 ipcm->channels = pcm->channels;
1078 ipcm->tram_start = pcm->tram_start;
1079 ipcm->buffer_size = pcm->buffer_size;
1080 ipcm->gpr_size = pcm->gpr_size;
1081 ipcm->gpr_ptr = pcm->gpr_ptr;
1082 ipcm->gpr_count = pcm->gpr_count;
1083 ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
1084 ipcm->gpr_trigger = pcm->gpr_trigger;
1085 ipcm->gpr_running = pcm->gpr_running;
1086 for (i = 0; i < pcm->channels; i++)
1087 ipcm->etram[i] = pcm->etram[i];
1088 ipcm->res1 = ipcm->res2 = 0;
1089 ipcm->pad = 0;
1090 spin_unlock_irq(&emu->reg_lock);
1091 mutex_unlock(&emu->fx8010.lock);
1092 return err;
1093 }
1094
1095 #define SND_EMU10K1_GPR_CONTROLS 44
1096 #define SND_EMU10K1_INPUTS 12
1097 #define SND_EMU10K1_PLAYBACK_CHANNELS 8
1098 #define SND_EMU10K1_CAPTURE_CHANNELS 4
1099
1100 static void
1101 snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1102 const char *name, int gpr, int defval)
1103 {
1104 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1105 strcpy(ctl->id.name, name);
1106 ctl->vcount = ctl->count = 1;
1107 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1108 if (high_res_gpr_volume) {
1109 ctl->min = 0;
1110 ctl->max = 0x7fffffff;
1111 ctl->tlv = snd_emu10k1_db_linear;
1112 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
1113 } else {
1114 ctl->min = 0;
1115 ctl->max = 100;
1116 ctl->tlv = snd_emu10k1_db_scale1;
1117 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
1118 }
1119 }
1120
1121 static void
1122 snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1123 const char *name, int gpr, int defval)
1124 {
1125 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1126 strcpy(ctl->id.name, name);
1127 ctl->vcount = ctl->count = 2;
1128 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1129 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1130 if (high_res_gpr_volume) {
1131 ctl->min = 0;
1132 ctl->max = 0x7fffffff;
1133 ctl->tlv = snd_emu10k1_db_linear;
1134 ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
1135 } else {
1136 ctl->min = 0;
1137 ctl->max = 100;
1138 ctl->tlv = snd_emu10k1_db_scale1;
1139 ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
1140 }
1141 }
1142
1143 static void
1144 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1145 const char *name, int gpr, int defval)
1146 {
1147 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1148 strcpy(ctl->id.name, name);
1149 ctl->vcount = ctl->count = 1;
1150 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1151 ctl->min = 0;
1152 ctl->max = 1;
1153 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1154 }
1155
1156 static void
1157 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1158 const char *name, int gpr, int defval)
1159 {
1160 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1161 strcpy(ctl->id.name, name);
1162 ctl->vcount = ctl->count = 2;
1163 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1164 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1165 ctl->min = 0;
1166 ctl->max = 1;
1167 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1168 }
1169
1170 /*
1171 * Used for emu1010 - conversion from 32-bit capture inputs from HANA
1172 * to 2 x 16-bit registers in audigy - their values are read via DMA.
1173 * Conversion is performed by Audigy DSP instructions of FX8010.
1174 */
1175 static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1176 struct snd_emu10k1_fx8010_code *icode,
1177 u32 *ptr, int tmp, int bit_shifter16,
1178 int reg_in, int reg_out)
1179 {
1180 A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
1181 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
1182 A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
1183 A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
1184 A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
1185 A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
1186 A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
1187 A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
1188 return 1;
1189 }
1190
1191 /*
1192 * initial DSP configuration for Audigy
1193 */
1194
1195 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
1196 {
1197 int err, i, z, gpr, nctl;
1198 int bit_shifter16;
1199 const int playback = 10;
1200 const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
1201 const int stereo_mix = capture + 2;
1202 const int tmp = 0x88;
1203 u32 ptr;
1204 struct snd_emu10k1_fx8010_code *icode = NULL;
1205 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1206 u32 *gpr_map;
1207
1208 err = -ENOMEM;
1209 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1210 if (!icode)
1211 return err;
1212
1213 icode->gpr_map = (u_int32_t __user *) kcalloc(512 + 256 + 256 + 2 * 1024,
1214 sizeof(u_int32_t), GFP_KERNEL);
1215 if (!icode->gpr_map)
1216 goto __err_gpr;
1217 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1218 sizeof(*controls), GFP_KERNEL);
1219 if (!controls)
1220 goto __err_ctrls;
1221
1222 gpr_map = (u32 __force *)icode->gpr_map;
1223
1224 icode->tram_data_map = icode->gpr_map + 512;
1225 icode->tram_addr_map = icode->tram_data_map + 256;
1226 icode->code = icode->tram_addr_map + 256;
1227
1228 /* clear free GPRs */
1229 for (i = 0; i < 512; i++)
1230 set_bit(i, icode->gpr_valid);
1231
1232 /* clear TRAM data & address lines */
1233 for (i = 0; i < 256; i++)
1234 set_bit(i, icode->tram_valid);
1235
1236 strcpy(icode->name, "Audigy DSP code for ALSA");
1237 ptr = 0;
1238 nctl = 0;
1239 gpr = stereo_mix + 10;
1240 gpr_map[gpr++] = 0x00007fff;
1241 gpr_map[gpr++] = 0x00008000;
1242 gpr_map[gpr++] = 0x0000ffff;
1243 bit_shifter16 = gpr;
1244
1245 /* stop FX processor */
1246 snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
1247
1248 #if 1
1249 /* PCM front Playback Volume (independent from stereo mix)
1250 * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
1251 * where gpr contains attenuation from corresponding mixer control
1252 * (snd_emu10k1_init_stereo_control)
1253 */
1254 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
1255 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
1256 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
1257 gpr += 2;
1258
1259 /* PCM Surround Playback (independent from stereo mix) */
1260 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
1261 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
1262 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
1263 gpr += 2;
1264
1265 /* PCM Side Playback (independent from stereo mix) */
1266 if (emu->card_capabilities->spk71) {
1267 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
1268 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
1269 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
1270 gpr += 2;
1271 }
1272
1273 /* PCM Center Playback (independent from stereo mix) */
1274 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
1275 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
1276 gpr++;
1277
1278 /* PCM LFE Playback (independent from stereo mix) */
1279 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
1280 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
1281 gpr++;
1282
1283 /*
1284 * Stereo Mix
1285 */
1286 /* Wave (PCM) Playback Volume (will be renamed later) */
1287 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1288 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1289 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
1290 gpr += 2;
1291
1292 /* Synth Playback */
1293 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1294 A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1295 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
1296 gpr += 2;
1297
1298 /* Wave (PCM) Capture */
1299 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1300 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1301 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
1302 gpr += 2;
1303
1304 /* Synth Capture */
1305 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1306 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1307 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
1308 gpr += 2;
1309
1310 /*
1311 * inputs
1312 */
1313 #define A_ADD_VOLUME_IN(var,vol,input) \
1314 A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
1315
1316 /* emu1212 DSP 0 and DSP 1 Capture */
1317 if (emu->card_capabilities->emu_model) {
1318 if (emu->card_capabilities->ca0108_chip) {
1319 /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
1320 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
1321 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
1322 A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
1323 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
1324 } else {
1325 A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
1326 A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
1327 }
1328 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
1329 gpr += 2;
1330 }
1331 /* AC'97 Playback Volume - used only for mic (renamed later) */
1332 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
1333 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
1334 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
1335 gpr += 2;
1336 /* AC'97 Capture Volume - used only for mic */
1337 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
1338 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
1339 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
1340 gpr += 2;
1341
1342 /* mic capture buffer */
1343 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
1344
1345 /* Audigy CD Playback Volume */
1346 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
1347 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1348 snd_emu10k1_init_stereo_control(&controls[nctl++],
1349 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
1350 gpr, 0);
1351 gpr += 2;
1352 /* Audigy CD Capture Volume */
1353 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
1354 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1355 snd_emu10k1_init_stereo_control(&controls[nctl++],
1356 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
1357 gpr, 0);
1358 gpr += 2;
1359
1360 /* Optical SPDIF Playback Volume */
1361 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
1362 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1363 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
1364 gpr += 2;
1365 /* Optical SPDIF Capture Volume */
1366 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
1367 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1368 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
1369 gpr += 2;
1370
1371 /* Line2 Playback Volume */
1372 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
1373 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
1374 snd_emu10k1_init_stereo_control(&controls[nctl++],
1375 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
1376 gpr, 0);
1377 gpr += 2;
1378 /* Line2 Capture Volume */
1379 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
1380 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
1381 snd_emu10k1_init_stereo_control(&controls[nctl++],
1382 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
1383 gpr, 0);
1384 gpr += 2;
1385
1386 /* Philips ADC Playback Volume */
1387 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
1388 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
1389 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
1390 gpr += 2;
1391 /* Philips ADC Capture Volume */
1392 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
1393 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
1394 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
1395 gpr += 2;
1396
1397 /* Aux2 Playback Volume */
1398 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
1399 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
1400 snd_emu10k1_init_stereo_control(&controls[nctl++],
1401 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
1402 gpr, 0);
1403 gpr += 2;
1404 /* Aux2 Capture Volume */
1405 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
1406 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
1407 snd_emu10k1_init_stereo_control(&controls[nctl++],
1408 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
1409 gpr, 0);
1410 gpr += 2;
1411
1412 /* Stereo Mix Front Playback Volume */
1413 A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
1414 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1415 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
1416 gpr += 2;
1417
1418 /* Stereo Mix Surround Playback */
1419 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
1420 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1421 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
1422 gpr += 2;
1423
1424 /* Stereo Mix Center Playback */
1425 /* Center = sub = Left/2 + Right/2 */
1426 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
1427 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
1428 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
1429 gpr++;
1430
1431 /* Stereo Mix LFE Playback */
1432 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
1433 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
1434 gpr++;
1435
1436 if (emu->card_capabilities->spk71) {
1437 /* Stereo Mix Side Playback */
1438 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
1439 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1440 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
1441 gpr += 2;
1442 }
1443
1444 /*
1445 * outputs
1446 */
1447 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
1448 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
1449 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
1450
1451 #define _A_SWITCH(icode, ptr, dst, src, sw) \
1452 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
1453 #define A_SWITCH(icode, ptr, dst, src, sw) \
1454 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
1455 #define _A_SWITCH_NEG(icode, ptr, dst, src) \
1456 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
1457 #define A_SWITCH_NEG(icode, ptr, dst, src) \
1458 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
1459
1460
1461 /*
1462 * Process tone control
1463 */
1464 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
1465 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
1466 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
1467 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
1468 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
1469 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
1470 if (emu->card_capabilities->spk71) {
1471 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
1472 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
1473 }
1474
1475
1476 ctl = &controls[nctl + 0];
1477 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1478 strcpy(ctl->id.name, "Tone Control - Bass");
1479 ctl->vcount = 2;
1480 ctl->count = 10;
1481 ctl->min = 0;
1482 ctl->max = 40;
1483 ctl->value[0] = ctl->value[1] = 20;
1484 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
1485 ctl = &controls[nctl + 1];
1486 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1487 strcpy(ctl->id.name, "Tone Control - Treble");
1488 ctl->vcount = 2;
1489 ctl->count = 10;
1490 ctl->min = 0;
1491 ctl->max = 40;
1492 ctl->value[0] = ctl->value[1] = 20;
1493 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
1494
1495 #define BASS_GPR 0x8c
1496 #define TREBLE_GPR 0x96
1497
1498 for (z = 0; z < 5; z++) {
1499 int j;
1500 for (j = 0; j < 2; j++) {
1501 controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
1502 controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
1503 }
1504 }
1505 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
1506 int j, k, l, d;
1507 for (j = 0; j < 2; j++) { /* left/right */
1508 k = 0xb0 + (z * 8) + (j * 4);
1509 l = 0xe0 + (z * 8) + (j * 4);
1510 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
1511
1512 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
1513 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
1514 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
1515 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
1516 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
1517 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
1518
1519 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
1520 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
1521 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
1522 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
1523 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
1524 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
1525
1526 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
1527
1528 if (z == 2) /* center */
1529 break;
1530 }
1531 }
1532 nctl += 2;
1533
1534 #undef BASS_GPR
1535 #undef TREBLE_GPR
1536
1537 for (z = 0; z < 8; z++) {
1538 A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
1539 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
1540 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
1541 A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1542 }
1543 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
1544 gpr += 2;
1545
1546 /* Master volume (will be renamed later) */
1547 A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
1548 A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
1549 A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
1550 A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
1551 A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
1552 A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
1553 A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
1554 A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
1555 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
1556 gpr += 2;
1557
1558 /* analog speakers */
1559 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1560 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
1561 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
1562 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
1563 if (emu->card_capabilities->spk71)
1564 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
1565
1566 /* headphone */
1567 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1568
1569 /* digital outputs */
1570 /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
1571 if (emu->card_capabilities->emu_model) {
1572 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
1573 dev_info(emu->card->dev, "EMU outputs on\n");
1574 for (z = 0; z < 8; z++) {
1575 if (emu->card_capabilities->ca0108_chip) {
1576 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
1577 } else {
1578 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
1579 }
1580 }
1581 }
1582
1583 /* IEC958 Optical Raw Playback Switch */
1584 gpr_map[gpr++] = 0;
1585 gpr_map[gpr++] = 0x1008;
1586 gpr_map[gpr++] = 0xffff0000;
1587 for (z = 0; z < 2; z++) {
1588 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
1589 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
1590 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
1591 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
1592 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
1593 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
1594 A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
1595 if ((z==1) && (emu->card_capabilities->spdif_bug)) {
1596 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
1597 dev_info(emu->card->dev,
1598 "Installing spdif_bug patch: %s\n",
1599 emu->card_capabilities->name);
1600 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
1601 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1602 } else {
1603 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1604 }
1605 }
1606 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
1607 gpr += 2;
1608
1609 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
1610 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
1611 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
1612
1613 /* ADC buffer */
1614 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
1615 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
1616 #else
1617 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
1618 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
1619 #endif
1620
1621 if (emu->card_capabilities->emu_model) {
1622 if (emu->card_capabilities->ca0108_chip) {
1623 dev_info(emu->card->dev, "EMU2 inputs on\n");
1624 for (z = 0; z < 0x10; z++) {
1625 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
1626 bit_shifter16,
1627 A3_EMU32IN(z),
1628 A_FXBUS2(z*2) );
1629 }
1630 } else {
1631 dev_info(emu->card->dev, "EMU inputs on\n");
1632 /* Capture 16 (originally 8) channels of S32_LE sound */
1633
1634 /*
1635 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
1636 gpr, tmp);
1637 */
1638 /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
1639 /* A_P16VIN(0) is delayed by one sample,
1640 * so all other A_P16VIN channels will need to also be delayed
1641 */
1642 /* Left ADC in. 1 of 2 */
1643 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
1644 /* Right ADC in 1 of 2 */
1645 gpr_map[gpr++] = 0x00000000;
1646 /* Delaying by one sample: instead of copying the input
1647 * value A_P16VIN to output A_FXBUS2 as in the first channel,
1648 * we use an auxiliary register, delaying the value by one
1649 * sample
1650 */
1651 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
1652 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
1653 gpr_map[gpr++] = 0x00000000;
1654 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
1655 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
1656 gpr_map[gpr++] = 0x00000000;
1657 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
1658 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
1659 /* For 96kHz mode */
1660 /* Left ADC in. 2 of 2 */
1661 gpr_map[gpr++] = 0x00000000;
1662 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
1663 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
1664 /* Right ADC in 2 of 2 */
1665 gpr_map[gpr++] = 0x00000000;
1666 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
1667 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
1668 gpr_map[gpr++] = 0x00000000;
1669 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
1670 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
1671 gpr_map[gpr++] = 0x00000000;
1672 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
1673 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
1674 /* Pavel Hofman - we still have voices, A_FXBUS2s, and
1675 * A_P16VINs available -
1676 * let's add 8 more capture channels - total of 16
1677 */
1678 gpr_map[gpr++] = 0x00000000;
1679 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1680 bit_shifter16,
1681 A_GPR(gpr - 1),
1682 A_FXBUS2(0x10));
1683 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
1684 A_C_00000000, A_C_00000000);
1685 gpr_map[gpr++] = 0x00000000;
1686 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1687 bit_shifter16,
1688 A_GPR(gpr - 1),
1689 A_FXBUS2(0x12));
1690 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
1691 A_C_00000000, A_C_00000000);
1692 gpr_map[gpr++] = 0x00000000;
1693 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1694 bit_shifter16,
1695 A_GPR(gpr - 1),
1696 A_FXBUS2(0x14));
1697 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
1698 A_C_00000000, A_C_00000000);
1699 gpr_map[gpr++] = 0x00000000;
1700 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1701 bit_shifter16,
1702 A_GPR(gpr - 1),
1703 A_FXBUS2(0x16));
1704 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
1705 A_C_00000000, A_C_00000000);
1706 gpr_map[gpr++] = 0x00000000;
1707 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1708 bit_shifter16,
1709 A_GPR(gpr - 1),
1710 A_FXBUS2(0x18));
1711 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
1712 A_C_00000000, A_C_00000000);
1713 gpr_map[gpr++] = 0x00000000;
1714 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1715 bit_shifter16,
1716 A_GPR(gpr - 1),
1717 A_FXBUS2(0x1a));
1718 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
1719 A_C_00000000, A_C_00000000);
1720 gpr_map[gpr++] = 0x00000000;
1721 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1722 bit_shifter16,
1723 A_GPR(gpr - 1),
1724 A_FXBUS2(0x1c));
1725 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
1726 A_C_00000000, A_C_00000000);
1727 gpr_map[gpr++] = 0x00000000;
1728 snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
1729 bit_shifter16,
1730 A_GPR(gpr - 1),
1731 A_FXBUS2(0x1e));
1732 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
1733 A_C_00000000, A_C_00000000);
1734 }
1735
1736 #if 0
1737 for (z = 4; z < 8; z++) {
1738 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1739 }
1740 for (z = 0xc; z < 0x10; z++) {
1741 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1742 }
1743 #endif
1744 } else {
1745 /* EFX capture - capture the 16 EXTINs */
1746 /* Capture 16 channels of S16_LE sound */
1747 for (z = 0; z < 16; z++) {
1748 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
1749 }
1750 }
1751
1752 #endif /* JCD test */
1753 /*
1754 * ok, set up done..
1755 */
1756
1757 if (gpr > tmp) {
1758 snd_BUG();
1759 err = -EIO;
1760 goto __err;
1761 }
1762 /* clear remaining instruction memory */
1763 while (ptr < 0x400)
1764 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
1765
1766 icode->gpr_add_control_count = nctl;
1767 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
1768 emu->support_tlv = 1; /* support TLV */
1769 err = snd_emu10k1_icode_poke(emu, icode, true);
1770 emu->support_tlv = 0; /* clear again */
1771
1772 __err:
1773 kfree(controls);
1774 __err_ctrls:
1775 kfree((void __force *)icode->gpr_map);
1776 __err_gpr:
1777 kfree(icode);
1778 return err;
1779 }
1780
1781
1782 /*
1783 * initial DSP configuration for Emu10k1
1784 */
1785
1786 /* when volume = max, then copy only to avoid volume modification */
1787 /* with iMAC0 (negative values) */
1788 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1789 {
1790 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
1791 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1792 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
1793 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
1794 }
1795 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1796 {
1797 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1798 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1799 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
1800 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
1801 OP(icode, ptr, iMAC0, dst, dst, src, vol);
1802 }
1803 static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1804 {
1805 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
1806 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1807 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
1808 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
1809 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
1810 }
1811
1812 #define VOLUME(icode, ptr, dst, src, vol) \
1813 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1814 #define VOLUME_IN(icode, ptr, dst, src, vol) \
1815 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1816 #define VOLUME_ADD(icode, ptr, dst, src, vol) \
1817 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1818 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
1819 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1820 #define VOLUME_OUT(icode, ptr, dst, src, vol) \
1821 _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1822 #define _SWITCH(icode, ptr, dst, src, sw) \
1823 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1824 #define SWITCH(icode, ptr, dst, src, sw) \
1825 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1826 #define SWITCH_IN(icode, ptr, dst, src, sw) \
1827 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1828 #define _SWITCH_NEG(icode, ptr, dst, src) \
1829 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1830 #define SWITCH_NEG(icode, ptr, dst, src) \
1831 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1832
1833
1834 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
1835 {
1836 int err, i, z, gpr, tmp, playback, capture;
1837 u32 ptr;
1838 struct snd_emu10k1_fx8010_code *icode;
1839 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
1840 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1841 u32 *gpr_map;
1842
1843 err = -ENOMEM;
1844 icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1845 if (!icode)
1846 return err;
1847
1848 icode->gpr_map = (u_int32_t __user *) kcalloc(256 + 160 + 160 + 2 * 512,
1849 sizeof(u_int32_t), GFP_KERNEL);
1850 if (!icode->gpr_map)
1851 goto __err_gpr;
1852
1853 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1854 sizeof(struct snd_emu10k1_fx8010_control_gpr),
1855 GFP_KERNEL);
1856 if (!controls)
1857 goto __err_ctrls;
1858
1859 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
1860 if (!ipcm)
1861 goto __err_ipcm;
1862
1863 gpr_map = (u32 __force *)icode->gpr_map;
1864
1865 icode->tram_data_map = icode->gpr_map + 256;
1866 icode->tram_addr_map = icode->tram_data_map + 160;
1867 icode->code = icode->tram_addr_map + 160;
1868
1869 /* clear free GPRs */
1870 for (i = 0; i < 256; i++)
1871 set_bit(i, icode->gpr_valid);
1872
1873 /* clear TRAM data & address lines */
1874 for (i = 0; i < 160; i++)
1875 set_bit(i, icode->tram_valid);
1876
1877 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
1878 ptr = 0; i = 0;
1879 /* we have 12 inputs */
1880 playback = SND_EMU10K1_INPUTS;
1881 /* we have 6 playback channels and tone control doubles */
1882 capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
1883 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
1884 tmp = 0x88; /* we need 4 temporary GPR */
1885 /* from 0x8c to 0xff is the area for tone control */
1886
1887 /* stop FX processor */
1888 snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
1889
1890 /*
1891 * Process FX Buses
1892 */
1893 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
1894 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
1895 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
1896 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
1897 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
1898 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
1899 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
1900 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
1901 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
1902 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
1903 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
1904 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
1905
1906 /* Raw S/PDIF PCM */
1907 ipcm->substream = 0;
1908 ipcm->channels = 2;
1909 ipcm->tram_start = 0;
1910 ipcm->buffer_size = (64 * 1024) / 2;
1911 ipcm->gpr_size = gpr++;
1912 ipcm->gpr_ptr = gpr++;
1913 ipcm->gpr_count = gpr++;
1914 ipcm->gpr_tmpcount = gpr++;
1915 ipcm->gpr_trigger = gpr++;
1916 ipcm->gpr_running = gpr++;
1917 ipcm->etram[0] = 0;
1918 ipcm->etram[1] = 1;
1919
1920 gpr_map[gpr + 0] = 0xfffff000;
1921 gpr_map[gpr + 1] = 0xffff0000;
1922 gpr_map[gpr + 2] = 0x70000000;
1923 gpr_map[gpr + 3] = 0x00000007;
1924 gpr_map[gpr + 4] = 0x001f << 11;
1925 gpr_map[gpr + 5] = 0x001c << 11;
1926 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
1927 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
1928 gpr_map[gpr + 8] = 0x2000000 + (2<<11);
1929 gpr_map[gpr + 9] = 0x4000000 + (2<<11);
1930 gpr_map[gpr + 10] = 1<<11;
1931 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
1932 gpr_map[gpr + 12] = 0;
1933
1934 /* if the trigger flag is not set, skip */
1935 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
1936 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
1937 /* if the running flag is set, we're running */
1938 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
1939 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
1940 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
1941 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
1942 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
1943 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
1944 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
1945
1946 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
1947 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
1948 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
1949 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
1950
1951 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
1952 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1953 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1954 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1955 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
1956
1957 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
1958 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1959 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1960 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1961 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
1962
1963 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
1964 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
1965 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
1966 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
1967 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
1968
1969 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
1970 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1971 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
1972 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
1973 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
1974
1975 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
1976 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
1977
1978 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
1979 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
1980
1981 /* 24: */
1982 gpr += 13;
1983
1984 /* Wave Playback Volume */
1985 for (z = 0; z < 2; z++)
1986 VOLUME(icode, &ptr, playback + z, z, gpr + z);
1987 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
1988 gpr += 2;
1989
1990 /* Wave Surround Playback Volume */
1991 for (z = 0; z < 2; z++)
1992 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
1993 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
1994 gpr += 2;
1995
1996 /* Wave Center/LFE Playback Volume */
1997 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
1998 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
1999 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
2000 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
2001 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
2002 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
2003
2004 /* Wave Capture Volume + Switch */
2005 for (z = 0; z < 2; z++) {
2006 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
2007 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
2008 }
2009 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
2010 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
2011 gpr += 4;
2012
2013 /* Synth Playback Volume */
2014 for (z = 0; z < 2; z++)
2015 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
2016 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
2017 gpr += 2;
2018
2019 /* Synth Capture Volume + Switch */
2020 for (z = 0; z < 2; z++) {
2021 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
2022 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2023 }
2024 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
2025 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
2026 gpr += 4;
2027
2028 /* Surround Digital Playback Volume (renamed later without Digital) */
2029 for (z = 0; z < 2; z++)
2030 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
2031 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
2032 gpr += 2;
2033
2034 /* Surround Capture Volume + Switch */
2035 for (z = 0; z < 2; z++) {
2036 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
2037 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2038 }
2039 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
2040 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
2041 gpr += 4;
2042
2043 /* Center Playback Volume (renamed later without Digital) */
2044 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
2045 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
2046
2047 /* LFE Playback Volume + Switch (renamed later without Digital) */
2048 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
2049 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
2050
2051 /* Front Playback Volume */
2052 for (z = 0; z < 2; z++)
2053 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
2054 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
2055 gpr += 2;
2056
2057 /* Front Capture Volume + Switch */
2058 for (z = 0; z < 2; z++) {
2059 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
2060 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2061 }
2062 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
2063 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
2064 gpr += 3;
2065
2066 /*
2067 * Process inputs
2068 */
2069
2070 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
2071 /* AC'97 Playback Volume */
2072 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
2073 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
2074 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
2075 /* AC'97 Capture Volume */
2076 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
2077 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
2078 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
2079 }
2080
2081 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
2082 /* IEC958 TTL Playback Volume */
2083 for (z = 0; z < 2; z++)
2084 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
2085 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
2086 gpr += 2;
2087
2088 /* IEC958 TTL Capture Volume + Switch */
2089 for (z = 0; z < 2; z++) {
2090 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
2091 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2092 }
2093 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
2094 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
2095 gpr += 4;
2096 }
2097
2098 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
2099 /* Zoom Video Playback Volume */
2100 for (z = 0; z < 2; z++)
2101 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
2102 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
2103 gpr += 2;
2104
2105 /* Zoom Video Capture Volume + Switch */
2106 for (z = 0; z < 2; z++) {
2107 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
2108 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2109 }
2110 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
2111 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
2112 gpr += 4;
2113 }
2114
2115 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
2116 /* IEC958 Optical Playback Volume */
2117 for (z = 0; z < 2; z++)
2118 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
2119 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
2120 gpr += 2;
2121
2122 /* IEC958 Optical Capture Volume */
2123 for (z = 0; z < 2; z++) {
2124 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
2125 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2126 }
2127 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
2128 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
2129 gpr += 4;
2130 }
2131
2132 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
2133 /* Line LiveDrive Playback Volume */
2134 for (z = 0; z < 2; z++)
2135 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
2136 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
2137 gpr += 2;
2138
2139 /* Line LiveDrive Capture Volume + Switch */
2140 for (z = 0; z < 2; z++) {
2141 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
2142 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2143 }
2144 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
2145 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
2146 gpr += 4;
2147 }
2148
2149 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
2150 /* IEC958 Coax Playback Volume */
2151 for (z = 0; z < 2; z++)
2152 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
2153 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
2154 gpr += 2;
2155
2156 /* IEC958 Coax Capture Volume + Switch */
2157 for (z = 0; z < 2; z++) {
2158 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
2159 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2160 }
2161 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
2162 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
2163 gpr += 4;
2164 }
2165
2166 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
2167 /* Line LiveDrive Playback Volume */
2168 for (z = 0; z < 2; z++)
2169 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
2170 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
2171 controls[i-1].id.index = 1;
2172 gpr += 2;
2173
2174 /* Line LiveDrive Capture Volume */
2175 for (z = 0; z < 2; z++) {
2176 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
2177 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2178 }
2179 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
2180 controls[i-1].id.index = 1;
2181 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
2182 controls[i-1].id.index = 1;
2183 gpr += 4;
2184 }
2185
2186 /*
2187 * Process tone control
2188 */
2189 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
2190 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
2191 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
2192 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
2193 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
2194 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
2195
2196 ctl = &controls[i + 0];
2197 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2198 strcpy(ctl->id.name, "Tone Control - Bass");
2199 ctl->vcount = 2;
2200 ctl->count = 10;
2201 ctl->min = 0;
2202 ctl->max = 40;
2203 ctl->value[0] = ctl->value[1] = 20;
2204 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2205 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
2206 ctl = &controls[i + 1];
2207 ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2208 strcpy(ctl->id.name, "Tone Control - Treble");
2209 ctl->vcount = 2;
2210 ctl->count = 10;
2211 ctl->min = 0;
2212 ctl->max = 40;
2213 ctl->value[0] = ctl->value[1] = 20;
2214 ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2215 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
2216
2217 #define BASS_GPR 0x8c
2218 #define TREBLE_GPR 0x96
2219
2220 for (z = 0; z < 5; z++) {
2221 int j;
2222 for (j = 0; j < 2; j++) {
2223 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
2224 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
2225 }
2226 }
2227 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
2228 int j, k, l, d;
2229 for (j = 0; j < 2; j++) { /* left/right */
2230 k = 0xa0 + (z * 8) + (j * 4);
2231 l = 0xd0 + (z * 8) + (j * 4);
2232 d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
2233
2234 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
2235 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
2236 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
2237 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
2238 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
2239 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
2240
2241 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
2242 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
2243 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
2244 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
2245 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
2246 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
2247
2248 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
2249
2250 if (z == 2) /* center */
2251 break;
2252 }
2253 }
2254 i += 2;
2255
2256 #undef BASS_GPR
2257 #undef TREBLE_GPR
2258
2259 for (z = 0; z < 6; z++) {
2260 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
2261 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
2262 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2263 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2264 }
2265 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
2266 gpr += 2;
2267
2268 /*
2269 * Process outputs
2270 */
2271 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
2272 /* AC'97 Playback Volume */
2273
2274 for (z = 0; z < 2; z++)
2275 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
2276 }
2277
2278 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
2279 /* IEC958 Optical Raw Playback Switch */
2280
2281 for (z = 0; z < 2; z++) {
2282 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
2283 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
2284 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
2285 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2286 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
2287 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2288 #endif
2289 }
2290
2291 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
2292 gpr += 2;
2293 }
2294
2295 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
2296 /* Headphone Playback Volume */
2297
2298 for (z = 0; z < 2; z++) {
2299 SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
2300 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
2301 SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
2302 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2303 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
2304 }
2305
2306 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
2307 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
2308 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
2309 controls[i-1].id.index = 1;
2310 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
2311 controls[i-1].id.index = 1;
2312
2313 gpr += 4;
2314 }
2315
2316 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
2317 for (z = 0; z < 2; z++)
2318 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
2319
2320 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
2321 for (z = 0; z < 2; z++)
2322 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
2323
2324 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
2325 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2326 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
2327 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
2328 #else
2329 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
2330 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
2331 #endif
2332 }
2333
2334 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
2335 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2336 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
2337 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
2338 #else
2339 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
2340 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
2341 #endif
2342 }
2343
2344 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
2345 for (z = 0; z < 2; z++)
2346 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
2347 #endif
2348
2349 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
2350 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
2351
2352 /* EFX capture - capture the 16 EXTINS */
2353 if (emu->card_capabilities->sblive51) {
2354 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
2355 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
2356 *
2357 * Since only 14 of the 16 EXTINs are used, this is not a big problem.
2358 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
2359 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
2360 * channel. Multitrack recorders will still see the center/lfe output signal
2361 * on the second and third channels.
2362 */
2363 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
2364 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
2365 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
2366 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
2367 for (z = 4; z < 14; z++)
2368 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2369 } else {
2370 for (z = 0; z < 16; z++)
2371 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2372 }
2373
2374
2375 if (gpr > tmp) {
2376 snd_BUG();
2377 err = -EIO;
2378 goto __err;
2379 }
2380 if (i > SND_EMU10K1_GPR_CONTROLS) {
2381 snd_BUG();
2382 err = -EIO;
2383 goto __err;
2384 }
2385
2386 /* clear remaining instruction memory */
2387 while (ptr < 0x200)
2388 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
2389
2390 if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
2391 goto __err;
2392 icode->gpr_add_control_count = i;
2393 icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
2394 emu->support_tlv = 1; /* support TLV */
2395 err = snd_emu10k1_icode_poke(emu, icode, true);
2396 emu->support_tlv = 0; /* clear again */
2397 if (err >= 0)
2398 err = snd_emu10k1_ipcm_poke(emu, ipcm);
2399 __err:
2400 kfree(ipcm);
2401 __err_ipcm:
2402 kfree(controls);
2403 __err_ctrls:
2404 kfree((void __force *)icode->gpr_map);
2405 __err_gpr:
2406 kfree(icode);
2407 return err;
2408 }
2409
2410 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
2411 {
2412 spin_lock_init(&emu->fx8010.irq_lock);
2413 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
2414 if (emu->audigy)
2415 return _snd_emu10k1_audigy_init_efx(emu);
2416 else
2417 return _snd_emu10k1_init_efx(emu);
2418 }
2419
2420 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
2421 {
2422 /* stop processor */
2423 if (emu->audigy)
2424 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
2425 else
2426 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
2427 }
2428
2429 #if 0 /* FIXME: who use them? */
2430 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
2431 {
2432 if (output < 0 || output >= 6)
2433 return -EINVAL;
2434 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
2435 return 0;
2436 }
2437
2438 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
2439 {
2440 if (output < 0 || output >= 6)
2441 return -EINVAL;
2442 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
2443 return 0;
2444 }
2445 #endif
2446
2447 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
2448 {
2449 u8 size_reg = 0;
2450
2451 /* size is in samples */
2452 if (size != 0) {
2453 size = (size - 1) >> 13;
2454
2455 while (size) {
2456 size >>= 1;
2457 size_reg++;
2458 }
2459 size = 0x2000 << size_reg;
2460 }
2461 if ((emu->fx8010.etram_pages.bytes / 2) == size)
2462 return 0;
2463 spin_lock_irq(&emu->emu_lock);
2464 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2465 spin_unlock_irq(&emu->emu_lock);
2466 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
2467 snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
2468 if (emu->fx8010.etram_pages.area != NULL) {
2469 snd_dma_free_pages(&emu->fx8010.etram_pages);
2470 emu->fx8010.etram_pages.area = NULL;
2471 emu->fx8010.etram_pages.bytes = 0;
2472 }
2473
2474 if (size > 0) {
2475 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
2476 size * 2, &emu->fx8010.etram_pages) < 0)
2477 return -ENOMEM;
2478 memset(emu->fx8010.etram_pages.area, 0, size * 2);
2479 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2480 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2481 spin_lock_irq(&emu->emu_lock);
2482 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2483 spin_unlock_irq(&emu->emu_lock);
2484 }
2485
2486 return 0;
2487 }
2488
2489 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
2490 {
2491 return 0;
2492 }
2493
2494 static void copy_string(char *dst, char *src, char *null, int idx)
2495 {
2496 if (src == NULL)
2497 sprintf(dst, "%s %02X", null, idx);
2498 else
2499 strcpy(dst, src);
2500 }
2501
2502 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
2503 struct snd_emu10k1_fx8010_info *info)
2504 {
2505 char **fxbus, **extin, **extout;
2506 unsigned short fxbus_mask, extin_mask, extout_mask;
2507 int res;
2508
2509 info->internal_tram_size = emu->fx8010.itram_size;
2510 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
2511 fxbus = fxbuses;
2512 extin = emu->audigy ? audigy_ins : creative_ins;
2513 extout = emu->audigy ? audigy_outs : creative_outs;
2514 fxbus_mask = emu->fx8010.fxbus_mask;
2515 extin_mask = emu->fx8010.extin_mask;
2516 extout_mask = emu->fx8010.extout_mask;
2517 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
2518 copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
2519 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
2520 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2521 }
2522 for (res = 16; res < 32; res++, extout++)
2523 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2524 info->gpr_controls = emu->fx8010.gpr_count;
2525 }
2526
2527 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
2528 {
2529 struct snd_emu10k1 *emu = hw->private_data;
2530 struct snd_emu10k1_fx8010_info *info;
2531 struct snd_emu10k1_fx8010_code *icode;
2532 struct snd_emu10k1_fx8010_pcm_rec *ipcm;
2533 unsigned int addr;
2534 void __user *argp = (void __user *)arg;
2535 int res;
2536
2537 switch (cmd) {
2538 case SNDRV_EMU10K1_IOCTL_PVERSION:
2539 emu->support_tlv = 1;
2540 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
2541 case SNDRV_EMU10K1_IOCTL_INFO:
2542 info = kmalloc(sizeof(*info), GFP_KERNEL);
2543 if (!info)
2544 return -ENOMEM;
2545 snd_emu10k1_fx8010_info(emu, info);
2546 if (copy_to_user(argp, info, sizeof(*info))) {
2547 kfree(info);
2548 return -EFAULT;
2549 }
2550 kfree(info);
2551 return 0;
2552 case SNDRV_EMU10K1_IOCTL_CODE_POKE:
2553 if (!capable(CAP_SYS_ADMIN))
2554 return -EPERM;
2555
2556 icode = memdup_user(argp, sizeof(*icode));
2557 if (IS_ERR(icode))
2558 return PTR_ERR(icode);
2559 res = snd_emu10k1_icode_poke(emu, icode, false);
2560 kfree(icode);
2561 return res;
2562 case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
2563 icode = memdup_user(argp, sizeof(*icode));
2564 if (IS_ERR(icode))
2565 return PTR_ERR(icode);
2566 res = snd_emu10k1_icode_peek(emu, icode);
2567 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
2568 kfree(icode);
2569 return -EFAULT;
2570 }
2571 kfree(icode);
2572 return res;
2573 case SNDRV_EMU10K1_IOCTL_PCM_POKE:
2574 ipcm = memdup_user(argp, sizeof(*ipcm));
2575 if (IS_ERR(ipcm))
2576 return PTR_ERR(ipcm);
2577 res = snd_emu10k1_ipcm_poke(emu, ipcm);
2578 kfree(ipcm);
2579 return res;
2580 case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
2581 ipcm = memdup_user(argp, sizeof(*ipcm));
2582 if (IS_ERR(ipcm))
2583 return PTR_ERR(ipcm);
2584 res = snd_emu10k1_ipcm_peek(emu, ipcm);
2585 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
2586 kfree(ipcm);
2587 return -EFAULT;
2588 }
2589 kfree(ipcm);
2590 return res;
2591 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
2592 if (!capable(CAP_SYS_ADMIN))
2593 return -EPERM;
2594 if (get_user(addr, (unsigned int __user *)argp))
2595 return -EFAULT;
2596 mutex_lock(&emu->fx8010.lock);
2597 res = snd_emu10k1_fx8010_tram_setup(emu, addr);
2598 mutex_unlock(&emu->fx8010.lock);
2599 return res;
2600 case SNDRV_EMU10K1_IOCTL_STOP:
2601 if (!capable(CAP_SYS_ADMIN))
2602 return -EPERM;
2603 if (emu->audigy)
2604 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2605 else
2606 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2607 return 0;
2608 case SNDRV_EMU10K1_IOCTL_CONTINUE:
2609 if (!capable(CAP_SYS_ADMIN))
2610 return -EPERM;
2611 if (emu->audigy)
2612 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
2613 else
2614 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
2615 return 0;
2616 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
2617 if (!capable(CAP_SYS_ADMIN))
2618 return -EPERM;
2619 if (emu->audigy)
2620 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
2621 else
2622 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
2623 udelay(10);
2624 if (emu->audigy)
2625 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2626 else
2627 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2628 return 0;
2629 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
2630 if (!capable(CAP_SYS_ADMIN))
2631 return -EPERM;
2632 if (get_user(addr, (unsigned int __user *)argp))
2633 return -EFAULT;
2634 if (addr > 0x1ff)
2635 return -EINVAL;
2636 if (emu->audigy)
2637 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
2638 else
2639 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
2640 udelay(10);
2641 if (emu->audigy)
2642 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
2643 else
2644 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
2645 return 0;
2646 case SNDRV_EMU10K1_IOCTL_DBG_READ:
2647 if (emu->audigy)
2648 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
2649 else
2650 addr = snd_emu10k1_ptr_read(emu, DBG, 0);
2651 if (put_user(addr, (unsigned int __user *)argp))
2652 return -EFAULT;
2653 return 0;
2654 }
2655 return -ENOTTY;
2656 }
2657
2658 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
2659 {
2660 return 0;
2661 }
2662
2663 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
2664 {
2665 struct snd_hwdep *hw;
2666 int err;
2667
2668 if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
2669 return err;
2670 strcpy(hw->name, "EMU10K1 (FX8010)");
2671 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
2672 hw->ops.open = snd_emu10k1_fx8010_open;
2673 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
2674 hw->ops.release = snd_emu10k1_fx8010_release;
2675 hw->private_data = emu;
2676 return 0;
2677 }
2678
2679 #ifdef CONFIG_PM_SLEEP
2680 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
2681 {
2682 int len;
2683
2684 len = emu->audigy ? 0x200 : 0x100;
2685 emu->saved_gpr = kmalloc(len * 4, GFP_KERNEL);
2686 if (! emu->saved_gpr)
2687 return -ENOMEM;
2688 len = emu->audigy ? 0x100 : 0xa0;
2689 emu->tram_val_saved = kmalloc(len * 4, GFP_KERNEL);
2690 emu->tram_addr_saved = kmalloc(len * 4, GFP_KERNEL);
2691 if (! emu->tram_val_saved || ! emu->tram_addr_saved)
2692 return -ENOMEM;
2693 len = emu->audigy ? 2 * 1024 : 2 * 512;
2694 emu->saved_icode = vmalloc(len * 4);
2695 if (! emu->saved_icode)
2696 return -ENOMEM;
2697 return 0;
2698 }
2699
2700 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
2701 {
2702 kfree(emu->saved_gpr);
2703 kfree(emu->tram_val_saved);
2704 kfree(emu->tram_addr_saved);
2705 vfree(emu->saved_icode);
2706 }
2707
2708 /*
2709 * save/restore GPR, TRAM and codes
2710 */
2711 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
2712 {
2713 int i, len;
2714
2715 len = emu->audigy ? 0x200 : 0x100;
2716 for (i = 0; i < len; i++)
2717 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
2718
2719 len = emu->audigy ? 0x100 : 0xa0;
2720 for (i = 0; i < len; i++) {
2721 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
2722 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
2723 if (emu->audigy) {
2724 emu->tram_addr_saved[i] >>= 12;
2725 emu->tram_addr_saved[i] |=
2726 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
2727 }
2728 }
2729
2730 len = emu->audigy ? 2 * 1024 : 2 * 512;
2731 for (i = 0; i < len; i++)
2732 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
2733 }
2734
2735 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
2736 {
2737 int i, len;
2738
2739 /* set up TRAM */
2740 if (emu->fx8010.etram_pages.bytes > 0) {
2741 unsigned size, size_reg = 0;
2742 size = emu->fx8010.etram_pages.bytes / 2;
2743 size = (size - 1) >> 13;
2744 while (size) {
2745 size >>= 1;
2746 size_reg++;
2747 }
2748 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2749 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2750 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2751 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2752 }
2753
2754 if (emu->audigy)
2755 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
2756 else
2757 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
2758
2759 len = emu->audigy ? 0x200 : 0x100;
2760 for (i = 0; i < len; i++)
2761 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
2762
2763 len = emu->audigy ? 0x100 : 0xa0;
2764 for (i = 0; i < len; i++) {
2765 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
2766 emu->tram_val_saved[i]);
2767 if (! emu->audigy)
2768 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2769 emu->tram_addr_saved[i]);
2770 else {
2771 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2772 emu->tram_addr_saved[i] << 12);
2773 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2774 emu->tram_addr_saved[i] >> 20);
2775 }
2776 }
2777
2778 len = emu->audigy ? 2 * 1024 : 2 * 512;
2779 for (i = 0; i < len; i++)
2780 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
2781
2782 /* start FX processor when the DSP code is updated */
2783 if (emu->audigy)
2784 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2785 else
2786 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2787 }
2788 #endif
Ubuntu Artful kernel mirror