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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
4 * Driver p16v chips
5 * Version: 0.21
6 *
7 * FEATURES currently supported:
8 * Output fixed at S32_LE, 2 channel to hw:0,0
9 * Rates: 44.1, 48, 96, 192.
10 *
11 * Changelog:
12 * 0.8
13 * Use separate card based buffer for periods table.
14 * 0.9
15 * Use 2 channel output streams instead of 8 channel.
16 * (8 channel output streams might be good for ASIO type output)
17 * Corrected speaker output, so Front -> Front etc.
18 * 0.10
19 * Fixed missed interrupts.
20 * 0.11
21 * Add Sound card model number and names.
22 * Add Analog volume controls.
23 * 0.12
24 * Corrected playback interrupts. Now interrupt per period, instead of half period.
25 * 0.13
26 * Use single trigger for multichannel.
27 * 0.14
28 * Mic capture now works at fixed: S32_LE, 96000Hz, Stereo.
29 * 0.15
30 * Force buffer_size / period_size == INTEGER.
31 * 0.16
32 * Update p16v.c to work with changed alsa api.
33 * 0.17
34 * Update p16v.c to work with changed alsa api. Removed boot_devs.
35 * 0.18
36 * Merging with snd-emu10k1 driver.
37 * 0.19
38 * One stereo channel at 24bit now works.
39 * 0.20
40 * Added better register defines.
41 * 0.21
42 * Split from p16v.c
43 *
44 * BUGS:
45 * Some stability problems when unloading the snd-p16v kernel module.
46 * --
47 *
48 * TODO:
49 * SPDIF out.
50 * Find out how to change capture sample rates. E.g. To record SPDIF at 48000Hz.
51 * Currently capture fixed at 48000Hz.
52 *
53 * --
54 * GENERAL INFO:
55 * Model: SB0240
56 * P16V Chip: CA0151-DBS
57 * Audigy 2 Chip: CA0102-IAT
58 * AC97 Codec: STAC 9721
59 * ADC: Philips 1361T (Stereo 24bit)
60 * DAC: CS4382-K (8-channel, 24bit, 192Khz)
61 *
62 * This code was initially based on code from ALSA's emu10k1x.c which is:
63 * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
64 */
65
66 /********************************************************************************************************/
67 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */
68 /********************************************************************************************************/
69
70 /* The sample rate of the SPDIF outputs is set by modifying a register in the EMU10K2 PTR register A_SPDIF_SAMPLERATE.
71 * The sample rate is also controlled by the same registers that control the rate of the EMU10K2 sample rate converters.
72 */
73
74 /* Initially all registers from 0x00 to 0x3f have zero contents. */
75 #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
76 /* One list entry: 4 bytes for DMA address,
77 * 4 bytes for period_size << 16.
78 * One list entry is 8 bytes long.
79 * One list entry for each period in the buffer.
80 */
81 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
82 #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
83 #define PLAYBACK_UNKNOWN3 0x03 /* Not used */
84 #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */
85 #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */
86 #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
87 #define PLAYBACK_FIFO_END_ADDRESS 0x07 /* Playback FIFO end address */
88 #define PLAYBACK_FIFO_POINTER 0x08 /* Playback FIFO pointer and number of valid sound samples in cache */
89 #define PLAYBACK_UNKNOWN9 0x09 /* Not used */
90 #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
91 #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
92 #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
93 #define CAPTURE_FIFO_POINTER 0x13 /* Capture FIFO pointer and number of valid sound samples in cache */
94 #define CAPTURE_P16V_VOLUME1 0x14 /* Low: Capture volume 0xXXXX3030 */
95 #define CAPTURE_P16V_VOLUME2 0x15 /* High:Has no effect on capture volume */
96 #define CAPTURE_P16V_SOURCE 0x16 /* P16V source select. Set to 0x0700E4E5 for AC97 CAPTURE */
97 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
98 * 1 = Capture output 1.
99 * 2 = Capture output 2.
100 * 3 = Capture output 3.
101 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
102 * 1 = Capture output 1.
103 * 2 = Capture output 2.
104 * 3 = Capture output 3.
105 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
106 * 1 = Capture output 1.
107 * 2 = Capture output 2.
108 * 3 = Capture output 3.
109 * [7:6] Capture input 3 channel select. 0 = Capture output 0.
110 * 1 = Capture output 1.
111 * 2 = Capture output 2.
112 * 3 = Capture output 3.
113 * [9:8] Playback input 0 channel select. 0 = Play output 0.
114 * 1 = Play output 1.
115 * 2 = Play output 2.
116 * 3 = Play output 3.
117 * [11:10] Playback input 1 channel select. 0 = Play output 0.
118 * 1 = Play output 1.
119 * 2 = Play output 2.
120 * 3 = Play output 3.
121 * [13:12] Playback input 2 channel select. 0 = Play output 0.
122 * 1 = Play output 1.
123 * 2 = Play output 2.
124 * 3 = Play output 3.
125 * [15:14] Playback input 3 channel select. 0 = Play output 0.
126 * 1 = Play output 1.
127 * 2 = Play output 2.
128 * 3 = Play output 3.
129 * [19:16] Playback mixer output enable. 1 bit per channel.
130 * [23:20] Capture mixer output enable. 1 bit per channel.
131 * [26:24] FX engine channel capture 0 = 0x60-0x67.
132 * 1 = 0x68-0x6f.
133 * 2 = 0x70-0x77.
134 * 3 = 0x78-0x7f.
135 * 4 = 0x80-0x87.
136 * 5 = 0x88-0x8f.
137 * 6 = 0x90-0x97.
138 * 7 = 0x98-0x9f.
139 * [31:27] Not used.
140 */
141
142 /* 0x1 = capture on.
143 * 0x100 = capture off.
144 * 0x200 = capture off.
145 * 0x1000 = capture off.
146 */
147 #define CAPTURE_RATE_STATUS 0x17 /* Capture sample rate. Read only */
148 /* [15:0] Not used.
149 * [18:16] Channel 0 Detected sample rate. 0 - 44.1khz
150 * 1 - 48 khz
151 * 2 - 96 khz
152 * 3 - 192 khz
153 * 7 - undefined rate.
154 * [19] Channel 0. 1 - Valid, 0 - Not Valid.
155 * [22:20] Channel 1 Detected sample rate.
156 * [23] Channel 1. 1 - Valid, 0 - Not Valid.
157 * [26:24] Channel 2 Detected sample rate.
158 * [27] Channel 2. 1 - Valid, 0 - Not Valid.
159 * [30:28] Channel 3 Detected sample rate.
160 * [31] Channel 3. 1 - Valid, 0 - Not Valid.
161 */
162 /* 0x18 - 0x1f unused */
163 #define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played. Read only */
164 /* 0x21 - 0x3f unused */
165 #define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */
166 /* Playback (0x1<<channel_id) Don't touch high 16bits. */
167 /* Capture (0x100<<channel_id). not tested */
168 /* Start Playback [3:0] (one bit per channel)
169 * Start Capture [11:8] (one bit per channel)
170 * Record source select for channel 0 [18:16]
171 * Record source select for channel 1 [22:20]
172 * Record source select for channel 2 [26:24]
173 * Record source select for channel 3 [30:28]
174 * 0 - SPDIF channel.
175 * 1 - I2S channel.
176 * 2 - SRC48 channel.
177 * 3 - SRCMulti_SPDIF channel.
178 * 4 - SRCMulti_I2S channel.
179 * 5 - SPDIF channel.
180 * 6 - fxengine capture.
181 * 7 - AC97 capture.
182 */
183 /* Default 41110000.
184 * Writing 0xffffffff hangs the PC.
185 * Writing 0xffff0000 -> 77770000 so it must be some sort of route.
186 * bit 0x1 starts DMA playback on channel_id 0
187 */
188 /* 0x41,42 take values from 0 - 0xffffffff, but have no effect on playback */
189 /* 0x43,0x48 do not remember settings */
190 /* 0x41-45 unused */
191 #define WATERMARK 0x46 /* Test bit to indicate cache level usage */
192 /* Values it can have while playing on channel 0.
193 * 0000f000, 0000f004, 0000f008, 0000f00c.
194 * Readonly.
195 */
196 /* 0x47-0x4f unused */
197 /* 0x50-0x5f Capture cache data */
198 #define SRCSel 0x60 /* SRCSel. Default 0x4. Bypass P16V 0x14 */
199 /* [0] 0 = 10K2 audio, 1 = SRC48 mixer output.
200 * [2] 0 = 10K2 audio, 1 = SRCMulti SPDIF mixer output.
201 * [4] 0 = 10K2 audio, 1 = SRCMulti I2S mixer output.
202 */
203 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
204 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
205 /* SRC48 and SRCMULTI sample rate select and output select. */
206 /* 0xffffffff -> 0xC0000015
207 * 0xXXXXXXX4 = Enable Front Left/Right
208 * Enable PCMs
209 */
210
211 /* 0x61 -> 0x6c are Volume controls */
212 #define PLAYBACK_VOLUME_MIXER1 0x61 /* SRC48 Low to mixer input volume control. */
213 #define PLAYBACK_VOLUME_MIXER2 0x62 /* SRC48 High to mixer input volume control. */
214 #define PLAYBACK_VOLUME_MIXER3 0x63 /* SRCMULTI SPDIF Low to mixer input volume control. */
215 #define PLAYBACK_VOLUME_MIXER4 0x64 /* SRCMULTI SPDIF High to mixer input volume control. */
216 #define PLAYBACK_VOLUME_MIXER5 0x65 /* SRCMULTI I2S Low to mixer input volume control. */
217 #define PLAYBACK_VOLUME_MIXER6 0x66 /* SRCMULTI I2S High to mixer input volume control. */
218 #define PLAYBACK_VOLUME_MIXER7 0x67 /* P16V Low to SRCMULTI SPDIF mixer input volume control. */
219 #define PLAYBACK_VOLUME_MIXER8 0x68 /* P16V High to SRCMULTI SPDIF mixer input volume control. */
220 #define PLAYBACK_VOLUME_MIXER9 0x69 /* P16V Low to SRCMULTI I2S mixer input volume control. */
221 /* 0xXXXX3030 = PCM0 Volume (Front).
222 * 0x3030XXXX = PCM1 Volume (Center)
223 */
224 #define PLAYBACK_VOLUME_MIXER10 0x6a /* P16V High to SRCMULTI I2S mixer input volume control. */
225 /* 0x3030XXXX = PCM3 Volume (Rear). */
226 #define PLAYBACK_VOLUME_MIXER11 0x6b /* E10K2 Low to SRC48 mixer input volume control. */
227 #define PLAYBACK_VOLUME_MIXER12 0x6c /* E10K2 High to SRC48 mixer input volume control. */
228
229 #define SRC48_ENABLE 0x6d /* SRC48 input audio enable */
230 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
231 /* [23:16] The corresponding P16V channel to SRC48 enabled if == 1.
232 * [31:24] The corresponding E10K2 channel to SRC48 enabled.
233 */
234 #define SRCMULTI_ENABLE 0x6e /* SRCMulti input audio enable. Default 0xffffffff */
235 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
236 /* [7:0] The corresponding P16V channel to SRCMulti_I2S enabled if == 1.
237 * [15:8] The corresponding E10K2 channel to SRCMulti I2S enabled.
238 * [23:16] The corresponding P16V channel to SRCMulti SPDIF enabled.
239 * [31:24] The corresponding E10K2 channel to SRCMulti SPDIF enabled.
240 */
241 /* Bypass P16V 0xff00ff00
242 * Bitmap. 0 = Off, 1 = On.
243 * P16V playback outputs:
244 * 0xXXXXXXX1 = PCM0 Left. (Front)
245 * 0xXXXXXXX2 = PCM0 Right.
246 * 0xXXXXXXX4 = PCM1 Left. (Center/LFE)
247 * 0xXXXXXXX8 = PCM1 Right.
248 * 0xXXXXXX1X = PCM2 Left. (Unknown)
249 * 0xXXXXXX2X = PCM2 Right.
250 * 0xXXXXXX4X = PCM3 Left. (Rear)
251 * 0xXXXXXX8X = PCM3 Right.
252 */
253 #define AUDIO_OUT_ENABLE 0x6f /* Default: 000100FF */
254 /* [3:0] Does something, but not documented. Probably capture enable.
255 * [7:4] Playback channels enable. not documented.
256 * [16] AC97 output enable if == 1
257 * [30] 0 = SRCMulti_I2S input from fxengine 0x68-0x6f.
258 * 1 = SRCMulti_I2S input from SRC48 output.
259 * [31] 0 = SRCMulti_SPDIF input from fxengine 0x60-0x67.
260 * 1 = SRCMulti_SPDIF input from SRC48 output.
261 */
262 /* 0xffffffff -> C00100FF */
263 /* 0 -> Not playback sound, irq still running */
264 /* 0xXXXXXX10 = PCM0 Left/Right On. (Front)
265 * 0xXXXXXX20 = PCM1 Left/Right On. (Center/LFE)
266 * 0xXXXXXX40 = PCM2 Left/Right On. (Unknown)
267 * 0xXXXXXX80 = PCM3 Left/Right On. (Rear)
268 */
269 #define PLAYBACK_SPDIF_SELECT 0x70 /* Default: 12030F00 */
270 /* 0xffffffff -> 3FF30FFF */
271 /* 0x00000001 pauses stream/irq fail. */
272 /* All other bits do not effect playback */
273 #define PLAYBACK_SPDIF_SRC_SELECT 0x71 /* Default: 0000E4E4 */
274 /* 0xffffffff -> F33FFFFF */
275 /* All bits do not effect playback */
276 #define PLAYBACK_SPDIF_USER_DATA0 0x72 /* SPDIF out user data 0 */
277 #define PLAYBACK_SPDIF_USER_DATA1 0x73 /* SPDIF out user data 1 */
278 /* 0x74-0x75 unknown */
279 #define CAPTURE_SPDIF_CONTROL 0x76 /* SPDIF in control setting */
280 #define CAPTURE_SPDIF_STATUS 0x77 /* SPDIF in status */
281 #define CAPURE_SPDIF_USER_DATA0 0x78 /* SPDIF in user data 0 */
282 #define CAPURE_SPDIF_USER_DATA1 0x79 /* SPDIF in user data 1 */
283 #define CAPURE_SPDIF_USER_DATA2 0x7a /* SPDIF in user data 2 */
284