1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Implementation of primary alsa driver code base for Intel HD Audio.
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
12 #include <linux/clocksource.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
21 /* for art-tsc conversion */
25 #include <sound/core.h>
26 #include <sound/initval.h>
27 #include "hda_controller.h"
29 #define CREATE_TRACE_POINTS
30 #include "hda_controller_trace.h"
32 /* DSP lock helpers */
33 #define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
34 #define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
35 #define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
37 /* assign a stream for the PCM */
38 static inline struct azx_dev
*
39 azx_assign_device(struct azx
*chip
, struct snd_pcm_substream
*substream
)
41 struct hdac_stream
*s
;
43 s
= snd_hdac_stream_assign(azx_bus(chip
), substream
);
46 return stream_to_azx_dev(s
);
49 /* release the assigned stream */
50 static inline void azx_release_device(struct azx_dev
*azx_dev
)
52 snd_hdac_stream_release(azx_stream(azx_dev
));
55 static inline struct hda_pcm_stream
*
56 to_hda_pcm_stream(struct snd_pcm_substream
*substream
)
58 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
59 return &apcm
->info
->stream
[substream
->stream
];
62 static u64
azx_adjust_codec_delay(struct snd_pcm_substream
*substream
,
65 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
66 struct hda_pcm_stream
*hinfo
= to_hda_pcm_stream(substream
);
67 u64 codec_frames
, codec_nsecs
;
69 if (!hinfo
->ops
.get_delay
)
72 codec_frames
= hinfo
->ops
.get_delay(hinfo
, apcm
->codec
, substream
);
73 codec_nsecs
= div_u64(codec_frames
* 1000000000LL,
74 substream
->runtime
->rate
);
76 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
77 return nsec
+ codec_nsecs
;
79 return (nsec
> codec_nsecs
) ? nsec
- codec_nsecs
: 0;
86 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
88 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
89 struct hda_pcm_stream
*hinfo
= to_hda_pcm_stream(substream
);
90 struct azx
*chip
= apcm
->chip
;
91 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
93 trace_azx_pcm_close(chip
, azx_dev
);
94 mutex_lock(&chip
->open_mutex
);
95 azx_release_device(azx_dev
);
97 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
98 snd_hda_power_down(apcm
->codec
);
99 mutex_unlock(&chip
->open_mutex
);
100 snd_hda_codec_pcm_put(apcm
->info
);
104 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
105 struct snd_pcm_hw_params
*hw_params
)
107 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
108 struct azx
*chip
= apcm
->chip
;
109 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
112 trace_azx_pcm_hw_params(chip
, azx_dev
);
114 if (dsp_is_locked(azx_dev
)) {
119 azx_dev
->core
.bufsize
= 0;
120 azx_dev
->core
.period_bytes
= 0;
121 azx_dev
->core
.format_val
= 0;
128 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
130 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
131 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
132 struct hda_pcm_stream
*hinfo
= to_hda_pcm_stream(substream
);
134 /* reset BDL address */
136 if (!dsp_is_locked(azx_dev
))
137 snd_hdac_stream_cleanup(azx_stream(azx_dev
));
139 snd_hda_codec_cleanup(apcm
->codec
, hinfo
, substream
);
141 azx_stream(azx_dev
)->prepared
= 0;
146 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
148 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
149 struct azx
*chip
= apcm
->chip
;
150 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
151 struct hda_pcm_stream
*hinfo
= to_hda_pcm_stream(substream
);
152 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
153 unsigned int format_val
, stream_tag
;
155 struct hda_spdif_out
*spdif
=
156 snd_hda_spdif_out_of_nid(apcm
->codec
, hinfo
->nid
);
157 unsigned short ctls
= spdif
? spdif
->ctls
: 0;
159 trace_azx_pcm_prepare(chip
, azx_dev
);
161 if (dsp_is_locked(azx_dev
)) {
166 snd_hdac_stream_reset(azx_stream(azx_dev
));
167 format_val
= snd_hdac_calc_stream_format(runtime
->rate
,
173 dev_err(chip
->card
->dev
,
174 "invalid format_val, rate=%d, ch=%d, format=%d\n",
175 runtime
->rate
, runtime
->channels
, runtime
->format
);
180 err
= snd_hdac_stream_set_params(azx_stream(azx_dev
), format_val
);
184 snd_hdac_stream_setup(azx_stream(azx_dev
));
186 stream_tag
= azx_dev
->core
.stream_tag
;
187 /* CA-IBG chips need the playback stream starting from 1 */
188 if ((chip
->driver_caps
& AZX_DCAPS_CTX_WORKAROUND
) &&
189 stream_tag
> chip
->capture_streams
)
190 stream_tag
-= chip
->capture_streams
;
191 err
= snd_hda_codec_prepare(apcm
->codec
, hinfo
, stream_tag
,
192 azx_dev
->core
.format_val
, substream
);
196 azx_stream(azx_dev
)->prepared
= 1;
201 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
203 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
204 struct azx
*chip
= apcm
->chip
;
205 struct hdac_bus
*bus
= azx_bus(chip
);
206 struct azx_dev
*azx_dev
;
207 struct snd_pcm_substream
*s
;
208 struct hdac_stream
*hstr
;
213 azx_dev
= get_azx_dev(substream
);
214 trace_azx_pcm_trigger(chip
, azx_dev
, cmd
);
216 hstr
= azx_stream(azx_dev
);
217 if (chip
->driver_caps
& AZX_DCAPS_OLD_SSYNC
)
218 sync_reg
= AZX_REG_OLD_SSYNC
;
220 sync_reg
= AZX_REG_SSYNC
;
222 if (dsp_is_locked(azx_dev
) || !hstr
->prepared
)
226 case SNDRV_PCM_TRIGGER_START
:
227 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
228 case SNDRV_PCM_TRIGGER_RESUME
:
231 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
232 case SNDRV_PCM_TRIGGER_SUSPEND
:
233 case SNDRV_PCM_TRIGGER_STOP
:
240 snd_pcm_group_for_each_entry(s
, substream
) {
241 if (s
->pcm
->card
!= substream
->pcm
->card
)
243 azx_dev
= get_azx_dev(s
);
244 sbits
|= 1 << azx_dev
->core
.index
;
245 snd_pcm_trigger_done(s
, substream
);
248 spin_lock(&bus
->reg_lock
);
250 /* first, set SYNC bits of corresponding streams */
251 snd_hdac_stream_sync_trigger(hstr
, true, sbits
, sync_reg
);
253 snd_pcm_group_for_each_entry(s
, substream
) {
254 if (s
->pcm
->card
!= substream
->pcm
->card
)
256 azx_dev
= get_azx_dev(s
);
258 azx_dev
->insufficient
= 1;
259 snd_hdac_stream_start(azx_stream(azx_dev
), true);
261 snd_hdac_stream_stop(azx_stream(azx_dev
));
264 spin_unlock(&bus
->reg_lock
);
266 snd_hdac_stream_sync(hstr
, start
, sbits
);
268 spin_lock(&bus
->reg_lock
);
269 /* reset SYNC bits */
270 snd_hdac_stream_sync_trigger(hstr
, false, sbits
, sync_reg
);
272 snd_hdac_stream_timecounter_init(hstr
, sbits
);
273 spin_unlock(&bus
->reg_lock
);
277 unsigned int azx_get_pos_lpib(struct azx
*chip
, struct azx_dev
*azx_dev
)
279 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev
));
281 EXPORT_SYMBOL_GPL(azx_get_pos_lpib
);
283 unsigned int azx_get_pos_posbuf(struct azx
*chip
, struct azx_dev
*azx_dev
)
285 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev
));
287 EXPORT_SYMBOL_GPL(azx_get_pos_posbuf
);
289 unsigned int azx_get_position(struct azx
*chip
,
290 struct azx_dev
*azx_dev
)
292 struct snd_pcm_substream
*substream
= azx_dev
->core
.substream
;
294 int stream
= substream
->stream
;
297 if (chip
->get_position
[stream
])
298 pos
= chip
->get_position
[stream
](chip
, azx_dev
);
299 else /* use the position buffer as default */
300 pos
= azx_get_pos_posbuf(chip
, azx_dev
);
302 if (pos
>= azx_dev
->core
.bufsize
)
305 if (substream
->runtime
) {
306 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
307 struct hda_pcm_stream
*hinfo
= to_hda_pcm_stream(substream
);
309 if (chip
->get_delay
[stream
])
310 delay
+= chip
->get_delay
[stream
](chip
, azx_dev
, pos
);
311 if (hinfo
->ops
.get_delay
)
312 delay
+= hinfo
->ops
.get_delay(hinfo
, apcm
->codec
,
314 substream
->runtime
->delay
= delay
;
317 trace_azx_get_position(chip
, azx_dev
, pos
, delay
);
320 EXPORT_SYMBOL_GPL(azx_get_position
);
322 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
324 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
325 struct azx
*chip
= apcm
->chip
;
326 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
327 return bytes_to_frames(substream
->runtime
,
328 azx_get_position(chip
, azx_dev
));
332 * azx_scale64: Scale base by mult/div while not overflowing sanely
334 * Derived from scale64_check_overflow in kernel/time/timekeeping.c
336 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
337 * is about 384307 ie ~4.5 days.
339 * This scales the calculation so that overflow will happen but after 2^64 /
340 * 48000 secs, which is pretty large!
343 * base may overflow, but since there isn’t any additional division
344 * performed on base it’s OK
345 * rem can’t overflow because both are 32-bit values
349 static u64
azx_scale64(u64 base
, u32 num
, u32 den
)
353 rem
= do_div(base
, den
);
363 static int azx_get_sync_time(ktime_t
*device
,
364 struct system_counterval_t
*system
, void *ctx
)
366 struct snd_pcm_substream
*substream
= ctx
;
367 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
368 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
369 struct azx
*chip
= apcm
->chip
;
370 struct snd_pcm_runtime
*runtime
;
371 u64 ll_counter
, ll_counter_l
, ll_counter_h
;
372 u64 tsc_counter
, tsc_counter_l
, tsc_counter_h
;
373 u32 wallclk_ctr
, wallclk_cycles
;
379 runtime
= substream
->runtime
;
381 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
386 /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
389 dma_select
= (direction
<< GTSCC_CDMAS_DMA_DIR_SHIFT
) |
390 (azx_dev
->core
.stream_tag
- 1);
391 snd_hdac_chip_writel(azx_bus(chip
), GTSCC
, dma_select
);
393 /* Enable the capture */
394 snd_hdac_chip_updatel(azx_bus(chip
), GTSCC
, 0, GTSCC_TSCCI_MASK
);
397 if (snd_hdac_chip_readl(azx_bus(chip
), GTSCC
) &
405 dev_err(chip
->card
->dev
, "GTSCC capture Timedout!\n");
409 /* Read wall clock counter */
410 wallclk_ctr
= snd_hdac_chip_readl(azx_bus(chip
), WALFCC
);
412 /* Read TSC counter */
413 tsc_counter_l
= snd_hdac_chip_readl(azx_bus(chip
), TSCCL
);
414 tsc_counter_h
= snd_hdac_chip_readl(azx_bus(chip
), TSCCU
);
416 /* Read Link counter */
417 ll_counter_l
= snd_hdac_chip_readl(azx_bus(chip
), LLPCL
);
418 ll_counter_h
= snd_hdac_chip_readl(azx_bus(chip
), LLPCU
);
420 /* Ack: registers read done */
421 snd_hdac_chip_writel(azx_bus(chip
), GTSCC
, GTSCC_TSCCD_SHIFT
);
423 tsc_counter
= (tsc_counter_h
<< TSCCU_CCU_SHIFT
) |
426 ll_counter
= (ll_counter_h
<< LLPC_CCU_SHIFT
) | ll_counter_l
;
427 wallclk_cycles
= wallclk_ctr
& WALFCC_CIF_MASK
;
430 * An error occurs near frame "rollover". The clocks in
431 * frame value indicates whether this error may have
432 * occurred. Here we use the value of 10 i.e.,
433 * HDA_MAX_CYCLE_OFFSET
435 if (wallclk_cycles
< HDA_MAX_CYCLE_VALUE
- HDA_MAX_CYCLE_OFFSET
436 && wallclk_cycles
> HDA_MAX_CYCLE_OFFSET
)
440 * Sleep before we read again, else we may again get
441 * value near to MAX_CYCLE. Try to sleep for different
442 * amount of time so we dont hit the same number again
444 udelay(retry_count
++);
446 } while (retry_count
!= HDA_MAX_CYCLE_READ_RETRY
);
448 if (retry_count
== HDA_MAX_CYCLE_READ_RETRY
) {
449 dev_err_ratelimited(chip
->card
->dev
,
450 "Error in WALFCC cycle count\n");
454 *device
= ns_to_ktime(azx_scale64(ll_counter
,
455 NSEC_PER_SEC
, runtime
->rate
));
456 *device
= ktime_add_ns(*device
, (wallclk_cycles
* NSEC_PER_SEC
) /
457 ((HDA_MAX_CYCLE_VALUE
+ 1) * runtime
->rate
));
459 *system
= convert_art_to_tsc(tsc_counter
);
465 static int azx_get_sync_time(ktime_t
*device
,
466 struct system_counterval_t
*system
, void *ctx
)
472 static int azx_get_crosststamp(struct snd_pcm_substream
*substream
,
473 struct system_device_crosststamp
*xtstamp
)
475 return get_device_system_crosststamp(azx_get_sync_time
,
476 substream
, NULL
, xtstamp
);
479 static inline bool is_link_time_supported(struct snd_pcm_runtime
*runtime
,
480 struct snd_pcm_audio_tstamp_config
*ts
)
482 if (runtime
->hw
.info
& SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
)
483 if (ts
->type_requested
== SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED
)
489 static int azx_get_time_info(struct snd_pcm_substream
*substream
,
490 struct timespec64
*system_ts
, struct timespec64
*audio_ts
,
491 struct snd_pcm_audio_tstamp_config
*audio_tstamp_config
,
492 struct snd_pcm_audio_tstamp_report
*audio_tstamp_report
)
494 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
495 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
496 struct system_device_crosststamp xtstamp
;
500 if ((substream
->runtime
->hw
.info
& SNDRV_PCM_INFO_HAS_LINK_ATIME
) &&
501 (audio_tstamp_config
->type_requested
== SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK
)) {
503 snd_pcm_gettime(substream
->runtime
, system_ts
);
505 nsec
= timecounter_read(&azx_dev
->core
.tc
);
506 nsec
= div_u64(nsec
, 3); /* can be optimized */
507 if (audio_tstamp_config
->report_delay
)
508 nsec
= azx_adjust_codec_delay(substream
, nsec
);
510 *audio_ts
= ns_to_timespec64(nsec
);
512 audio_tstamp_report
->actual_type
= SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK
;
513 audio_tstamp_report
->accuracy_report
= 1; /* rest of structure is valid */
514 audio_tstamp_report
->accuracy
= 42; /* 24 MHz WallClock == 42ns resolution */
516 } else if (is_link_time_supported(runtime
, audio_tstamp_config
)) {
518 ret
= azx_get_crosststamp(substream
, &xtstamp
);
522 switch (runtime
->tstamp_type
) {
523 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC
:
526 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW
:
527 *system_ts
= ktime_to_timespec64(xtstamp
.sys_monoraw
);
531 *system_ts
= ktime_to_timespec64(xtstamp
.sys_realtime
);
536 *audio_ts
= ktime_to_timespec64(xtstamp
.device
);
538 audio_tstamp_report
->actual_type
=
539 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED
;
540 audio_tstamp_report
->accuracy_report
= 1;
541 /* 24 MHz WallClock == 42ns resolution */
542 audio_tstamp_report
->accuracy
= 42;
545 audio_tstamp_report
->actual_type
= SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT
;
551 static const struct snd_pcm_hardware azx_pcm_hw
= {
552 .info
= (SNDRV_PCM_INFO_MMAP
|
553 SNDRV_PCM_INFO_INTERLEAVED
|
554 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
555 SNDRV_PCM_INFO_MMAP_VALID
|
556 /* No full-resume yet implemented */
557 /* SNDRV_PCM_INFO_RESUME |*/
558 SNDRV_PCM_INFO_PAUSE
|
559 SNDRV_PCM_INFO_SYNC_START
|
560 SNDRV_PCM_INFO_HAS_WALL_CLOCK
| /* legacy */
561 SNDRV_PCM_INFO_HAS_LINK_ATIME
|
562 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
),
563 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
564 .rates
= SNDRV_PCM_RATE_48000
,
569 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
570 .period_bytes_min
= 128,
571 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
573 .periods_max
= AZX_MAX_FRAG
,
577 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
579 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
580 struct hda_pcm_stream
*hinfo
= to_hda_pcm_stream(substream
);
581 struct azx
*chip
= apcm
->chip
;
582 struct azx_dev
*azx_dev
;
583 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
587 snd_hda_codec_pcm_get(apcm
->info
);
588 mutex_lock(&chip
->open_mutex
);
589 azx_dev
= azx_assign_device(chip
, substream
);
590 trace_azx_pcm_open(chip
, azx_dev
);
591 if (azx_dev
== NULL
) {
595 runtime
->private_data
= azx_dev
;
597 runtime
->hw
= azx_pcm_hw
;
598 if (chip
->gts_present
)
599 runtime
->hw
.info
|= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
;
600 runtime
->hw
.channels_min
= hinfo
->channels_min
;
601 runtime
->hw
.channels_max
= hinfo
->channels_max
;
602 runtime
->hw
.formats
= hinfo
->formats
;
603 runtime
->hw
.rates
= hinfo
->rates
;
604 snd_pcm_limit_hw_rates(runtime
);
605 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
607 /* avoid wrap-around with wall-clock */
608 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_TIME
,
612 if (chip
->align_buffer_size
)
613 /* constrain buffer sizes to be multiple of 128
614 bytes. This is more efficient in terms of memory
615 access but isn't required by the HDA spec and
616 prevents users from specifying exact period/buffer
617 sizes. For example for 44.1kHz, a period size set
618 to 20ms will be rounded to 19.59ms. */
621 /* Don't enforce steps on buffer sizes, still need to
622 be multiple of 4 bytes (HDA spec). Tested on Intel
623 HDA controllers, may not work on all devices where
624 option needs to be disabled */
627 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
629 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
631 snd_hda_power_up(apcm
->codec
);
633 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
637 azx_release_device(azx_dev
);
640 snd_pcm_limit_hw_rates(runtime
);
642 if (snd_BUG_ON(!runtime
->hw
.channels_min
) ||
643 snd_BUG_ON(!runtime
->hw
.channels_max
) ||
644 snd_BUG_ON(!runtime
->hw
.formats
) ||
645 snd_BUG_ON(!runtime
->hw
.rates
)) {
646 azx_release_device(azx_dev
);
647 if (hinfo
->ops
.close
)
648 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
653 /* disable LINK_ATIME timestamps for capture streams
654 until we figure out how to handle digital inputs */
655 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
) {
656 runtime
->hw
.info
&= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK
; /* legacy */
657 runtime
->hw
.info
&= ~SNDRV_PCM_INFO_HAS_LINK_ATIME
;
660 snd_pcm_set_sync(substream
);
661 mutex_unlock(&chip
->open_mutex
);
665 snd_hda_power_down(apcm
->codec
);
667 mutex_unlock(&chip
->open_mutex
);
668 snd_hda_codec_pcm_put(apcm
->info
);
672 static int azx_pcm_mmap(struct snd_pcm_substream
*substream
,
673 struct vm_area_struct
*area
)
675 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
676 struct azx
*chip
= apcm
->chip
;
677 if (chip
->ops
->pcm_mmap_prepare
)
678 chip
->ops
->pcm_mmap_prepare(substream
, area
);
679 return snd_pcm_lib_default_mmap(substream
, area
);
682 static const struct snd_pcm_ops azx_pcm_ops
= {
683 .open
= azx_pcm_open
,
684 .close
= azx_pcm_close
,
685 .hw_params
= azx_pcm_hw_params
,
686 .hw_free
= azx_pcm_hw_free
,
687 .prepare
= azx_pcm_prepare
,
688 .trigger
= azx_pcm_trigger
,
689 .pointer
= azx_pcm_pointer
,
690 .get_time_info
= azx_get_time_info
,
691 .mmap
= azx_pcm_mmap
,
694 static void azx_pcm_free(struct snd_pcm
*pcm
)
696 struct azx_pcm
*apcm
= pcm
->private_data
;
698 list_del(&apcm
->list
);
699 apcm
->info
->pcm
= NULL
;
704 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
706 int snd_hda_attach_pcm_stream(struct hda_bus
*_bus
, struct hda_codec
*codec
,
707 struct hda_pcm
*cpcm
)
709 struct hdac_bus
*bus
= &_bus
->core
;
710 struct azx
*chip
= bus_to_azx(bus
);
712 struct azx_pcm
*apcm
;
713 int pcm_dev
= cpcm
->device
;
716 int type
= SNDRV_DMA_TYPE_DEV_SG
;
718 list_for_each_entry(apcm
, &chip
->pcm_list
, list
) {
719 if (apcm
->pcm
->device
== pcm_dev
) {
720 dev_err(chip
->card
->dev
, "PCM %d already exists\n",
725 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
726 cpcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].substreams
,
727 cpcm
->stream
[SNDRV_PCM_STREAM_CAPTURE
].substreams
,
731 strscpy(pcm
->name
, cpcm
->name
, sizeof(pcm
->name
));
732 apcm
= kzalloc(sizeof(*apcm
), GFP_KERNEL
);
734 snd_device_free(chip
->card
, pcm
);
741 pcm
->private_data
= apcm
;
742 pcm
->private_free
= azx_pcm_free
;
743 if (cpcm
->pcm_type
== HDA_PCM_TYPE_MODEM
)
744 pcm
->dev_class
= SNDRV_PCM_CLASS_MODEM
;
745 list_add_tail(&apcm
->list
, &chip
->pcm_list
);
747 for (s
= 0; s
< 2; s
++) {
748 if (cpcm
->stream
[s
].substreams
)
749 snd_pcm_set_ops(pcm
, s
, &azx_pcm_ops
);
751 /* buffer pre-allocation */
752 size
= CONFIG_SND_HDA_PREALLOC_SIZE
* 1024;
753 if (size
> MAX_PREALLOC_SIZE
)
754 size
= MAX_PREALLOC_SIZE
;
756 type
= SNDRV_DMA_TYPE_DEV_UC_SG
;
757 snd_pcm_set_managed_buffer_all(pcm
, type
, chip
->card
->dev
,
758 size
, MAX_PREALLOC_SIZE
);
762 static unsigned int azx_command_addr(u32 cmd
)
764 unsigned int addr
= cmd
>> 28;
766 if (addr
>= AZX_MAX_CODECS
) {
774 /* receive a response */
775 static int azx_rirb_get_response(struct hdac_bus
*bus
, unsigned int addr
,
778 struct azx
*chip
= bus_to_azx(bus
);
779 struct hda_bus
*hbus
= &chip
->bus
;
783 err
= snd_hdac_bus_get_response(bus
, addr
, res
);
787 if (hbus
->no_response_fallback
)
790 if (!bus
->polling_mode
) {
791 dev_warn(chip
->card
->dev
,
792 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
793 bus
->last_cmd
[addr
]);
794 bus
->polling_mode
= 1;
799 dev_warn(chip
->card
->dev
,
800 "No response from codec, disabling MSI: last cmd=0x%08x\n",
801 bus
->last_cmd
[addr
]);
802 if (chip
->ops
->disable_msi_reset_irq
&&
803 chip
->ops
->disable_msi_reset_irq(chip
) < 0)
809 /* If this critical timeout happens during the codec probing
810 * phase, this is likely an access to a non-existing codec
811 * slot. Better to return an error and reset the system.
816 /* no fallback mechanism? */
817 if (!chip
->fallback_to_single_cmd
)
820 /* a fatal communication error; need either to reset or to fallback
821 * to the single_cmd mode
823 if (hbus
->allow_bus_reset
&& !hbus
->response_reset
&& !hbus
->in_reset
) {
824 hbus
->response_reset
= 1;
825 dev_err(chip
->card
->dev
,
826 "No response from codec, resetting bus: last cmd=0x%08x\n",
827 bus
->last_cmd
[addr
]);
828 return -EAGAIN
; /* give a chance to retry */
831 dev_err(chip
->card
->dev
,
832 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
833 bus
->last_cmd
[addr
]);
834 chip
->single_cmd
= 1;
835 hbus
->response_reset
= 0;
836 snd_hdac_bus_stop_cmd_io(bus
);
841 * Use the single immediate command instead of CORB/RIRB for simplicity
843 * Note: according to Intel, this is not preferred use. The command was
844 * intended for the BIOS only, and may get confused with unsolicited
845 * responses. So, we shouldn't use it for normal operation from the
847 * I left the codes, however, for debugging/testing purposes.
850 /* receive a response */
851 static int azx_single_wait_for_response(struct azx
*chip
, unsigned int addr
)
856 /* check IRV busy bit */
857 if (azx_readw(chip
, IRS
) & AZX_IRS_VALID
) {
858 /* reuse rirb.res as the response return value */
859 azx_bus(chip
)->rirb
.res
[addr
] = azx_readl(chip
, IR
);
864 if (printk_ratelimit())
865 dev_dbg(chip
->card
->dev
, "get_response timeout: IRS=0x%x\n",
866 azx_readw(chip
, IRS
));
867 azx_bus(chip
)->rirb
.res
[addr
] = -1;
872 static int azx_single_send_cmd(struct hdac_bus
*bus
, u32 val
)
874 struct azx
*chip
= bus_to_azx(bus
);
875 unsigned int addr
= azx_command_addr(val
);
878 bus
->last_cmd
[azx_command_addr(val
)] = val
;
880 /* check ICB busy bit */
881 if (!((azx_readw(chip
, IRS
) & AZX_IRS_BUSY
))) {
882 /* Clear IRV valid bit */
883 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
885 azx_writel(chip
, IC
, val
);
886 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
888 return azx_single_wait_for_response(chip
, addr
);
892 if (printk_ratelimit())
893 dev_dbg(chip
->card
->dev
,
894 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
895 azx_readw(chip
, IRS
), val
);
899 /* receive a response */
900 static int azx_single_get_response(struct hdac_bus
*bus
, unsigned int addr
,
904 *res
= bus
->rirb
.res
[addr
];
909 * The below are the main callbacks from hda_codec.
911 * They are just the skeleton to call sub-callbacks according to the
912 * current setting of chip->single_cmd.
916 static int azx_send_cmd(struct hdac_bus
*bus
, unsigned int val
)
918 struct azx
*chip
= bus_to_azx(bus
);
922 if (chip
->single_cmd
)
923 return azx_single_send_cmd(bus
, val
);
925 return snd_hdac_bus_send_cmd(bus
, val
);
929 static int azx_get_response(struct hdac_bus
*bus
, unsigned int addr
,
932 struct azx
*chip
= bus_to_azx(bus
);
936 if (chip
->single_cmd
)
937 return azx_single_get_response(bus
, addr
, res
);
939 return azx_rirb_get_response(bus
, addr
, res
);
942 static const struct hdac_bus_ops bus_core_ops
= {
943 .command
= azx_send_cmd
,
944 .get_response
= azx_get_response
,
947 #ifdef CONFIG_SND_HDA_DSP_LOADER
949 * DSP loading code (e.g. for CA0132)
952 /* use the first stream for loading DSP */
953 static struct azx_dev
*
954 azx_get_dsp_loader_dev(struct azx
*chip
)
956 struct hdac_bus
*bus
= azx_bus(chip
);
957 struct hdac_stream
*s
;
959 list_for_each_entry(s
, &bus
->stream_list
, list
)
960 if (s
->index
== chip
->playback_index_offset
)
961 return stream_to_azx_dev(s
);
966 int snd_hda_codec_load_dsp_prepare(struct hda_codec
*codec
, unsigned int format
,
967 unsigned int byte_size
,
968 struct snd_dma_buffer
*bufp
)
970 struct hdac_bus
*bus
= &codec
->bus
->core
;
971 struct azx
*chip
= bus_to_azx(bus
);
972 struct azx_dev
*azx_dev
;
973 struct hdac_stream
*hstr
;
977 azx_dev
= azx_get_dsp_loader_dev(chip
);
978 hstr
= azx_stream(azx_dev
);
979 spin_lock_irq(&bus
->reg_lock
);
981 chip
->saved_azx_dev
= *azx_dev
;
984 spin_unlock_irq(&bus
->reg_lock
);
986 err
= snd_hdac_dsp_prepare(hstr
, format
, byte_size
, bufp
);
988 spin_lock_irq(&bus
->reg_lock
);
990 *azx_dev
= chip
->saved_azx_dev
;
991 spin_unlock_irq(&bus
->reg_lock
);
998 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare
);
1000 void snd_hda_codec_load_dsp_trigger(struct hda_codec
*codec
, bool start
)
1002 struct hdac_bus
*bus
= &codec
->bus
->core
;
1003 struct azx
*chip
= bus_to_azx(bus
);
1004 struct azx_dev
*azx_dev
= azx_get_dsp_loader_dev(chip
);
1006 snd_hdac_dsp_trigger(azx_stream(azx_dev
), start
);
1008 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger
);
1010 void snd_hda_codec_load_dsp_cleanup(struct hda_codec
*codec
,
1011 struct snd_dma_buffer
*dmab
)
1013 struct hdac_bus
*bus
= &codec
->bus
->core
;
1014 struct azx
*chip
= bus_to_azx(bus
);
1015 struct azx_dev
*azx_dev
= azx_get_dsp_loader_dev(chip
);
1016 struct hdac_stream
*hstr
= azx_stream(azx_dev
);
1018 if (!dmab
->area
|| !hstr
->locked
)
1021 snd_hdac_dsp_cleanup(hstr
, dmab
);
1022 spin_lock_irq(&bus
->reg_lock
);
1024 *azx_dev
= chip
->saved_azx_dev
;
1025 hstr
->locked
= false;
1026 spin_unlock_irq(&bus
->reg_lock
);
1028 EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup
);
1029 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1032 * reset and start the controller registers
1034 void azx_init_chip(struct azx
*chip
, bool full_reset
)
1036 if (snd_hdac_bus_init_chip(azx_bus(chip
), full_reset
)) {
1037 /* correct RINTCNT for CXT */
1038 if (chip
->driver_caps
& AZX_DCAPS_CTX_WORKAROUND
)
1039 azx_writew(chip
, RINTCNT
, 0xc0);
1042 EXPORT_SYMBOL_GPL(azx_init_chip
);
1044 void azx_stop_all_streams(struct azx
*chip
)
1046 struct hdac_bus
*bus
= azx_bus(chip
);
1047 struct hdac_stream
*s
;
1049 list_for_each_entry(s
, &bus
->stream_list
, list
)
1050 snd_hdac_stream_stop(s
);
1052 EXPORT_SYMBOL_GPL(azx_stop_all_streams
);
1054 void azx_stop_chip(struct azx
*chip
)
1056 snd_hdac_bus_stop_chip(azx_bus(chip
));
1058 EXPORT_SYMBOL_GPL(azx_stop_chip
);
1063 static void stream_update(struct hdac_bus
*bus
, struct hdac_stream
*s
)
1065 struct azx
*chip
= bus_to_azx(bus
);
1066 struct azx_dev
*azx_dev
= stream_to_azx_dev(s
);
1068 /* check whether this IRQ is really acceptable */
1069 if (!chip
->ops
->position_check
||
1070 chip
->ops
->position_check(chip
, azx_dev
)) {
1071 spin_unlock(&bus
->reg_lock
);
1072 snd_pcm_period_elapsed(azx_stream(azx_dev
)->substream
);
1073 spin_lock(&bus
->reg_lock
);
1077 irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
1079 struct azx
*chip
= dev_id
;
1080 struct hdac_bus
*bus
= azx_bus(chip
);
1082 bool active
, handled
= false;
1083 int repeat
= 0; /* count for avoiding endless loop */
1086 if (azx_has_pm_runtime(chip
))
1087 if (!pm_runtime_active(chip
->card
->dev
))
1091 spin_lock(&bus
->reg_lock
);
1097 status
= azx_readl(chip
, INTSTS
);
1098 if (status
== 0 || status
== 0xffffffff)
1103 if (snd_hdac_bus_handle_stream_irq(bus
, status
, stream_update
))
1106 status
= azx_readb(chip
, RIRBSTS
);
1107 if (status
& RIRB_INT_MASK
) {
1109 * Clearing the interrupt status here ensures that no
1110 * interrupt gets masked after the RIRB wp is read in
1111 * snd_hdac_bus_update_rirb. This avoids a possible
1112 * race condition where codec response in RIRB may
1113 * remain unserviced by IRQ, eventually falling back
1114 * to polling mode in azx_rirb_get_response.
1116 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1118 if (status
& RIRB_INT_RESPONSE
) {
1119 if (chip
->driver_caps
& AZX_DCAPS_CTX_WORKAROUND
)
1121 snd_hdac_bus_update_rirb(bus
);
1124 } while (active
&& ++repeat
< 10);
1127 spin_unlock(&bus
->reg_lock
);
1129 return IRQ_RETVAL(handled
);
1131 EXPORT_SYMBOL_GPL(azx_interrupt
);
1138 * Probe the given codec address
1140 static int probe_codec(struct azx
*chip
, int addr
)
1142 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
1143 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
1144 struct hdac_bus
*bus
= azx_bus(chip
);
1146 unsigned int res
= -1;
1148 mutex_lock(&bus
->cmd_mutex
);
1150 azx_send_cmd(bus
, cmd
);
1151 err
= azx_get_response(bus
, addr
, &res
);
1153 mutex_unlock(&bus
->cmd_mutex
);
1154 if (err
< 0 || res
== -1)
1156 dev_dbg(chip
->card
->dev
, "codec #%d probed OK\n", addr
);
1160 void snd_hda_bus_reset(struct hda_bus
*bus
)
1162 struct azx
*chip
= bus_to_azx(&bus
->core
);
1165 azx_stop_chip(chip
);
1166 azx_init_chip(chip
, true);
1167 if (bus
->core
.chip_init
)
1168 snd_hda_bus_reset_codecs(bus
);
1172 /* HD-audio bus initialization */
1173 int azx_bus_init(struct azx
*chip
, const char *model
)
1175 struct hda_bus
*bus
= &chip
->bus
;
1178 err
= snd_hdac_bus_init(&bus
->core
, chip
->card
->dev
, &bus_core_ops
);
1182 bus
->card
= chip
->card
;
1183 mutex_init(&bus
->prepare_mutex
);
1184 bus
->pci
= chip
->pci
;
1185 bus
->modelname
= model
;
1186 bus
->mixer_assigned
= -1;
1187 bus
->core
.snoop
= azx_snoop(chip
);
1188 if (chip
->get_position
[0] != azx_get_pos_lpib
||
1189 chip
->get_position
[1] != azx_get_pos_lpib
)
1190 bus
->core
.use_posbuf
= true;
1191 bus
->core
.bdl_pos_adj
= chip
->bdl_pos_adj
;
1192 if (chip
->driver_caps
& AZX_DCAPS_CORBRP_SELF_CLEAR
)
1193 bus
->core
.corbrp_self_clear
= true;
1195 if (chip
->driver_caps
& AZX_DCAPS_4K_BDLE_BOUNDARY
)
1196 bus
->core
.align_bdle_4k
= true;
1198 /* enable sync_write flag for stable communication as default */
1199 bus
->core
.sync_write
= 1;
1203 EXPORT_SYMBOL_GPL(azx_bus_init
);
1206 int azx_probe_codecs(struct azx
*chip
, unsigned int max_slots
)
1208 struct hdac_bus
*bus
= azx_bus(chip
);
1213 max_slots
= AZX_DEFAULT_CODECS
;
1215 /* First try to probe all given codec slots */
1216 for (c
= 0; c
< max_slots
; c
++) {
1217 if ((bus
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1218 if (probe_codec(chip
, c
) < 0) {
1219 /* Some BIOSen give you wrong codec addresses
1222 dev_warn(chip
->card
->dev
,
1223 "Codec #%d probe error; disabling it...\n", c
);
1224 bus
->codec_mask
&= ~(1 << c
);
1225 /* More badly, accessing to a non-existing
1226 * codec often screws up the controller chip,
1227 * and disturbs the further communications.
1228 * Thus if an error occurs during probing,
1229 * better to reset the controller chip to
1230 * get back to the sanity state.
1232 azx_stop_chip(chip
);
1233 azx_init_chip(chip
, true);
1238 /* Then create codec instances */
1239 for (c
= 0; c
< max_slots
; c
++) {
1240 if ((bus
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1241 struct hda_codec
*codec
;
1242 err
= snd_hda_codec_new(&chip
->bus
, chip
->card
, c
, &codec
);
1245 codec
->jackpoll_interval
= chip
->jackpoll_interval
;
1246 codec
->beep_mode
= chip
->beep_mode
;
1251 dev_err(chip
->card
->dev
, "no codecs initialized\n");
1256 EXPORT_SYMBOL_GPL(azx_probe_codecs
);
1258 /* configure each codec instance */
1259 int azx_codec_configure(struct azx
*chip
)
1261 struct hda_codec
*codec
, *next
;
1263 /* use _safe version here since snd_hda_codec_configure() deregisters
1264 * the device upon error and deletes itself from the bus list.
1266 list_for_each_codec_safe(codec
, next
, &chip
->bus
) {
1267 snd_hda_codec_configure(codec
);
1270 if (!azx_bus(chip
)->num_codecs
)
1274 EXPORT_SYMBOL_GPL(azx_codec_configure
);
1276 static int stream_direction(struct azx
*chip
, unsigned char index
)
1278 if (index
>= chip
->capture_index_offset
&&
1279 index
< chip
->capture_index_offset
+ chip
->capture_streams
)
1280 return SNDRV_PCM_STREAM_CAPTURE
;
1281 return SNDRV_PCM_STREAM_PLAYBACK
;
1284 /* initialize SD streams */
1285 int azx_init_streams(struct azx
*chip
)
1288 int stream_tags
[2] = { 0, 0 };
1290 /* initialize each stream (aka device)
1291 * assign the starting bdl address to each stream (device)
1294 for (i
= 0; i
< chip
->num_streams
; i
++) {
1295 struct azx_dev
*azx_dev
= kzalloc(sizeof(*azx_dev
), GFP_KERNEL
);
1301 dir
= stream_direction(chip
, i
);
1302 /* stream tag must be unique throughout
1303 * the stream direction group,
1304 * valid values 1...15
1305 * use separate stream tag if the flag
1306 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1308 if (chip
->driver_caps
& AZX_DCAPS_SEPARATE_STREAM_TAG
)
1309 tag
= ++stream_tags
[dir
];
1312 snd_hdac_stream_init(azx_bus(chip
), azx_stream(azx_dev
),
1318 EXPORT_SYMBOL_GPL(azx_init_streams
);
1320 void azx_free_streams(struct azx
*chip
)
1322 struct hdac_bus
*bus
= azx_bus(chip
);
1323 struct hdac_stream
*s
;
1325 while (!list_empty(&bus
->stream_list
)) {
1326 s
= list_first_entry(&bus
->stream_list
, struct hdac_stream
, list
);
1328 kfree(stream_to_azx_dev(s
));
1331 EXPORT_SYMBOL_GPL(azx_free_streams
);