3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/set_memory.h>
57 #include <asm/cpufeature.h>
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
73 /* position fix mode */
83 /* Defines for ATI HD Audio support in SB450 south bridge */
84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
87 /* Defines for Nvidia HDA support */
88 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90 #define NVIDIA_HDA_ISTRM_COH 0x4d
91 #define NVIDIA_HDA_OSTRM_COH 0x4c
92 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
94 /* Defines for Intel SCH HDA snoop control */
95 #define INTEL_HDA_CGCTL 0x48
96 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
97 #define INTEL_SCH_HDA_DEVC 0x78
98 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
100 /* Define IN stream 0 FIFO size offset in VIA controller */
101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102 /* Define VIA HD Audio Device ID*/
103 #define VIA_HDAC_DEVICE_ID 0x3288
105 /* max number of SDs */
106 /* ICH, ATI and VIA have 4 playback and 4 capture */
107 #define ICH6_NUM_CAPTURE 4
108 #define ICH6_NUM_PLAYBACK 4
110 /* ULI has 6 playback and 5 capture */
111 #define ULI_NUM_CAPTURE 5
112 #define ULI_NUM_PLAYBACK 6
114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
115 #define ATIHDMI_NUM_CAPTURE 0
116 #define ATIHDMI_NUM_PLAYBACK 8
118 /* TERA has 4 playback and 3 capture */
119 #define TERA_NUM_CAPTURE 3
120 #define TERA_NUM_PLAYBACK 4
123 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
124 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
125 static bool enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
126 static char *model
[SNDRV_CARDS
];
127 static int position_fix
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
128 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
129 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
130 static int probe_only
[SNDRV_CARDS
];
131 static int jackpoll_ms
[SNDRV_CARDS
];
132 static int single_cmd
= -1;
133 static int enable_msi
= -1;
134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
135 static char *patch
[SNDRV_CARDS
];
137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
138 static bool beep_mode
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] =
139 CONFIG_SND_HDA_INPUT_BEEP_MODE
};
142 module_param_array(index
, int, NULL
, 0444);
143 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
144 module_param_array(id
, charp
, NULL
, 0444);
145 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
146 module_param_array(enable
, bool, NULL
, 0444);
147 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
148 module_param_array(model
, charp
, NULL
, 0444);
149 MODULE_PARM_DESC(model
, "Use the given board model.");
150 module_param_array(position_fix
, int, NULL
, 0444);
151 MODULE_PARM_DESC(position_fix
, "DMA pointer read method."
152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
153 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
154 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
155 module_param_array(probe_mask
, int, NULL
, 0444);
156 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
157 module_param_array(probe_only
, int, NULL
, 0444);
158 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
159 module_param_array(jackpoll_ms
, int, NULL
, 0444);
160 MODULE_PARM_DESC(jackpoll_ms
, "Ms between polling for jack events (default = 0, using unsol events only)");
161 module_param(single_cmd
, bint
, 0444);
162 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
163 "(for debugging only).");
164 module_param(enable_msi
, bint
, 0444);
165 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
167 module_param_array(patch
, charp
, NULL
, 0444);
168 MODULE_PARM_DESC(patch
, "Patch file for Intel HD audio interface.");
170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
171 module_param_array(beep_mode
, bool, NULL
, 0444);
172 MODULE_PARM_DESC(beep_mode
, "Select HDA Beep registration mode "
173 "(0=off, 1=on) (default=1).");
177 static int param_set_xint(const char *val
, const struct kernel_param
*kp
);
178 static const struct kernel_param_ops param_ops_xint
= {
179 .set
= param_set_xint
,
180 .get
= param_get_int
,
182 #define param_check_xint param_check_int
184 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
185 module_param(power_save
, xint
, 0644);
186 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
189 static bool pm_blacklist
= true;
190 module_param(pm_blacklist
, bool, 0644);
191 MODULE_PARM_DESC(pm_blacklist
, "Enable power-management blacklist");
193 /* reset the HD-audio controller in power save mode.
194 * this may give more power-saving, but will take longer time to
197 static bool power_save_controller
= 1;
198 module_param(power_save_controller
, bool, 0644);
199 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
202 #endif /* CONFIG_PM */
204 static int align_buffer_size
= -1;
205 module_param(align_buffer_size
, bint
, 0644);
206 MODULE_PARM_DESC(align_buffer_size
,
207 "Force buffer and period sizes to be multiple of 128 bytes.");
210 static int hda_snoop
= -1;
211 module_param_named(snoop
, hda_snoop
, bint
, 0444);
212 MODULE_PARM_DESC(snoop
, "Enable/disable snooping");
214 #define hda_snoop true
218 MODULE_LICENSE("GPL");
219 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
253 MODULE_DESCRIPTION("Intel HDA driver");
255 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
256 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
257 #define SUPPORT_VGA_SWITCHEROO
274 AZX_DRIVER_ATIHDMI_NS
,
284 AZX_NUM_DRIVERS
, /* keep this as last entry */
287 #define azx_get_snoop_type(chip) \
288 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
289 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
291 /* quirks for old Intel chipsets */
292 #define AZX_DCAPS_INTEL_ICH \
293 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
295 /* quirks for Intel PCH */
296 #define AZX_DCAPS_INTEL_PCH_BASE \
297 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
300 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
301 #define AZX_DCAPS_INTEL_PCH_NOPM \
302 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
304 /* PCH for HSW/BDW; with runtime PM */
305 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
306 #define AZX_DCAPS_INTEL_PCH \
307 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
310 #define AZX_DCAPS_INTEL_HASWELL \
311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
313 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
315 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
316 #define AZX_DCAPS_INTEL_BROADWELL \
317 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
318 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
319 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
321 #define AZX_DCAPS_INTEL_BAYTRAIL \
322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
323 AZX_DCAPS_I915_POWERWELL)
325 #define AZX_DCAPS_INTEL_BRASWELL \
326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
329 #define AZX_DCAPS_INTEL_SKYLAKE \
330 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
331 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
332 AZX_DCAPS_I915_POWERWELL)
334 #define AZX_DCAPS_INTEL_BROXTON \
335 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
336 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
337 AZX_DCAPS_I915_POWERWELL)
339 /* quirks for ATI SB / AMD Hudson */
340 #define AZX_DCAPS_PRESET_ATI_SB \
341 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
342 AZX_DCAPS_SNOOP_TYPE(ATI))
344 /* quirks for ATI/AMD HDMI */
345 #define AZX_DCAPS_PRESET_ATI_HDMI \
346 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
349 /* quirks for ATI HDMI with snoop off */
350 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
351 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
353 /* quirks for Nvidia */
354 #define AZX_DCAPS_PRESET_NVIDIA \
355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
356 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
358 #define AZX_DCAPS_PRESET_CTHDA \
359 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
360 AZX_DCAPS_NO_64BIT |\
361 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
364 * vga_switcheroo support
366 #ifdef SUPPORT_VGA_SWITCHEROO
367 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
369 #define use_vga_switcheroo(chip) 0
372 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
373 ((pci)->device == 0x0c0c) || \
374 ((pci)->device == 0x0d0c) || \
375 ((pci)->device == 0x160c))
377 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
378 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
380 static char *driver_short_names
[] = {
381 [AZX_DRIVER_ICH
] = "HDA Intel",
382 [AZX_DRIVER_PCH
] = "HDA Intel PCH",
383 [AZX_DRIVER_SCH
] = "HDA Intel MID",
384 [AZX_DRIVER_SKL
] = "HDA Intel PCH", /* kept old name for compatibility */
385 [AZX_DRIVER_HDMI
] = "HDA Intel HDMI",
386 [AZX_DRIVER_ATI
] = "HDA ATI SB",
387 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
388 [AZX_DRIVER_ATIHDMI_NS
] = "HDA ATI HDMI",
389 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
390 [AZX_DRIVER_SIS
] = "HDA SIS966",
391 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
392 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
393 [AZX_DRIVER_TERA
] = "HDA Teradici",
394 [AZX_DRIVER_CTX
] = "HDA Creative",
395 [AZX_DRIVER_CTHDA
] = "HDA Creative",
396 [AZX_DRIVER_CMEDIA
] = "HDA C-Media",
397 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
401 static void __mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*dmab
, bool on
)
407 if (!dmab
|| !dmab
->area
|| !dmab
->bytes
)
410 #ifdef CONFIG_SND_DMA_SGBUF
411 if (dmab
->dev
.type
== SNDRV_DMA_TYPE_DEV_SG
) {
412 struct snd_sg_buf
*sgbuf
= dmab
->private_data
;
413 if (chip
->driver_type
== AZX_DRIVER_CMEDIA
)
414 return; /* deal with only CORB/RIRB buffers */
416 set_pages_array_wc(sgbuf
->page_table
, sgbuf
->pages
);
418 set_pages_array_wb(sgbuf
->page_table
, sgbuf
->pages
);
423 pages
= (dmab
->bytes
+ PAGE_SIZE
- 1) >> PAGE_SHIFT
;
425 set_memory_wc((unsigned long)dmab
->area
, pages
);
427 set_memory_wb((unsigned long)dmab
->area
, pages
);
430 static inline void mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*buf
,
433 __mark_pages_wc(chip
, buf
, on
);
435 static inline void mark_runtime_wc(struct azx
*chip
, struct azx_dev
*azx_dev
,
436 struct snd_pcm_substream
*substream
, bool on
)
438 if (azx_dev
->wc_marked
!= on
) {
439 __mark_pages_wc(chip
, snd_pcm_get_dma_buf(substream
), on
);
440 azx_dev
->wc_marked
= on
;
444 /* NOP for other archs */
445 static inline void mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*buf
,
449 static inline void mark_runtime_wc(struct azx
*chip
, struct azx_dev
*azx_dev
,
450 struct snd_pcm_substream
*substream
, bool on
)
455 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
458 * initialize the PCI registers
460 /* update bits in a PCI register byte */
461 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
462 unsigned char mask
, unsigned char val
)
466 pci_read_config_byte(pci
, reg
, &data
);
468 data
|= (val
& mask
);
469 pci_write_config_byte(pci
, reg
, data
);
472 static void azx_init_pci(struct azx
*chip
)
474 int snoop_type
= azx_get_snoop_type(chip
);
476 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
477 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
478 * Ensuring these bits are 0 clears playback static on some HD Audio
480 * The PCI register TCSEL is defined in the Intel manuals.
482 if (!(chip
->driver_caps
& AZX_DCAPS_NO_TCSEL
)) {
483 dev_dbg(chip
->card
->dev
, "Clearing TCSEL\n");
484 update_pci_byte(chip
->pci
, AZX_PCIREG_TCSEL
, 0x07, 0);
487 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
488 * we need to enable snoop.
490 if (snoop_type
== AZX_SNOOP_TYPE_ATI
) {
491 dev_dbg(chip
->card
->dev
, "Setting ATI snoop: %d\n",
493 update_pci_byte(chip
->pci
,
494 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
, 0x07,
495 azx_snoop(chip
) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP
: 0);
498 /* For NVIDIA HDA, enable snoop */
499 if (snoop_type
== AZX_SNOOP_TYPE_NVIDIA
) {
500 dev_dbg(chip
->card
->dev
, "Setting Nvidia snoop: %d\n",
502 update_pci_byte(chip
->pci
,
503 NVIDIA_HDA_TRANSREG_ADDR
,
504 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
505 update_pci_byte(chip
->pci
,
506 NVIDIA_HDA_ISTRM_COH
,
507 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
508 update_pci_byte(chip
->pci
,
509 NVIDIA_HDA_OSTRM_COH
,
510 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
513 /* Enable SCH/PCH snoop if needed */
514 if (snoop_type
== AZX_SNOOP_TYPE_SCH
) {
515 unsigned short snoop
;
516 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
517 if ((!azx_snoop(chip
) && !(snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)) ||
518 (azx_snoop(chip
) && (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
))) {
519 snoop
&= ~INTEL_SCH_HDA_DEVC_NOSNOOP
;
520 if (!azx_snoop(chip
))
521 snoop
|= INTEL_SCH_HDA_DEVC_NOSNOOP
;
522 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, snoop
);
523 pci_read_config_word(chip
->pci
,
524 INTEL_SCH_HDA_DEVC
, &snoop
);
526 dev_dbg(chip
->card
->dev
, "SCH snoop: %s\n",
527 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) ?
528 "Disabled" : "Enabled");
533 * In BXT-P A0, HD-Audio DMA requests is later than expected,
534 * and makes an audio stream sensitive to system latencies when
535 * 24/32 bits are playing.
536 * Adjusting threshold of DMA fifo to force the DMA request
537 * sooner to improve latency tolerance at the expense of power.
539 static void bxt_reduce_dma_latency(struct azx
*chip
)
543 val
= azx_readl(chip
, VS_EM4L
);
545 azx_writel(chip
, VS_EM4L
, val
);
550 * bit 0: 6 MHz Supported
551 * bit 1: 12 MHz Supported
552 * bit 2: 24 MHz Supported
553 * bit 3: 48 MHz Supported
554 * bit 4: 96 MHz Supported
555 * bit 5: 192 MHz Supported
557 static int intel_get_lctl_scf(struct azx
*chip
)
559 struct hdac_bus
*bus
= azx_bus(chip
);
560 static int preferred_bits
[] = { 2, 3, 1, 4, 5 };
564 val
= readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCAP
);
566 for (i
= 0; i
< ARRAY_SIZE(preferred_bits
); i
++) {
567 t
= preferred_bits
[i
];
572 dev_warn(chip
->card
->dev
, "set audio clock frequency to 6MHz");
576 static int intel_ml_lctl_set_power(struct azx
*chip
, int state
)
578 struct hdac_bus
*bus
= azx_bus(chip
);
583 * the codecs are sharing the first link setting by default
584 * If other links are enabled for stream, they need similar fix
586 val
= readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
587 val
&= ~AZX_MLCTL_SPA
;
588 val
|= state
<< AZX_MLCTL_SPA_SHIFT
;
589 writel(val
, bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
593 if (((readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
)) &
594 AZX_MLCTL_CPA
) == (state
<< AZX_MLCTL_CPA_SHIFT
))
603 static void intel_init_lctl(struct azx
*chip
)
605 struct hdac_bus
*bus
= azx_bus(chip
);
609 /* 0. check lctl register value is correct or not */
610 val
= readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
611 /* if SCF is already set, let's use it */
612 if ((val
& ML_LCTL_SCF_MASK
) != 0)
616 * Before operating on SPA, CPA must match SPA.
617 * Any deviation may result in undefined behavior.
619 if (((val
& AZX_MLCTL_SPA
) >> AZX_MLCTL_SPA_SHIFT
) !=
620 ((val
& AZX_MLCTL_CPA
) >> AZX_MLCTL_CPA_SHIFT
))
623 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
624 ret
= intel_ml_lctl_set_power(chip
, 0);
629 /* 2. update SCF to select a properly audio clock*/
630 val
&= ~ML_LCTL_SCF_MASK
;
631 val
|= intel_get_lctl_scf(chip
);
632 writel(val
, bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
635 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
636 intel_ml_lctl_set_power(chip
, 1);
640 static void hda_intel_init_chip(struct azx
*chip
, bool full_reset
)
642 struct hdac_bus
*bus
= azx_bus(chip
);
643 struct pci_dev
*pci
= chip
->pci
;
646 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
647 snd_hdac_set_codec_wakeup(bus
, true);
648 if (chip
->driver_type
== AZX_DRIVER_SKL
) {
649 pci_read_config_dword(pci
, INTEL_HDA_CGCTL
, &val
);
650 val
= val
& ~INTEL_HDA_CGCTL_MISCBDCGE
;
651 pci_write_config_dword(pci
, INTEL_HDA_CGCTL
, val
);
653 azx_init_chip(chip
, full_reset
);
654 if (chip
->driver_type
== AZX_DRIVER_SKL
) {
655 pci_read_config_dword(pci
, INTEL_HDA_CGCTL
, &val
);
656 val
= val
| INTEL_HDA_CGCTL_MISCBDCGE
;
657 pci_write_config_dword(pci
, INTEL_HDA_CGCTL
, val
);
659 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
660 snd_hdac_set_codec_wakeup(bus
, false);
662 /* reduce dma latency to avoid noise */
664 bxt_reduce_dma_latency(chip
);
666 if (bus
->mlcap
!= NULL
)
667 intel_init_lctl(chip
);
670 /* calculate runtime delay from LPIB */
671 static int azx_get_delay_from_lpib(struct azx
*chip
, struct azx_dev
*azx_dev
,
674 struct snd_pcm_substream
*substream
= azx_dev
->core
.substream
;
675 int stream
= substream
->stream
;
676 unsigned int lpib_pos
= azx_get_pos_lpib(chip
, azx_dev
);
679 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
680 delay
= pos
- lpib_pos
;
682 delay
= lpib_pos
- pos
;
684 if (delay
>= azx_dev
->core
.delay_negative_threshold
)
687 delay
+= azx_dev
->core
.bufsize
;
690 if (delay
>= azx_dev
->core
.period_bytes
) {
691 dev_info(chip
->card
->dev
,
692 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
693 delay
, azx_dev
->core
.period_bytes
);
695 chip
->driver_caps
&= ~AZX_DCAPS_COUNT_LPIB_DELAY
;
696 chip
->get_delay
[stream
] = NULL
;
699 return bytes_to_frames(substream
->runtime
, delay
);
702 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
704 /* called from IRQ */
705 static int azx_position_check(struct azx
*chip
, struct azx_dev
*azx_dev
)
707 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
710 ok
= azx_position_ok(chip
, azx_dev
);
712 azx_dev
->irq_pending
= 0;
714 } else if (ok
== 0) {
715 /* bogus IRQ, process it later */
716 azx_dev
->irq_pending
= 1;
717 schedule_work(&hda
->irq_pending_work
);
722 /* Enable/disable i915 display power for the link */
723 static int azx_intel_link_power(struct azx
*chip
, bool enable
)
725 struct hdac_bus
*bus
= azx_bus(chip
);
727 return snd_hdac_display_power(bus
, enable
);
731 * Check whether the current DMA position is acceptable for updating
732 * periods. Returns non-zero if it's OK.
734 * Many HD-audio controllers appear pretty inaccurate about
735 * the update-IRQ timing. The IRQ is issued before actually the
736 * data is processed. So, we need to process it afterwords in a
739 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
741 struct snd_pcm_substream
*substream
= azx_dev
->core
.substream
;
742 int stream
= substream
->stream
;
746 wallclk
= azx_readl(chip
, WALLCLK
) - azx_dev
->core
.start_wallclk
;
747 if (wallclk
< (azx_dev
->core
.period_wallclk
* 2) / 3)
748 return -1; /* bogus (too early) interrupt */
750 if (chip
->get_position
[stream
])
751 pos
= chip
->get_position
[stream
](chip
, azx_dev
);
752 else { /* use the position buffer as default */
753 pos
= azx_get_pos_posbuf(chip
, azx_dev
);
754 if (!pos
|| pos
== (u32
)-1) {
755 dev_info(chip
->card
->dev
,
756 "Invalid position buffer, using LPIB read method instead.\n");
757 chip
->get_position
[stream
] = azx_get_pos_lpib
;
758 if (chip
->get_position
[0] == azx_get_pos_lpib
&&
759 chip
->get_position
[1] == azx_get_pos_lpib
)
760 azx_bus(chip
)->use_posbuf
= false;
761 pos
= azx_get_pos_lpib(chip
, azx_dev
);
762 chip
->get_delay
[stream
] = NULL
;
764 chip
->get_position
[stream
] = azx_get_pos_posbuf
;
765 if (chip
->driver_caps
& AZX_DCAPS_COUNT_LPIB_DELAY
)
766 chip
->get_delay
[stream
] = azx_get_delay_from_lpib
;
770 if (pos
>= azx_dev
->core
.bufsize
)
773 if (WARN_ONCE(!azx_dev
->core
.period_bytes
,
774 "hda-intel: zero azx_dev->period_bytes"))
775 return -1; /* this shouldn't happen! */
776 if (wallclk
< (azx_dev
->core
.period_wallclk
* 5) / 4 &&
777 pos
% azx_dev
->core
.period_bytes
> azx_dev
->core
.period_bytes
/ 2)
778 /* NG - it's below the first next period boundary */
779 return chip
->bdl_pos_adj
? 0 : -1;
780 azx_dev
->core
.start_wallclk
+= wallclk
;
781 return 1; /* OK, it's fine */
785 * The work for pending PCM period updates.
787 static void azx_irq_pending_work(struct work_struct
*work
)
789 struct hda_intel
*hda
= container_of(work
, struct hda_intel
, irq_pending_work
);
790 struct azx
*chip
= &hda
->chip
;
791 struct hdac_bus
*bus
= azx_bus(chip
);
792 struct hdac_stream
*s
;
795 if (!hda
->irq_pending_warned
) {
796 dev_info(chip
->card
->dev
,
797 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
799 hda
->irq_pending_warned
= 1;
804 spin_lock_irq(&bus
->reg_lock
);
805 list_for_each_entry(s
, &bus
->stream_list
, list
) {
806 struct azx_dev
*azx_dev
= stream_to_azx_dev(s
);
807 if (!azx_dev
->irq_pending
||
811 ok
= azx_position_ok(chip
, azx_dev
);
813 azx_dev
->irq_pending
= 0;
814 spin_unlock(&bus
->reg_lock
);
815 snd_pcm_period_elapsed(s
->substream
);
816 spin_lock(&bus
->reg_lock
);
818 pending
= 0; /* too early */
822 spin_unlock_irq(&bus
->reg_lock
);
829 /* clear irq_pending flags and assure no on-going workq */
830 static void azx_clear_irq_pending(struct azx
*chip
)
832 struct hdac_bus
*bus
= azx_bus(chip
);
833 struct hdac_stream
*s
;
835 spin_lock_irq(&bus
->reg_lock
);
836 list_for_each_entry(s
, &bus
->stream_list
, list
) {
837 struct azx_dev
*azx_dev
= stream_to_azx_dev(s
);
838 azx_dev
->irq_pending
= 0;
840 spin_unlock_irq(&bus
->reg_lock
);
843 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
845 struct hdac_bus
*bus
= azx_bus(chip
);
847 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
848 chip
->msi
? 0 : IRQF_SHARED
,
849 chip
->card
->irq_descr
, chip
)) {
850 dev_err(chip
->card
->dev
,
851 "unable to grab IRQ %d, disabling device\n",
854 snd_card_disconnect(chip
->card
);
857 bus
->irq
= chip
->pci
->irq
;
858 pci_intx(chip
->pci
, !chip
->msi
);
862 /* get the current DMA position with correction on VIA chips */
863 static unsigned int azx_via_get_position(struct azx
*chip
,
864 struct azx_dev
*azx_dev
)
866 unsigned int link_pos
, mini_pos
, bound_pos
;
867 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
868 unsigned int fifo_size
;
870 link_pos
= snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev
));
871 if (azx_dev
->core
.substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
872 /* Playback, no problem using link position */
878 * use mod to get the DMA position just like old chipset
880 mod_dma_pos
= le32_to_cpu(*azx_dev
->core
.posbuf
);
881 mod_dma_pos
%= azx_dev
->core
.period_bytes
;
883 /* azx_dev->fifo_size can't get FIFO size of in stream.
884 * Get from base address + offset.
886 fifo_size
= readw(azx_bus(chip
)->remap_addr
+
887 VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
889 if (azx_dev
->insufficient
) {
890 /* Link position never gather than FIFO size */
891 if (link_pos
<= fifo_size
)
894 azx_dev
->insufficient
= 0;
897 if (link_pos
<= fifo_size
)
898 mini_pos
= azx_dev
->core
.bufsize
+ link_pos
- fifo_size
;
900 mini_pos
= link_pos
- fifo_size
;
902 /* Find nearest previous boudary */
903 mod_mini_pos
= mini_pos
% azx_dev
->core
.period_bytes
;
904 mod_link_pos
= link_pos
% azx_dev
->core
.period_bytes
;
905 if (mod_link_pos
>= fifo_size
)
906 bound_pos
= link_pos
- mod_link_pos
;
907 else if (mod_dma_pos
>= mod_mini_pos
)
908 bound_pos
= mini_pos
- mod_mini_pos
;
910 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->core
.period_bytes
;
911 if (bound_pos
>= azx_dev
->core
.bufsize
)
915 /* Calculate real DMA position we want */
916 return bound_pos
+ mod_dma_pos
;
919 static unsigned int azx_skl_get_dpib_pos(struct azx
*chip
,
920 struct azx_dev
*azx_dev
)
922 return _snd_hdac_chip_readl(azx_bus(chip
),
923 AZX_REG_VS_SDXDPIB_XBASE
+
924 (AZX_REG_VS_SDXDPIB_XINTERVAL
*
925 azx_dev
->core
.index
));
928 /* get the current DMA position with correction on SKL+ chips */
929 static unsigned int azx_get_pos_skl(struct azx
*chip
, struct azx_dev
*azx_dev
)
931 /* DPIB register gives a more accurate position for playback */
932 if (azx_dev
->core
.substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
933 return azx_skl_get_dpib_pos(chip
, azx_dev
);
935 /* For capture, we need to read posbuf, but it requires a delay
936 * for the possible boundary overlap; the read of DPIB fetches the
940 azx_skl_get_dpib_pos(chip
, azx_dev
);
941 return azx_get_pos_posbuf(chip
, azx_dev
);
945 static DEFINE_MUTEX(card_list_lock
);
946 static LIST_HEAD(card_list
);
948 static void azx_add_card_list(struct azx
*chip
)
950 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
951 mutex_lock(&card_list_lock
);
952 list_add(&hda
->list
, &card_list
);
953 mutex_unlock(&card_list_lock
);
956 static void azx_del_card_list(struct azx
*chip
)
958 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
959 mutex_lock(&card_list_lock
);
960 list_del_init(&hda
->list
);
961 mutex_unlock(&card_list_lock
);
964 /* trigger power-save check at writing parameter */
965 static int param_set_xint(const char *val
, const struct kernel_param
*kp
)
967 struct hda_intel
*hda
;
969 int prev
= power_save
;
970 int ret
= param_set_int(val
, kp
);
972 if (ret
|| prev
== power_save
)
975 mutex_lock(&card_list_lock
);
976 list_for_each_entry(hda
, &card_list
, list
) {
978 if (!hda
->probe_continued
|| chip
->disabled
)
980 snd_hda_set_power_save(&chip
->bus
, power_save
* 1000);
982 mutex_unlock(&card_list_lock
);
986 #define azx_add_card_list(chip) /* NOP */
987 #define azx_del_card_list(chip) /* NOP */
988 #endif /* CONFIG_PM */
990 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
994 static int azx_suspend(struct device
*dev
)
996 struct snd_card
*card
= dev_get_drvdata(dev
);
998 struct hda_intel
*hda
;
999 struct hdac_bus
*bus
;
1004 chip
= card
->private_data
;
1005 hda
= container_of(chip
, struct hda_intel
, chip
);
1006 if (chip
->disabled
|| hda
->init_failed
|| !chip
->running
)
1009 bus
= azx_bus(chip
);
1010 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1011 azx_clear_irq_pending(chip
);
1012 azx_stop_chip(chip
);
1013 azx_enter_link_reset(chip
);
1014 if (bus
->irq
>= 0) {
1015 free_irq(bus
->irq
, chip
);
1020 pci_disable_msi(chip
->pci
);
1021 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
1022 && hda
->need_i915_power
)
1023 snd_hdac_display_power(bus
, false);
1025 trace_azx_suspend(chip
);
1029 static int azx_resume(struct device
*dev
)
1031 struct pci_dev
*pci
= to_pci_dev(dev
);
1032 struct snd_card
*card
= dev_get_drvdata(dev
);
1034 struct hda_intel
*hda
;
1035 struct hdac_bus
*bus
;
1040 chip
= card
->private_data
;
1041 hda
= container_of(chip
, struct hda_intel
, chip
);
1042 bus
= azx_bus(chip
);
1043 if (chip
->disabled
|| hda
->init_failed
|| !chip
->running
)
1046 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
1047 snd_hdac_display_power(bus
, true);
1048 if (hda
->need_i915_power
)
1049 snd_hdac_i915_set_bclk(bus
);
1053 if (pci_enable_msi(pci
) < 0)
1055 if (azx_acquire_irq(chip
, 1) < 0)
1059 hda_intel_init_chip(chip
, true);
1061 /* power down again for link-controlled chips */
1062 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) &&
1063 !hda
->need_i915_power
)
1064 snd_hdac_display_power(bus
, false);
1066 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1068 trace_azx_resume(chip
);
1071 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1073 #ifdef CONFIG_PM_SLEEP
1074 /* put codec down to D3 at hibernation for Intel SKL+;
1075 * otherwise BIOS may still access the codec and screw up the driver
1077 static int azx_freeze_noirq(struct device
*dev
)
1079 struct snd_card
*card
= dev_get_drvdata(dev
);
1080 struct azx
*chip
= card
->private_data
;
1081 struct pci_dev
*pci
= to_pci_dev(dev
);
1083 if (chip
->driver_type
== AZX_DRIVER_SKL
)
1084 pci_set_power_state(pci
, PCI_D3hot
);
1089 static int azx_thaw_noirq(struct device
*dev
)
1091 struct snd_card
*card
= dev_get_drvdata(dev
);
1092 struct azx
*chip
= card
->private_data
;
1093 struct pci_dev
*pci
= to_pci_dev(dev
);
1095 if (chip
->driver_type
== AZX_DRIVER_SKL
)
1096 pci_set_power_state(pci
, PCI_D0
);
1100 #endif /* CONFIG_PM_SLEEP */
1103 static int azx_runtime_suspend(struct device
*dev
)
1105 struct snd_card
*card
= dev_get_drvdata(dev
);
1107 struct hda_intel
*hda
;
1112 chip
= card
->private_data
;
1113 hda
= container_of(chip
, struct hda_intel
, chip
);
1114 if (chip
->disabled
|| hda
->init_failed
)
1117 if (!azx_has_pm_runtime(chip
))
1120 /* enable controller wake up event */
1121 azx_writew(chip
, WAKEEN
, azx_readw(chip
, WAKEEN
) |
1124 azx_stop_chip(chip
);
1125 azx_enter_link_reset(chip
);
1126 azx_clear_irq_pending(chip
);
1127 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
1128 && hda
->need_i915_power
)
1129 snd_hdac_display_power(azx_bus(chip
), false);
1131 trace_azx_runtime_suspend(chip
);
1135 static int azx_runtime_resume(struct device
*dev
)
1137 struct snd_card
*card
= dev_get_drvdata(dev
);
1139 struct hda_intel
*hda
;
1140 struct hdac_bus
*bus
;
1141 struct hda_codec
*codec
;
1147 chip
= card
->private_data
;
1148 hda
= container_of(chip
, struct hda_intel
, chip
);
1149 bus
= azx_bus(chip
);
1150 if (chip
->disabled
|| hda
->init_failed
)
1153 if (!azx_has_pm_runtime(chip
))
1156 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
1157 snd_hdac_display_power(bus
, true);
1158 if (hda
->need_i915_power
)
1159 snd_hdac_i915_set_bclk(bus
);
1162 /* Read STATESTS before controller reset */
1163 status
= azx_readw(chip
, STATESTS
);
1166 hda_intel_init_chip(chip
, true);
1169 list_for_each_codec(codec
, &chip
->bus
)
1170 if (status
& (1 << codec
->addr
))
1171 schedule_delayed_work(&codec
->jackpoll_work
,
1172 codec
->jackpoll_interval
);
1175 /* disable controller Wake Up event*/
1176 azx_writew(chip
, WAKEEN
, azx_readw(chip
, WAKEEN
) &
1177 ~STATESTS_INT_MASK
);
1179 /* power down again for link-controlled chips */
1180 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) &&
1181 !hda
->need_i915_power
)
1182 snd_hdac_display_power(bus
, false);
1184 trace_azx_runtime_resume(chip
);
1188 static int azx_runtime_idle(struct device
*dev
)
1190 struct snd_card
*card
= dev_get_drvdata(dev
);
1192 struct hda_intel
*hda
;
1197 chip
= card
->private_data
;
1198 hda
= container_of(chip
, struct hda_intel
, chip
);
1199 if (chip
->disabled
|| hda
->init_failed
)
1202 if (!power_save_controller
|| !azx_has_pm_runtime(chip
) ||
1203 azx_bus(chip
)->codec_powered
|| !chip
->running
)
1209 static const struct dev_pm_ops azx_pm
= {
1210 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend
, azx_resume
)
1211 #ifdef CONFIG_PM_SLEEP
1212 .freeze_noirq
= azx_freeze_noirq
,
1213 .thaw_noirq
= azx_thaw_noirq
,
1215 SET_RUNTIME_PM_OPS(azx_runtime_suspend
, azx_runtime_resume
, azx_runtime_idle
)
1218 #define AZX_PM_OPS &azx_pm
1220 #define AZX_PM_OPS NULL
1221 #endif /* CONFIG_PM */
1224 static int azx_probe_continue(struct azx
*chip
);
1226 #ifdef SUPPORT_VGA_SWITCHEROO
1227 static struct pci_dev
*get_bound_vga(struct pci_dev
*pci
);
1229 static void azx_vs_set_state(struct pci_dev
*pci
,
1230 enum vga_switcheroo_state state
)
1232 struct snd_card
*card
= pci_get_drvdata(pci
);
1233 struct azx
*chip
= card
->private_data
;
1234 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1237 wait_for_completion(&hda
->probe_wait
);
1238 if (hda
->init_failed
)
1241 disabled
= (state
== VGA_SWITCHEROO_OFF
);
1242 if (chip
->disabled
== disabled
)
1245 if (!hda
->probe_continued
) {
1246 chip
->disabled
= disabled
;
1248 dev_info(chip
->card
->dev
,
1249 "Start delayed initialization\n");
1250 if (azx_probe_continue(chip
) < 0) {
1251 dev_err(chip
->card
->dev
, "initialization error\n");
1252 hda
->init_failed
= true;
1256 dev_info(chip
->card
->dev
, "%s via vga_switcheroo\n",
1257 disabled
? "Disabling" : "Enabling");
1259 pm_runtime_put_sync_suspend(card
->dev
);
1260 azx_suspend(card
->dev
);
1261 /* when we get suspended by vga_switcheroo we end up in D3cold,
1262 * however we have no ACPI handle, so pci/acpi can't put us there,
1263 * put ourselves there */
1264 pci
->current_state
= PCI_D3cold
;
1265 chip
->disabled
= true;
1266 if (snd_hda_lock_devices(&chip
->bus
))
1267 dev_warn(chip
->card
->dev
,
1268 "Cannot lock devices!\n");
1270 snd_hda_unlock_devices(&chip
->bus
);
1271 pm_runtime_get_noresume(card
->dev
);
1272 chip
->disabled
= false;
1273 azx_resume(card
->dev
);
1278 static bool azx_vs_can_switch(struct pci_dev
*pci
)
1280 struct snd_card
*card
= pci_get_drvdata(pci
);
1281 struct azx
*chip
= card
->private_data
;
1282 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1284 wait_for_completion(&hda
->probe_wait
);
1285 if (hda
->init_failed
)
1287 if (chip
->disabled
|| !hda
->probe_continued
)
1289 if (snd_hda_lock_devices(&chip
->bus
))
1291 snd_hda_unlock_devices(&chip
->bus
);
1295 static void init_vga_switcheroo(struct azx
*chip
)
1297 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1298 struct pci_dev
*p
= get_bound_vga(chip
->pci
);
1300 dev_info(chip
->card
->dev
,
1301 "Handle vga_switcheroo audio client\n");
1302 hda
->use_vga_switcheroo
= 1;
1307 static const struct vga_switcheroo_client_ops azx_vs_ops
= {
1308 .set_gpu_state
= azx_vs_set_state
,
1309 .can_switch
= azx_vs_can_switch
,
1312 static int register_vga_switcheroo(struct azx
*chip
)
1314 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1318 if (!hda
->use_vga_switcheroo
)
1321 p
= get_bound_vga(chip
->pci
);
1322 err
= vga_switcheroo_register_audio_client(chip
->pci
, &azx_vs_ops
, p
);
1327 hda
->vga_switcheroo_registered
= 1;
1329 /* register as an optimus hdmi audio power domain */
1330 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip
->card
->dev
,
1331 &hda
->hdmi_pm_domain
);
1335 #define init_vga_switcheroo(chip) /* NOP */
1336 #define register_vga_switcheroo(chip) 0
1337 #define check_hdmi_disabled(pci) false
1338 #endif /* SUPPORT_VGA_SWITCHER */
1343 static int azx_free(struct azx
*chip
)
1345 struct pci_dev
*pci
= chip
->pci
;
1346 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1347 struct hdac_bus
*bus
= azx_bus(chip
);
1349 if (azx_has_pm_runtime(chip
) && chip
->running
)
1350 pm_runtime_get_noresume(&pci
->dev
);
1352 azx_del_card_list(chip
);
1354 hda
->init_failed
= 1; /* to be sure */
1355 complete_all(&hda
->probe_wait
);
1357 if (use_vga_switcheroo(hda
)) {
1358 if (chip
->disabled
&& hda
->probe_continued
)
1359 snd_hda_unlock_devices(&chip
->bus
);
1360 if (hda
->vga_switcheroo_registered
) {
1361 vga_switcheroo_unregister_client(chip
->pci
);
1362 vga_switcheroo_fini_domain_pm_ops(chip
->card
->dev
);
1366 if (bus
->chip_init
) {
1367 azx_clear_irq_pending(chip
);
1368 azx_stop_all_streams(chip
);
1369 azx_stop_chip(chip
);
1373 free_irq(bus
->irq
, (void*)chip
);
1375 pci_disable_msi(chip
->pci
);
1376 iounmap(bus
->remap_addr
);
1378 azx_free_stream_pages(chip
);
1379 azx_free_streams(chip
);
1380 snd_hdac_bus_exit(bus
);
1382 if (chip
->region_requested
)
1383 pci_release_regions(chip
->pci
);
1385 pci_disable_device(chip
->pci
);
1386 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1387 release_firmware(chip
->fw
);
1390 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
1391 if (hda
->need_i915_power
)
1392 snd_hdac_display_power(bus
, false);
1394 if (chip
->driver_caps
& AZX_DCAPS_I915_COMPONENT
)
1395 snd_hdac_i915_exit(bus
);
1401 static int azx_dev_disconnect(struct snd_device
*device
)
1403 struct azx
*chip
= device
->device_data
;
1405 chip
->bus
.shutdown
= 1;
1409 static int azx_dev_free(struct snd_device
*device
)
1411 return azx_free(device
->device_data
);
1414 #ifdef SUPPORT_VGA_SWITCHEROO
1416 * Check of disabled HDMI controller by vga_switcheroo
1418 static struct pci_dev
*get_bound_vga(struct pci_dev
*pci
)
1422 /* check only discrete GPU */
1423 switch (pci
->vendor
) {
1424 case PCI_VENDOR_ID_ATI
:
1425 case PCI_VENDOR_ID_AMD
:
1426 case PCI_VENDOR_ID_NVIDIA
:
1427 if (pci
->devfn
== 1) {
1428 p
= pci_get_domain_bus_and_slot(pci_domain_nr(pci
->bus
),
1429 pci
->bus
->number
, 0);
1431 if ((p
->class >> 16) == PCI_BASE_CLASS_DISPLAY
)
1441 static bool check_hdmi_disabled(struct pci_dev
*pci
)
1443 bool vga_inactive
= false;
1444 struct pci_dev
*p
= get_bound_vga(pci
);
1447 if (vga_switcheroo_get_client_state(p
) == VGA_SWITCHEROO_OFF
)
1448 vga_inactive
= true;
1451 return vga_inactive
;
1453 #endif /* SUPPORT_VGA_SWITCHEROO */
1456 * white/black-listing for position_fix
1458 static struct snd_pci_quirk position_fix_list
[] = {
1459 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
1460 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
1461 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB
),
1462 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
1463 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB
),
1464 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB
),
1465 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB
),
1466 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB
),
1467 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB
),
1468 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB
),
1469 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB
),
1470 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB
),
1471 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB
),
1472 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB
),
1476 static int check_position_fix(struct azx
*chip
, int fix
)
1478 const struct snd_pci_quirk
*q
;
1483 case POS_FIX_POSBUF
:
1484 case POS_FIX_VIACOMBO
:
1490 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
1492 dev_info(chip
->card
->dev
,
1493 "position_fix set to %d for device %04x:%04x\n",
1494 q
->value
, q
->subvendor
, q
->subdevice
);
1498 /* Check VIA/ATI HD Audio Controller exist */
1499 if (chip
->driver_type
== AZX_DRIVER_VIA
) {
1500 dev_dbg(chip
->card
->dev
, "Using VIACOMBO position fix\n");
1501 return POS_FIX_VIACOMBO
;
1503 if (chip
->driver_caps
& AZX_DCAPS_POSFIX_LPIB
) {
1504 dev_dbg(chip
->card
->dev
, "Using LPIB position fix\n");
1505 return POS_FIX_LPIB
;
1507 if (chip
->driver_type
== AZX_DRIVER_SKL
) {
1508 dev_dbg(chip
->card
->dev
, "Using SKL position fix\n");
1511 return POS_FIX_AUTO
;
1514 static void assign_position_fix(struct azx
*chip
, int fix
)
1516 static azx_get_pos_callback_t callbacks
[] = {
1517 [POS_FIX_AUTO
] = NULL
,
1518 [POS_FIX_LPIB
] = azx_get_pos_lpib
,
1519 [POS_FIX_POSBUF
] = azx_get_pos_posbuf
,
1520 [POS_FIX_VIACOMBO
] = azx_via_get_position
,
1521 [POS_FIX_COMBO
] = azx_get_pos_lpib
,
1522 [POS_FIX_SKL
] = azx_get_pos_skl
,
1525 chip
->get_position
[0] = chip
->get_position
[1] = callbacks
[fix
];
1527 /* combo mode uses LPIB only for playback */
1528 if (fix
== POS_FIX_COMBO
)
1529 chip
->get_position
[1] = NULL
;
1531 if ((fix
== POS_FIX_POSBUF
|| fix
== POS_FIX_SKL
) &&
1532 (chip
->driver_caps
& AZX_DCAPS_COUNT_LPIB_DELAY
)) {
1533 chip
->get_delay
[0] = chip
->get_delay
[1] =
1534 azx_get_delay_from_lpib
;
1540 * black-lists for probe_mask
1542 static struct snd_pci_quirk probe_mask_list
[] = {
1543 /* Thinkpad often breaks the controller communication when accessing
1544 * to the non-working (or non-existing) modem codec slot.
1546 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1547 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1548 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1550 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1551 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1552 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1553 /* forced codec slots */
1554 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1555 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1556 /* WinFast VP200 H (Teradici) user reported broken communication */
1557 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1561 #define AZX_FORCE_CODEC_MASK 0x100
1563 static void check_probe_mask(struct azx
*chip
, int dev
)
1565 const struct snd_pci_quirk
*q
;
1567 chip
->codec_probe_mask
= probe_mask
[dev
];
1568 if (chip
->codec_probe_mask
== -1) {
1569 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
1571 dev_info(chip
->card
->dev
,
1572 "probe_mask set to 0x%x for device %04x:%04x\n",
1573 q
->value
, q
->subvendor
, q
->subdevice
);
1574 chip
->codec_probe_mask
= q
->value
;
1578 /* check forced option */
1579 if (chip
->codec_probe_mask
!= -1 &&
1580 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
1581 azx_bus(chip
)->codec_mask
= chip
->codec_probe_mask
& 0xff;
1582 dev_info(chip
->card
->dev
, "codec_mask forced to 0x%x\n",
1583 (int)azx_bus(chip
)->codec_mask
);
1588 * white/black-list for enable_msi
1590 static struct snd_pci_quirk msi_black_list
[] = {
1591 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1592 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1593 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1594 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1595 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1596 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1597 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1598 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1599 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1600 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1604 static void check_msi(struct azx
*chip
)
1606 const struct snd_pci_quirk
*q
;
1608 if (enable_msi
>= 0) {
1609 chip
->msi
= !!enable_msi
;
1612 chip
->msi
= 1; /* enable MSI as default */
1613 q
= snd_pci_quirk_lookup(chip
->pci
, msi_black_list
);
1615 dev_info(chip
->card
->dev
,
1616 "msi for device %04x:%04x set to %d\n",
1617 q
->subvendor
, q
->subdevice
, q
->value
);
1618 chip
->msi
= q
->value
;
1622 /* NVidia chipsets seem to cause troubles with MSI */
1623 if (chip
->driver_caps
& AZX_DCAPS_NO_MSI
) {
1624 dev_info(chip
->card
->dev
, "Disabling MSI\n");
1629 /* check the snoop mode availability */
1630 static void azx_check_snoop_available(struct azx
*chip
)
1632 int snoop
= hda_snoop
;
1635 dev_info(chip
->card
->dev
, "Force to %s mode by module option\n",
1636 snoop
? "snoop" : "non-snoop");
1637 chip
->snoop
= snoop
;
1642 if (azx_get_snoop_type(chip
) == AZX_SNOOP_TYPE_NONE
&&
1643 chip
->driver_type
== AZX_DRIVER_VIA
) {
1644 /* force to non-snoop mode for a new VIA controller
1648 pci_read_config_byte(chip
->pci
, 0x42, &val
);
1649 if (!(val
& 0x80) && (chip
->pci
->revision
== 0x30 ||
1650 chip
->pci
->revision
== 0x20))
1654 if (chip
->driver_caps
& AZX_DCAPS_SNOOP_OFF
)
1657 chip
->snoop
= snoop
;
1659 dev_info(chip
->card
->dev
, "Force to non-snoop mode\n");
1662 static void azx_probe_work(struct work_struct
*work
)
1664 struct hda_intel
*hda
= container_of(work
, struct hda_intel
, probe_work
);
1665 azx_probe_continue(&hda
->chip
);
1668 static int default_bdl_pos_adj(struct azx
*chip
)
1670 /* some exceptions: Atoms seem problematic with value 1 */
1671 if (chip
->pci
->vendor
== PCI_VENDOR_ID_INTEL
) {
1672 switch (chip
->pci
->device
) {
1673 case 0x0f04: /* Baytrail */
1674 case 0x2284: /* Braswell */
1679 switch (chip
->driver_type
) {
1680 case AZX_DRIVER_ICH
:
1681 case AZX_DRIVER_PCH
:
1691 static const struct hdac_io_ops pci_hda_io_ops
;
1692 static const struct hda_controller_ops pci_hda_ops
;
1694 static int azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1695 int dev
, unsigned int driver_caps
,
1698 static struct snd_device_ops ops
= {
1699 .dev_disconnect
= azx_dev_disconnect
,
1700 .dev_free
= azx_dev_free
,
1702 struct hda_intel
*hda
;
1708 err
= pci_enable_device(pci
);
1712 hda
= kzalloc(sizeof(*hda
), GFP_KERNEL
);
1714 pci_disable_device(pci
);
1719 mutex_init(&chip
->open_mutex
);
1722 chip
->ops
= &pci_hda_ops
;
1723 chip
->driver_caps
= driver_caps
;
1724 chip
->driver_type
= driver_caps
& 0xff;
1726 chip
->dev_index
= dev
;
1727 chip
->jackpoll_ms
= jackpoll_ms
;
1728 INIT_LIST_HEAD(&chip
->pcm_list
);
1729 INIT_WORK(&hda
->irq_pending_work
, azx_irq_pending_work
);
1730 INIT_LIST_HEAD(&hda
->list
);
1731 init_vga_switcheroo(chip
);
1732 init_completion(&hda
->probe_wait
);
1734 assign_position_fix(chip
, check_position_fix(chip
, position_fix
[dev
]));
1736 check_probe_mask(chip
, dev
);
1738 if (single_cmd
< 0) /* allow fallback to single_cmd at errors */
1739 chip
->fallback_to_single_cmd
= 1;
1740 else /* explicitly set to single_cmd or not */
1741 chip
->single_cmd
= single_cmd
;
1743 azx_check_snoop_available(chip
);
1745 if (bdl_pos_adj
[dev
] < 0)
1746 chip
->bdl_pos_adj
= default_bdl_pos_adj(chip
);
1748 chip
->bdl_pos_adj
= bdl_pos_adj
[dev
];
1750 /* Workaround for a communication error on CFL (bko#199007) */
1752 chip
->polling_mode
= 1;
1754 err
= azx_bus_init(chip
, model
[dev
], &pci_hda_io_ops
);
1757 pci_disable_device(pci
);
1761 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
) {
1762 dev_dbg(chip
->card
->dev
, "Enable delay in RIRB handling\n");
1763 chip
->bus
.needs_damn_long_delay
= 1;
1766 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
1768 dev_err(card
->dev
, "Error creating device [card]!\n");
1773 /* continue probing in work context as may trigger request module */
1774 INIT_WORK(&hda
->probe_work
, azx_probe_work
);
1781 static int azx_first_init(struct azx
*chip
)
1783 int dev
= chip
->dev_index
;
1784 struct pci_dev
*pci
= chip
->pci
;
1785 struct snd_card
*card
= chip
->card
;
1786 struct hdac_bus
*bus
= azx_bus(chip
);
1788 unsigned short gcap
;
1789 unsigned int dma_bits
= 64;
1791 #if BITS_PER_LONG != 64
1792 /* Fix up base address on ULI M5461 */
1793 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1795 pci_read_config_word(pci
, 0x40, &tmp3
);
1796 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1797 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1801 err
= pci_request_regions(pci
, "ICH HD audio");
1804 chip
->region_requested
= 1;
1806 bus
->addr
= pci_resource_start(pci
, 0);
1807 bus
->remap_addr
= pci_ioremap_bar(pci
, 0);
1808 if (bus
->remap_addr
== NULL
) {
1809 dev_err(card
->dev
, "ioremap error\n");
1813 if (chip
->driver_type
== AZX_DRIVER_SKL
)
1814 snd_hdac_bus_parse_capabilities(bus
);
1817 * Some Intel CPUs has always running timer (ART) feature and
1818 * controller may have Global time sync reporting capability, so
1819 * check both of these before declaring synchronized time reporting
1820 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1822 chip
->gts_present
= false;
1825 if (bus
->ppcap
&& boot_cpu_has(X86_FEATURE_ART
))
1826 chip
->gts_present
= true;
1830 if (chip
->driver_caps
& AZX_DCAPS_NO_MSI64
) {
1831 dev_dbg(card
->dev
, "Disabling 64bit MSI\n");
1832 pci
->no_64bit_msi
= true;
1834 if (pci_enable_msi(pci
) < 0)
1838 if (azx_acquire_irq(chip
, 0) < 0)
1841 pci_set_master(pci
);
1842 synchronize_irq(bus
->irq
);
1844 gcap
= azx_readw(chip
, GCAP
);
1845 dev_dbg(card
->dev
, "chipset global capabilities = 0x%x\n", gcap
);
1847 /* AMD devices support 40 or 48bit DMA, take the safe one */
1848 if (chip
->pci
->vendor
== PCI_VENDOR_ID_AMD
)
1851 /* disable SB600 64bit support for safety */
1852 if (chip
->pci
->vendor
== PCI_VENDOR_ID_ATI
) {
1853 struct pci_dev
*p_smbus
;
1855 p_smbus
= pci_get_device(PCI_VENDOR_ID_ATI
,
1856 PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
1859 if (p_smbus
->revision
< 0x30)
1860 gcap
&= ~AZX_GCAP_64OK
;
1861 pci_dev_put(p_smbus
);
1865 /* NVidia hardware normally only supports up to 40 bits of DMA */
1866 if (chip
->pci
->vendor
== PCI_VENDOR_ID_NVIDIA
)
1869 /* disable 64bit DMA address on some devices */
1870 if (chip
->driver_caps
& AZX_DCAPS_NO_64BIT
) {
1871 dev_dbg(card
->dev
, "Disabling 64bit DMA\n");
1872 gcap
&= ~AZX_GCAP_64OK
;
1875 /* disable buffer size rounding to 128-byte multiples if supported */
1876 if (align_buffer_size
>= 0)
1877 chip
->align_buffer_size
= !!align_buffer_size
;
1879 if (chip
->driver_caps
& AZX_DCAPS_NO_ALIGN_BUFSIZE
)
1880 chip
->align_buffer_size
= 0;
1882 chip
->align_buffer_size
= 1;
1885 /* allow 64bit DMA address if supported by H/W */
1886 if (!(gcap
& AZX_GCAP_64OK
))
1888 if (!dma_set_mask(&pci
->dev
, DMA_BIT_MASK(dma_bits
))) {
1889 dma_set_coherent_mask(&pci
->dev
, DMA_BIT_MASK(dma_bits
));
1891 dma_set_mask(&pci
->dev
, DMA_BIT_MASK(32));
1892 dma_set_coherent_mask(&pci
->dev
, DMA_BIT_MASK(32));
1895 /* read number of streams from GCAP register instead of using
1898 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
1899 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
1900 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
1901 /* gcap didn't give any info, switching to old method */
1903 switch (chip
->driver_type
) {
1904 case AZX_DRIVER_ULI
:
1905 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1906 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1908 case AZX_DRIVER_ATIHDMI
:
1909 case AZX_DRIVER_ATIHDMI_NS
:
1910 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
1911 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
1913 case AZX_DRIVER_GENERIC
:
1915 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1916 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1920 chip
->capture_index_offset
= 0;
1921 chip
->playback_index_offset
= chip
->capture_streams
;
1922 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1924 /* sanity check for the SDxCTL.STRM field overflow */
1925 if (chip
->num_streams
> 15 &&
1926 (chip
->driver_caps
& AZX_DCAPS_SEPARATE_STREAM_TAG
) == 0) {
1927 dev_warn(chip
->card
->dev
, "number of I/O streams is %d, "
1928 "forcing separate stream tags", chip
->num_streams
);
1929 chip
->driver_caps
|= AZX_DCAPS_SEPARATE_STREAM_TAG
;
1932 /* initialize streams */
1933 err
= azx_init_streams(chip
);
1937 err
= azx_alloc_stream_pages(chip
);
1941 /* initialize chip */
1944 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
1945 snd_hdac_i915_set_bclk(bus
);
1947 hda_intel_init_chip(chip
, (probe_only
[dev
] & 2) == 0);
1949 /* codec detection */
1950 if (!azx_bus(chip
)->codec_mask
) {
1951 dev_err(card
->dev
, "no codecs found!\n");
1955 strcpy(card
->driver
, "HDA-Intel");
1956 strlcpy(card
->shortname
, driver_short_names
[chip
->driver_type
],
1957 sizeof(card
->shortname
));
1958 snprintf(card
->longname
, sizeof(card
->longname
),
1959 "%s at 0x%lx irq %i",
1960 card
->shortname
, bus
->addr
, bus
->irq
);
1965 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1966 /* callback from request_firmware_nowait() */
1967 static void azx_firmware_cb(const struct firmware
*fw
, void *context
)
1969 struct snd_card
*card
= context
;
1970 struct azx
*chip
= card
->private_data
;
1971 struct pci_dev
*pci
= chip
->pci
;
1974 dev_err(card
->dev
, "Cannot load firmware, aborting\n");
1979 if (!chip
->disabled
) {
1980 /* continue probing */
1981 if (azx_probe_continue(chip
))
1987 snd_card_free(card
);
1988 pci_set_drvdata(pci
, NULL
);
1993 * HDA controller ops.
1996 /* PCI register access. */
1997 static void pci_azx_writel(u32 value
, u32 __iomem
*addr
)
1999 writel(value
, addr
);
2002 static u32
pci_azx_readl(u32 __iomem
*addr
)
2007 static void pci_azx_writew(u16 value
, u16 __iomem
*addr
)
2009 writew(value
, addr
);
2012 static u16
pci_azx_readw(u16 __iomem
*addr
)
2017 static void pci_azx_writeb(u8 value
, u8 __iomem
*addr
)
2019 writeb(value
, addr
);
2022 static u8
pci_azx_readb(u8 __iomem
*addr
)
2027 static int disable_msi_reset_irq(struct azx
*chip
)
2029 struct hdac_bus
*bus
= azx_bus(chip
);
2032 free_irq(bus
->irq
, chip
);
2034 pci_disable_msi(chip
->pci
);
2036 err
= azx_acquire_irq(chip
, 1);
2043 /* DMA page allocation helpers. */
2044 static int dma_alloc_pages(struct hdac_bus
*bus
,
2047 struct snd_dma_buffer
*buf
)
2049 struct azx
*chip
= bus_to_azx(bus
);
2052 err
= snd_dma_alloc_pages(type
,
2057 mark_pages_wc(chip
, buf
, true);
2061 static void dma_free_pages(struct hdac_bus
*bus
, struct snd_dma_buffer
*buf
)
2063 struct azx
*chip
= bus_to_azx(bus
);
2065 mark_pages_wc(chip
, buf
, false);
2066 snd_dma_free_pages(buf
);
2069 static int substream_alloc_pages(struct azx
*chip
,
2070 struct snd_pcm_substream
*substream
,
2073 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
2076 mark_runtime_wc(chip
, azx_dev
, substream
, false);
2077 ret
= snd_pcm_lib_malloc_pages(substream
, size
);
2080 mark_runtime_wc(chip
, azx_dev
, substream
, true);
2084 static int substream_free_pages(struct azx
*chip
,
2085 struct snd_pcm_substream
*substream
)
2087 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
2088 mark_runtime_wc(chip
, azx_dev
, substream
, false);
2089 return snd_pcm_lib_free_pages(substream
);
2092 static void pcm_mmap_prepare(struct snd_pcm_substream
*substream
,
2093 struct vm_area_struct
*area
)
2096 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
2097 struct azx
*chip
= apcm
->chip
;
2098 if (!azx_snoop(chip
) && chip
->driver_type
!= AZX_DRIVER_CMEDIA
)
2099 area
->vm_page_prot
= pgprot_writecombine(area
->vm_page_prot
);
2103 static const struct hdac_io_ops pci_hda_io_ops
= {
2104 .reg_writel
= pci_azx_writel
,
2105 .reg_readl
= pci_azx_readl
,
2106 .reg_writew
= pci_azx_writew
,
2107 .reg_readw
= pci_azx_readw
,
2108 .reg_writeb
= pci_azx_writeb
,
2109 .reg_readb
= pci_azx_readb
,
2110 .dma_alloc_pages
= dma_alloc_pages
,
2111 .dma_free_pages
= dma_free_pages
,
2114 static const struct hda_controller_ops pci_hda_ops
= {
2115 .disable_msi_reset_irq
= disable_msi_reset_irq
,
2116 .substream_alloc_pages
= substream_alloc_pages
,
2117 .substream_free_pages
= substream_free_pages
,
2118 .pcm_mmap_prepare
= pcm_mmap_prepare
,
2119 .position_check
= azx_position_check
,
2120 .link_power
= azx_intel_link_power
,
2123 static int azx_probe(struct pci_dev
*pci
,
2124 const struct pci_device_id
*pci_id
)
2127 struct snd_card
*card
;
2128 struct hda_intel
*hda
;
2130 bool schedule_probe
;
2133 if (dev
>= SNDRV_CARDS
)
2140 err
= snd_card_new(&pci
->dev
, index
[dev
], id
[dev
], THIS_MODULE
,
2143 dev_err(&pci
->dev
, "Error creating card!\n");
2147 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2150 card
->private_data
= chip
;
2151 hda
= container_of(chip
, struct hda_intel
, chip
);
2153 pci_set_drvdata(pci
, card
);
2155 err
= register_vga_switcheroo(chip
);
2157 dev_err(card
->dev
, "Error registering vga_switcheroo client\n");
2161 if (check_hdmi_disabled(pci
)) {
2162 dev_info(card
->dev
, "VGA controller is disabled\n");
2163 dev_info(card
->dev
, "Delaying initialization\n");
2164 chip
->disabled
= true;
2167 schedule_probe
= !chip
->disabled
;
2169 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2170 if (patch
[dev
] && *patch
[dev
]) {
2171 dev_info(card
->dev
, "Applying patch firmware '%s'\n",
2173 err
= request_firmware_nowait(THIS_MODULE
, true, patch
[dev
],
2174 &pci
->dev
, GFP_KERNEL
, card
,
2178 schedule_probe
= false; /* continued in azx_firmware_cb() */
2180 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2182 #ifndef CONFIG_SND_HDA_I915
2183 if (CONTROLLER_IN_GPU(pci
))
2184 dev_err(card
->dev
, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2188 schedule_work(&hda
->probe_work
);
2192 complete_all(&hda
->probe_wait
);
2196 snd_card_free(card
);
2201 /* On some boards setting power_save to a non 0 value leads to clicking /
2202 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2203 * figure out how to avoid these sounds, but that is not always feasible.
2204 * So we keep a list of devices where we disable powersaving as its known
2205 * to causes problems on these devices.
2207 static struct snd_pci_quirk power_save_blacklist
[] = {
2208 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2209 SND_PCI_QUIRK(0x1849, 0x0c0c, "Asrock B85M-ITX", 0),
2210 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2211 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2212 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2213 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2214 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2215 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2216 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2217 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2218 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2219 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2222 #endif /* CONFIG_PM */
2224 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2225 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] = {
2226 [AZX_DRIVER_NVIDIA
] = 8,
2227 [AZX_DRIVER_TERA
] = 1,
2230 static int azx_probe_continue(struct azx
*chip
)
2232 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
2233 struct hdac_bus
*bus
= azx_bus(chip
);
2234 struct pci_dev
*pci
= chip
->pci
;
2235 int dev
= chip
->dev_index
;
2239 hda
->probe_continued
= 1;
2241 /* bind with i915 if needed */
2242 if (chip
->driver_caps
& AZX_DCAPS_I915_COMPONENT
) {
2243 err
= snd_hdac_i915_init(bus
);
2245 /* if the controller is bound only with HDMI/DP
2246 * (for HSW and BDW), we need to abort the probe;
2247 * for other chips, still continue probing as other
2248 * codecs can be on the same link.
2250 if (CONTROLLER_IN_GPU(pci
)) {
2251 dev_err(chip
->card
->dev
,
2252 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2255 /* don't bother any longer */
2256 chip
->driver_caps
&=
2257 ~(AZX_DCAPS_I915_COMPONENT
| AZX_DCAPS_I915_POWERWELL
);
2262 /* Request display power well for the HDA controller or codec. For
2263 * Haswell/Broadwell, both the display HDA controller and codec need
2264 * this power. For other platforms, like Baytrail/Braswell, only the
2265 * display codec needs the power and it can be released after probe.
2267 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
2268 /* HSW/BDW controllers need this power */
2269 if (CONTROLLER_IN_GPU(pci
))
2270 hda
->need_i915_power
= 1;
2272 err
= snd_hdac_display_power(bus
, true);
2274 dev_err(chip
->card
->dev
,
2275 "Cannot turn on display power on i915\n");
2276 goto i915_power_fail
;
2280 err
= azx_first_init(chip
);
2284 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2285 chip
->beep_mode
= beep_mode
[dev
];
2288 /* create codec instances */
2289 err
= azx_probe_codecs(chip
, azx_max_codecs
[chip
->driver_type
]);
2293 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2295 err
= snd_hda_load_patch(&chip
->bus
, chip
->fw
->size
,
2300 release_firmware(chip
->fw
); /* no longer needed */
2305 if ((probe_only
[dev
] & 1) == 0) {
2306 err
= azx_codec_configure(chip
);
2311 err
= snd_card_register(chip
->card
);
2316 azx_add_card_list(chip
);
2321 const struct snd_pci_quirk
*q
;
2323 q
= snd_pci_quirk_lookup(chip
->pci
, power_save_blacklist
);
2325 dev_info(chip
->card
->dev
, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2326 q
->subvendor
, q
->subdevice
);
2330 #endif /* CONFIG_PM */
2331 snd_hda_set_power_save(&chip
->bus
, val
* 1000);
2332 if (azx_has_pm_runtime(chip
) || hda
->use_vga_switcheroo
)
2333 pm_runtime_put_autosuspend(&pci
->dev
);
2336 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
2337 && !hda
->need_i915_power
)
2338 snd_hdac_display_power(bus
, false);
2342 hda
->init_failed
= 1;
2343 complete_all(&hda
->probe_wait
);
2347 static void azx_remove(struct pci_dev
*pci
)
2349 struct snd_card
*card
= pci_get_drvdata(pci
);
2351 struct hda_intel
*hda
;
2354 /* cancel the pending probing work */
2355 chip
= card
->private_data
;
2356 hda
= container_of(chip
, struct hda_intel
, chip
);
2357 /* FIXME: below is an ugly workaround.
2358 * Both device_release_driver() and driver_probe_device()
2359 * take *both* the device's and its parent's lock before
2360 * calling the remove() and probe() callbacks. The codec
2361 * probe takes the locks of both the codec itself and its
2362 * parent, i.e. the PCI controller dev. Meanwhile, when
2363 * the PCI controller is unbound, it takes its lock, too
2364 * ==> ouch, a deadlock!
2365 * As a workaround, we unlock temporarily here the controller
2366 * device during cancel_work_sync() call.
2368 device_unlock(&pci
->dev
);
2369 cancel_work_sync(&hda
->probe_work
);
2370 device_lock(&pci
->dev
);
2372 snd_card_free(card
);
2376 static void azx_shutdown(struct pci_dev
*pci
)
2378 struct snd_card
*card
= pci_get_drvdata(pci
);
2383 chip
= card
->private_data
;
2384 if (chip
&& chip
->running
)
2385 azx_stop_chip(chip
);
2389 static const struct pci_device_id azx_ids
[] = {
2391 { PCI_DEVICE(0x8086, 0x1c20),
2392 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2394 { PCI_DEVICE(0x8086, 0x1d20),
2395 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2397 { PCI_DEVICE(0x8086, 0x1e20),
2398 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2400 { PCI_DEVICE(0x8086, 0x8c20),
2401 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2403 { PCI_DEVICE(0x8086, 0x8ca0),
2404 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2406 { PCI_DEVICE(0x8086, 0x8d20),
2407 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2408 { PCI_DEVICE(0x8086, 0x8d21),
2409 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2411 { PCI_DEVICE(0x8086, 0xa1f0),
2412 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_SKYLAKE
},
2413 { PCI_DEVICE(0x8086, 0xa270),
2414 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_SKYLAKE
},
2416 { PCI_DEVICE(0x8086, 0x9c20),
2417 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2419 { PCI_DEVICE(0x8086, 0x9c21),
2420 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2421 /* Wildcat Point-LP */
2422 { PCI_DEVICE(0x8086, 0x9ca0),
2423 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2425 { PCI_DEVICE(0x8086, 0xa170),
2426 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2427 /* Sunrise Point-LP */
2428 { PCI_DEVICE(0x8086, 0x9d70),
2429 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2431 { PCI_DEVICE(0x8086, 0xa171),
2432 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2434 { PCI_DEVICE(0x8086, 0x9d71),
2435 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2437 { PCI_DEVICE(0x8086, 0xa2f0),
2438 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2440 { PCI_DEVICE(0x8086, 0xa348),
2441 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2443 { PCI_DEVICE(0x8086, 0x9dc8),
2444 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2445 /* Broxton-P(Apollolake) */
2446 { PCI_DEVICE(0x8086, 0x5a98),
2447 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_BROXTON
},
2449 { PCI_DEVICE(0x8086, 0x1a98),
2450 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_BROXTON
},
2452 { PCI_DEVICE(0x8086, 0x3198),
2453 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_BROXTON
},
2455 { PCI_DEVICE(0x8086, 0x0a0c),
2456 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_HASWELL
},
2457 { PCI_DEVICE(0x8086, 0x0c0c),
2458 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_HASWELL
},
2459 { PCI_DEVICE(0x8086, 0x0d0c),
2460 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_HASWELL
},
2462 { PCI_DEVICE(0x8086, 0x160c),
2463 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_BROADWELL
},
2465 { PCI_DEVICE(0x8086, 0x3b56),
2466 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2468 { PCI_DEVICE(0x8086, 0x811b),
2469 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_INTEL_PCH_BASE
},
2471 { PCI_DEVICE(0x8086, 0x080a),
2472 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_INTEL_PCH_BASE
},
2474 { PCI_DEVICE(0x8086, 0x0f04),
2475 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_BAYTRAIL
},
2477 { PCI_DEVICE(0x8086, 0x2284),
2478 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_BRASWELL
},
2480 { PCI_DEVICE(0x8086, 0x2668),
2481 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2483 { PCI_DEVICE(0x8086, 0x27d8),
2484 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2486 { PCI_DEVICE(0x8086, 0x269a),
2487 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2489 { PCI_DEVICE(0x8086, 0x284b),
2490 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2492 { PCI_DEVICE(0x8086, 0x293e),
2493 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2495 { PCI_DEVICE(0x8086, 0x293f),
2496 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2498 { PCI_DEVICE(0x8086, 0x3a3e),
2499 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2501 { PCI_DEVICE(0x8086, 0x3a6e),
2502 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2504 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
),
2505 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2506 .class_mask
= 0xffffff,
2507 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_NO_ALIGN_BUFSIZE
},
2508 /* ATI SB 450/600/700/800/900 */
2509 { PCI_DEVICE(0x1002, 0x437b),
2510 .driver_data
= AZX_DRIVER_ATI
| AZX_DCAPS_PRESET_ATI_SB
},
2511 { PCI_DEVICE(0x1002, 0x4383),
2512 .driver_data
= AZX_DRIVER_ATI
| AZX_DCAPS_PRESET_ATI_SB
},
2514 { PCI_DEVICE(0x1022, 0x780d),
2515 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_SB
},
2517 { PCI_DEVICE(0x1022, 0x15e3),
2518 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_SB
|
2519 AZX_DCAPS_PM_RUNTIME
},
2521 { PCI_DEVICE(0x1002, 0x0002),
2522 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2523 { PCI_DEVICE(0x1002, 0x1308),
2524 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2525 { PCI_DEVICE(0x1002, 0x157a),
2526 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2527 { PCI_DEVICE(0x1002, 0x15b3),
2528 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2529 { PCI_DEVICE(0x1002, 0x793b),
2530 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2531 { PCI_DEVICE(0x1002, 0x7919),
2532 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2533 { PCI_DEVICE(0x1002, 0x960f),
2534 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2535 { PCI_DEVICE(0x1002, 0x970f),
2536 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2537 { PCI_DEVICE(0x1002, 0x9840),
2538 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2539 { PCI_DEVICE(0x1002, 0xaa00),
2540 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2541 { PCI_DEVICE(0x1002, 0xaa08),
2542 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2543 { PCI_DEVICE(0x1002, 0xaa10),
2544 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2545 { PCI_DEVICE(0x1002, 0xaa18),
2546 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2547 { PCI_DEVICE(0x1002, 0xaa20),
2548 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2549 { PCI_DEVICE(0x1002, 0xaa28),
2550 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2551 { PCI_DEVICE(0x1002, 0xaa30),
2552 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2553 { PCI_DEVICE(0x1002, 0xaa38),
2554 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2555 { PCI_DEVICE(0x1002, 0xaa40),
2556 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2557 { PCI_DEVICE(0x1002, 0xaa48),
2558 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2559 { PCI_DEVICE(0x1002, 0xaa50),
2560 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2561 { PCI_DEVICE(0x1002, 0xaa58),
2562 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2563 { PCI_DEVICE(0x1002, 0xaa60),
2564 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2565 { PCI_DEVICE(0x1002, 0xaa68),
2566 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2567 { PCI_DEVICE(0x1002, 0xaa80),
2568 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2569 { PCI_DEVICE(0x1002, 0xaa88),
2570 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2571 { PCI_DEVICE(0x1002, 0xaa90),
2572 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2573 { PCI_DEVICE(0x1002, 0xaa98),
2574 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2575 { PCI_DEVICE(0x1002, 0x9902),
2576 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2577 { PCI_DEVICE(0x1002, 0xaaa0),
2578 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2579 { PCI_DEVICE(0x1002, 0xaaa8),
2580 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2581 { PCI_DEVICE(0x1002, 0xaab0),
2582 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2583 { PCI_DEVICE(0x1002, 0xaac0),
2584 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2585 { PCI_DEVICE(0x1002, 0xaac8),
2586 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2587 { PCI_DEVICE(0x1002, 0xaad8),
2588 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2589 { PCI_DEVICE(0x1002, 0xaae8),
2590 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2591 { PCI_DEVICE(0x1002, 0xaae0),
2592 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2593 { PCI_DEVICE(0x1002, 0xaaf0),
2594 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2595 /* VIA VT8251/VT8237A */
2596 { PCI_DEVICE(0x1106, 0x3288), .driver_data
= AZX_DRIVER_VIA
},
2597 /* VIA GFX VT7122/VX900 */
2598 { PCI_DEVICE(0x1106, 0x9170), .driver_data
= AZX_DRIVER_GENERIC
},
2599 /* VIA GFX VT6122/VX11 */
2600 { PCI_DEVICE(0x1106, 0x9140), .driver_data
= AZX_DRIVER_GENERIC
},
2602 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
2604 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
2606 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
),
2607 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2608 .class_mask
= 0xffffff,
2609 .driver_data
= AZX_DRIVER_NVIDIA
| AZX_DCAPS_PRESET_NVIDIA
},
2611 { PCI_DEVICE(0x6549, 0x1200),
2612 .driver_data
= AZX_DRIVER_TERA
| AZX_DCAPS_NO_64BIT
},
2613 { PCI_DEVICE(0x6549, 0x2200),
2614 .driver_data
= AZX_DRIVER_TERA
| AZX_DCAPS_NO_64BIT
},
2615 /* Creative X-Fi (CA0110-IBG) */
2617 { PCI_DEVICE(0x1102, 0x0010),
2618 .driver_data
= AZX_DRIVER_CTHDA
| AZX_DCAPS_PRESET_CTHDA
},
2619 { PCI_DEVICE(0x1102, 0x0012),
2620 .driver_data
= AZX_DRIVER_CTHDA
| AZX_DCAPS_PRESET_CTHDA
},
2621 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2622 /* the following entry conflicts with snd-ctxfi driver,
2623 * as ctxfi driver mutates from HD-audio to native mode with
2624 * a special command sequence.
2626 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE
, PCI_ANY_ID
),
2627 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2628 .class_mask
= 0xffffff,
2629 .driver_data
= AZX_DRIVER_CTX
| AZX_DCAPS_CTX_WORKAROUND
|
2630 AZX_DCAPS_NO_64BIT
| AZX_DCAPS_POSFIX_LPIB
},
2632 /* this entry seems still valid -- i.e. without emu20kx chip */
2633 { PCI_DEVICE(0x1102, 0x0009),
2634 .driver_data
= AZX_DRIVER_CTX
| AZX_DCAPS_CTX_WORKAROUND
|
2635 AZX_DCAPS_NO_64BIT
| AZX_DCAPS_POSFIX_LPIB
},
2638 { PCI_DEVICE(0x13f6, 0x5011),
2639 .driver_data
= AZX_DRIVER_CMEDIA
|
2640 AZX_DCAPS_NO_MSI
| AZX_DCAPS_POSFIX_LPIB
| AZX_DCAPS_SNOOP_OFF
},
2642 { PCI_DEVICE(0x17f3, 0x3010), .driver_data
= AZX_DRIVER_GENERIC
},
2643 /* VMware HDAudio */
2644 { PCI_DEVICE(0x15ad, 0x1977), .driver_data
= AZX_DRIVER_GENERIC
},
2645 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2646 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
2647 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2648 .class_mask
= 0xffffff,
2649 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_HDMI
},
2650 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
),
2651 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2652 .class_mask
= 0xffffff,
2653 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_HDMI
},
2656 MODULE_DEVICE_TABLE(pci
, azx_ids
);
2658 /* pci_driver definition */
2659 static struct pci_driver azx_driver
= {
2660 .name
= KBUILD_MODNAME
,
2661 .id_table
= azx_ids
,
2663 .remove
= azx_remove
,
2664 .shutdown
= azx_shutdown
,
2670 module_pci_driver(azx_driver
);