3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
55 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
56 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
57 static char *model
[SNDRV_CARDS
];
58 static int position_fix
[SNDRV_CARDS
];
59 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
60 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
61 static int probe_only
[SNDRV_CARDS
];
62 static int single_cmd
;
63 static int enable_msi
= -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch
[SNDRV_CARDS
];
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE
};
72 module_param_array(index
, int, NULL
, 0444);
73 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
74 module_param_array(id
, charp
, NULL
, 0444);
75 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
76 module_param_array(enable
, bool, NULL
, 0444);
77 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
78 module_param_array(model
, charp
, NULL
, 0444);
79 MODULE_PARM_DESC(model
, "Use the given board model.");
80 module_param_array(position_fix
, int, NULL
, 0444);
81 MODULE_PARM_DESC(position_fix
, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
83 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
85 module_param_array(probe_mask
, int, NULL
, 0444);
86 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only
, int, NULL
, 0444);
88 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
89 module_param(single_cmd
, bool, 0444);
90 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi
, int, 0444);
93 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch
, charp
, NULL
, 0444);
96 MODULE_PARM_DESC(patch
, "Patch file for Intel HD audio interface.");
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode
, int, NULL
, 0444);
100 MODULE_PARM_DESC(beep_mode
, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
106 module_param(power_save
, int, 0644);
107 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
114 static int power_save_controller
= 1;
115 module_param(power_save_controller
, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
147 MODULE_DESCRIPTION("Intel HDA driver");
149 #ifdef CONFIG_SND_VERBOSE_PRINTK
150 #define SFX /* nop */
152 #define SFX "hda-intel: "
158 #define ICH6_REG_GCAP 0x00
159 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
160 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
161 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
162 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
163 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
164 #define ICH6_REG_VMIN 0x02
165 #define ICH6_REG_VMAJ 0x03
166 #define ICH6_REG_OUTPAY 0x04
167 #define ICH6_REG_INPAY 0x06
168 #define ICH6_REG_GCTL 0x08
169 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
170 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
171 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
172 #define ICH6_REG_WAKEEN 0x0c
173 #define ICH6_REG_STATESTS 0x0e
174 #define ICH6_REG_GSTS 0x10
175 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
176 #define ICH6_REG_INTCTL 0x20
177 #define ICH6_REG_INTSTS 0x24
178 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
179 #define ICH6_REG_SYNC 0x34
180 #define ICH6_REG_CORBLBASE 0x40
181 #define ICH6_REG_CORBUBASE 0x44
182 #define ICH6_REG_CORBWP 0x48
183 #define ICH6_REG_CORBRP 0x4a
184 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
185 #define ICH6_REG_CORBCTL 0x4c
186 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
187 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
188 #define ICH6_REG_CORBSTS 0x4d
189 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
190 #define ICH6_REG_CORBSIZE 0x4e
192 #define ICH6_REG_RIRBLBASE 0x50
193 #define ICH6_REG_RIRBUBASE 0x54
194 #define ICH6_REG_RIRBWP 0x58
195 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
196 #define ICH6_REG_RINTCNT 0x5a
197 #define ICH6_REG_RIRBCTL 0x5c
198 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
199 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
200 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
201 #define ICH6_REG_RIRBSTS 0x5d
202 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
203 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
204 #define ICH6_REG_RIRBSIZE 0x5e
206 #define ICH6_REG_IC 0x60
207 #define ICH6_REG_IR 0x64
208 #define ICH6_REG_IRS 0x68
209 #define ICH6_IRS_VALID (1<<1)
210 #define ICH6_IRS_BUSY (1<<0)
212 #define ICH6_REG_DPLBASE 0x70
213 #define ICH6_REG_DPUBASE 0x74
214 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
216 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
217 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
219 /* stream register offsets from stream base */
220 #define ICH6_REG_SD_CTL 0x00
221 #define ICH6_REG_SD_STS 0x03
222 #define ICH6_REG_SD_LPIB 0x04
223 #define ICH6_REG_SD_CBL 0x08
224 #define ICH6_REG_SD_LVI 0x0c
225 #define ICH6_REG_SD_FIFOW 0x0e
226 #define ICH6_REG_SD_FIFOSIZE 0x10
227 #define ICH6_REG_SD_FORMAT 0x12
228 #define ICH6_REG_SD_BDLPL 0x18
229 #define ICH6_REG_SD_BDLPU 0x1c
232 #define ICH6_PCIREG_TCSEL 0x44
238 /* max number of SDs */
239 /* ICH, ATI and VIA have 4 playback and 4 capture */
240 #define ICH6_NUM_CAPTURE 4
241 #define ICH6_NUM_PLAYBACK 4
243 /* ULI has 6 playback and 5 capture */
244 #define ULI_NUM_CAPTURE 5
245 #define ULI_NUM_PLAYBACK 6
247 /* ATI HDMI has 1 playback and 0 capture */
248 #define ATIHDMI_NUM_CAPTURE 0
249 #define ATIHDMI_NUM_PLAYBACK 1
251 /* TERA has 4 playback and 3 capture */
252 #define TERA_NUM_CAPTURE 3
253 #define TERA_NUM_PLAYBACK 4
255 /* this number is statically defined for simplicity */
256 #define MAX_AZX_DEV 16
258 /* max number of fragments - we may use more if allocating more pages for BDL */
259 #define BDL_SIZE 4096
260 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
261 #define AZX_MAX_FRAG 32
262 /* max buffer size - no h/w limit, you can increase as you like */
263 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
265 /* RIRB int mask: overrun[2], response[0] */
266 #define RIRB_INT_RESPONSE 0x01
267 #define RIRB_INT_OVERRUN 0x04
268 #define RIRB_INT_MASK 0x05
270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
271 #define AZX_MAX_CODECS 8
272 #define AZX_DEFAULT_CODECS 4
273 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
276 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
277 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
278 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
279 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
280 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
281 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
282 #define SD_CTL_STREAM_TAG_SHIFT 20
284 /* SD_CTL and SD_STS */
285 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
286 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
287 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
288 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
292 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
294 /* INTCTL and INTSTS */
295 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
296 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
297 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
299 /* below are so far hardcoded - should read registers in future */
300 #define ICH6_MAX_CORB_ENTRIES 256
301 #define ICH6_MAX_RIRB_ENTRIES 256
303 /* position fix mode */
311 /* Defines for ATI HD Audio support in SB450 south bridge */
312 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
313 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
315 /* Defines for Nvidia HDA support */
316 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
317 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
318 #define NVIDIA_HDA_ISTRM_COH 0x4d
319 #define NVIDIA_HDA_OSTRM_COH 0x4c
320 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
322 /* Defines for Intel SCH HDA snoop control */
323 #define INTEL_SCH_HDA_DEVC 0x78
324 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
326 /* Define IN stream 0 FIFO size offset in VIA controller */
327 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
328 /* Define VIA HD Audio Device ID*/
329 #define VIA_HDAC_DEVICE_ID 0x3288
331 /* HD Audio class code */
332 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
338 struct snd_dma_buffer bdl
; /* BDL buffer */
339 u32
*posbuf
; /* position buffer pointer */
341 unsigned int bufsize
; /* size of the play buffer in bytes */
342 unsigned int period_bytes
; /* size of the period in bytes */
343 unsigned int frags
; /* number for period in the play buffer */
344 unsigned int fifo_size
; /* FIFO size */
345 unsigned long start_wallclk
; /* start + minimum wallclk */
346 unsigned long period_wallclk
; /* wallclk for period */
348 void __iomem
*sd_addr
; /* stream descriptor pointer */
350 u32 sd_int_sta_mask
; /* stream int status mask */
353 struct snd_pcm_substream
*substream
; /* assigned substream,
356 unsigned int format_val
; /* format value to be set in the
357 * controller and the codec
359 unsigned char stream_tag
; /* assigned stream */
360 unsigned char index
; /* stream index */
361 int device
; /* last device number assigned to */
363 unsigned int opened
:1;
364 unsigned int running
:1;
365 unsigned int irq_pending
:1;
368 * A flag to ensure DMA position is 0
369 * when link position is not greater than FIFO size
371 unsigned int insufficient
:1;
376 u32
*buf
; /* CORB/RIRB buffer
377 * Each CORB entry is 4byte, RIRB is 8byte
379 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
381 unsigned short rp
, wp
; /* read/write pointers */
382 int cmds
[AZX_MAX_CODECS
]; /* number of pending requests */
383 u32 res
[AZX_MAX_CODECS
]; /* last read value */
387 struct snd_card
*card
;
391 /* chip type specific */
393 int playback_streams
;
394 int playback_index_offset
;
396 int capture_index_offset
;
401 void __iomem
*remap_addr
;
406 struct mutex open_mutex
;
408 /* streams (x num_streams) */
409 struct azx_dev
*azx_dev
;
412 struct snd_pcm
*pcm
[HDA_MAX_PCMS
];
415 unsigned short codec_mask
;
416 int codec_probe_mask
; /* copied from probe_mask option */
418 unsigned int beep_mode
;
424 /* CORB/RIRB and position buffers */
425 struct snd_dma_buffer rb
;
426 struct snd_dma_buffer posbuf
;
429 int position_fix
[2]; /* for both playback/capture streams */
431 unsigned int running
:1;
432 unsigned int initialized
:1;
433 unsigned int single_cmd
:1;
434 unsigned int polling_mode
:1;
436 unsigned int irq_pending_warned
:1;
437 unsigned int probing
:1; /* codec probing phase */
440 unsigned int last_cmd
[AZX_MAX_CODECS
];
442 /* for pending irqs */
443 struct work_struct irq_pending_work
;
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier
;
463 AZX_NUM_DRIVERS
, /* keep this as last entry */
466 static char *driver_short_names
[] __devinitdata
= {
467 [AZX_DRIVER_ICH
] = "HDA Intel",
468 [AZX_DRIVER_PCH
] = "HDA Intel PCH",
469 [AZX_DRIVER_SCH
] = "HDA Intel MID",
470 [AZX_DRIVER_ATI
] = "HDA ATI SB",
471 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
472 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
473 [AZX_DRIVER_SIS
] = "HDA SIS966",
474 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
475 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
476 [AZX_DRIVER_TERA
] = "HDA Teradici",
477 [AZX_DRIVER_CTX
] = "HDA Creative",
478 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
482 * macros for easy use
484 #define azx_writel(chip,reg,value) \
485 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
486 #define azx_readl(chip,reg) \
487 readl((chip)->remap_addr + ICH6_REG_##reg)
488 #define azx_writew(chip,reg,value) \
489 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
490 #define azx_readw(chip,reg) \
491 readw((chip)->remap_addr + ICH6_REG_##reg)
492 #define azx_writeb(chip,reg,value) \
493 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
494 #define azx_readb(chip,reg) \
495 readb((chip)->remap_addr + ICH6_REG_##reg)
497 #define azx_sd_writel(dev,reg,value) \
498 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
499 #define azx_sd_readl(dev,reg) \
500 readl((dev)->sd_addr + ICH6_REG_##reg)
501 #define azx_sd_writew(dev,reg,value) \
502 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
503 #define azx_sd_readw(dev,reg) \
504 readw((dev)->sd_addr + ICH6_REG_##reg)
505 #define azx_sd_writeb(dev,reg,value) \
506 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
507 #define azx_sd_readb(dev,reg) \
508 readb((dev)->sd_addr + ICH6_REG_##reg)
510 /* for pcm support */
511 #define get_azx_dev(substream) (substream->runtime->private_data)
513 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
514 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
);
516 * Interface for HD codec
520 * CORB / RIRB interface
522 static int azx_alloc_cmd_io(struct azx
*chip
)
526 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
527 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
528 snd_dma_pci_data(chip
->pci
),
529 PAGE_SIZE
, &chip
->rb
);
531 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
537 static void azx_init_cmd_io(struct azx
*chip
)
539 spin_lock_irq(&chip
->reg_lock
);
541 chip
->corb
.addr
= chip
->rb
.addr
;
542 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
543 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
544 azx_writel(chip
, CORBUBASE
, upper_32_bits(chip
->corb
.addr
));
546 /* set the corb size to 256 entries (ULI requires explicitly) */
547 azx_writeb(chip
, CORBSIZE
, 0x02);
548 /* set the corb write pointer to 0 */
549 azx_writew(chip
, CORBWP
, 0);
550 /* reset the corb hw read pointer */
551 azx_writew(chip
, CORBRP
, ICH6_CORBRP_RST
);
552 /* enable corb dma */
553 azx_writeb(chip
, CORBCTL
, ICH6_CORBCTL_RUN
);
556 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
557 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
558 chip
->rirb
.wp
= chip
->rirb
.rp
= 0;
559 memset(chip
->rirb
.cmds
, 0, sizeof(chip
->rirb
.cmds
));
560 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
561 azx_writel(chip
, RIRBUBASE
, upper_32_bits(chip
->rirb
.addr
));
563 /* set the rirb size to 256 entries (ULI requires explicitly) */
564 azx_writeb(chip
, RIRBSIZE
, 0x02);
565 /* reset the rirb hw write pointer */
566 azx_writew(chip
, RIRBWP
, ICH6_RIRBWP_RST
);
567 /* set N=1, get RIRB response interrupt for new entry */
568 if (chip
->driver_type
== AZX_DRIVER_CTX
)
569 azx_writew(chip
, RINTCNT
, 0xc0);
571 azx_writew(chip
, RINTCNT
, 1);
572 /* enable rirb dma and response irq */
573 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
574 spin_unlock_irq(&chip
->reg_lock
);
577 static void azx_free_cmd_io(struct azx
*chip
)
579 spin_lock_irq(&chip
->reg_lock
);
580 /* disable ringbuffer DMAs */
581 azx_writeb(chip
, RIRBCTL
, 0);
582 azx_writeb(chip
, CORBCTL
, 0);
583 spin_unlock_irq(&chip
->reg_lock
);
586 static unsigned int azx_command_addr(u32 cmd
)
588 unsigned int addr
= cmd
>> 28;
590 if (addr
>= AZX_MAX_CODECS
) {
598 static unsigned int azx_response_addr(u32 res
)
600 unsigned int addr
= res
& 0xf;
602 if (addr
>= AZX_MAX_CODECS
) {
611 static int azx_corb_send_cmd(struct hda_bus
*bus
, u32 val
)
613 struct azx
*chip
= bus
->private_data
;
614 unsigned int addr
= azx_command_addr(val
);
617 spin_lock_irq(&chip
->reg_lock
);
619 /* add command to corb */
620 wp
= azx_readb(chip
, CORBWP
);
622 wp
%= ICH6_MAX_CORB_ENTRIES
;
624 chip
->rirb
.cmds
[addr
]++;
625 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
626 azx_writel(chip
, CORBWP
, wp
);
628 spin_unlock_irq(&chip
->reg_lock
);
633 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
635 /* retrieve RIRB entry - called from interrupt handler */
636 static void azx_update_rirb(struct azx
*chip
)
642 wp
= azx_readb(chip
, RIRBWP
);
643 if (wp
== chip
->rirb
.wp
)
647 while (chip
->rirb
.rp
!= wp
) {
649 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
651 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
652 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
653 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
654 addr
= azx_response_addr(res_ex
);
655 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
656 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
657 else if (chip
->rirb
.cmds
[addr
]) {
658 chip
->rirb
.res
[addr
] = res
;
660 chip
->rirb
.cmds
[addr
]--;
662 snd_printk(KERN_ERR SFX
"spurious response %#x:%#x, "
665 chip
->last_cmd
[addr
]);
669 /* receive a response */
670 static unsigned int azx_rirb_get_response(struct hda_bus
*bus
,
673 struct azx
*chip
= bus
->private_data
;
674 unsigned long timeout
;
678 timeout
= jiffies
+ msecs_to_jiffies(1000);
680 if (chip
->polling_mode
|| do_poll
) {
681 spin_lock_irq(&chip
->reg_lock
);
682 azx_update_rirb(chip
);
683 spin_unlock_irq(&chip
->reg_lock
);
685 if (!chip
->rirb
.cmds
[addr
]) {
690 chip
->poll_count
= 0;
691 return chip
->rirb
.res
[addr
]; /* the last value */
693 if (time_after(jiffies
, timeout
))
695 if (bus
->needs_damn_long_delay
)
696 msleep(2); /* temporary workaround */
703 if (!chip
->polling_mode
&& chip
->poll_count
< 2) {
704 snd_printdd(SFX
"azx_get_response timeout, "
705 "polling the codec once: last cmd=0x%08x\n",
706 chip
->last_cmd
[addr
]);
713 if (!chip
->polling_mode
) {
714 snd_printk(KERN_WARNING SFX
"azx_get_response timeout, "
715 "switching to polling mode: last cmd=0x%08x\n",
716 chip
->last_cmd
[addr
]);
717 chip
->polling_mode
= 1;
722 snd_printk(KERN_WARNING SFX
"No response from codec, "
723 "disabling MSI: last cmd=0x%08x\n",
724 chip
->last_cmd
[addr
]);
725 free_irq(chip
->irq
, chip
);
727 pci_disable_msi(chip
->pci
);
729 if (azx_acquire_irq(chip
, 1) < 0) {
737 /* If this critical timeout happens during the codec probing
738 * phase, this is likely an access to a non-existing codec
739 * slot. Better to return an error and reset the system.
744 /* a fatal communication error; need either to reset or to fallback
745 * to the single_cmd mode
748 if (bus
->allow_bus_reset
&& !bus
->response_reset
&& !bus
->in_reset
) {
749 bus
->response_reset
= 1;
750 return -1; /* give a chance to retry */
753 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
754 "switching to single_cmd mode: last cmd=0x%08x\n",
755 chip
->last_cmd
[addr
]);
756 chip
->single_cmd
= 1;
757 bus
->response_reset
= 0;
758 /* release CORB/RIRB */
759 azx_free_cmd_io(chip
);
760 /* disable unsolicited responses */
761 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_UNSOL
);
766 * Use the single immediate command instead of CORB/RIRB for simplicity
768 * Note: according to Intel, this is not preferred use. The command was
769 * intended for the BIOS only, and may get confused with unsolicited
770 * responses. So, we shouldn't use it for normal operation from the
772 * I left the codes, however, for debugging/testing purposes.
775 /* receive a response */
776 static int azx_single_wait_for_response(struct azx
*chip
, unsigned int addr
)
781 /* check IRV busy bit */
782 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
) {
783 /* reuse rirb.res as the response return value */
784 chip
->rirb
.res
[addr
] = azx_readl(chip
, IR
);
789 if (printk_ratelimit())
790 snd_printd(SFX
"get_response timeout: IRS=0x%x\n",
791 azx_readw(chip
, IRS
));
792 chip
->rirb
.res
[addr
] = -1;
797 static int azx_single_send_cmd(struct hda_bus
*bus
, u32 val
)
799 struct azx
*chip
= bus
->private_data
;
800 unsigned int addr
= azx_command_addr(val
);
805 /* check ICB busy bit */
806 if (!((azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
))) {
807 /* Clear IRV valid bit */
808 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
810 azx_writel(chip
, IC
, val
);
811 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
813 return azx_single_wait_for_response(chip
, addr
);
817 if (printk_ratelimit())
818 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
819 azx_readw(chip
, IRS
), val
);
823 /* receive a response */
824 static unsigned int azx_single_get_response(struct hda_bus
*bus
,
827 struct azx
*chip
= bus
->private_data
;
828 return chip
->rirb
.res
[addr
];
832 * The below are the main callbacks from hda_codec.
834 * They are just the skeleton to call sub-callbacks according to the
835 * current setting of chip->single_cmd.
839 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
)
841 struct azx
*chip
= bus
->private_data
;
843 chip
->last_cmd
[azx_command_addr(val
)] = val
;
844 if (chip
->single_cmd
)
845 return azx_single_send_cmd(bus
, val
);
847 return azx_corb_send_cmd(bus
, val
);
851 static unsigned int azx_get_response(struct hda_bus
*bus
,
854 struct azx
*chip
= bus
->private_data
;
855 if (chip
->single_cmd
)
856 return azx_single_get_response(bus
, addr
);
858 return azx_rirb_get_response(bus
, addr
);
861 #ifdef CONFIG_SND_HDA_POWER_SAVE
862 static void azx_power_notify(struct hda_bus
*bus
);
865 /* reset codec link */
866 static int azx_reset(struct azx
*chip
, int full_reset
)
874 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
876 /* reset controller */
877 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
880 while (azx_readb(chip
, GCTL
) && --count
)
883 /* delay for >= 100us for codec PLL to settle per spec
884 * Rev 0.9 section 5.5.1
888 /* Bring controller out of reset */
889 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
892 while (!azx_readb(chip
, GCTL
) && --count
)
895 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
899 /* check to see if controller is ready */
900 if (!azx_readb(chip
, GCTL
)) {
901 snd_printd(SFX
"azx_reset: controller not ready!\n");
905 /* Accept unsolicited responses */
906 if (!chip
->single_cmd
)
907 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) |
911 if (!chip
->codec_mask
) {
912 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
913 snd_printdd(SFX
"codec_mask = 0x%x\n", chip
->codec_mask
);
924 /* enable interrupts */
925 static void azx_int_enable(struct azx
*chip
)
927 /* enable controller CIE and GIE */
928 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
929 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
932 /* disable interrupts */
933 static void azx_int_disable(struct azx
*chip
)
937 /* disable interrupts in stream descriptor */
938 for (i
= 0; i
< chip
->num_streams
; i
++) {
939 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
940 azx_sd_writeb(azx_dev
, SD_CTL
,
941 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
944 /* disable SIE for all streams */
945 azx_writeb(chip
, INTCTL
, 0);
947 /* disable controller CIE and GIE */
948 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
949 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
952 /* clear interrupts */
953 static void azx_int_clear(struct azx
*chip
)
957 /* clear stream status */
958 for (i
= 0; i
< chip
->num_streams
; i
++) {
959 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
960 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
964 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
966 /* clear rirb status */
967 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
969 /* clear int status */
970 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
974 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
977 * Before stream start, initialize parameter
979 azx_dev
->insufficient
= 1;
982 azx_writel(chip
, INTCTL
,
983 azx_readl(chip
, INTCTL
) | (1 << azx_dev
->index
));
984 /* set DMA start and interrupt mask */
985 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
986 SD_CTL_DMA_START
| SD_INT_MASK
);
990 static void azx_stream_clear(struct azx
*chip
, struct azx_dev
*azx_dev
)
992 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
993 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
994 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
998 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
1000 azx_stream_clear(chip
, azx_dev
);
1002 azx_writel(chip
, INTCTL
,
1003 azx_readl(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
1008 * reset and start the controller registers
1010 static void azx_init_chip(struct azx
*chip
, int full_reset
)
1012 if (chip
->initialized
)
1015 /* reset controller */
1016 azx_reset(chip
, full_reset
);
1018 /* initialize interrupts */
1019 azx_int_clear(chip
);
1020 azx_int_enable(chip
);
1022 /* initialize the codec command I/O */
1023 if (!chip
->single_cmd
)
1024 azx_init_cmd_io(chip
);
1026 /* program the position buffer */
1027 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
1028 azx_writel(chip
, DPUBASE
, upper_32_bits(chip
->posbuf
.addr
));
1030 chip
->initialized
= 1;
1034 * initialize the PCI registers
1036 /* update bits in a PCI register byte */
1037 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
1038 unsigned char mask
, unsigned char val
)
1042 pci_read_config_byte(pci
, reg
, &data
);
1044 data
|= (val
& mask
);
1045 pci_write_config_byte(pci
, reg
, data
);
1048 static void azx_init_pci(struct azx
*chip
)
1050 unsigned short snoop
;
1052 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1053 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1054 * Ensuring these bits are 0 clears playback static on some HD Audio
1057 update_pci_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, 0x07, 0);
1059 switch (chip
->driver_type
) {
1060 case AZX_DRIVER_ATI
:
1061 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1062 update_pci_byte(chip
->pci
,
1063 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
1064 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
1066 case AZX_DRIVER_NVIDIA
:
1067 /* For NVIDIA HDA, enable snoop */
1068 update_pci_byte(chip
->pci
,
1069 NVIDIA_HDA_TRANSREG_ADDR
,
1070 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
1071 update_pci_byte(chip
->pci
,
1072 NVIDIA_HDA_ISTRM_COH
,
1073 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1074 update_pci_byte(chip
->pci
,
1075 NVIDIA_HDA_OSTRM_COH
,
1076 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1078 case AZX_DRIVER_SCH
:
1079 case AZX_DRIVER_PCH
:
1080 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
1081 if (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) {
1082 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
,
1083 snoop
& (~INTEL_SCH_HDA_DEVC_NOSNOOP
));
1084 pci_read_config_word(chip
->pci
,
1085 INTEL_SCH_HDA_DEVC
, &snoop
);
1086 snd_printdd(SFX
"HDA snoop disabled, enabling ... %s\n",
1087 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)
1096 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
1101 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
1103 struct azx
*chip
= dev_id
;
1104 struct azx_dev
*azx_dev
;
1109 spin_lock(&chip
->reg_lock
);
1111 status
= azx_readl(chip
, INTSTS
);
1113 spin_unlock(&chip
->reg_lock
);
1117 for (i
= 0; i
< chip
->num_streams
; i
++) {
1118 azx_dev
= &chip
->azx_dev
[i
];
1119 if (status
& azx_dev
->sd_int_sta_mask
) {
1120 sd_status
= azx_sd_readb(azx_dev
, SD_STS
);
1121 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
1122 if (!azx_dev
->substream
|| !azx_dev
->running
||
1123 !(sd_status
& SD_INT_COMPLETE
))
1125 /* check whether this IRQ is really acceptable */
1126 ok
= azx_position_ok(chip
, azx_dev
);
1128 azx_dev
->irq_pending
= 0;
1129 spin_unlock(&chip
->reg_lock
);
1130 snd_pcm_period_elapsed(azx_dev
->substream
);
1131 spin_lock(&chip
->reg_lock
);
1132 } else if (ok
== 0 && chip
->bus
&& chip
->bus
->workq
) {
1133 /* bogus IRQ, process it later */
1134 azx_dev
->irq_pending
= 1;
1135 queue_work(chip
->bus
->workq
,
1136 &chip
->irq_pending_work
);
1141 /* clear rirb int */
1142 status
= azx_readb(chip
, RIRBSTS
);
1143 if (status
& RIRB_INT_MASK
) {
1144 if (status
& RIRB_INT_RESPONSE
) {
1145 if (chip
->driver_type
== AZX_DRIVER_CTX
)
1147 azx_update_rirb(chip
);
1149 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1153 /* clear state status int */
1154 if (azx_readb(chip
, STATESTS
) & 0x04)
1155 azx_writeb(chip
, STATESTS
, 0x04);
1157 spin_unlock(&chip
->reg_lock
);
1164 * set up a BDL entry
1166 static int setup_bdle(struct snd_pcm_substream
*substream
,
1167 struct azx_dev
*azx_dev
, u32
**bdlp
,
1168 int ofs
, int size
, int with_ioc
)
1176 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
1179 addr
= snd_pcm_sgbuf_get_addr(substream
, ofs
);
1180 /* program the address field of the BDL entry */
1181 bdl
[0] = cpu_to_le32((u32
)addr
);
1182 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
1183 /* program the size field of the BDL entry */
1184 chunk
= snd_pcm_sgbuf_get_chunk_size(substream
, ofs
, size
);
1185 bdl
[2] = cpu_to_le32(chunk
);
1186 /* program the IOC to enable interrupt
1187 * only when the whole fragment is processed
1190 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
1200 * set up BDL entries
1202 static int azx_setup_periods(struct azx
*chip
,
1203 struct snd_pcm_substream
*substream
,
1204 struct azx_dev
*azx_dev
)
1207 int i
, ofs
, periods
, period_bytes
;
1210 /* reset BDL address */
1211 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1212 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1214 period_bytes
= azx_dev
->period_bytes
;
1215 periods
= azx_dev
->bufsize
/ period_bytes
;
1217 /* program the initial BDL entries */
1218 bdl
= (u32
*)azx_dev
->bdl
.area
;
1221 pos_adj
= bdl_pos_adj
[chip
->dev_index
];
1223 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1224 int pos_align
= pos_adj
;
1225 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
1227 pos_adj
= pos_align
;
1229 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
1231 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
1232 if (pos_adj
>= period_bytes
) {
1233 snd_printk(KERN_WARNING SFX
"Too big adjustment %d\n",
1234 bdl_pos_adj
[chip
->dev_index
]);
1237 ofs
= setup_bdle(substream
, azx_dev
,
1238 &bdl
, ofs
, pos_adj
, 1);
1244 for (i
= 0; i
< periods
; i
++) {
1245 if (i
== periods
- 1 && pos_adj
)
1246 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1247 period_bytes
- pos_adj
, 0);
1249 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1257 snd_printk(KERN_ERR SFX
"Too many BDL entries: buffer=%d, period=%d\n",
1258 azx_dev
->bufsize
, period_bytes
);
1263 static void azx_stream_reset(struct azx
*chip
, struct azx_dev
*azx_dev
)
1268 azx_stream_clear(chip
, azx_dev
);
1270 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
1271 SD_CTL_STREAM_RESET
);
1274 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1277 val
&= ~SD_CTL_STREAM_RESET
;
1278 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
1282 /* waiting for hardware to report that the stream is out of reset */
1283 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1287 /* reset first position - may not be synced with hw at this time */
1288 *azx_dev
->posbuf
= 0;
1292 * set up the SD for streaming
1294 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
1296 /* make sure the run bit is zero for SD */
1297 azx_stream_clear(chip
, azx_dev
);
1298 /* program the stream_tag */
1299 azx_sd_writel(azx_dev
, SD_CTL
,
1300 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
)|
1301 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
1303 /* program the length of samples in cyclic buffer */
1304 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
1306 /* program the stream format */
1307 /* this value needs to be the same as the one programmed */
1308 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
1310 /* program the stream LVI (last valid index) of the BDL */
1311 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
1313 /* program the BDL address */
1314 /* lower BDL address */
1315 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
1316 /* upper BDL address */
1317 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32_bits(azx_dev
->bdl
.addr
));
1319 /* enable the position buffer */
1320 if (chip
->position_fix
[0] != POS_FIX_LPIB
||
1321 chip
->position_fix
[1] != POS_FIX_LPIB
) {
1322 if (!(azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
1323 azx_writel(chip
, DPLBASE
,
1324 (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
1327 /* set the interrupt enable bits in the descriptor control register */
1328 azx_sd_writel(azx_dev
, SD_CTL
,
1329 azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
1335 * Probe the given codec address
1337 static int probe_codec(struct azx
*chip
, int addr
)
1339 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
1340 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
1343 mutex_lock(&chip
->bus
->cmd_mutex
);
1345 azx_send_cmd(chip
->bus
, cmd
);
1346 res
= azx_get_response(chip
->bus
, addr
);
1348 mutex_unlock(&chip
->bus
->cmd_mutex
);
1351 snd_printdd(SFX
"codec #%d probed OK\n", addr
);
1355 static int azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1356 struct hda_pcm
*cpcm
);
1357 static void azx_stop_chip(struct azx
*chip
);
1359 static void azx_bus_reset(struct hda_bus
*bus
)
1361 struct azx
*chip
= bus
->private_data
;
1364 azx_stop_chip(chip
);
1365 azx_init_chip(chip
, 1);
1367 if (chip
->initialized
) {
1370 for (i
= 0; i
< HDA_MAX_PCMS
; i
++)
1371 snd_pcm_suspend_all(chip
->pcm
[i
]);
1372 snd_hda_suspend(chip
->bus
);
1373 snd_hda_resume(chip
->bus
);
1380 * Codec initialization
1383 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1384 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] __devinitdata
= {
1385 [AZX_DRIVER_NVIDIA
] = 8,
1386 [AZX_DRIVER_TERA
] = 1,
1389 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
1391 struct hda_bus_template bus_temp
;
1395 memset(&bus_temp
, 0, sizeof(bus_temp
));
1396 bus_temp
.private_data
= chip
;
1397 bus_temp
.modelname
= model
;
1398 bus_temp
.pci
= chip
->pci
;
1399 bus_temp
.ops
.command
= azx_send_cmd
;
1400 bus_temp
.ops
.get_response
= azx_get_response
;
1401 bus_temp
.ops
.attach_pcm
= azx_attach_pcm_stream
;
1402 bus_temp
.ops
.bus_reset
= azx_bus_reset
;
1403 #ifdef CONFIG_SND_HDA_POWER_SAVE
1404 bus_temp
.power_save
= &power_save
;
1405 bus_temp
.ops
.pm_notify
= azx_power_notify
;
1408 err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
);
1412 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
)
1413 chip
->bus
->needs_damn_long_delay
= 1;
1416 max_slots
= azx_max_codecs
[chip
->driver_type
];
1418 max_slots
= AZX_DEFAULT_CODECS
;
1420 /* First try to probe all given codec slots */
1421 for (c
= 0; c
< max_slots
; c
++) {
1422 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1423 if (probe_codec(chip
, c
) < 0) {
1424 /* Some BIOSen give you wrong codec addresses
1427 snd_printk(KERN_WARNING SFX
1428 "Codec #%d probe error; "
1429 "disabling it...\n", c
);
1430 chip
->codec_mask
&= ~(1 << c
);
1431 /* More badly, accessing to a non-existing
1432 * codec often screws up the controller chip,
1433 * and disturbs the further communications.
1434 * Thus if an error occurs during probing,
1435 * better to reset the controller chip to
1436 * get back to the sanity state.
1438 azx_stop_chip(chip
);
1439 azx_init_chip(chip
, 1);
1444 /* Then create codec instances */
1445 for (c
= 0; c
< max_slots
; c
++) {
1446 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1447 struct hda_codec
*codec
;
1448 err
= snd_hda_codec_new(chip
->bus
, c
, &codec
);
1451 codec
->beep_mode
= chip
->beep_mode
;
1456 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1462 /* configure each codec instance */
1463 static int __devinit
azx_codec_configure(struct azx
*chip
)
1465 struct hda_codec
*codec
;
1466 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
1467 snd_hda_codec_configure(codec
);
1477 /* assign a stream for the PCM */
1478 static inline struct azx_dev
*
1479 azx_assign_device(struct azx
*chip
, struct snd_pcm_substream
*substream
)
1482 struct azx_dev
*res
= NULL
;
1484 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1485 dev
= chip
->playback_index_offset
;
1486 nums
= chip
->playback_streams
;
1488 dev
= chip
->capture_index_offset
;
1489 nums
= chip
->capture_streams
;
1491 for (i
= 0; i
< nums
; i
++, dev
++)
1492 if (!chip
->azx_dev
[dev
].opened
) {
1493 res
= &chip
->azx_dev
[dev
];
1494 if (res
->device
== substream
->pcm
->device
)
1499 res
->device
= substream
->pcm
->device
;
1504 /* release the assigned stream */
1505 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1507 azx_dev
->opened
= 0;
1510 static struct snd_pcm_hardware azx_pcm_hw
= {
1511 .info
= (SNDRV_PCM_INFO_MMAP
|
1512 SNDRV_PCM_INFO_INTERLEAVED
|
1513 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1514 SNDRV_PCM_INFO_MMAP_VALID
|
1515 /* No full-resume yet implemented */
1516 /* SNDRV_PCM_INFO_RESUME |*/
1517 SNDRV_PCM_INFO_PAUSE
|
1518 SNDRV_PCM_INFO_SYNC_START
),
1519 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1520 .rates
= SNDRV_PCM_RATE_48000
,
1525 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1526 .period_bytes_min
= 128,
1527 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1529 .periods_max
= AZX_MAX_FRAG
,
1535 struct hda_codec
*codec
;
1536 struct hda_pcm_stream
*hinfo
[2];
1539 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1541 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1542 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1543 struct azx
*chip
= apcm
->chip
;
1544 struct azx_dev
*azx_dev
;
1545 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1546 unsigned long flags
;
1549 mutex_lock(&chip
->open_mutex
);
1550 azx_dev
= azx_assign_device(chip
, substream
);
1551 if (azx_dev
== NULL
) {
1552 mutex_unlock(&chip
->open_mutex
);
1555 runtime
->hw
= azx_pcm_hw
;
1556 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1557 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1558 runtime
->hw
.formats
= hinfo
->formats
;
1559 runtime
->hw
.rates
= hinfo
->rates
;
1560 snd_pcm_limit_hw_rates(runtime
);
1561 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1562 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1564 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1566 snd_hda_power_up(apcm
->codec
);
1567 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
1569 azx_release_device(azx_dev
);
1570 snd_hda_power_down(apcm
->codec
);
1571 mutex_unlock(&chip
->open_mutex
);
1574 snd_pcm_limit_hw_rates(runtime
);
1576 if (snd_BUG_ON(!runtime
->hw
.channels_min
) ||
1577 snd_BUG_ON(!runtime
->hw
.channels_max
) ||
1578 snd_BUG_ON(!runtime
->hw
.formats
) ||
1579 snd_BUG_ON(!runtime
->hw
.rates
)) {
1580 azx_release_device(azx_dev
);
1581 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1582 snd_hda_power_down(apcm
->codec
);
1583 mutex_unlock(&chip
->open_mutex
);
1586 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1587 azx_dev
->substream
= substream
;
1588 azx_dev
->running
= 0;
1589 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1591 runtime
->private_data
= azx_dev
;
1592 snd_pcm_set_sync(substream
);
1593 mutex_unlock(&chip
->open_mutex
);
1597 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1599 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1600 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1601 struct azx
*chip
= apcm
->chip
;
1602 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1603 unsigned long flags
;
1605 mutex_lock(&chip
->open_mutex
);
1606 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1607 azx_dev
->substream
= NULL
;
1608 azx_dev
->running
= 0;
1609 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1610 azx_release_device(azx_dev
);
1611 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1612 snd_hda_power_down(apcm
->codec
);
1613 mutex_unlock(&chip
->open_mutex
);
1617 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
1618 struct snd_pcm_hw_params
*hw_params
)
1620 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1622 azx_dev
->bufsize
= 0;
1623 azx_dev
->period_bytes
= 0;
1624 azx_dev
->format_val
= 0;
1625 return snd_pcm_lib_malloc_pages(substream
,
1626 params_buffer_bytes(hw_params
));
1629 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1631 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1632 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1633 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1635 /* reset BDL address */
1636 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1637 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1638 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1639 azx_dev
->bufsize
= 0;
1640 azx_dev
->period_bytes
= 0;
1641 azx_dev
->format_val
= 0;
1643 snd_hda_codec_cleanup(apcm
->codec
, hinfo
, substream
);
1645 return snd_pcm_lib_free_pages(substream
);
1648 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1650 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1651 struct azx
*chip
= apcm
->chip
;
1652 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1653 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1654 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1655 unsigned int bufsize
, period_bytes
, format_val
, stream_tag
;
1658 azx_stream_reset(chip
, azx_dev
);
1659 format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1663 apcm
->codec
->spdif_ctls
);
1665 snd_printk(KERN_ERR SFX
1666 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1667 runtime
->rate
, runtime
->channels
, runtime
->format
);
1671 bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1672 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1674 snd_printdd(SFX
"azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1675 bufsize
, format_val
);
1677 if (bufsize
!= azx_dev
->bufsize
||
1678 period_bytes
!= azx_dev
->period_bytes
||
1679 format_val
!= azx_dev
->format_val
) {
1680 azx_dev
->bufsize
= bufsize
;
1681 azx_dev
->period_bytes
= period_bytes
;
1682 azx_dev
->format_val
= format_val
;
1683 err
= azx_setup_periods(chip
, substream
, azx_dev
);
1688 /* wallclk has 24Mhz clock source */
1689 azx_dev
->period_wallclk
= (((runtime
->period_size
* 24000) /
1690 runtime
->rate
) * 1000);
1691 azx_setup_controller(chip
, azx_dev
);
1692 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1693 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1695 azx_dev
->fifo_size
= 0;
1697 stream_tag
= azx_dev
->stream_tag
;
1698 /* CA-IBG chips need the playback stream starting from 1 */
1699 if (chip
->driver_type
== AZX_DRIVER_CTX
&&
1700 stream_tag
> chip
->capture_streams
)
1701 stream_tag
-= chip
->capture_streams
;
1702 return snd_hda_codec_prepare(apcm
->codec
, hinfo
, stream_tag
,
1703 azx_dev
->format_val
, substream
);
1706 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1708 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1709 struct azx
*chip
= apcm
->chip
;
1710 struct azx_dev
*azx_dev
;
1711 struct snd_pcm_substream
*s
;
1712 int rstart
= 0, start
, nsync
= 0, sbits
= 0;
1716 case SNDRV_PCM_TRIGGER_START
:
1718 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1719 case SNDRV_PCM_TRIGGER_RESUME
:
1722 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1723 case SNDRV_PCM_TRIGGER_SUSPEND
:
1724 case SNDRV_PCM_TRIGGER_STOP
:
1731 snd_pcm_group_for_each_entry(s
, substream
) {
1732 if (s
->pcm
->card
!= substream
->pcm
->card
)
1734 azx_dev
= get_azx_dev(s
);
1735 sbits
|= 1 << azx_dev
->index
;
1737 snd_pcm_trigger_done(s
, substream
);
1740 spin_lock(&chip
->reg_lock
);
1742 /* first, set SYNC bits of corresponding streams */
1743 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) | sbits
);
1745 snd_pcm_group_for_each_entry(s
, substream
) {
1746 if (s
->pcm
->card
!= substream
->pcm
->card
)
1748 azx_dev
= get_azx_dev(s
);
1750 azx_dev
->start_wallclk
= azx_readl(chip
, WALLCLK
);
1752 azx_dev
->start_wallclk
-=
1753 azx_dev
->period_wallclk
;
1754 azx_stream_start(chip
, azx_dev
);
1756 azx_stream_stop(chip
, azx_dev
);
1758 azx_dev
->running
= start
;
1760 spin_unlock(&chip
->reg_lock
);
1764 /* wait until all FIFOs get ready */
1765 for (timeout
= 5000; timeout
; timeout
--) {
1767 snd_pcm_group_for_each_entry(s
, substream
) {
1768 if (s
->pcm
->card
!= substream
->pcm
->card
)
1770 azx_dev
= get_azx_dev(s
);
1771 if (!(azx_sd_readb(azx_dev
, SD_STS
) &
1780 /* wait until all RUN bits are cleared */
1781 for (timeout
= 5000; timeout
; timeout
--) {
1783 snd_pcm_group_for_each_entry(s
, substream
) {
1784 if (s
->pcm
->card
!= substream
->pcm
->card
)
1786 azx_dev
= get_azx_dev(s
);
1787 if (azx_sd_readb(azx_dev
, SD_CTL
) &
1797 spin_lock(&chip
->reg_lock
);
1798 /* reset SYNC bits */
1799 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) & ~sbits
);
1800 spin_unlock(&chip
->reg_lock
);
1805 /* get the current DMA position with correction on VIA chips */
1806 static unsigned int azx_via_get_position(struct azx
*chip
,
1807 struct azx_dev
*azx_dev
)
1809 unsigned int link_pos
, mini_pos
, bound_pos
;
1810 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
1811 unsigned int fifo_size
;
1813 link_pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1814 if (azx_dev
->index
>= 4) {
1815 /* Playback, no problem using link position */
1821 * use mod to get the DMA position just like old chipset
1823 mod_dma_pos
= le32_to_cpu(*azx_dev
->posbuf
);
1824 mod_dma_pos
%= azx_dev
->period_bytes
;
1826 /* azx_dev->fifo_size can't get FIFO size of in stream.
1827 * Get from base address + offset.
1829 fifo_size
= readw(chip
->remap_addr
+ VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
1831 if (azx_dev
->insufficient
) {
1832 /* Link position never gather than FIFO size */
1833 if (link_pos
<= fifo_size
)
1836 azx_dev
->insufficient
= 0;
1839 if (link_pos
<= fifo_size
)
1840 mini_pos
= azx_dev
->bufsize
+ link_pos
- fifo_size
;
1842 mini_pos
= link_pos
- fifo_size
;
1844 /* Find nearest previous boudary */
1845 mod_mini_pos
= mini_pos
% azx_dev
->period_bytes
;
1846 mod_link_pos
= link_pos
% azx_dev
->period_bytes
;
1847 if (mod_link_pos
>= fifo_size
)
1848 bound_pos
= link_pos
- mod_link_pos
;
1849 else if (mod_dma_pos
>= mod_mini_pos
)
1850 bound_pos
= mini_pos
- mod_mini_pos
;
1852 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->period_bytes
;
1853 if (bound_pos
>= azx_dev
->bufsize
)
1857 /* Calculate real DMA position we want */
1858 return bound_pos
+ mod_dma_pos
;
1861 static unsigned int azx_get_position(struct azx
*chip
,
1862 struct azx_dev
*azx_dev
)
1865 int stream
= azx_dev
->substream
->stream
;
1867 switch (chip
->position_fix
[stream
]) {
1870 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1872 case POS_FIX_VIACOMBO
:
1873 pos
= azx_via_get_position(chip
, azx_dev
);
1876 /* use the position buffer */
1877 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1880 if (pos
>= azx_dev
->bufsize
)
1885 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1887 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1888 struct azx
*chip
= apcm
->chip
;
1889 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1890 return bytes_to_frames(substream
->runtime
,
1891 azx_get_position(chip
, azx_dev
));
1895 * Check whether the current DMA position is acceptable for updating
1896 * periods. Returns non-zero if it's OK.
1898 * Many HD-audio controllers appear pretty inaccurate about
1899 * the update-IRQ timing. The IRQ is issued before actually the
1900 * data is processed. So, we need to process it afterwords in a
1903 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
1909 wallclk
= azx_readl(chip
, WALLCLK
) - azx_dev
->start_wallclk
;
1910 if (wallclk
< (azx_dev
->period_wallclk
* 2) / 3)
1911 return -1; /* bogus (too early) interrupt */
1913 stream
= azx_dev
->substream
->stream
;
1914 pos
= azx_get_position(chip
, azx_dev
);
1915 if (chip
->position_fix
[stream
] == POS_FIX_AUTO
) {
1918 "hda-intel: Invalid position buffer, "
1919 "using LPIB read method instead.\n");
1920 chip
->position_fix
[stream
] = POS_FIX_LPIB
;
1921 pos
= azx_get_position(chip
, azx_dev
);
1923 chip
->position_fix
[stream
] = POS_FIX_POSBUF
;
1926 if (WARN_ONCE(!azx_dev
->period_bytes
,
1927 "hda-intel: zero azx_dev->period_bytes"))
1928 return -1; /* this shouldn't happen! */
1929 if (wallclk
< (azx_dev
->period_wallclk
* 5) / 4 &&
1930 pos
% azx_dev
->period_bytes
> azx_dev
->period_bytes
/ 2)
1931 /* NG - it's below the first next period boundary */
1932 return bdl_pos_adj
[chip
->dev_index
] ? 0 : -1;
1933 azx_dev
->start_wallclk
+= wallclk
;
1934 return 1; /* OK, it's fine */
1938 * The work for pending PCM period updates.
1940 static void azx_irq_pending_work(struct work_struct
*work
)
1942 struct azx
*chip
= container_of(work
, struct azx
, irq_pending_work
);
1945 if (!chip
->irq_pending_warned
) {
1947 "hda-intel: IRQ timing workaround is activated "
1948 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1949 chip
->card
->number
);
1950 chip
->irq_pending_warned
= 1;
1955 spin_lock_irq(&chip
->reg_lock
);
1956 for (i
= 0; i
< chip
->num_streams
; i
++) {
1957 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1958 if (!azx_dev
->irq_pending
||
1959 !azx_dev
->substream
||
1962 ok
= azx_position_ok(chip
, azx_dev
);
1964 azx_dev
->irq_pending
= 0;
1965 spin_unlock(&chip
->reg_lock
);
1966 snd_pcm_period_elapsed(azx_dev
->substream
);
1967 spin_lock(&chip
->reg_lock
);
1968 } else if (ok
< 0) {
1969 pending
= 0; /* too early */
1973 spin_unlock_irq(&chip
->reg_lock
);
1980 /* clear irq_pending flags and assure no on-going workq */
1981 static void azx_clear_irq_pending(struct azx
*chip
)
1985 spin_lock_irq(&chip
->reg_lock
);
1986 for (i
= 0; i
< chip
->num_streams
; i
++)
1987 chip
->azx_dev
[i
].irq_pending
= 0;
1988 spin_unlock_irq(&chip
->reg_lock
);
1991 static struct snd_pcm_ops azx_pcm_ops
= {
1992 .open
= azx_pcm_open
,
1993 .close
= azx_pcm_close
,
1994 .ioctl
= snd_pcm_lib_ioctl
,
1995 .hw_params
= azx_pcm_hw_params
,
1996 .hw_free
= azx_pcm_hw_free
,
1997 .prepare
= azx_pcm_prepare
,
1998 .trigger
= azx_pcm_trigger
,
1999 .pointer
= azx_pcm_pointer
,
2000 .page
= snd_pcm_sgbuf_ops_page
,
2003 static void azx_pcm_free(struct snd_pcm
*pcm
)
2005 struct azx_pcm
*apcm
= pcm
->private_data
;
2007 apcm
->chip
->pcm
[pcm
->device
] = NULL
;
2013 azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
2014 struct hda_pcm
*cpcm
)
2016 struct azx
*chip
= bus
->private_data
;
2017 struct snd_pcm
*pcm
;
2018 struct azx_pcm
*apcm
;
2019 int pcm_dev
= cpcm
->device
;
2022 if (pcm_dev
>= HDA_MAX_PCMS
) {
2023 snd_printk(KERN_ERR SFX
"Invalid PCM device number %d\n",
2027 if (chip
->pcm
[pcm_dev
]) {
2028 snd_printk(KERN_ERR SFX
"PCM %d already exists\n", pcm_dev
);
2031 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
2032 cpcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].substreams
,
2033 cpcm
->stream
[SNDRV_PCM_STREAM_CAPTURE
].substreams
,
2037 strlcpy(pcm
->name
, cpcm
->name
, sizeof(pcm
->name
));
2038 apcm
= kzalloc(sizeof(*apcm
), GFP_KERNEL
);
2042 apcm
->codec
= codec
;
2043 pcm
->private_data
= apcm
;
2044 pcm
->private_free
= azx_pcm_free
;
2045 if (cpcm
->pcm_type
== HDA_PCM_TYPE_MODEM
)
2046 pcm
->dev_class
= SNDRV_PCM_CLASS_MODEM
;
2047 chip
->pcm
[pcm_dev
] = pcm
;
2049 for (s
= 0; s
< 2; s
++) {
2050 apcm
->hinfo
[s
] = &cpcm
->stream
[s
];
2051 if (cpcm
->stream
[s
].substreams
)
2052 snd_pcm_set_ops(pcm
, s
, &azx_pcm_ops
);
2054 /* buffer pre-allocation */
2055 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV_SG
,
2056 snd_dma_pci_data(chip
->pci
),
2057 1024 * 64, 32 * 1024 * 1024);
2062 * mixer creation - all stuff is implemented in hda module
2064 static int __devinit
azx_mixer_create(struct azx
*chip
)
2066 return snd_hda_build_controls(chip
->bus
);
2071 * initialize SD streams
2073 static int __devinit
azx_init_stream(struct azx
*chip
)
2077 /* initialize each stream (aka device)
2078 * assign the starting bdl address to each stream (device)
2081 for (i
= 0; i
< chip
->num_streams
; i
++) {
2082 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
2083 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
2084 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2085 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
2086 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2087 azx_dev
->sd_int_sta_mask
= 1 << i
;
2088 /* stream tag: must be non-zero and unique */
2090 azx_dev
->stream_tag
= i
+ 1;
2096 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
2098 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
2099 chip
->msi
? 0 : IRQF_SHARED
,
2100 "hda_intel", chip
)) {
2101 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
2102 "disabling device\n", chip
->pci
->irq
);
2104 snd_card_disconnect(chip
->card
);
2107 chip
->irq
= chip
->pci
->irq
;
2108 pci_intx(chip
->pci
, !chip
->msi
);
2113 static void azx_stop_chip(struct azx
*chip
)
2115 if (!chip
->initialized
)
2118 /* disable interrupts */
2119 azx_int_disable(chip
);
2120 azx_int_clear(chip
);
2122 /* disable CORB/RIRB */
2123 azx_free_cmd_io(chip
);
2125 /* disable position buffer */
2126 azx_writel(chip
, DPLBASE
, 0);
2127 azx_writel(chip
, DPUBASE
, 0);
2129 chip
->initialized
= 0;
2132 #ifdef CONFIG_SND_HDA_POWER_SAVE
2133 /* power-up/down the controller */
2134 static void azx_power_notify(struct hda_bus
*bus
)
2136 struct azx
*chip
= bus
->private_data
;
2137 struct hda_codec
*c
;
2140 list_for_each_entry(c
, &bus
->codec_list
, list
) {
2147 azx_init_chip(chip
, 1);
2148 else if (chip
->running
&& power_save_controller
&&
2149 !bus
->power_keep_link_on
)
2150 azx_stop_chip(chip
);
2152 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2159 static int snd_hda_codecs_inuse(struct hda_bus
*bus
)
2161 struct hda_codec
*codec
;
2163 list_for_each_entry(codec
, &bus
->codec_list
, list
) {
2164 if (snd_hda_codec_needs_resume(codec
))
2170 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
2172 struct snd_card
*card
= pci_get_drvdata(pci
);
2173 struct azx
*chip
= card
->private_data
;
2176 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
2177 azx_clear_irq_pending(chip
);
2178 for (i
= 0; i
< HDA_MAX_PCMS
; i
++)
2179 snd_pcm_suspend_all(chip
->pcm
[i
]);
2180 if (chip
->initialized
)
2181 snd_hda_suspend(chip
->bus
);
2182 azx_stop_chip(chip
);
2183 if (chip
->irq
>= 0) {
2184 free_irq(chip
->irq
, chip
);
2188 pci_disable_msi(chip
->pci
);
2189 pci_disable_device(pci
);
2190 pci_save_state(pci
);
2191 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
2195 static int azx_resume(struct pci_dev
*pci
)
2197 struct snd_card
*card
= pci_get_drvdata(pci
);
2198 struct azx
*chip
= card
->private_data
;
2200 pci_set_power_state(pci
, PCI_D0
);
2201 pci_restore_state(pci
);
2202 if (pci_enable_device(pci
) < 0) {
2203 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
2204 "disabling device\n");
2205 snd_card_disconnect(card
);
2208 pci_set_master(pci
);
2210 if (pci_enable_msi(pci
) < 0)
2212 if (azx_acquire_irq(chip
, 1) < 0)
2216 if (snd_hda_codecs_inuse(chip
->bus
))
2217 azx_init_chip(chip
, 1);
2219 snd_hda_resume(chip
->bus
);
2220 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2223 #endif /* CONFIG_PM */
2227 * reboot notifier for hang-up problem at power-down
2229 static int azx_halt(struct notifier_block
*nb
, unsigned long event
, void *buf
)
2231 struct azx
*chip
= container_of(nb
, struct azx
, reboot_notifier
);
2232 snd_hda_bus_reboot_notify(chip
->bus
);
2233 azx_stop_chip(chip
);
2237 static void azx_notifier_register(struct azx
*chip
)
2239 chip
->reboot_notifier
.notifier_call
= azx_halt
;
2240 register_reboot_notifier(&chip
->reboot_notifier
);
2243 static void azx_notifier_unregister(struct azx
*chip
)
2245 if (chip
->reboot_notifier
.notifier_call
)
2246 unregister_reboot_notifier(&chip
->reboot_notifier
);
2252 static int azx_free(struct azx
*chip
)
2256 azx_notifier_unregister(chip
);
2258 if (chip
->initialized
) {
2259 azx_clear_irq_pending(chip
);
2260 for (i
= 0; i
< chip
->num_streams
; i
++)
2261 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
2262 azx_stop_chip(chip
);
2266 free_irq(chip
->irq
, (void*)chip
);
2268 pci_disable_msi(chip
->pci
);
2269 if (chip
->remap_addr
)
2270 iounmap(chip
->remap_addr
);
2272 if (chip
->azx_dev
) {
2273 for (i
= 0; i
< chip
->num_streams
; i
++)
2274 if (chip
->azx_dev
[i
].bdl
.area
)
2275 snd_dma_free_pages(&chip
->azx_dev
[i
].bdl
);
2278 snd_dma_free_pages(&chip
->rb
);
2279 if (chip
->posbuf
.area
)
2280 snd_dma_free_pages(&chip
->posbuf
);
2281 pci_release_regions(chip
->pci
);
2282 pci_disable_device(chip
->pci
);
2283 kfree(chip
->azx_dev
);
2289 static int azx_dev_free(struct snd_device
*device
)
2291 return azx_free(device
->device_data
);
2295 * white/black-listing for position_fix
2297 static struct snd_pci_quirk position_fix_list
[] __devinitdata
= {
2298 SND_PCI_QUIRK(0x1025, 0x009f, "Acer Aspire 5110", POS_FIX_LPIB
),
2299 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
2300 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
2301 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB
),
2302 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB
),
2303 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
2304 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB
),
2305 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB
),
2306 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB
),
2307 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB
),
2308 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB
),
2309 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB
),
2310 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB
),
2311 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB
),
2312 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB
),
2313 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB
),
2314 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB
),
2315 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB
),
2316 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB
),
2320 static int __devinit
check_position_fix(struct azx
*chip
, int fix
)
2322 const struct snd_pci_quirk
*q
;
2326 case POS_FIX_POSBUF
:
2327 case POS_FIX_VIACOMBO
:
2331 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
2334 "hda_intel: position_fix set to %d "
2335 "for device %04x:%04x\n",
2336 q
->value
, q
->subvendor
, q
->subdevice
);
2340 /* Check VIA/ATI HD Audio Controller exist */
2341 switch (chip
->driver_type
) {
2342 case AZX_DRIVER_VIA
:
2343 case AZX_DRIVER_ATI
:
2344 /* Use link position directly, avoid any transfer problem. */
2345 return POS_FIX_VIACOMBO
;
2348 return POS_FIX_AUTO
;
2352 * black-lists for probe_mask
2354 static struct snd_pci_quirk probe_mask_list
[] __devinitdata
= {
2355 /* Thinkpad often breaks the controller communication when accessing
2356 * to the non-working (or non-existing) modem codec slot.
2358 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2359 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2360 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2362 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2363 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2364 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2365 /* forced codec slots */
2366 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2367 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2371 #define AZX_FORCE_CODEC_MASK 0x100
2373 static void __devinit
check_probe_mask(struct azx
*chip
, int dev
)
2375 const struct snd_pci_quirk
*q
;
2377 chip
->codec_probe_mask
= probe_mask
[dev
];
2378 if (chip
->codec_probe_mask
== -1) {
2379 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
2382 "hda_intel: probe_mask set to 0x%x "
2383 "for device %04x:%04x\n",
2384 q
->value
, q
->subvendor
, q
->subdevice
);
2385 chip
->codec_probe_mask
= q
->value
;
2389 /* check forced option */
2390 if (chip
->codec_probe_mask
!= -1 &&
2391 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
2392 chip
->codec_mask
= chip
->codec_probe_mask
& 0xff;
2393 printk(KERN_INFO
"hda_intel: codec_mask forced to 0x%x\n",
2399 * white/black-list for enable_msi
2401 static struct snd_pci_quirk msi_black_list
[] __devinitdata
= {
2402 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2403 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2404 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2405 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2406 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2410 static void __devinit
check_msi(struct azx
*chip
)
2412 const struct snd_pci_quirk
*q
;
2414 if (enable_msi
>= 0) {
2415 chip
->msi
= !!enable_msi
;
2418 chip
->msi
= 1; /* enable MSI as default */
2419 q
= snd_pci_quirk_lookup(chip
->pci
, msi_black_list
);
2422 "hda_intel: msi for device %04x:%04x set to %d\n",
2423 q
->subvendor
, q
->subdevice
, q
->value
);
2424 chip
->msi
= q
->value
;
2428 /* NVidia chipsets seem to cause troubles with MSI */
2429 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
) {
2430 printk(KERN_INFO
"hda_intel: Disable MSI for Nvidia chipset\n");
2439 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
2440 int dev
, int driver_type
,
2445 unsigned short gcap
;
2446 static struct snd_device_ops ops
= {
2447 .dev_free
= azx_dev_free
,
2452 err
= pci_enable_device(pci
);
2456 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
2458 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
2459 pci_disable_device(pci
);
2463 spin_lock_init(&chip
->reg_lock
);
2464 mutex_init(&chip
->open_mutex
);
2468 chip
->driver_type
= driver_type
;
2470 chip
->dev_index
= dev
;
2471 INIT_WORK(&chip
->irq_pending_work
, azx_irq_pending_work
);
2473 chip
->position_fix
[0] = chip
->position_fix
[1] =
2474 check_position_fix(chip
, position_fix
[dev
]);
2475 check_probe_mask(chip
, dev
);
2477 chip
->single_cmd
= single_cmd
;
2479 if (bdl_pos_adj
[dev
] < 0) {
2480 switch (chip
->driver_type
) {
2481 case AZX_DRIVER_ICH
:
2482 case AZX_DRIVER_PCH
:
2483 bdl_pos_adj
[dev
] = 1;
2486 bdl_pos_adj
[dev
] = 32;
2491 #if BITS_PER_LONG != 64
2492 /* Fix up base address on ULI M5461 */
2493 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
2495 pci_read_config_word(pci
, 0x40, &tmp3
);
2496 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
2497 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
2501 err
= pci_request_regions(pci
, "ICH HD audio");
2504 pci_disable_device(pci
);
2508 chip
->addr
= pci_resource_start(pci
, 0);
2509 chip
->remap_addr
= pci_ioremap_bar(pci
, 0);
2510 if (chip
->remap_addr
== NULL
) {
2511 snd_printk(KERN_ERR SFX
"ioremap error\n");
2517 if (pci_enable_msi(pci
) < 0)
2520 if (azx_acquire_irq(chip
, 0) < 0) {
2525 pci_set_master(pci
);
2526 synchronize_irq(chip
->irq
);
2528 gcap
= azx_readw(chip
, GCAP
);
2529 snd_printdd(SFX
"chipset global capabilities = 0x%x\n", gcap
);
2531 /* disable SB600 64bit support for safety */
2532 if ((chip
->driver_type
== AZX_DRIVER_ATI
) ||
2533 (chip
->driver_type
== AZX_DRIVER_ATIHDMI
)) {
2534 struct pci_dev
*p_smbus
;
2535 p_smbus
= pci_get_device(PCI_VENDOR_ID_ATI
,
2536 PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2539 if (p_smbus
->revision
< 0x30)
2540 gcap
&= ~ICH6_GCAP_64OK
;
2541 pci_dev_put(p_smbus
);
2545 /* disable 64bit DMA address for Teradici */
2546 /* it does not work with device 6549:1200 subsys e4a2:040b */
2547 if (chip
->driver_type
== AZX_DRIVER_TERA
)
2548 gcap
&= ~ICH6_GCAP_64OK
;
2550 /* allow 64bit DMA address if supported by H/W */
2551 if ((gcap
& ICH6_GCAP_64OK
) && !pci_set_dma_mask(pci
, DMA_BIT_MASK(64)))
2552 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(64));
2554 pci_set_dma_mask(pci
, DMA_BIT_MASK(32));
2555 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(32));
2558 /* read number of streams from GCAP register instead of using
2561 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
2562 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
2563 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
2564 /* gcap didn't give any info, switching to old method */
2566 switch (chip
->driver_type
) {
2567 case AZX_DRIVER_ULI
:
2568 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
2569 chip
->capture_streams
= ULI_NUM_CAPTURE
;
2571 case AZX_DRIVER_ATIHDMI
:
2572 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
2573 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
2575 case AZX_DRIVER_GENERIC
:
2577 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
2578 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
2582 chip
->capture_index_offset
= 0;
2583 chip
->playback_index_offset
= chip
->capture_streams
;
2584 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
2585 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
),
2587 if (!chip
->azx_dev
) {
2588 snd_printk(KERN_ERR SFX
"cannot malloc azx_dev\n");
2592 for (i
= 0; i
< chip
->num_streams
; i
++) {
2593 /* allocate memory for the BDL for each stream */
2594 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2595 snd_dma_pci_data(chip
->pci
),
2596 BDL_SIZE
, &chip
->azx_dev
[i
].bdl
);
2598 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
2602 /* allocate memory for the position buffer */
2603 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2604 snd_dma_pci_data(chip
->pci
),
2605 chip
->num_streams
* 8, &chip
->posbuf
);
2607 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
2610 /* allocate CORB/RIRB */
2611 err
= azx_alloc_cmd_io(chip
);
2615 /* initialize streams */
2616 azx_init_stream(chip
);
2618 /* initialize chip */
2620 azx_init_chip(chip
, (probe_only
[dev
] & 2) == 0);
2622 /* codec detection */
2623 if (!chip
->codec_mask
) {
2624 snd_printk(KERN_ERR SFX
"no codecs found!\n");
2629 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
2631 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
2635 strcpy(card
->driver
, "HDA-Intel");
2636 strlcpy(card
->shortname
, driver_short_names
[chip
->driver_type
],
2637 sizeof(card
->shortname
));
2638 snprintf(card
->longname
, sizeof(card
->longname
),
2639 "%s at 0x%lx irq %i",
2640 card
->shortname
, chip
->addr
, chip
->irq
);
2650 static void power_down_all_codecs(struct azx
*chip
)
2652 #ifdef CONFIG_SND_HDA_POWER_SAVE
2653 /* The codecs were powered up in snd_hda_codec_new().
2654 * Now all initialization done, so turn them down if possible
2656 struct hda_codec
*codec
;
2657 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
2658 snd_hda_power_down(codec
);
2663 static int __devinit
azx_probe(struct pci_dev
*pci
,
2664 const struct pci_device_id
*pci_id
)
2667 struct snd_card
*card
;
2671 if (dev
>= SNDRV_CARDS
)
2678 err
= snd_card_create(index
[dev
], id
[dev
], THIS_MODULE
, 0, &card
);
2680 snd_printk(KERN_ERR SFX
"Error creating card!\n");
2684 /* set this here since it's referred in snd_hda_load_patch() */
2685 snd_card_set_dev(card
, &pci
->dev
);
2687 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2690 card
->private_data
= chip
;
2692 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2693 chip
->beep_mode
= beep_mode
[dev
];
2696 /* create codec instances */
2697 err
= azx_codec_create(chip
, model
[dev
]);
2700 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2702 snd_printk(KERN_ERR SFX
"Applying patch firmware '%s'\n",
2704 err
= snd_hda_load_patch(chip
->bus
, patch
[dev
]);
2709 if ((probe_only
[dev
] & 1) == 0) {
2710 err
= azx_codec_configure(chip
);
2715 /* create PCM streams */
2716 err
= snd_hda_build_pcms(chip
->bus
);
2720 /* create mixer controls */
2721 err
= azx_mixer_create(chip
);
2725 err
= snd_card_register(card
);
2729 pci_set_drvdata(pci
, card
);
2731 power_down_all_codecs(chip
);
2732 azx_notifier_register(chip
);
2737 snd_card_free(card
);
2741 static void __devexit
azx_remove(struct pci_dev
*pci
)
2743 snd_card_free(pci_get_drvdata(pci
));
2744 pci_set_drvdata(pci
, NULL
);
2748 static DEFINE_PCI_DEVICE_TABLE(azx_ids
) = {
2750 { PCI_DEVICE(0x8086, 0x1c20), .driver_data
= AZX_DRIVER_PCH
},
2752 { PCI_DEVICE(0x8086, 0x1d20), .driver_data
= AZX_DRIVER_PCH
},
2754 { PCI_DEVICE(0x8086, 0x811b), .driver_data
= AZX_DRIVER_SCH
},
2756 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
),
2757 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2758 .class_mask
= 0xffffff,
2759 .driver_data
= AZX_DRIVER_ICH
},
2760 /* ATI SB 450/600 */
2761 { PCI_DEVICE(0x1002, 0x437b), .driver_data
= AZX_DRIVER_ATI
},
2762 { PCI_DEVICE(0x1002, 0x4383), .driver_data
= AZX_DRIVER_ATI
},
2764 { PCI_DEVICE(0x1002, 0x793b), .driver_data
= AZX_DRIVER_ATIHDMI
},
2765 { PCI_DEVICE(0x1002, 0x7919), .driver_data
= AZX_DRIVER_ATIHDMI
},
2766 { PCI_DEVICE(0x1002, 0x960f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2767 { PCI_DEVICE(0x1002, 0x970f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2768 { PCI_DEVICE(0x1002, 0xaa00), .driver_data
= AZX_DRIVER_ATIHDMI
},
2769 { PCI_DEVICE(0x1002, 0xaa08), .driver_data
= AZX_DRIVER_ATIHDMI
},
2770 { PCI_DEVICE(0x1002, 0xaa10), .driver_data
= AZX_DRIVER_ATIHDMI
},
2771 { PCI_DEVICE(0x1002, 0xaa18), .driver_data
= AZX_DRIVER_ATIHDMI
},
2772 { PCI_DEVICE(0x1002, 0xaa20), .driver_data
= AZX_DRIVER_ATIHDMI
},
2773 { PCI_DEVICE(0x1002, 0xaa28), .driver_data
= AZX_DRIVER_ATIHDMI
},
2774 { PCI_DEVICE(0x1002, 0xaa30), .driver_data
= AZX_DRIVER_ATIHDMI
},
2775 { PCI_DEVICE(0x1002, 0xaa38), .driver_data
= AZX_DRIVER_ATIHDMI
},
2776 { PCI_DEVICE(0x1002, 0xaa40), .driver_data
= AZX_DRIVER_ATIHDMI
},
2777 { PCI_DEVICE(0x1002, 0xaa48), .driver_data
= AZX_DRIVER_ATIHDMI
},
2778 /* VIA VT8251/VT8237A */
2779 { PCI_DEVICE(0x1106, 0x3288), .driver_data
= AZX_DRIVER_VIA
},
2781 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
2783 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
2785 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
),
2786 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2787 .class_mask
= 0xffffff,
2788 .driver_data
= AZX_DRIVER_NVIDIA
},
2790 { PCI_DEVICE(0x6549, 0x1200), .driver_data
= AZX_DRIVER_TERA
},
2791 /* Creative X-Fi (CA0110-IBG) */
2792 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2793 /* the following entry conflicts with snd-ctxfi driver,
2794 * as ctxfi driver mutates from HD-audio to native mode with
2795 * a special command sequence.
2797 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE
, PCI_ANY_ID
),
2798 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2799 .class_mask
= 0xffffff,
2800 .driver_data
= AZX_DRIVER_CTX
},
2802 /* this entry seems still valid -- i.e. without emu20kx chip */
2803 { PCI_DEVICE(0x1102, 0x0009), .driver_data
= AZX_DRIVER_CTX
},
2806 { PCI_DEVICE(0x17f3, 0x3010), .driver_data
= AZX_DRIVER_GENERIC
},
2807 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2808 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
2809 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2810 .class_mask
= 0xffffff,
2811 .driver_data
= AZX_DRIVER_GENERIC
},
2812 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
),
2813 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2814 .class_mask
= 0xffffff,
2815 .driver_data
= AZX_DRIVER_GENERIC
},
2818 MODULE_DEVICE_TABLE(pci
, azx_ids
);
2820 /* pci_driver definition */
2821 static struct pci_driver driver
= {
2822 .name
= "HDA Intel",
2823 .id_table
= azx_ids
,
2825 .remove
= __devexit_p(azx_remove
),
2827 .suspend
= azx_suspend
,
2828 .resume
= azx_resume
,
2832 static int __init
alsa_card_azx_init(void)
2834 return pci_register_driver(&driver
);
2837 static void __exit
alsa_card_azx_exit(void)
2839 pci_unregister_driver(&driver
);
2842 module_init(alsa_card_azx_init
)
2843 module_exit(alsa_card_azx_exit
)