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1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_priv.h"
66 #include "hda_i915.h"
67
68 /* position fix mode */
69 enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75 };
76
77 /* Defines for ATI HD Audio support in SB450 south bridge */
78 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81 /* Defines for Nvidia HDA support */
82 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84 #define NVIDIA_HDA_ISTRM_COH 0x4d
85 #define NVIDIA_HDA_OSTRM_COH 0x4c
86 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88 /* Defines for Intel SCH HDA snoop control */
89 #define INTEL_SCH_HDA_DEVC 0x78
90 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92 /* Define IN stream 0 FIFO size offset in VIA controller */
93 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94 /* Define VIA HD Audio Device ID*/
95 #define VIA_HDAC_DEVICE_ID 0x3288
96
97 /* max number of SDs */
98 /* ICH, ATI and VIA have 4 playback and 4 capture */
99 #define ICH6_NUM_CAPTURE 4
100 #define ICH6_NUM_PLAYBACK 4
101
102 /* ULI has 6 playback and 5 capture */
103 #define ULI_NUM_CAPTURE 5
104 #define ULI_NUM_PLAYBACK 6
105
106 /* ATI HDMI may have up to 8 playbacks and 0 capture */
107 #define ATIHDMI_NUM_CAPTURE 0
108 #define ATIHDMI_NUM_PLAYBACK 8
109
110 /* TERA has 4 playback and 3 capture */
111 #define TERA_NUM_CAPTURE 3
112 #define TERA_NUM_PLAYBACK 4
113
114
115 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
117 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
118 static char *model[SNDRV_CARDS];
119 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
122 static int probe_only[SNDRV_CARDS];
123 static int jackpoll_ms[SNDRV_CARDS];
124 static bool single_cmd;
125 static int enable_msi = -1;
126 #ifdef CONFIG_SND_HDA_PATCH_LOADER
127 static char *patch[SNDRV_CARDS];
128 #endif
129 #ifdef CONFIG_SND_HDA_INPUT_BEEP
130 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132 #endif
133
134 module_param_array(index, int, NULL, 0444);
135 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
136 module_param_array(id, charp, NULL, 0444);
137 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
138 module_param_array(enable, bool, NULL, 0444);
139 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140 module_param_array(model, charp, NULL, 0444);
141 MODULE_PARM_DESC(model, "Use the given board model.");
142 module_param_array(position_fix, int, NULL, 0444);
143 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
145 module_param_array(bdl_pos_adj, int, NULL, 0644);
146 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
147 module_param_array(probe_mask, int, NULL, 0444);
148 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
149 module_param_array(probe_only, int, NULL, 0444);
150 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
151 module_param_array(jackpoll_ms, int, NULL, 0444);
152 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
153 module_param(single_cmd, bool, 0444);
154 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
156 module_param(enable_msi, bint, 0444);
157 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
158 #ifdef CONFIG_SND_HDA_PATCH_LOADER
159 module_param_array(patch, charp, NULL, 0444);
160 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161 #endif
162 #ifdef CONFIG_SND_HDA_INPUT_BEEP
163 module_param_array(beep_mode, bool, NULL, 0444);
164 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
165 "(0=off, 1=on) (default=1).");
166 #endif
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 static int *power_save_addr = &power_save;
178 module_param(power_save, xint, 0644);
179 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
181
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
189 #else
190 static int *power_save_addr;
191 #endif /* CONFIG_PM */
192
193 static int align_buffer_size = -1;
194 module_param(align_buffer_size, bint, 0644);
195 MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
198 #ifdef CONFIG_X86
199 static bool hda_snoop = true;
200 module_param_named(snoop, hda_snoop, bool, 0444);
201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
202 #else
203 #define hda_snoop true
204 #endif
205
206
207 MODULE_LICENSE("GPL");
208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
210 "{Intel, ICH7},"
211 "{Intel, ESB2},"
212 "{Intel, ICH8},"
213 "{Intel, ICH9},"
214 "{Intel, ICH10},"
215 "{Intel, PCH},"
216 "{Intel, CPT},"
217 "{Intel, PPT},"
218 "{Intel, LPT},"
219 "{Intel, LPT_LP},"
220 "{Intel, WPT_LP},"
221 "{Intel, HPT},"
222 "{Intel, PBG},"
223 "{Intel, SCH},"
224 "{ATI, SB450},"
225 "{ATI, SB600},"
226 "{ATI, RS600},"
227 "{ATI, RS690},"
228 "{ATI, RS780},"
229 "{ATI, R600},"
230 "{ATI, RV630},"
231 "{ATI, RV610},"
232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
236 "{VIA, VT8251},"
237 "{VIA, VT8237A},"
238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
240 MODULE_DESCRIPTION("Intel HDA driver");
241
242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
244 #define SUPPORT_VGA_SWITCHEROO
245 #endif
246 #endif
247
248
249 /*
250 */
251
252 /* driver types */
253 enum {
254 AZX_DRIVER_ICH,
255 AZX_DRIVER_PCH,
256 AZX_DRIVER_SCH,
257 AZX_DRIVER_HDMI,
258 AZX_DRIVER_ATI,
259 AZX_DRIVER_ATIHDMI,
260 AZX_DRIVER_ATIHDMI_NS,
261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
264 AZX_DRIVER_NVIDIA,
265 AZX_DRIVER_TERA,
266 AZX_DRIVER_CTX,
267 AZX_DRIVER_CTHDA,
268 AZX_DRIVER_GENERIC,
269 AZX_NUM_DRIVERS, /* keep this as last entry */
270 };
271
272 /* quirks for Intel PCH */
273 #define AZX_DCAPS_INTEL_PCH_NOPM \
274 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
275 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_REVERSE_ASSIGN)
276
277 #define AZX_DCAPS_INTEL_PCH \
278 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
279
280 #define AZX_DCAPS_INTEL_HASWELL \
281 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
282 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
283 AZX_DCAPS_I915_POWERWELL)
284
285 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
286 #define AZX_DCAPS_INTEL_BROADWELL \
287 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
288 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
289 AZX_DCAPS_I915_POWERWELL)
290
291 /* quirks for ATI SB / AMD Hudson */
292 #define AZX_DCAPS_PRESET_ATI_SB \
293 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
294 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
295
296 /* quirks for ATI/AMD HDMI */
297 #define AZX_DCAPS_PRESET_ATI_HDMI \
298 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
299
300 /* quirks for Nvidia */
301 #define AZX_DCAPS_PRESET_NVIDIA \
302 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
303 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
304 AZX_DCAPS_CORBRP_SELF_CLEAR)
305
306 #define AZX_DCAPS_PRESET_CTHDA \
307 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
308
309 /*
310 * VGA-switcher support
311 */
312 #ifdef SUPPORT_VGA_SWITCHEROO
313 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
314 #else
315 #define use_vga_switcheroo(chip) 0
316 #endif
317
318 static char *driver_short_names[] = {
319 [AZX_DRIVER_ICH] = "HDA Intel",
320 [AZX_DRIVER_PCH] = "HDA Intel PCH",
321 [AZX_DRIVER_SCH] = "HDA Intel MID",
322 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
323 [AZX_DRIVER_ATI] = "HDA ATI SB",
324 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
325 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
326 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
327 [AZX_DRIVER_SIS] = "HDA SIS966",
328 [AZX_DRIVER_ULI] = "HDA ULI M5461",
329 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
330 [AZX_DRIVER_TERA] = "HDA Teradici",
331 [AZX_DRIVER_CTX] = "HDA Creative",
332 [AZX_DRIVER_CTHDA] = "HDA Creative",
333 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
334 };
335
336 struct hda_intel {
337 struct azx chip;
338
339 /* for pending irqs */
340 struct work_struct irq_pending_work;
341
342 /* sync probing */
343 struct completion probe_wait;
344 struct work_struct probe_work;
345
346 /* card list (for power_save trigger) */
347 struct list_head list;
348
349 /* extra flags */
350 unsigned int irq_pending_warned:1;
351
352 /* VGA-switcheroo setup */
353 unsigned int use_vga_switcheroo:1;
354 unsigned int vga_switcheroo_registered:1;
355 unsigned int init_failed:1; /* delayed init failed */
356
357 /* secondary power domain for hdmi audio under vga device */
358 struct dev_pm_domain hdmi_pm_domain;
359 };
360
361 #ifdef CONFIG_X86
362 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
363 {
364 int pages;
365
366 if (azx_snoop(chip))
367 return;
368 if (!dmab || !dmab->area || !dmab->bytes)
369 return;
370
371 #ifdef CONFIG_SND_DMA_SGBUF
372 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
373 struct snd_sg_buf *sgbuf = dmab->private_data;
374 if (on)
375 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
376 else
377 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
378 return;
379 }
380 #endif
381
382 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
383 if (on)
384 set_memory_wc((unsigned long)dmab->area, pages);
385 else
386 set_memory_wb((unsigned long)dmab->area, pages);
387 }
388
389 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
390 bool on)
391 {
392 __mark_pages_wc(chip, buf, on);
393 }
394 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
395 struct snd_pcm_substream *substream, bool on)
396 {
397 if (azx_dev->wc_marked != on) {
398 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
399 azx_dev->wc_marked = on;
400 }
401 }
402 #else
403 /* NOP for other archs */
404 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
405 bool on)
406 {
407 }
408 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
409 struct snd_pcm_substream *substream, bool on)
410 {
411 }
412 #endif
413
414 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
415
416 /*
417 * initialize the PCI registers
418 */
419 /* update bits in a PCI register byte */
420 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
421 unsigned char mask, unsigned char val)
422 {
423 unsigned char data;
424
425 pci_read_config_byte(pci, reg, &data);
426 data &= ~mask;
427 data |= (val & mask);
428 pci_write_config_byte(pci, reg, data);
429 }
430
431 static void azx_init_pci(struct azx *chip)
432 {
433 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
434 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
435 * Ensuring these bits are 0 clears playback static on some HD Audio
436 * codecs.
437 * The PCI register TCSEL is defined in the Intel manuals.
438 */
439 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
440 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
441 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
442 }
443
444 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
445 * we need to enable snoop.
446 */
447 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
448 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
449 azx_snoop(chip));
450 update_pci_byte(chip->pci,
451 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
452 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
453 }
454
455 /* For NVIDIA HDA, enable snoop */
456 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
457 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
458 azx_snoop(chip));
459 update_pci_byte(chip->pci,
460 NVIDIA_HDA_TRANSREG_ADDR,
461 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
462 update_pci_byte(chip->pci,
463 NVIDIA_HDA_ISTRM_COH,
464 0x01, NVIDIA_HDA_ENABLE_COHBIT);
465 update_pci_byte(chip->pci,
466 NVIDIA_HDA_OSTRM_COH,
467 0x01, NVIDIA_HDA_ENABLE_COHBIT);
468 }
469
470 /* Enable SCH/PCH snoop if needed */
471 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
472 unsigned short snoop;
473 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
474 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
475 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
476 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
477 if (!azx_snoop(chip))
478 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
479 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
480 pci_read_config_word(chip->pci,
481 INTEL_SCH_HDA_DEVC, &snoop);
482 }
483 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
484 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
485 "Disabled" : "Enabled");
486 }
487 }
488
489 /* calculate runtime delay from LPIB */
490 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
491 unsigned int pos)
492 {
493 struct snd_pcm_substream *substream = azx_dev->substream;
494 int stream = substream->stream;
495 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
496 int delay;
497
498 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
499 delay = pos - lpib_pos;
500 else
501 delay = lpib_pos - pos;
502 if (delay < 0) {
503 if (delay >= azx_dev->delay_negative_threshold)
504 delay = 0;
505 else
506 delay += azx_dev->bufsize;
507 }
508
509 if (delay >= azx_dev->period_bytes) {
510 dev_info(chip->card->dev,
511 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
512 delay, azx_dev->period_bytes);
513 delay = 0;
514 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
515 chip->get_delay[stream] = NULL;
516 }
517
518 return bytes_to_frames(substream->runtime, delay);
519 }
520
521 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
522
523 /* called from IRQ */
524 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
525 {
526 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
527 int ok;
528
529 ok = azx_position_ok(chip, azx_dev);
530 if (ok == 1) {
531 azx_dev->irq_pending = 0;
532 return ok;
533 } else if (ok == 0 && chip->bus && chip->bus->workq) {
534 /* bogus IRQ, process it later */
535 azx_dev->irq_pending = 1;
536 queue_work(chip->bus->workq, &hda->irq_pending_work);
537 }
538 return 0;
539 }
540
541 /*
542 * Check whether the current DMA position is acceptable for updating
543 * periods. Returns non-zero if it's OK.
544 *
545 * Many HD-audio controllers appear pretty inaccurate about
546 * the update-IRQ timing. The IRQ is issued before actually the
547 * data is processed. So, we need to process it afterwords in a
548 * workqueue.
549 */
550 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
551 {
552 struct snd_pcm_substream *substream = azx_dev->substream;
553 int stream = substream->stream;
554 u32 wallclk;
555 unsigned int pos;
556
557 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
558 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
559 return -1; /* bogus (too early) interrupt */
560
561 if (chip->get_position[stream])
562 pos = chip->get_position[stream](chip, azx_dev);
563 else { /* use the position buffer as default */
564 pos = azx_get_pos_posbuf(chip, azx_dev);
565 if (!pos || pos == (u32)-1) {
566 dev_info(chip->card->dev,
567 "Invalid position buffer, using LPIB read method instead.\n");
568 chip->get_position[stream] = azx_get_pos_lpib;
569 pos = azx_get_pos_lpib(chip, azx_dev);
570 chip->get_delay[stream] = NULL;
571 } else {
572 chip->get_position[stream] = azx_get_pos_posbuf;
573 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
574 chip->get_delay[stream] = azx_get_delay_from_lpib;
575 }
576 }
577
578 if (pos >= azx_dev->bufsize)
579 pos = 0;
580
581 if (WARN_ONCE(!azx_dev->period_bytes,
582 "hda-intel: zero azx_dev->period_bytes"))
583 return -1; /* this shouldn't happen! */
584 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
585 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
586 /* NG - it's below the first next period boundary */
587 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
588 azx_dev->start_wallclk += wallclk;
589 return 1; /* OK, it's fine */
590 }
591
592 /*
593 * The work for pending PCM period updates.
594 */
595 static void azx_irq_pending_work(struct work_struct *work)
596 {
597 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
598 struct azx *chip = &hda->chip;
599 int i, pending, ok;
600
601 if (!hda->irq_pending_warned) {
602 dev_info(chip->card->dev,
603 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
604 chip->card->number);
605 hda->irq_pending_warned = 1;
606 }
607
608 for (;;) {
609 pending = 0;
610 spin_lock_irq(&chip->reg_lock);
611 for (i = 0; i < chip->num_streams; i++) {
612 struct azx_dev *azx_dev = &chip->azx_dev[i];
613 if (!azx_dev->irq_pending ||
614 !azx_dev->substream ||
615 !azx_dev->running)
616 continue;
617 ok = azx_position_ok(chip, azx_dev);
618 if (ok > 0) {
619 azx_dev->irq_pending = 0;
620 spin_unlock(&chip->reg_lock);
621 snd_pcm_period_elapsed(azx_dev->substream);
622 spin_lock(&chip->reg_lock);
623 } else if (ok < 0) {
624 pending = 0; /* too early */
625 } else
626 pending++;
627 }
628 spin_unlock_irq(&chip->reg_lock);
629 if (!pending)
630 return;
631 msleep(1);
632 }
633 }
634
635 /* clear irq_pending flags and assure no on-going workq */
636 static void azx_clear_irq_pending(struct azx *chip)
637 {
638 int i;
639
640 spin_lock_irq(&chip->reg_lock);
641 for (i = 0; i < chip->num_streams; i++)
642 chip->azx_dev[i].irq_pending = 0;
643 spin_unlock_irq(&chip->reg_lock);
644 }
645
646 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
647 {
648 if (request_irq(chip->pci->irq, azx_interrupt,
649 chip->msi ? 0 : IRQF_SHARED,
650 KBUILD_MODNAME, chip)) {
651 dev_err(chip->card->dev,
652 "unable to grab IRQ %d, disabling device\n",
653 chip->pci->irq);
654 if (do_disconnect)
655 snd_card_disconnect(chip->card);
656 return -1;
657 }
658 chip->irq = chip->pci->irq;
659 pci_intx(chip->pci, !chip->msi);
660 return 0;
661 }
662
663 /* get the current DMA position with correction on VIA chips */
664 static unsigned int azx_via_get_position(struct azx *chip,
665 struct azx_dev *azx_dev)
666 {
667 unsigned int link_pos, mini_pos, bound_pos;
668 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
669 unsigned int fifo_size;
670
671 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
672 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
673 /* Playback, no problem using link position */
674 return link_pos;
675 }
676
677 /* Capture */
678 /* For new chipset,
679 * use mod to get the DMA position just like old chipset
680 */
681 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
682 mod_dma_pos %= azx_dev->period_bytes;
683
684 /* azx_dev->fifo_size can't get FIFO size of in stream.
685 * Get from base address + offset.
686 */
687 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
688
689 if (azx_dev->insufficient) {
690 /* Link position never gather than FIFO size */
691 if (link_pos <= fifo_size)
692 return 0;
693
694 azx_dev->insufficient = 0;
695 }
696
697 if (link_pos <= fifo_size)
698 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
699 else
700 mini_pos = link_pos - fifo_size;
701
702 /* Find nearest previous boudary */
703 mod_mini_pos = mini_pos % azx_dev->period_bytes;
704 mod_link_pos = link_pos % azx_dev->period_bytes;
705 if (mod_link_pos >= fifo_size)
706 bound_pos = link_pos - mod_link_pos;
707 else if (mod_dma_pos >= mod_mini_pos)
708 bound_pos = mini_pos - mod_mini_pos;
709 else {
710 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
711 if (bound_pos >= azx_dev->bufsize)
712 bound_pos = 0;
713 }
714
715 /* Calculate real DMA position we want */
716 return bound_pos + mod_dma_pos;
717 }
718
719 #ifdef CONFIG_PM
720 static DEFINE_MUTEX(card_list_lock);
721 static LIST_HEAD(card_list);
722
723 static void azx_add_card_list(struct azx *chip)
724 {
725 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
726 mutex_lock(&card_list_lock);
727 list_add(&hda->list, &card_list);
728 mutex_unlock(&card_list_lock);
729 }
730
731 static void azx_del_card_list(struct azx *chip)
732 {
733 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
734 mutex_lock(&card_list_lock);
735 list_del_init(&hda->list);
736 mutex_unlock(&card_list_lock);
737 }
738
739 /* trigger power-save check at writing parameter */
740 static int param_set_xint(const char *val, const struct kernel_param *kp)
741 {
742 struct hda_intel *hda;
743 struct azx *chip;
744 struct hda_codec *c;
745 int prev = power_save;
746 int ret = param_set_int(val, kp);
747
748 if (ret || prev == power_save)
749 return ret;
750
751 mutex_lock(&card_list_lock);
752 list_for_each_entry(hda, &card_list, list) {
753 chip = &hda->chip;
754 if (!chip->bus || chip->disabled)
755 continue;
756 list_for_each_entry(c, &chip->bus->codec_list, list)
757 snd_hda_power_sync(c);
758 }
759 mutex_unlock(&card_list_lock);
760 return 0;
761 }
762 #else
763 #define azx_add_card_list(chip) /* NOP */
764 #define azx_del_card_list(chip) /* NOP */
765 #endif /* CONFIG_PM */
766
767 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
768 /*
769 * power management
770 */
771 static int azx_suspend(struct device *dev)
772 {
773 struct pci_dev *pci = to_pci_dev(dev);
774 struct snd_card *card = dev_get_drvdata(dev);
775 struct azx *chip;
776 struct hda_intel *hda;
777 struct azx_pcm *p;
778
779 if (!card)
780 return 0;
781
782 chip = card->private_data;
783 hda = container_of(chip, struct hda_intel, chip);
784 if (chip->disabled || hda->init_failed)
785 return 0;
786
787 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
788 azx_clear_irq_pending(chip);
789 list_for_each_entry(p, &chip->pcm_list, list)
790 snd_pcm_suspend_all(p->pcm);
791 if (chip->initialized)
792 snd_hda_suspend(chip->bus);
793 azx_stop_chip(chip);
794 azx_enter_link_reset(chip);
795 if (chip->irq >= 0) {
796 free_irq(chip->irq, chip);
797 chip->irq = -1;
798 }
799
800 if (chip->msi)
801 pci_disable_msi(chip->pci);
802 pci_disable_device(pci);
803 pci_save_state(pci);
804 pci_set_power_state(pci, PCI_D3hot);
805 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
806 hda_display_power(false);
807 return 0;
808 }
809
810 static int azx_resume(struct device *dev)
811 {
812 struct pci_dev *pci = to_pci_dev(dev);
813 struct snd_card *card = dev_get_drvdata(dev);
814 struct azx *chip;
815 struct hda_intel *hda;
816
817 if (!card)
818 return 0;
819
820 chip = card->private_data;
821 hda = container_of(chip, struct hda_intel, chip);
822 if (chip->disabled || hda->init_failed)
823 return 0;
824
825 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
826 hda_display_power(true);
827 haswell_set_bclk(chip);
828 }
829 pci_set_power_state(pci, PCI_D0);
830 pci_restore_state(pci);
831 if (pci_enable_device(pci) < 0) {
832 dev_err(chip->card->dev,
833 "pci_enable_device failed, disabling device\n");
834 snd_card_disconnect(card);
835 return -EIO;
836 }
837 pci_set_master(pci);
838 if (chip->msi)
839 if (pci_enable_msi(pci) < 0)
840 chip->msi = 0;
841 if (azx_acquire_irq(chip, 1) < 0)
842 return -EIO;
843 azx_init_pci(chip);
844
845 azx_init_chip(chip, true);
846
847 snd_hda_resume(chip->bus);
848 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
849 return 0;
850 }
851 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
852
853 #ifdef CONFIG_PM_RUNTIME
854 static int azx_runtime_suspend(struct device *dev)
855 {
856 struct snd_card *card = dev_get_drvdata(dev);
857 struct azx *chip;
858 struct hda_intel *hda;
859
860 if (!card)
861 return 0;
862
863 chip = card->private_data;
864 hda = container_of(chip, struct hda_intel, chip);
865 if (chip->disabled || hda->init_failed)
866 return 0;
867
868 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
869 return 0;
870
871 /* enable controller wake up event */
872 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
873 STATESTS_INT_MASK);
874
875 azx_stop_chip(chip);
876 azx_enter_link_reset(chip);
877 azx_clear_irq_pending(chip);
878 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
879 hda_display_power(false);
880
881 return 0;
882 }
883
884 static int azx_runtime_resume(struct device *dev)
885 {
886 struct snd_card *card = dev_get_drvdata(dev);
887 struct azx *chip;
888 struct hda_intel *hda;
889 struct hda_bus *bus;
890 struct hda_codec *codec;
891 int status;
892
893 if (!card)
894 return 0;
895
896 chip = card->private_data;
897 hda = container_of(chip, struct hda_intel, chip);
898 if (chip->disabled || hda->init_failed)
899 return 0;
900
901 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
902 return 0;
903
904 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
905 hda_display_power(true);
906 haswell_set_bclk(chip);
907 }
908
909 /* Read STATESTS before controller reset */
910 status = azx_readw(chip, STATESTS);
911
912 azx_init_pci(chip);
913 azx_init_chip(chip, true);
914
915 bus = chip->bus;
916 if (status && bus) {
917 list_for_each_entry(codec, &bus->codec_list, list)
918 if (status & (1 << codec->addr))
919 queue_delayed_work(codec->bus->workq,
920 &codec->jackpoll_work, codec->jackpoll_interval);
921 }
922
923 /* disable controller Wake Up event*/
924 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
925 ~STATESTS_INT_MASK);
926
927 return 0;
928 }
929
930 static int azx_runtime_idle(struct device *dev)
931 {
932 struct snd_card *card = dev_get_drvdata(dev);
933 struct azx *chip;
934 struct hda_intel *hda;
935
936 if (!card)
937 return 0;
938
939 chip = card->private_data;
940 hda = container_of(chip, struct hda_intel, chip);
941 if (chip->disabled || hda->init_failed)
942 return 0;
943
944 if (!power_save_controller ||
945 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
946 return -EBUSY;
947
948 return 0;
949 }
950
951 #endif /* CONFIG_PM_RUNTIME */
952
953 #ifdef CONFIG_PM
954 static const struct dev_pm_ops azx_pm = {
955 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
956 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
957 };
958
959 #define AZX_PM_OPS &azx_pm
960 #else
961 #define AZX_PM_OPS NULL
962 #endif /* CONFIG_PM */
963
964
965 static int azx_probe_continue(struct azx *chip);
966
967 #ifdef SUPPORT_VGA_SWITCHEROO
968 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
969
970 static void azx_vs_set_state(struct pci_dev *pci,
971 enum vga_switcheroo_state state)
972 {
973 struct snd_card *card = pci_get_drvdata(pci);
974 struct azx *chip = card->private_data;
975 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
976 bool disabled;
977
978 wait_for_completion(&hda->probe_wait);
979 if (hda->init_failed)
980 return;
981
982 disabled = (state == VGA_SWITCHEROO_OFF);
983 if (chip->disabled == disabled)
984 return;
985
986 if (!chip->bus) {
987 chip->disabled = disabled;
988 if (!disabled) {
989 dev_info(chip->card->dev,
990 "Start delayed initialization\n");
991 if (azx_probe_continue(chip) < 0) {
992 dev_err(chip->card->dev, "initialization error\n");
993 hda->init_failed = true;
994 }
995 }
996 } else {
997 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
998 disabled ? "Disabling" : "Enabling");
999 if (disabled) {
1000 pm_runtime_put_sync_suspend(card->dev);
1001 azx_suspend(card->dev);
1002 /* when we get suspended by vga switcheroo we end up in D3cold,
1003 * however we have no ACPI handle, so pci/acpi can't put us there,
1004 * put ourselves there */
1005 pci->current_state = PCI_D3cold;
1006 chip->disabled = true;
1007 if (snd_hda_lock_devices(chip->bus))
1008 dev_warn(chip->card->dev,
1009 "Cannot lock devices!\n");
1010 } else {
1011 snd_hda_unlock_devices(chip->bus);
1012 pm_runtime_get_noresume(card->dev);
1013 chip->disabled = false;
1014 azx_resume(card->dev);
1015 }
1016 }
1017 }
1018
1019 static bool azx_vs_can_switch(struct pci_dev *pci)
1020 {
1021 struct snd_card *card = pci_get_drvdata(pci);
1022 struct azx *chip = card->private_data;
1023 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1024
1025 wait_for_completion(&hda->probe_wait);
1026 if (hda->init_failed)
1027 return false;
1028 if (chip->disabled || !chip->bus)
1029 return true;
1030 if (snd_hda_lock_devices(chip->bus))
1031 return false;
1032 snd_hda_unlock_devices(chip->bus);
1033 return true;
1034 }
1035
1036 static void init_vga_switcheroo(struct azx *chip)
1037 {
1038 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1039 struct pci_dev *p = get_bound_vga(chip->pci);
1040 if (p) {
1041 dev_info(chip->card->dev,
1042 "Handle VGA-switcheroo audio client\n");
1043 hda->use_vga_switcheroo = 1;
1044 pci_dev_put(p);
1045 }
1046 }
1047
1048 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1049 .set_gpu_state = azx_vs_set_state,
1050 .can_switch = azx_vs_can_switch,
1051 };
1052
1053 static int register_vga_switcheroo(struct azx *chip)
1054 {
1055 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1056 int err;
1057
1058 if (!hda->use_vga_switcheroo)
1059 return 0;
1060 /* FIXME: currently only handling DIS controller
1061 * is there any machine with two switchable HDMI audio controllers?
1062 */
1063 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1064 VGA_SWITCHEROO_DIS,
1065 chip->bus != NULL);
1066 if (err < 0)
1067 return err;
1068 hda->vga_switcheroo_registered = 1;
1069
1070 /* register as an optimus hdmi audio power domain */
1071 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1072 &hda->hdmi_pm_domain);
1073 return 0;
1074 }
1075 #else
1076 #define init_vga_switcheroo(chip) /* NOP */
1077 #define register_vga_switcheroo(chip) 0
1078 #define check_hdmi_disabled(pci) false
1079 #endif /* SUPPORT_VGA_SWITCHER */
1080
1081 /*
1082 * destructor
1083 */
1084 static int azx_free(struct azx *chip)
1085 {
1086 struct pci_dev *pci = chip->pci;
1087 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1088 int i;
1089
1090 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1091 && chip->running)
1092 pm_runtime_get_noresume(&pci->dev);
1093
1094 azx_del_card_list(chip);
1095
1096 azx_notifier_unregister(chip);
1097
1098 hda->init_failed = 1; /* to be sure */
1099 complete_all(&hda->probe_wait);
1100
1101 if (use_vga_switcheroo(hda)) {
1102 if (chip->disabled && chip->bus)
1103 snd_hda_unlock_devices(chip->bus);
1104 if (hda->vga_switcheroo_registered)
1105 vga_switcheroo_unregister_client(chip->pci);
1106 }
1107
1108 if (chip->initialized) {
1109 azx_clear_irq_pending(chip);
1110 for (i = 0; i < chip->num_streams; i++)
1111 azx_stream_stop(chip, &chip->azx_dev[i]);
1112 azx_stop_chip(chip);
1113 }
1114
1115 if (chip->irq >= 0)
1116 free_irq(chip->irq, (void*)chip);
1117 if (chip->msi)
1118 pci_disable_msi(chip->pci);
1119 if (chip->remap_addr)
1120 iounmap(chip->remap_addr);
1121
1122 azx_free_stream_pages(chip);
1123 if (chip->region_requested)
1124 pci_release_regions(chip->pci);
1125 pci_disable_device(chip->pci);
1126 kfree(chip->azx_dev);
1127 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1128 if (chip->fw)
1129 release_firmware(chip->fw);
1130 #endif
1131 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1132 hda_display_power(false);
1133 hda_i915_exit();
1134 }
1135 kfree(hda);
1136
1137 return 0;
1138 }
1139
1140 static int azx_dev_free(struct snd_device *device)
1141 {
1142 return azx_free(device->device_data);
1143 }
1144
1145 #ifdef SUPPORT_VGA_SWITCHEROO
1146 /*
1147 * Check of disabled HDMI controller by vga-switcheroo
1148 */
1149 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1150 {
1151 struct pci_dev *p;
1152
1153 /* check only discrete GPU */
1154 switch (pci->vendor) {
1155 case PCI_VENDOR_ID_ATI:
1156 case PCI_VENDOR_ID_AMD:
1157 case PCI_VENDOR_ID_NVIDIA:
1158 if (pci->devfn == 1) {
1159 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1160 pci->bus->number, 0);
1161 if (p) {
1162 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1163 return p;
1164 pci_dev_put(p);
1165 }
1166 }
1167 break;
1168 }
1169 return NULL;
1170 }
1171
1172 static bool check_hdmi_disabled(struct pci_dev *pci)
1173 {
1174 bool vga_inactive = false;
1175 struct pci_dev *p = get_bound_vga(pci);
1176
1177 if (p) {
1178 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1179 vga_inactive = true;
1180 pci_dev_put(p);
1181 }
1182 return vga_inactive;
1183 }
1184 #endif /* SUPPORT_VGA_SWITCHEROO */
1185
1186 /*
1187 * white/black-listing for position_fix
1188 */
1189 static struct snd_pci_quirk position_fix_list[] = {
1190 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1191 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1192 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1193 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1194 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1195 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1196 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1197 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1198 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1199 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1200 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1201 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1202 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1203 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1204 {}
1205 };
1206
1207 static int check_position_fix(struct azx *chip, int fix)
1208 {
1209 const struct snd_pci_quirk *q;
1210
1211 switch (fix) {
1212 case POS_FIX_AUTO:
1213 case POS_FIX_LPIB:
1214 case POS_FIX_POSBUF:
1215 case POS_FIX_VIACOMBO:
1216 case POS_FIX_COMBO:
1217 return fix;
1218 }
1219
1220 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1221 if (q) {
1222 dev_info(chip->card->dev,
1223 "position_fix set to %d for device %04x:%04x\n",
1224 q->value, q->subvendor, q->subdevice);
1225 return q->value;
1226 }
1227
1228 /* Check VIA/ATI HD Audio Controller exist */
1229 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1230 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1231 return POS_FIX_VIACOMBO;
1232 }
1233 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1234 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1235 return POS_FIX_LPIB;
1236 }
1237 return POS_FIX_AUTO;
1238 }
1239
1240 static void assign_position_fix(struct azx *chip, int fix)
1241 {
1242 static azx_get_pos_callback_t callbacks[] = {
1243 [POS_FIX_AUTO] = NULL,
1244 [POS_FIX_LPIB] = azx_get_pos_lpib,
1245 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1246 [POS_FIX_VIACOMBO] = azx_via_get_position,
1247 [POS_FIX_COMBO] = azx_get_pos_lpib,
1248 };
1249
1250 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1251
1252 /* combo mode uses LPIB only for playback */
1253 if (fix == POS_FIX_COMBO)
1254 chip->get_position[1] = NULL;
1255
1256 if (fix == POS_FIX_POSBUF &&
1257 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1258 chip->get_delay[0] = chip->get_delay[1] =
1259 azx_get_delay_from_lpib;
1260 }
1261
1262 }
1263
1264 /*
1265 * black-lists for probe_mask
1266 */
1267 static struct snd_pci_quirk probe_mask_list[] = {
1268 /* Thinkpad often breaks the controller communication when accessing
1269 * to the non-working (or non-existing) modem codec slot.
1270 */
1271 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1272 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1273 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1274 /* broken BIOS */
1275 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1276 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1277 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1278 /* forced codec slots */
1279 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1280 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1281 /* WinFast VP200 H (Teradici) user reported broken communication */
1282 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1283 {}
1284 };
1285
1286 #define AZX_FORCE_CODEC_MASK 0x100
1287
1288 static void check_probe_mask(struct azx *chip, int dev)
1289 {
1290 const struct snd_pci_quirk *q;
1291
1292 chip->codec_probe_mask = probe_mask[dev];
1293 if (chip->codec_probe_mask == -1) {
1294 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1295 if (q) {
1296 dev_info(chip->card->dev,
1297 "probe_mask set to 0x%x for device %04x:%04x\n",
1298 q->value, q->subvendor, q->subdevice);
1299 chip->codec_probe_mask = q->value;
1300 }
1301 }
1302
1303 /* check forced option */
1304 if (chip->codec_probe_mask != -1 &&
1305 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1306 chip->codec_mask = chip->codec_probe_mask & 0xff;
1307 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1308 chip->codec_mask);
1309 }
1310 }
1311
1312 /*
1313 * white/black-list for enable_msi
1314 */
1315 static struct snd_pci_quirk msi_black_list[] = {
1316 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1317 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1318 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1319 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1320 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1321 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1322 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1323 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1324 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1325 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1326 {}
1327 };
1328
1329 static void check_msi(struct azx *chip)
1330 {
1331 const struct snd_pci_quirk *q;
1332
1333 if (enable_msi >= 0) {
1334 chip->msi = !!enable_msi;
1335 return;
1336 }
1337 chip->msi = 1; /* enable MSI as default */
1338 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1339 if (q) {
1340 dev_info(chip->card->dev,
1341 "msi for device %04x:%04x set to %d\n",
1342 q->subvendor, q->subdevice, q->value);
1343 chip->msi = q->value;
1344 return;
1345 }
1346
1347 /* NVidia chipsets seem to cause troubles with MSI */
1348 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1349 dev_info(chip->card->dev, "Disabling MSI\n");
1350 chip->msi = 0;
1351 }
1352 }
1353
1354 /* check the snoop mode availability */
1355 static void azx_check_snoop_available(struct azx *chip)
1356 {
1357 bool snoop = chip->snoop;
1358
1359 switch (chip->driver_type) {
1360 case AZX_DRIVER_VIA:
1361 /* force to non-snoop mode for a new VIA controller
1362 * when BIOS is set
1363 */
1364 if (snoop) {
1365 u8 val;
1366 pci_read_config_byte(chip->pci, 0x42, &val);
1367 if (!(val & 0x80) && chip->pci->revision == 0x30)
1368 snoop = false;
1369 }
1370 break;
1371 case AZX_DRIVER_ATIHDMI_NS:
1372 /* new ATI HDMI requires non-snoop */
1373 snoop = false;
1374 break;
1375 case AZX_DRIVER_CTHDA:
1376 snoop = false;
1377 break;
1378 }
1379
1380 if (snoop != chip->snoop) {
1381 dev_info(chip->card->dev, "Force to %s mode\n",
1382 snoop ? "snoop" : "non-snoop");
1383 chip->snoop = snoop;
1384 }
1385 }
1386
1387 static void azx_probe_work(struct work_struct *work)
1388 {
1389 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1390 azx_probe_continue(&hda->chip);
1391 }
1392
1393 /*
1394 * constructor
1395 */
1396 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1397 int dev, unsigned int driver_caps,
1398 const struct hda_controller_ops *hda_ops,
1399 struct azx **rchip)
1400 {
1401 static struct snd_device_ops ops = {
1402 .dev_free = azx_dev_free,
1403 };
1404 struct hda_intel *hda;
1405 struct azx *chip;
1406 int err;
1407
1408 *rchip = NULL;
1409
1410 err = pci_enable_device(pci);
1411 if (err < 0)
1412 return err;
1413
1414 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1415 if (!hda) {
1416 dev_err(card->dev, "Cannot allocate hda\n");
1417 pci_disable_device(pci);
1418 return -ENOMEM;
1419 }
1420
1421 chip = &hda->chip;
1422 spin_lock_init(&chip->reg_lock);
1423 mutex_init(&chip->open_mutex);
1424 chip->card = card;
1425 chip->pci = pci;
1426 chip->ops = hda_ops;
1427 chip->irq = -1;
1428 chip->driver_caps = driver_caps;
1429 chip->driver_type = driver_caps & 0xff;
1430 check_msi(chip);
1431 chip->dev_index = dev;
1432 chip->jackpoll_ms = jackpoll_ms;
1433 INIT_LIST_HEAD(&chip->pcm_list);
1434 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1435 INIT_LIST_HEAD(&hda->list);
1436 init_vga_switcheroo(chip);
1437 init_completion(&hda->probe_wait);
1438
1439 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1440
1441 check_probe_mask(chip, dev);
1442
1443 chip->single_cmd = single_cmd;
1444 chip->snoop = hda_snoop;
1445 azx_check_snoop_available(chip);
1446
1447 if (bdl_pos_adj[dev] < 0) {
1448 switch (chip->driver_type) {
1449 case AZX_DRIVER_ICH:
1450 case AZX_DRIVER_PCH:
1451 bdl_pos_adj[dev] = 1;
1452 break;
1453 default:
1454 bdl_pos_adj[dev] = 32;
1455 break;
1456 }
1457 }
1458 chip->bdl_pos_adj = bdl_pos_adj;
1459
1460 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1461 if (err < 0) {
1462 dev_err(card->dev, "Error creating device [card]!\n");
1463 azx_free(chip);
1464 return err;
1465 }
1466
1467 /* continue probing in work context as may trigger request module */
1468 INIT_WORK(&hda->probe_work, azx_probe_work);
1469
1470 *rchip = chip;
1471
1472 return 0;
1473 }
1474
1475 static int azx_first_init(struct azx *chip)
1476 {
1477 int dev = chip->dev_index;
1478 struct pci_dev *pci = chip->pci;
1479 struct snd_card *card = chip->card;
1480 int err;
1481 unsigned short gcap;
1482
1483 #if BITS_PER_LONG != 64
1484 /* Fix up base address on ULI M5461 */
1485 if (chip->driver_type == AZX_DRIVER_ULI) {
1486 u16 tmp3;
1487 pci_read_config_word(pci, 0x40, &tmp3);
1488 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1489 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1490 }
1491 #endif
1492
1493 err = pci_request_regions(pci, "ICH HD audio");
1494 if (err < 0)
1495 return err;
1496 chip->region_requested = 1;
1497
1498 chip->addr = pci_resource_start(pci, 0);
1499 chip->remap_addr = pci_ioremap_bar(pci, 0);
1500 if (chip->remap_addr == NULL) {
1501 dev_err(card->dev, "ioremap error\n");
1502 return -ENXIO;
1503 }
1504
1505 if (chip->msi)
1506 if (pci_enable_msi(pci) < 0)
1507 chip->msi = 0;
1508
1509 if (azx_acquire_irq(chip, 0) < 0)
1510 return -EBUSY;
1511
1512 pci_set_master(pci);
1513 synchronize_irq(chip->irq);
1514
1515 gcap = azx_readw(chip, GCAP);
1516 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1517
1518 /* disable SB600 64bit support for safety */
1519 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1520 struct pci_dev *p_smbus;
1521 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1522 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1523 NULL);
1524 if (p_smbus) {
1525 if (p_smbus->revision < 0x30)
1526 gcap &= ~AZX_GCAP_64OK;
1527 pci_dev_put(p_smbus);
1528 }
1529 }
1530
1531 /* disable 64bit DMA address on some devices */
1532 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1533 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1534 gcap &= ~AZX_GCAP_64OK;
1535 }
1536
1537 /* disable buffer size rounding to 128-byte multiples if supported */
1538 if (align_buffer_size >= 0)
1539 chip->align_buffer_size = !!align_buffer_size;
1540 else {
1541 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1542 chip->align_buffer_size = 0;
1543 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1544 chip->align_buffer_size = 1;
1545 else
1546 chip->align_buffer_size = 1;
1547 }
1548
1549 /* allow 64bit DMA address if supported by H/W */
1550 if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
1551 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
1552 else {
1553 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1554 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1555 }
1556
1557 /* read number of streams from GCAP register instead of using
1558 * hardcoded value
1559 */
1560 chip->capture_streams = (gcap >> 8) & 0x0f;
1561 chip->playback_streams = (gcap >> 12) & 0x0f;
1562 if (!chip->playback_streams && !chip->capture_streams) {
1563 /* gcap didn't give any info, switching to old method */
1564
1565 switch (chip->driver_type) {
1566 case AZX_DRIVER_ULI:
1567 chip->playback_streams = ULI_NUM_PLAYBACK;
1568 chip->capture_streams = ULI_NUM_CAPTURE;
1569 break;
1570 case AZX_DRIVER_ATIHDMI:
1571 case AZX_DRIVER_ATIHDMI_NS:
1572 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1573 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1574 break;
1575 case AZX_DRIVER_GENERIC:
1576 default:
1577 chip->playback_streams = ICH6_NUM_PLAYBACK;
1578 chip->capture_streams = ICH6_NUM_CAPTURE;
1579 break;
1580 }
1581 }
1582 chip->capture_index_offset = 0;
1583 chip->playback_index_offset = chip->capture_streams;
1584 chip->num_streams = chip->playback_streams + chip->capture_streams;
1585 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1586 GFP_KERNEL);
1587 if (!chip->azx_dev) {
1588 dev_err(card->dev, "cannot malloc azx_dev\n");
1589 return -ENOMEM;
1590 }
1591
1592 err = azx_alloc_stream_pages(chip);
1593 if (err < 0)
1594 return err;
1595
1596 /* initialize streams */
1597 azx_init_stream(chip);
1598
1599 /* initialize chip */
1600 azx_init_pci(chip);
1601
1602 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1603 haswell_set_bclk(chip);
1604
1605 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1606
1607 /* codec detection */
1608 if (!chip->codec_mask) {
1609 dev_err(card->dev, "no codecs found!\n");
1610 return -ENODEV;
1611 }
1612
1613 strcpy(card->driver, "HDA-Intel");
1614 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1615 sizeof(card->shortname));
1616 snprintf(card->longname, sizeof(card->longname),
1617 "%s at 0x%lx irq %i",
1618 card->shortname, chip->addr, chip->irq);
1619
1620 return 0;
1621 }
1622
1623 static void power_down_all_codecs(struct azx *chip)
1624 {
1625 #ifdef CONFIG_PM
1626 /* The codecs were powered up in snd_hda_codec_new().
1627 * Now all initialization done, so turn them down if possible
1628 */
1629 struct hda_codec *codec;
1630 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1631 snd_hda_power_down(codec);
1632 }
1633 #endif
1634 }
1635
1636 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1637 /* callback from request_firmware_nowait() */
1638 static void azx_firmware_cb(const struct firmware *fw, void *context)
1639 {
1640 struct snd_card *card = context;
1641 struct azx *chip = card->private_data;
1642 struct pci_dev *pci = chip->pci;
1643
1644 if (!fw) {
1645 dev_err(card->dev, "Cannot load firmware, aborting\n");
1646 goto error;
1647 }
1648
1649 chip->fw = fw;
1650 if (!chip->disabled) {
1651 /* continue probing */
1652 if (azx_probe_continue(chip))
1653 goto error;
1654 }
1655 return; /* OK */
1656
1657 error:
1658 snd_card_free(card);
1659 pci_set_drvdata(pci, NULL);
1660 }
1661 #endif
1662
1663 /*
1664 * HDA controller ops.
1665 */
1666
1667 /* PCI register access. */
1668 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1669 {
1670 writel(value, addr);
1671 }
1672
1673 static u32 pci_azx_readl(u32 __iomem *addr)
1674 {
1675 return readl(addr);
1676 }
1677
1678 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1679 {
1680 writew(value, addr);
1681 }
1682
1683 static u16 pci_azx_readw(u16 __iomem *addr)
1684 {
1685 return readw(addr);
1686 }
1687
1688 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1689 {
1690 writeb(value, addr);
1691 }
1692
1693 static u8 pci_azx_readb(u8 __iomem *addr)
1694 {
1695 return readb(addr);
1696 }
1697
1698 static int disable_msi_reset_irq(struct azx *chip)
1699 {
1700 int err;
1701
1702 free_irq(chip->irq, chip);
1703 chip->irq = -1;
1704 pci_disable_msi(chip->pci);
1705 chip->msi = 0;
1706 err = azx_acquire_irq(chip, 1);
1707 if (err < 0)
1708 return err;
1709
1710 return 0;
1711 }
1712
1713 /* DMA page allocation helpers. */
1714 static int dma_alloc_pages(struct azx *chip,
1715 int type,
1716 size_t size,
1717 struct snd_dma_buffer *buf)
1718 {
1719 int err;
1720
1721 err = snd_dma_alloc_pages(type,
1722 chip->card->dev,
1723 size, buf);
1724 if (err < 0)
1725 return err;
1726 mark_pages_wc(chip, buf, true);
1727 return 0;
1728 }
1729
1730 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1731 {
1732 mark_pages_wc(chip, buf, false);
1733 snd_dma_free_pages(buf);
1734 }
1735
1736 static int substream_alloc_pages(struct azx *chip,
1737 struct snd_pcm_substream *substream,
1738 size_t size)
1739 {
1740 struct azx_dev *azx_dev = get_azx_dev(substream);
1741 int ret;
1742
1743 mark_runtime_wc(chip, azx_dev, substream, false);
1744 azx_dev->bufsize = 0;
1745 azx_dev->period_bytes = 0;
1746 azx_dev->format_val = 0;
1747 ret = snd_pcm_lib_malloc_pages(substream, size);
1748 if (ret < 0)
1749 return ret;
1750 mark_runtime_wc(chip, azx_dev, substream, true);
1751 return 0;
1752 }
1753
1754 static int substream_free_pages(struct azx *chip,
1755 struct snd_pcm_substream *substream)
1756 {
1757 struct azx_dev *azx_dev = get_azx_dev(substream);
1758 mark_runtime_wc(chip, azx_dev, substream, false);
1759 return snd_pcm_lib_free_pages(substream);
1760 }
1761
1762 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1763 struct vm_area_struct *area)
1764 {
1765 #ifdef CONFIG_X86
1766 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1767 struct azx *chip = apcm->chip;
1768 if (!azx_snoop(chip))
1769 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1770 #endif
1771 }
1772
1773 static const struct hda_controller_ops pci_hda_ops = {
1774 .reg_writel = pci_azx_writel,
1775 .reg_readl = pci_azx_readl,
1776 .reg_writew = pci_azx_writew,
1777 .reg_readw = pci_azx_readw,
1778 .reg_writeb = pci_azx_writeb,
1779 .reg_readb = pci_azx_readb,
1780 .disable_msi_reset_irq = disable_msi_reset_irq,
1781 .dma_alloc_pages = dma_alloc_pages,
1782 .dma_free_pages = dma_free_pages,
1783 .substream_alloc_pages = substream_alloc_pages,
1784 .substream_free_pages = substream_free_pages,
1785 .pcm_mmap_prepare = pcm_mmap_prepare,
1786 .position_check = azx_position_check,
1787 };
1788
1789 static int azx_probe(struct pci_dev *pci,
1790 const struct pci_device_id *pci_id)
1791 {
1792 static int dev;
1793 struct snd_card *card;
1794 struct hda_intel *hda;
1795 struct azx *chip;
1796 bool schedule_probe;
1797 int err;
1798
1799 if (dev >= SNDRV_CARDS)
1800 return -ENODEV;
1801 if (!enable[dev]) {
1802 dev++;
1803 return -ENOENT;
1804 }
1805
1806 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1807 0, &card);
1808 if (err < 0) {
1809 dev_err(&pci->dev, "Error creating card!\n");
1810 return err;
1811 }
1812
1813 err = azx_create(card, pci, dev, pci_id->driver_data,
1814 &pci_hda_ops, &chip);
1815 if (err < 0)
1816 goto out_free;
1817 card->private_data = chip;
1818 hda = container_of(chip, struct hda_intel, chip);
1819
1820 pci_set_drvdata(pci, card);
1821
1822 err = register_vga_switcheroo(chip);
1823 if (err < 0) {
1824 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1825 goto out_free;
1826 }
1827
1828 if (check_hdmi_disabled(pci)) {
1829 dev_info(card->dev, "VGA controller is disabled\n");
1830 dev_info(card->dev, "Delaying initialization\n");
1831 chip->disabled = true;
1832 }
1833
1834 schedule_probe = !chip->disabled;
1835
1836 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1837 if (patch[dev] && *patch[dev]) {
1838 dev_info(card->dev, "Applying patch firmware '%s'\n",
1839 patch[dev]);
1840 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1841 &pci->dev, GFP_KERNEL, card,
1842 azx_firmware_cb);
1843 if (err < 0)
1844 goto out_free;
1845 schedule_probe = false; /* continued in azx_firmware_cb() */
1846 }
1847 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1848
1849 #ifndef CONFIG_SND_HDA_I915
1850 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1851 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1852 #endif
1853
1854 if (schedule_probe)
1855 schedule_work(&hda->probe_work);
1856
1857 dev++;
1858 if (chip->disabled)
1859 complete_all(&hda->probe_wait);
1860 return 0;
1861
1862 out_free:
1863 snd_card_free(card);
1864 return err;
1865 }
1866
1867 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1868 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1869 [AZX_DRIVER_NVIDIA] = 8,
1870 [AZX_DRIVER_TERA] = 1,
1871 };
1872
1873 static int azx_probe_continue(struct azx *chip)
1874 {
1875 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1876 struct pci_dev *pci = chip->pci;
1877 int dev = chip->dev_index;
1878 int err;
1879
1880 /* Request power well for Haswell HDA controller and codec */
1881 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1882 #ifdef CONFIG_SND_HDA_I915
1883 err = hda_i915_init();
1884 if (err < 0) {
1885 dev_err(chip->card->dev,
1886 "Error request power-well from i915\n");
1887 goto out_free;
1888 }
1889 err = hda_display_power(true);
1890 if (err < 0) {
1891 dev_err(chip->card->dev,
1892 "Cannot turn on display power on i915\n");
1893 goto out_free;
1894 }
1895 #endif
1896 }
1897
1898 err = azx_first_init(chip);
1899 if (err < 0)
1900 goto out_free;
1901
1902 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1903 chip->beep_mode = beep_mode[dev];
1904 #endif
1905
1906 /* create codec instances */
1907 err = azx_codec_create(chip, model[dev],
1908 azx_max_codecs[chip->driver_type],
1909 power_save_addr);
1910
1911 if (err < 0)
1912 goto out_free;
1913 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1914 if (chip->fw) {
1915 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1916 chip->fw->data);
1917 if (err < 0)
1918 goto out_free;
1919 #ifndef CONFIG_PM
1920 release_firmware(chip->fw); /* no longer needed */
1921 chip->fw = NULL;
1922 #endif
1923 }
1924 #endif
1925 if ((probe_only[dev] & 1) == 0) {
1926 err = azx_codec_configure(chip);
1927 if (err < 0)
1928 goto out_free;
1929 }
1930
1931 /* create PCM streams */
1932 err = snd_hda_build_pcms(chip->bus);
1933 if (err < 0)
1934 goto out_free;
1935
1936 /* create mixer controls */
1937 err = azx_mixer_create(chip);
1938 if (err < 0)
1939 goto out_free;
1940
1941 err = snd_card_register(chip->card);
1942 if (err < 0)
1943 goto out_free;
1944
1945 chip->running = 1;
1946 power_down_all_codecs(chip);
1947 azx_notifier_register(chip);
1948 azx_add_card_list(chip);
1949 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
1950 pm_runtime_put_noidle(&pci->dev);
1951
1952 out_free:
1953 if (err < 0)
1954 hda->init_failed = 1;
1955 complete_all(&hda->probe_wait);
1956 return err;
1957 }
1958
1959 static void azx_remove(struct pci_dev *pci)
1960 {
1961 struct snd_card *card = pci_get_drvdata(pci);
1962
1963 if (card)
1964 snd_card_free(card);
1965 }
1966
1967 /* PCI IDs */
1968 static const struct pci_device_id azx_ids[] = {
1969 /* CPT */
1970 { PCI_DEVICE(0x8086, 0x1c20),
1971 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1972 /* PBG */
1973 { PCI_DEVICE(0x8086, 0x1d20),
1974 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1975 /* Panther Point */
1976 { PCI_DEVICE(0x8086, 0x1e20),
1977 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1978 /* Lynx Point */
1979 { PCI_DEVICE(0x8086, 0x8c20),
1980 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1981 /* 9 Series */
1982 { PCI_DEVICE(0x8086, 0x8ca0),
1983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1984 /* Wellsburg */
1985 { PCI_DEVICE(0x8086, 0x8d20),
1986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1987 { PCI_DEVICE(0x8086, 0x8d21),
1988 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1989 /* Lynx Point-LP */
1990 { PCI_DEVICE(0x8086, 0x9c20),
1991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1992 /* Lynx Point-LP */
1993 { PCI_DEVICE(0x8086, 0x9c21),
1994 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1995 /* Wildcat Point-LP */
1996 { PCI_DEVICE(0x8086, 0x9ca0),
1997 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1998 /* Haswell */
1999 { PCI_DEVICE(0x8086, 0x0a0c),
2000 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2001 { PCI_DEVICE(0x8086, 0x0c0c),
2002 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2003 { PCI_DEVICE(0x8086, 0x0d0c),
2004 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2005 /* Broadwell */
2006 { PCI_DEVICE(0x8086, 0x160c),
2007 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2008 /* 5 Series/3400 */
2009 { PCI_DEVICE(0x8086, 0x3b56),
2010 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2011 /* Poulsbo */
2012 { PCI_DEVICE(0x8086, 0x811b),
2013 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2014 /* Oaktrail */
2015 { PCI_DEVICE(0x8086, 0x080a),
2016 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2017 /* BayTrail */
2018 { PCI_DEVICE(0x8086, 0x0f04),
2019 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2020 /* Braswell */
2021 { PCI_DEVICE(0x8086, 0x2284),
2022 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2023 /* ICH */
2024 { PCI_DEVICE(0x8086, 0x2668),
2025 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2026 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2027 { PCI_DEVICE(0x8086, 0x27d8),
2028 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2029 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2030 { PCI_DEVICE(0x8086, 0x269a),
2031 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2032 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2033 { PCI_DEVICE(0x8086, 0x284b),
2034 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2035 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2036 { PCI_DEVICE(0x8086, 0x293e),
2037 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2038 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2039 { PCI_DEVICE(0x8086, 0x293f),
2040 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2041 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2042 { PCI_DEVICE(0x8086, 0x3a3e),
2043 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2044 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2045 { PCI_DEVICE(0x8086, 0x3a6e),
2046 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2047 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2048 /* Generic Intel */
2049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2050 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2051 .class_mask = 0xffffff,
2052 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2053 /* ATI SB 450/600/700/800/900 */
2054 { PCI_DEVICE(0x1002, 0x437b),
2055 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2056 { PCI_DEVICE(0x1002, 0x4383),
2057 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2058 /* AMD Hudson */
2059 { PCI_DEVICE(0x1022, 0x780d),
2060 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2061 /* ATI HDMI */
2062 { PCI_DEVICE(0x1002, 0x793b),
2063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2064 { PCI_DEVICE(0x1002, 0x7919),
2065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2066 { PCI_DEVICE(0x1002, 0x960f),
2067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2068 { PCI_DEVICE(0x1002, 0x970f),
2069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2070 { PCI_DEVICE(0x1002, 0xaa00),
2071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2072 { PCI_DEVICE(0x1002, 0xaa08),
2073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2074 { PCI_DEVICE(0x1002, 0xaa10),
2075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2076 { PCI_DEVICE(0x1002, 0xaa18),
2077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2078 { PCI_DEVICE(0x1002, 0xaa20),
2079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2080 { PCI_DEVICE(0x1002, 0xaa28),
2081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2082 { PCI_DEVICE(0x1002, 0xaa30),
2083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2084 { PCI_DEVICE(0x1002, 0xaa38),
2085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2086 { PCI_DEVICE(0x1002, 0xaa40),
2087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2088 { PCI_DEVICE(0x1002, 0xaa48),
2089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2090 { PCI_DEVICE(0x1002, 0xaa50),
2091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2092 { PCI_DEVICE(0x1002, 0xaa58),
2093 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2094 { PCI_DEVICE(0x1002, 0xaa60),
2095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2096 { PCI_DEVICE(0x1002, 0xaa68),
2097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2098 { PCI_DEVICE(0x1002, 0xaa80),
2099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2100 { PCI_DEVICE(0x1002, 0xaa88),
2101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2102 { PCI_DEVICE(0x1002, 0xaa90),
2103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2104 { PCI_DEVICE(0x1002, 0xaa98),
2105 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2106 { PCI_DEVICE(0x1002, 0x9902),
2107 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2108 { PCI_DEVICE(0x1002, 0xaaa0),
2109 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2110 { PCI_DEVICE(0x1002, 0xaaa8),
2111 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2112 { PCI_DEVICE(0x1002, 0xaab0),
2113 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2114 /* VIA VT8251/VT8237A */
2115 { PCI_DEVICE(0x1106, 0x3288),
2116 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2117 /* VIA GFX VT7122/VX900 */
2118 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2119 /* VIA GFX VT6122/VX11 */
2120 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2121 /* SIS966 */
2122 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2123 /* ULI M5461 */
2124 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2125 /* NVIDIA MCP */
2126 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2127 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2128 .class_mask = 0xffffff,
2129 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2130 /* Teradici */
2131 { PCI_DEVICE(0x6549, 0x1200),
2132 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2133 { PCI_DEVICE(0x6549, 0x2200),
2134 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2135 /* Creative X-Fi (CA0110-IBG) */
2136 /* CTHDA chips */
2137 { PCI_DEVICE(0x1102, 0x0010),
2138 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2139 { PCI_DEVICE(0x1102, 0x0012),
2140 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2141 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2142 /* the following entry conflicts with snd-ctxfi driver,
2143 * as ctxfi driver mutates from HD-audio to native mode with
2144 * a special command sequence.
2145 */
2146 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2147 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2148 .class_mask = 0xffffff,
2149 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2150 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2151 #else
2152 /* this entry seems still valid -- i.e. without emu20kx chip */
2153 { PCI_DEVICE(0x1102, 0x0009),
2154 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2155 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2156 #endif
2157 /* Vortex86MX */
2158 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2159 /* VMware HDAudio */
2160 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2161 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2162 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2163 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2164 .class_mask = 0xffffff,
2165 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2166 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2167 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2168 .class_mask = 0xffffff,
2169 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2170 { 0, }
2171 };
2172 MODULE_DEVICE_TABLE(pci, azx_ids);
2173
2174 /* pci_driver definition */
2175 static struct pci_driver azx_driver = {
2176 .name = KBUILD_MODNAME,
2177 .id_table = azx_ids,
2178 .probe = azx_probe,
2179 .remove = azx_remove,
2180 .driver = {
2181 .pm = AZX_PM_OPS,
2182 },
2183 };
2184
2185 module_pci_driver(azx_driver);
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