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Merge tag 'sound-fix-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_SCH_HDA_DEVC 0x78
94 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96 /* Define IN stream 0 FIFO size offset in VIA controller */
97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98 /* Define VIA HD Audio Device ID*/
99 #define VIA_HDAC_DEVICE_ID 0x3288
100
101 /* max number of SDs */
102 /* ICH, ATI and VIA have 4 playback and 4 capture */
103 #define ICH6_NUM_CAPTURE 4
104 #define ICH6_NUM_PLAYBACK 4
105
106 /* ULI has 6 playback and 5 capture */
107 #define ULI_NUM_CAPTURE 5
108 #define ULI_NUM_PLAYBACK 6
109
110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
111 #define ATIHDMI_NUM_CAPTURE 0
112 #define ATIHDMI_NUM_PLAYBACK 8
113
114 /* TERA has 4 playback and 3 capture */
115 #define TERA_NUM_CAPTURE 3
116 #define TERA_NUM_PLAYBACK 4
117
118
119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
122 static char *model[SNDRV_CARDS];
123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int probe_only[SNDRV_CARDS];
127 static int jackpoll_ms[SNDRV_CARDS];
128 static bool single_cmd;
129 static int enable_msi = -1;
130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
131 static char *patch[SNDRV_CARDS];
132 #endif
133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136 #endif
137
138 module_param_array(index, int, NULL, 0444);
139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
140 module_param_array(id, charp, NULL, 0444);
141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
142 module_param_array(enable, bool, NULL, 0444);
143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144 module_param_array(model, charp, NULL, 0444);
145 MODULE_PARM_DESC(model, "Use the given board model.");
146 module_param_array(position_fix, int, NULL, 0444);
147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
149 module_param_array(bdl_pos_adj, int, NULL, 0644);
150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
151 module_param_array(probe_mask, int, NULL, 0444);
152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
153 module_param_array(probe_only, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
155 module_param_array(jackpoll_ms, int, NULL, 0444);
156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
157 module_param(single_cmd, bool, 0444);
158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
160 module_param(enable_msi, bint, 0444);
161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
163 module_param_array(patch, charp, NULL, 0444);
164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165 #endif
166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
167 module_param_array(beep_mode, bool, NULL, 0444);
168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
169 "(0=off, 1=on) (default=1).");
170 #endif
171
172 #ifdef CONFIG_PM
173 static int param_set_xint(const char *val, const struct kernel_param *kp);
174 static const struct kernel_param_ops param_ops_xint = {
175 .set = param_set_xint,
176 .get = param_get_int,
177 };
178 #define param_check_xint param_check_int
179
180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
181 module_param(power_save, xint, 0644);
182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
213 "{Intel, ICH7},"
214 "{Intel, ESB2},"
215 "{Intel, ICH8},"
216 "{Intel, ICH9},"
217 "{Intel, ICH10},"
218 "{Intel, PCH},"
219 "{Intel, CPT},"
220 "{Intel, PPT},"
221 "{Intel, LPT},"
222 "{Intel, LPT_LP},"
223 "{Intel, WPT_LP},"
224 "{Intel, SPT},"
225 "{Intel, SPT_LP},"
226 "{Intel, HPT},"
227 "{Intel, PBG},"
228 "{Intel, SCH},"
229 "{ATI, SB450},"
230 "{ATI, SB600},"
231 "{ATI, RS600},"
232 "{ATI, RS690},"
233 "{ATI, RS780},"
234 "{ATI, R600},"
235 "{ATI, RV630},"
236 "{ATI, RV610},"
237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
241 "{VIA, VT8251},"
242 "{VIA, VT8237A},"
243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252
253
254 /*
255 */
256
257 /* driver types */
258 enum {
259 AZX_DRIVER_ICH,
260 AZX_DRIVER_PCH,
261 AZX_DRIVER_SCH,
262 AZX_DRIVER_HDMI,
263 AZX_DRIVER_ATI,
264 AZX_DRIVER_ATIHDMI,
265 AZX_DRIVER_ATIHDMI_NS,
266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
269 AZX_DRIVER_NVIDIA,
270 AZX_DRIVER_TERA,
271 AZX_DRIVER_CTX,
272 AZX_DRIVER_CTHDA,
273 AZX_DRIVER_CMEDIA,
274 AZX_DRIVER_GENERIC,
275 AZX_NUM_DRIVERS, /* keep this as last entry */
276 };
277
278 #define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
282 /* quirks for old Intel chipsets */
283 #define AZX_DCAPS_INTEL_ICH \
284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
285
286 /* quirks for Intel PCH */
287 #define AZX_DCAPS_INTEL_PCH_NOPM \
288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
290
291 #define AZX_DCAPS_INTEL_PCH \
292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
293
294 #define AZX_DCAPS_INTEL_HASWELL \
295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297 AZX_DCAPS_SNOOP_TYPE(SCH))
298
299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300 #define AZX_DCAPS_INTEL_BROADWELL \
301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
304
305 #define AZX_DCAPS_INTEL_BAYTRAIL \
306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307
308 #define AZX_DCAPS_INTEL_BRASWELL \
309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310
311 #define AZX_DCAPS_INTEL_SKYLAKE \
312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313 AZX_DCAPS_I915_POWERWELL)
314
315 /* quirks for ATI SB / AMD Hudson */
316 #define AZX_DCAPS_PRESET_ATI_SB \
317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
318 AZX_DCAPS_SNOOP_TYPE(ATI))
319
320 /* quirks for ATI/AMD HDMI */
321 #define AZX_DCAPS_PRESET_ATI_HDMI \
322 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
323 AZX_DCAPS_NO_MSI64)
324
325 /* quirks for ATI HDMI with snoop off */
326 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
327 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
328
329 /* quirks for Nvidia */
330 #define AZX_DCAPS_PRESET_NVIDIA \
331 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
332 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
333 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
334
335 #define AZX_DCAPS_PRESET_CTHDA \
336 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
337 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
338
339 /*
340 * VGA-switcher support
341 */
342 #ifdef SUPPORT_VGA_SWITCHEROO
343 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
344 #else
345 #define use_vga_switcheroo(chip) 0
346 #endif
347
348 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
349 ((pci)->device == 0x0c0c) || \
350 ((pci)->device == 0x0d0c) || \
351 ((pci)->device == 0x160c))
352
353 static char *driver_short_names[] = {
354 [AZX_DRIVER_ICH] = "HDA Intel",
355 [AZX_DRIVER_PCH] = "HDA Intel PCH",
356 [AZX_DRIVER_SCH] = "HDA Intel MID",
357 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
358 [AZX_DRIVER_ATI] = "HDA ATI SB",
359 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
360 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
361 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
362 [AZX_DRIVER_SIS] = "HDA SIS966",
363 [AZX_DRIVER_ULI] = "HDA ULI M5461",
364 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
365 [AZX_DRIVER_TERA] = "HDA Teradici",
366 [AZX_DRIVER_CTX] = "HDA Creative",
367 [AZX_DRIVER_CTHDA] = "HDA Creative",
368 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
369 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
370 };
371
372 #ifdef CONFIG_X86
373 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
374 {
375 int pages;
376
377 if (azx_snoop(chip))
378 return;
379 if (!dmab || !dmab->area || !dmab->bytes)
380 return;
381
382 #ifdef CONFIG_SND_DMA_SGBUF
383 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
384 struct snd_sg_buf *sgbuf = dmab->private_data;
385 if (chip->driver_type == AZX_DRIVER_CMEDIA)
386 return; /* deal with only CORB/RIRB buffers */
387 if (on)
388 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
389 else
390 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
391 return;
392 }
393 #endif
394
395 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
396 if (on)
397 set_memory_wc((unsigned long)dmab->area, pages);
398 else
399 set_memory_wb((unsigned long)dmab->area, pages);
400 }
401
402 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
403 bool on)
404 {
405 __mark_pages_wc(chip, buf, on);
406 }
407 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
408 struct snd_pcm_substream *substream, bool on)
409 {
410 if (azx_dev->wc_marked != on) {
411 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
412 azx_dev->wc_marked = on;
413 }
414 }
415 #else
416 /* NOP for other archs */
417 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
418 bool on)
419 {
420 }
421 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
422 struct snd_pcm_substream *substream, bool on)
423 {
424 }
425 #endif
426
427 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
428
429 /*
430 * initialize the PCI registers
431 */
432 /* update bits in a PCI register byte */
433 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
434 unsigned char mask, unsigned char val)
435 {
436 unsigned char data;
437
438 pci_read_config_byte(pci, reg, &data);
439 data &= ~mask;
440 data |= (val & mask);
441 pci_write_config_byte(pci, reg, data);
442 }
443
444 static void azx_init_pci(struct azx *chip)
445 {
446 int snoop_type = azx_get_snoop_type(chip);
447
448 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
449 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
450 * Ensuring these bits are 0 clears playback static on some HD Audio
451 * codecs.
452 * The PCI register TCSEL is defined in the Intel manuals.
453 */
454 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
455 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
456 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
457 }
458
459 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
460 * we need to enable snoop.
461 */
462 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
463 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
464 azx_snoop(chip));
465 update_pci_byte(chip->pci,
466 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
467 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
468 }
469
470 /* For NVIDIA HDA, enable snoop */
471 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
472 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
473 azx_snoop(chip));
474 update_pci_byte(chip->pci,
475 NVIDIA_HDA_TRANSREG_ADDR,
476 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
477 update_pci_byte(chip->pci,
478 NVIDIA_HDA_ISTRM_COH,
479 0x01, NVIDIA_HDA_ENABLE_COHBIT);
480 update_pci_byte(chip->pci,
481 NVIDIA_HDA_OSTRM_COH,
482 0x01, NVIDIA_HDA_ENABLE_COHBIT);
483 }
484
485 /* Enable SCH/PCH snoop if needed */
486 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
487 unsigned short snoop;
488 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
489 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
490 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
491 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
492 if (!azx_snoop(chip))
493 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
494 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
495 pci_read_config_word(chip->pci,
496 INTEL_SCH_HDA_DEVC, &snoop);
497 }
498 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
499 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
500 "Disabled" : "Enabled");
501 }
502 }
503
504 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
505 {
506 struct hdac_bus *bus = azx_bus(chip);
507
508 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
509 snd_hdac_set_codec_wakeup(bus, true);
510 azx_init_chip(chip, full_reset);
511 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
512 snd_hdac_set_codec_wakeup(bus, false);
513 }
514
515 /* calculate runtime delay from LPIB */
516 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
517 unsigned int pos)
518 {
519 struct snd_pcm_substream *substream = azx_dev->core.substream;
520 int stream = substream->stream;
521 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
522 int delay;
523
524 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
525 delay = pos - lpib_pos;
526 else
527 delay = lpib_pos - pos;
528 if (delay < 0) {
529 if (delay >= azx_dev->core.delay_negative_threshold)
530 delay = 0;
531 else
532 delay += azx_dev->core.bufsize;
533 }
534
535 if (delay >= azx_dev->core.period_bytes) {
536 dev_info(chip->card->dev,
537 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
538 delay, azx_dev->core.period_bytes);
539 delay = 0;
540 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
541 chip->get_delay[stream] = NULL;
542 }
543
544 return bytes_to_frames(substream->runtime, delay);
545 }
546
547 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
548
549 /* called from IRQ */
550 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
551 {
552 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
553 int ok;
554
555 ok = azx_position_ok(chip, azx_dev);
556 if (ok == 1) {
557 azx_dev->irq_pending = 0;
558 return ok;
559 } else if (ok == 0) {
560 /* bogus IRQ, process it later */
561 azx_dev->irq_pending = 1;
562 schedule_work(&hda->irq_pending_work);
563 }
564 return 0;
565 }
566
567 /* Enable/disable i915 display power for the link */
568 static int azx_intel_link_power(struct azx *chip, bool enable)
569 {
570 struct hdac_bus *bus = azx_bus(chip);
571
572 return snd_hdac_display_power(bus, enable);
573 }
574
575 /*
576 * Check whether the current DMA position is acceptable for updating
577 * periods. Returns non-zero if it's OK.
578 *
579 * Many HD-audio controllers appear pretty inaccurate about
580 * the update-IRQ timing. The IRQ is issued before actually the
581 * data is processed. So, we need to process it afterwords in a
582 * workqueue.
583 */
584 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
585 {
586 struct snd_pcm_substream *substream = azx_dev->core.substream;
587 int stream = substream->stream;
588 u32 wallclk;
589 unsigned int pos;
590
591 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
592 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
593 return -1; /* bogus (too early) interrupt */
594
595 if (chip->get_position[stream])
596 pos = chip->get_position[stream](chip, azx_dev);
597 else { /* use the position buffer as default */
598 pos = azx_get_pos_posbuf(chip, azx_dev);
599 if (!pos || pos == (u32)-1) {
600 dev_info(chip->card->dev,
601 "Invalid position buffer, using LPIB read method instead.\n");
602 chip->get_position[stream] = azx_get_pos_lpib;
603 if (chip->get_position[0] == azx_get_pos_lpib &&
604 chip->get_position[1] == azx_get_pos_lpib)
605 azx_bus(chip)->use_posbuf = false;
606 pos = azx_get_pos_lpib(chip, azx_dev);
607 chip->get_delay[stream] = NULL;
608 } else {
609 chip->get_position[stream] = azx_get_pos_posbuf;
610 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
611 chip->get_delay[stream] = azx_get_delay_from_lpib;
612 }
613 }
614
615 if (pos >= azx_dev->core.bufsize)
616 pos = 0;
617
618 if (WARN_ONCE(!azx_dev->core.period_bytes,
619 "hda-intel: zero azx_dev->period_bytes"))
620 return -1; /* this shouldn't happen! */
621 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
622 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
623 /* NG - it's below the first next period boundary */
624 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
625 azx_dev->core.start_wallclk += wallclk;
626 return 1; /* OK, it's fine */
627 }
628
629 /*
630 * The work for pending PCM period updates.
631 */
632 static void azx_irq_pending_work(struct work_struct *work)
633 {
634 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
635 struct azx *chip = &hda->chip;
636 struct hdac_bus *bus = azx_bus(chip);
637 struct hdac_stream *s;
638 int pending, ok;
639
640 if (!hda->irq_pending_warned) {
641 dev_info(chip->card->dev,
642 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
643 chip->card->number);
644 hda->irq_pending_warned = 1;
645 }
646
647 for (;;) {
648 pending = 0;
649 spin_lock_irq(&bus->reg_lock);
650 list_for_each_entry(s, &bus->stream_list, list) {
651 struct azx_dev *azx_dev = stream_to_azx_dev(s);
652 if (!azx_dev->irq_pending ||
653 !s->substream ||
654 !s->running)
655 continue;
656 ok = azx_position_ok(chip, azx_dev);
657 if (ok > 0) {
658 azx_dev->irq_pending = 0;
659 spin_unlock(&bus->reg_lock);
660 snd_pcm_period_elapsed(s->substream);
661 spin_lock(&bus->reg_lock);
662 } else if (ok < 0) {
663 pending = 0; /* too early */
664 } else
665 pending++;
666 }
667 spin_unlock_irq(&bus->reg_lock);
668 if (!pending)
669 return;
670 msleep(1);
671 }
672 }
673
674 /* clear irq_pending flags and assure no on-going workq */
675 static void azx_clear_irq_pending(struct azx *chip)
676 {
677 struct hdac_bus *bus = azx_bus(chip);
678 struct hdac_stream *s;
679
680 spin_lock_irq(&bus->reg_lock);
681 list_for_each_entry(s, &bus->stream_list, list) {
682 struct azx_dev *azx_dev = stream_to_azx_dev(s);
683 azx_dev->irq_pending = 0;
684 }
685 spin_unlock_irq(&bus->reg_lock);
686 }
687
688 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
689 {
690 struct hdac_bus *bus = azx_bus(chip);
691
692 if (request_irq(chip->pci->irq, azx_interrupt,
693 chip->msi ? 0 : IRQF_SHARED,
694 KBUILD_MODNAME, chip)) {
695 dev_err(chip->card->dev,
696 "unable to grab IRQ %d, disabling device\n",
697 chip->pci->irq);
698 if (do_disconnect)
699 snd_card_disconnect(chip->card);
700 return -1;
701 }
702 bus->irq = chip->pci->irq;
703 pci_intx(chip->pci, !chip->msi);
704 return 0;
705 }
706
707 /* get the current DMA position with correction on VIA chips */
708 static unsigned int azx_via_get_position(struct azx *chip,
709 struct azx_dev *azx_dev)
710 {
711 unsigned int link_pos, mini_pos, bound_pos;
712 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
713 unsigned int fifo_size;
714
715 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
716 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
717 /* Playback, no problem using link position */
718 return link_pos;
719 }
720
721 /* Capture */
722 /* For new chipset,
723 * use mod to get the DMA position just like old chipset
724 */
725 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
726 mod_dma_pos %= azx_dev->core.period_bytes;
727
728 /* azx_dev->fifo_size can't get FIFO size of in stream.
729 * Get from base address + offset.
730 */
731 fifo_size = readw(azx_bus(chip)->remap_addr +
732 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
733
734 if (azx_dev->insufficient) {
735 /* Link position never gather than FIFO size */
736 if (link_pos <= fifo_size)
737 return 0;
738
739 azx_dev->insufficient = 0;
740 }
741
742 if (link_pos <= fifo_size)
743 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
744 else
745 mini_pos = link_pos - fifo_size;
746
747 /* Find nearest previous boudary */
748 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
749 mod_link_pos = link_pos % azx_dev->core.period_bytes;
750 if (mod_link_pos >= fifo_size)
751 bound_pos = link_pos - mod_link_pos;
752 else if (mod_dma_pos >= mod_mini_pos)
753 bound_pos = mini_pos - mod_mini_pos;
754 else {
755 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
756 if (bound_pos >= azx_dev->core.bufsize)
757 bound_pos = 0;
758 }
759
760 /* Calculate real DMA position we want */
761 return bound_pos + mod_dma_pos;
762 }
763
764 #ifdef CONFIG_PM
765 static DEFINE_MUTEX(card_list_lock);
766 static LIST_HEAD(card_list);
767
768 static void azx_add_card_list(struct azx *chip)
769 {
770 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
771 mutex_lock(&card_list_lock);
772 list_add(&hda->list, &card_list);
773 mutex_unlock(&card_list_lock);
774 }
775
776 static void azx_del_card_list(struct azx *chip)
777 {
778 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
779 mutex_lock(&card_list_lock);
780 list_del_init(&hda->list);
781 mutex_unlock(&card_list_lock);
782 }
783
784 /* trigger power-save check at writing parameter */
785 static int param_set_xint(const char *val, const struct kernel_param *kp)
786 {
787 struct hda_intel *hda;
788 struct azx *chip;
789 int prev = power_save;
790 int ret = param_set_int(val, kp);
791
792 if (ret || prev == power_save)
793 return ret;
794
795 mutex_lock(&card_list_lock);
796 list_for_each_entry(hda, &card_list, list) {
797 chip = &hda->chip;
798 if (!hda->probe_continued || chip->disabled)
799 continue;
800 snd_hda_set_power_save(&chip->bus, power_save * 1000);
801 }
802 mutex_unlock(&card_list_lock);
803 return 0;
804 }
805 #else
806 #define azx_add_card_list(chip) /* NOP */
807 #define azx_del_card_list(chip) /* NOP */
808 #endif /* CONFIG_PM */
809
810 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
811 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
812 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
813 * BCLK = CDCLK * M / N
814 * The values will be lost when the display power well is disabled and need to
815 * be restored to avoid abnormal playback speed.
816 */
817 static void haswell_set_bclk(struct hda_intel *hda)
818 {
819 struct azx *chip = &hda->chip;
820 int cdclk_freq;
821 unsigned int bclk_m, bclk_n;
822
823 if (!hda->need_i915_power)
824 return;
825
826 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
827 switch (cdclk_freq) {
828 case 337500:
829 bclk_m = 16;
830 bclk_n = 225;
831 break;
832
833 case 450000:
834 default: /* default CDCLK 450MHz */
835 bclk_m = 4;
836 bclk_n = 75;
837 break;
838
839 case 540000:
840 bclk_m = 4;
841 bclk_n = 90;
842 break;
843
844 case 675000:
845 bclk_m = 8;
846 bclk_n = 225;
847 break;
848 }
849
850 azx_writew(chip, HSW_EM4, bclk_m);
851 azx_writew(chip, HSW_EM5, bclk_n);
852 }
853
854 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
855 /*
856 * power management
857 */
858 static int azx_suspend(struct device *dev)
859 {
860 struct snd_card *card = dev_get_drvdata(dev);
861 struct azx *chip;
862 struct hda_intel *hda;
863 struct hdac_bus *bus;
864
865 if (!card)
866 return 0;
867
868 chip = card->private_data;
869 hda = container_of(chip, struct hda_intel, chip);
870 if (chip->disabled || hda->init_failed)
871 return 0;
872
873 bus = azx_bus(chip);
874 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
875 azx_clear_irq_pending(chip);
876 azx_stop_chip(chip);
877 azx_enter_link_reset(chip);
878 if (bus->irq >= 0) {
879 free_irq(bus->irq, chip);
880 bus->irq = -1;
881 }
882
883 if (chip->msi)
884 pci_disable_msi(chip->pci);
885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
886 && hda->need_i915_power)
887 snd_hdac_display_power(bus, false);
888
889 trace_azx_suspend(chip);
890 return 0;
891 }
892
893 static int azx_resume(struct device *dev)
894 {
895 struct pci_dev *pci = to_pci_dev(dev);
896 struct snd_card *card = dev_get_drvdata(dev);
897 struct azx *chip;
898 struct hda_intel *hda;
899
900 if (!card)
901 return 0;
902
903 chip = card->private_data;
904 hda = container_of(chip, struct hda_intel, chip);
905 if (chip->disabled || hda->init_failed)
906 return 0;
907
908 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
909 && hda->need_i915_power) {
910 snd_hdac_display_power(azx_bus(chip), true);
911 haswell_set_bclk(hda);
912 }
913 if (chip->msi)
914 if (pci_enable_msi(pci) < 0)
915 chip->msi = 0;
916 if (azx_acquire_irq(chip, 1) < 0)
917 return -EIO;
918 azx_init_pci(chip);
919
920 hda_intel_init_chip(chip, true);
921
922 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
923
924 trace_azx_resume(chip);
925 return 0;
926 }
927 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
928
929 #ifdef CONFIG_PM
930 static int azx_runtime_suspend(struct device *dev)
931 {
932 struct snd_card *card = dev_get_drvdata(dev);
933 struct azx *chip;
934 struct hda_intel *hda;
935
936 if (!card)
937 return 0;
938
939 chip = card->private_data;
940 hda = container_of(chip, struct hda_intel, chip);
941 if (chip->disabled || hda->init_failed)
942 return 0;
943
944 if (!azx_has_pm_runtime(chip))
945 return 0;
946
947 /* enable controller wake up event */
948 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
949 STATESTS_INT_MASK);
950
951 azx_stop_chip(chip);
952 azx_enter_link_reset(chip);
953 azx_clear_irq_pending(chip);
954 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
955 && hda->need_i915_power)
956 snd_hdac_display_power(azx_bus(chip), false);
957
958 trace_azx_runtime_suspend(chip);
959 return 0;
960 }
961
962 static int azx_runtime_resume(struct device *dev)
963 {
964 struct snd_card *card = dev_get_drvdata(dev);
965 struct azx *chip;
966 struct hda_intel *hda;
967 struct hdac_bus *bus;
968 struct hda_codec *codec;
969 int status;
970
971 if (!card)
972 return 0;
973
974 chip = card->private_data;
975 hda = container_of(chip, struct hda_intel, chip);
976 if (chip->disabled || hda->init_failed)
977 return 0;
978
979 if (!azx_has_pm_runtime(chip))
980 return 0;
981
982 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
983 && hda->need_i915_power) {
984 bus = azx_bus(chip);
985 snd_hdac_display_power(bus, true);
986 haswell_set_bclk(hda);
987 /* toggle codec wakeup bit for STATESTS read */
988 snd_hdac_set_codec_wakeup(bus, true);
989 snd_hdac_set_codec_wakeup(bus, false);
990 }
991
992 /* Read STATESTS before controller reset */
993 status = azx_readw(chip, STATESTS);
994
995 azx_init_pci(chip);
996 hda_intel_init_chip(chip, true);
997
998 if (status) {
999 list_for_each_codec(codec, &chip->bus)
1000 if (status & (1 << codec->addr))
1001 schedule_delayed_work(&codec->jackpoll_work,
1002 codec->jackpoll_interval);
1003 }
1004
1005 /* disable controller Wake Up event*/
1006 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1007 ~STATESTS_INT_MASK);
1008
1009 trace_azx_runtime_resume(chip);
1010 return 0;
1011 }
1012
1013 static int azx_runtime_idle(struct device *dev)
1014 {
1015 struct snd_card *card = dev_get_drvdata(dev);
1016 struct azx *chip;
1017 struct hda_intel *hda;
1018
1019 if (!card)
1020 return 0;
1021
1022 chip = card->private_data;
1023 hda = container_of(chip, struct hda_intel, chip);
1024 if (chip->disabled || hda->init_failed)
1025 return 0;
1026
1027 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1028 azx_bus(chip)->codec_powered)
1029 return -EBUSY;
1030
1031 return 0;
1032 }
1033
1034 static const struct dev_pm_ops azx_pm = {
1035 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1036 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1037 };
1038
1039 #define AZX_PM_OPS &azx_pm
1040 #else
1041 #define AZX_PM_OPS NULL
1042 #endif /* CONFIG_PM */
1043
1044
1045 static int azx_probe_continue(struct azx *chip);
1046
1047 #ifdef SUPPORT_VGA_SWITCHEROO
1048 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1049
1050 static void azx_vs_set_state(struct pci_dev *pci,
1051 enum vga_switcheroo_state state)
1052 {
1053 struct snd_card *card = pci_get_drvdata(pci);
1054 struct azx *chip = card->private_data;
1055 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1056 bool disabled;
1057
1058 wait_for_completion(&hda->probe_wait);
1059 if (hda->init_failed)
1060 return;
1061
1062 disabled = (state == VGA_SWITCHEROO_OFF);
1063 if (chip->disabled == disabled)
1064 return;
1065
1066 if (!hda->probe_continued) {
1067 chip->disabled = disabled;
1068 if (!disabled) {
1069 dev_info(chip->card->dev,
1070 "Start delayed initialization\n");
1071 if (azx_probe_continue(chip) < 0) {
1072 dev_err(chip->card->dev, "initialization error\n");
1073 hda->init_failed = true;
1074 }
1075 }
1076 } else {
1077 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1078 disabled ? "Disabling" : "Enabling");
1079 if (disabled) {
1080 pm_runtime_put_sync_suspend(card->dev);
1081 azx_suspend(card->dev);
1082 /* when we get suspended by vga switcheroo we end up in D3cold,
1083 * however we have no ACPI handle, so pci/acpi can't put us there,
1084 * put ourselves there */
1085 pci->current_state = PCI_D3cold;
1086 chip->disabled = true;
1087 if (snd_hda_lock_devices(&chip->bus))
1088 dev_warn(chip->card->dev,
1089 "Cannot lock devices!\n");
1090 } else {
1091 snd_hda_unlock_devices(&chip->bus);
1092 pm_runtime_get_noresume(card->dev);
1093 chip->disabled = false;
1094 azx_resume(card->dev);
1095 }
1096 }
1097 }
1098
1099 static bool azx_vs_can_switch(struct pci_dev *pci)
1100 {
1101 struct snd_card *card = pci_get_drvdata(pci);
1102 struct azx *chip = card->private_data;
1103 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1104
1105 wait_for_completion(&hda->probe_wait);
1106 if (hda->init_failed)
1107 return false;
1108 if (chip->disabled || !hda->probe_continued)
1109 return true;
1110 if (snd_hda_lock_devices(&chip->bus))
1111 return false;
1112 snd_hda_unlock_devices(&chip->bus);
1113 return true;
1114 }
1115
1116 static void init_vga_switcheroo(struct azx *chip)
1117 {
1118 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1119 struct pci_dev *p = get_bound_vga(chip->pci);
1120 if (p) {
1121 dev_info(chip->card->dev,
1122 "Handle VGA-switcheroo audio client\n");
1123 hda->use_vga_switcheroo = 1;
1124 pci_dev_put(p);
1125 }
1126 }
1127
1128 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1129 .set_gpu_state = azx_vs_set_state,
1130 .can_switch = azx_vs_can_switch,
1131 };
1132
1133 static int register_vga_switcheroo(struct azx *chip)
1134 {
1135 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1136 int err;
1137
1138 if (!hda->use_vga_switcheroo)
1139 return 0;
1140 /* FIXME: currently only handling DIS controller
1141 * is there any machine with two switchable HDMI audio controllers?
1142 */
1143 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1144 VGA_SWITCHEROO_DIS,
1145 hda->probe_continued);
1146 if (err < 0)
1147 return err;
1148 hda->vga_switcheroo_registered = 1;
1149
1150 /* register as an optimus hdmi audio power domain */
1151 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1152 &hda->hdmi_pm_domain);
1153 return 0;
1154 }
1155 #else
1156 #define init_vga_switcheroo(chip) /* NOP */
1157 #define register_vga_switcheroo(chip) 0
1158 #define check_hdmi_disabled(pci) false
1159 #endif /* SUPPORT_VGA_SWITCHER */
1160
1161 /*
1162 * destructor
1163 */
1164 static int azx_free(struct azx *chip)
1165 {
1166 struct pci_dev *pci = chip->pci;
1167 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1168 struct hdac_bus *bus = azx_bus(chip);
1169
1170 if (azx_has_pm_runtime(chip) && chip->running)
1171 pm_runtime_get_noresume(&pci->dev);
1172
1173 azx_del_card_list(chip);
1174
1175 hda->init_failed = 1; /* to be sure */
1176 complete_all(&hda->probe_wait);
1177
1178 if (use_vga_switcheroo(hda)) {
1179 if (chip->disabled && hda->probe_continued)
1180 snd_hda_unlock_devices(&chip->bus);
1181 if (hda->vga_switcheroo_registered)
1182 vga_switcheroo_unregister_client(chip->pci);
1183 }
1184
1185 if (bus->chip_init) {
1186 azx_clear_irq_pending(chip);
1187 azx_stop_all_streams(chip);
1188 azx_stop_chip(chip);
1189 }
1190
1191 if (bus->irq >= 0)
1192 free_irq(bus->irq, (void*)chip);
1193 if (chip->msi)
1194 pci_disable_msi(chip->pci);
1195 iounmap(bus->remap_addr);
1196
1197 azx_free_stream_pages(chip);
1198 azx_free_streams(chip);
1199 snd_hdac_bus_exit(bus);
1200
1201 if (chip->region_requested)
1202 pci_release_regions(chip->pci);
1203
1204 pci_disable_device(chip->pci);
1205 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1206 release_firmware(chip->fw);
1207 #endif
1208
1209 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1210 if (hda->need_i915_power)
1211 snd_hdac_display_power(bus, false);
1212 snd_hdac_i915_exit(bus);
1213 }
1214 kfree(hda);
1215
1216 return 0;
1217 }
1218
1219 static int azx_dev_disconnect(struct snd_device *device)
1220 {
1221 struct azx *chip = device->device_data;
1222
1223 chip->bus.shutdown = 1;
1224 return 0;
1225 }
1226
1227 static int azx_dev_free(struct snd_device *device)
1228 {
1229 return azx_free(device->device_data);
1230 }
1231
1232 #ifdef SUPPORT_VGA_SWITCHEROO
1233 /*
1234 * Check of disabled HDMI controller by vga-switcheroo
1235 */
1236 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1237 {
1238 struct pci_dev *p;
1239
1240 /* check only discrete GPU */
1241 switch (pci->vendor) {
1242 case PCI_VENDOR_ID_ATI:
1243 case PCI_VENDOR_ID_AMD:
1244 case PCI_VENDOR_ID_NVIDIA:
1245 if (pci->devfn == 1) {
1246 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1247 pci->bus->number, 0);
1248 if (p) {
1249 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1250 return p;
1251 pci_dev_put(p);
1252 }
1253 }
1254 break;
1255 }
1256 return NULL;
1257 }
1258
1259 static bool check_hdmi_disabled(struct pci_dev *pci)
1260 {
1261 bool vga_inactive = false;
1262 struct pci_dev *p = get_bound_vga(pci);
1263
1264 if (p) {
1265 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1266 vga_inactive = true;
1267 pci_dev_put(p);
1268 }
1269 return vga_inactive;
1270 }
1271 #endif /* SUPPORT_VGA_SWITCHEROO */
1272
1273 /*
1274 * white/black-listing for position_fix
1275 */
1276 static struct snd_pci_quirk position_fix_list[] = {
1277 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1278 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1279 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1280 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1281 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1282 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1283 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1284 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1285 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1286 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1287 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1288 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1289 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1290 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1291 {}
1292 };
1293
1294 static int check_position_fix(struct azx *chip, int fix)
1295 {
1296 const struct snd_pci_quirk *q;
1297
1298 switch (fix) {
1299 case POS_FIX_AUTO:
1300 case POS_FIX_LPIB:
1301 case POS_FIX_POSBUF:
1302 case POS_FIX_VIACOMBO:
1303 case POS_FIX_COMBO:
1304 return fix;
1305 }
1306
1307 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1308 if (q) {
1309 dev_info(chip->card->dev,
1310 "position_fix set to %d for device %04x:%04x\n",
1311 q->value, q->subvendor, q->subdevice);
1312 return q->value;
1313 }
1314
1315 /* Check VIA/ATI HD Audio Controller exist */
1316 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1317 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1318 return POS_FIX_VIACOMBO;
1319 }
1320 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1321 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1322 return POS_FIX_LPIB;
1323 }
1324 return POS_FIX_AUTO;
1325 }
1326
1327 static void assign_position_fix(struct azx *chip, int fix)
1328 {
1329 static azx_get_pos_callback_t callbacks[] = {
1330 [POS_FIX_AUTO] = NULL,
1331 [POS_FIX_LPIB] = azx_get_pos_lpib,
1332 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1333 [POS_FIX_VIACOMBO] = azx_via_get_position,
1334 [POS_FIX_COMBO] = azx_get_pos_lpib,
1335 };
1336
1337 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1338
1339 /* combo mode uses LPIB only for playback */
1340 if (fix == POS_FIX_COMBO)
1341 chip->get_position[1] = NULL;
1342
1343 if (fix == POS_FIX_POSBUF &&
1344 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1345 chip->get_delay[0] = chip->get_delay[1] =
1346 azx_get_delay_from_lpib;
1347 }
1348
1349 }
1350
1351 /*
1352 * black-lists for probe_mask
1353 */
1354 static struct snd_pci_quirk probe_mask_list[] = {
1355 /* Thinkpad often breaks the controller communication when accessing
1356 * to the non-working (or non-existing) modem codec slot.
1357 */
1358 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1359 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1360 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1361 /* broken BIOS */
1362 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1363 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1364 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1365 /* forced codec slots */
1366 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1367 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1368 /* WinFast VP200 H (Teradici) user reported broken communication */
1369 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1370 {}
1371 };
1372
1373 #define AZX_FORCE_CODEC_MASK 0x100
1374
1375 static void check_probe_mask(struct azx *chip, int dev)
1376 {
1377 const struct snd_pci_quirk *q;
1378
1379 chip->codec_probe_mask = probe_mask[dev];
1380 if (chip->codec_probe_mask == -1) {
1381 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1382 if (q) {
1383 dev_info(chip->card->dev,
1384 "probe_mask set to 0x%x for device %04x:%04x\n",
1385 q->value, q->subvendor, q->subdevice);
1386 chip->codec_probe_mask = q->value;
1387 }
1388 }
1389
1390 /* check forced option */
1391 if (chip->codec_probe_mask != -1 &&
1392 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1393 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1394 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1395 (int)azx_bus(chip)->codec_mask);
1396 }
1397 }
1398
1399 /*
1400 * white/black-list for enable_msi
1401 */
1402 static struct snd_pci_quirk msi_black_list[] = {
1403 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1404 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1405 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1406 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1407 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1408 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1409 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1410 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1411 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1412 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1413 {}
1414 };
1415
1416 static void check_msi(struct azx *chip)
1417 {
1418 const struct snd_pci_quirk *q;
1419
1420 if (enable_msi >= 0) {
1421 chip->msi = !!enable_msi;
1422 return;
1423 }
1424 chip->msi = 1; /* enable MSI as default */
1425 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1426 if (q) {
1427 dev_info(chip->card->dev,
1428 "msi for device %04x:%04x set to %d\n",
1429 q->subvendor, q->subdevice, q->value);
1430 chip->msi = q->value;
1431 return;
1432 }
1433
1434 /* NVidia chipsets seem to cause troubles with MSI */
1435 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1436 dev_info(chip->card->dev, "Disabling MSI\n");
1437 chip->msi = 0;
1438 }
1439 }
1440
1441 /* check the snoop mode availability */
1442 static void azx_check_snoop_available(struct azx *chip)
1443 {
1444 int snoop = hda_snoop;
1445
1446 if (snoop >= 0) {
1447 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1448 snoop ? "snoop" : "non-snoop");
1449 chip->snoop = snoop;
1450 return;
1451 }
1452
1453 snoop = true;
1454 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1455 chip->driver_type == AZX_DRIVER_VIA) {
1456 /* force to non-snoop mode for a new VIA controller
1457 * when BIOS is set
1458 */
1459 u8 val;
1460 pci_read_config_byte(chip->pci, 0x42, &val);
1461 if (!(val & 0x80) && chip->pci->revision == 0x30)
1462 snoop = false;
1463 }
1464
1465 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1466 snoop = false;
1467
1468 chip->snoop = snoop;
1469 if (!snoop)
1470 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1471 }
1472
1473 static void azx_probe_work(struct work_struct *work)
1474 {
1475 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1476 azx_probe_continue(&hda->chip);
1477 }
1478
1479 /*
1480 * constructor
1481 */
1482 static const struct hdac_io_ops pci_hda_io_ops;
1483 static const struct hda_controller_ops pci_hda_ops;
1484
1485 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1486 int dev, unsigned int driver_caps,
1487 struct azx **rchip)
1488 {
1489 static struct snd_device_ops ops = {
1490 .dev_disconnect = azx_dev_disconnect,
1491 .dev_free = azx_dev_free,
1492 };
1493 struct hda_intel *hda;
1494 struct azx *chip;
1495 int err;
1496
1497 *rchip = NULL;
1498
1499 err = pci_enable_device(pci);
1500 if (err < 0)
1501 return err;
1502
1503 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1504 if (!hda) {
1505 pci_disable_device(pci);
1506 return -ENOMEM;
1507 }
1508
1509 chip = &hda->chip;
1510 mutex_init(&chip->open_mutex);
1511 chip->card = card;
1512 chip->pci = pci;
1513 chip->ops = &pci_hda_ops;
1514 chip->driver_caps = driver_caps;
1515 chip->driver_type = driver_caps & 0xff;
1516 check_msi(chip);
1517 chip->dev_index = dev;
1518 chip->jackpoll_ms = jackpoll_ms;
1519 INIT_LIST_HEAD(&chip->pcm_list);
1520 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1521 INIT_LIST_HEAD(&hda->list);
1522 init_vga_switcheroo(chip);
1523 init_completion(&hda->probe_wait);
1524
1525 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1526
1527 check_probe_mask(chip, dev);
1528
1529 chip->single_cmd = single_cmd;
1530 azx_check_snoop_available(chip);
1531
1532 if (bdl_pos_adj[dev] < 0) {
1533 switch (chip->driver_type) {
1534 case AZX_DRIVER_ICH:
1535 case AZX_DRIVER_PCH:
1536 bdl_pos_adj[dev] = 1;
1537 break;
1538 default:
1539 bdl_pos_adj[dev] = 32;
1540 break;
1541 }
1542 }
1543 chip->bdl_pos_adj = bdl_pos_adj;
1544
1545 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1546 if (err < 0) {
1547 kfree(hda);
1548 pci_disable_device(pci);
1549 return err;
1550 }
1551
1552 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1553 if (err < 0) {
1554 dev_err(card->dev, "Error creating device [card]!\n");
1555 azx_free(chip);
1556 return err;
1557 }
1558
1559 /* continue probing in work context as may trigger request module */
1560 INIT_WORK(&hda->probe_work, azx_probe_work);
1561
1562 *rchip = chip;
1563
1564 return 0;
1565 }
1566
1567 static int azx_first_init(struct azx *chip)
1568 {
1569 int dev = chip->dev_index;
1570 struct pci_dev *pci = chip->pci;
1571 struct snd_card *card = chip->card;
1572 struct hdac_bus *bus = azx_bus(chip);
1573 int err;
1574 unsigned short gcap;
1575 unsigned int dma_bits = 64;
1576
1577 #if BITS_PER_LONG != 64
1578 /* Fix up base address on ULI M5461 */
1579 if (chip->driver_type == AZX_DRIVER_ULI) {
1580 u16 tmp3;
1581 pci_read_config_word(pci, 0x40, &tmp3);
1582 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1583 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1584 }
1585 #endif
1586
1587 err = pci_request_regions(pci, "ICH HD audio");
1588 if (err < 0)
1589 return err;
1590 chip->region_requested = 1;
1591
1592 bus->addr = pci_resource_start(pci, 0);
1593 bus->remap_addr = pci_ioremap_bar(pci, 0);
1594 if (bus->remap_addr == NULL) {
1595 dev_err(card->dev, "ioremap error\n");
1596 return -ENXIO;
1597 }
1598
1599 if (chip->msi) {
1600 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1601 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1602 pci->no_64bit_msi = true;
1603 }
1604 if (pci_enable_msi(pci) < 0)
1605 chip->msi = 0;
1606 }
1607
1608 if (azx_acquire_irq(chip, 0) < 0)
1609 return -EBUSY;
1610
1611 pci_set_master(pci);
1612 synchronize_irq(bus->irq);
1613
1614 gcap = azx_readw(chip, GCAP);
1615 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1616
1617 /* AMD devices support 40 or 48bit DMA, take the safe one */
1618 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1619 dma_bits = 40;
1620
1621 /* disable SB600 64bit support for safety */
1622 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1623 struct pci_dev *p_smbus;
1624 dma_bits = 40;
1625 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1626 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1627 NULL);
1628 if (p_smbus) {
1629 if (p_smbus->revision < 0x30)
1630 gcap &= ~AZX_GCAP_64OK;
1631 pci_dev_put(p_smbus);
1632 }
1633 }
1634
1635 /* disable 64bit DMA address on some devices */
1636 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1637 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1638 gcap &= ~AZX_GCAP_64OK;
1639 }
1640
1641 /* disable buffer size rounding to 128-byte multiples if supported */
1642 if (align_buffer_size >= 0)
1643 chip->align_buffer_size = !!align_buffer_size;
1644 else {
1645 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1646 chip->align_buffer_size = 0;
1647 else
1648 chip->align_buffer_size = 1;
1649 }
1650
1651 /* allow 64bit DMA address if supported by H/W */
1652 if (!(gcap & AZX_GCAP_64OK))
1653 dma_bits = 32;
1654 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1655 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1656 } else {
1657 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1658 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1659 }
1660
1661 /* read number of streams from GCAP register instead of using
1662 * hardcoded value
1663 */
1664 chip->capture_streams = (gcap >> 8) & 0x0f;
1665 chip->playback_streams = (gcap >> 12) & 0x0f;
1666 if (!chip->playback_streams && !chip->capture_streams) {
1667 /* gcap didn't give any info, switching to old method */
1668
1669 switch (chip->driver_type) {
1670 case AZX_DRIVER_ULI:
1671 chip->playback_streams = ULI_NUM_PLAYBACK;
1672 chip->capture_streams = ULI_NUM_CAPTURE;
1673 break;
1674 case AZX_DRIVER_ATIHDMI:
1675 case AZX_DRIVER_ATIHDMI_NS:
1676 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1677 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1678 break;
1679 case AZX_DRIVER_GENERIC:
1680 default:
1681 chip->playback_streams = ICH6_NUM_PLAYBACK;
1682 chip->capture_streams = ICH6_NUM_CAPTURE;
1683 break;
1684 }
1685 }
1686 chip->capture_index_offset = 0;
1687 chip->playback_index_offset = chip->capture_streams;
1688 chip->num_streams = chip->playback_streams + chip->capture_streams;
1689
1690 /* initialize streams */
1691 err = azx_init_streams(chip);
1692 if (err < 0)
1693 return err;
1694
1695 err = azx_alloc_stream_pages(chip);
1696 if (err < 0)
1697 return err;
1698
1699 /* initialize chip */
1700 azx_init_pci(chip);
1701
1702 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1703 struct hda_intel *hda;
1704
1705 hda = container_of(chip, struct hda_intel, chip);
1706 haswell_set_bclk(hda);
1707 }
1708
1709 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1710
1711 /* codec detection */
1712 if (!azx_bus(chip)->codec_mask) {
1713 dev_err(card->dev, "no codecs found!\n");
1714 return -ENODEV;
1715 }
1716
1717 strcpy(card->driver, "HDA-Intel");
1718 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1719 sizeof(card->shortname));
1720 snprintf(card->longname, sizeof(card->longname),
1721 "%s at 0x%lx irq %i",
1722 card->shortname, bus->addr, bus->irq);
1723
1724 return 0;
1725 }
1726
1727 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1728 /* callback from request_firmware_nowait() */
1729 static void azx_firmware_cb(const struct firmware *fw, void *context)
1730 {
1731 struct snd_card *card = context;
1732 struct azx *chip = card->private_data;
1733 struct pci_dev *pci = chip->pci;
1734
1735 if (!fw) {
1736 dev_err(card->dev, "Cannot load firmware, aborting\n");
1737 goto error;
1738 }
1739
1740 chip->fw = fw;
1741 if (!chip->disabled) {
1742 /* continue probing */
1743 if (azx_probe_continue(chip))
1744 goto error;
1745 }
1746 return; /* OK */
1747
1748 error:
1749 snd_card_free(card);
1750 pci_set_drvdata(pci, NULL);
1751 }
1752 #endif
1753
1754 /*
1755 * HDA controller ops.
1756 */
1757
1758 /* PCI register access. */
1759 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1760 {
1761 writel(value, addr);
1762 }
1763
1764 static u32 pci_azx_readl(u32 __iomem *addr)
1765 {
1766 return readl(addr);
1767 }
1768
1769 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1770 {
1771 writew(value, addr);
1772 }
1773
1774 static u16 pci_azx_readw(u16 __iomem *addr)
1775 {
1776 return readw(addr);
1777 }
1778
1779 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1780 {
1781 writeb(value, addr);
1782 }
1783
1784 static u8 pci_azx_readb(u8 __iomem *addr)
1785 {
1786 return readb(addr);
1787 }
1788
1789 static int disable_msi_reset_irq(struct azx *chip)
1790 {
1791 struct hdac_bus *bus = azx_bus(chip);
1792 int err;
1793
1794 free_irq(bus->irq, chip);
1795 bus->irq = -1;
1796 pci_disable_msi(chip->pci);
1797 chip->msi = 0;
1798 err = azx_acquire_irq(chip, 1);
1799 if (err < 0)
1800 return err;
1801
1802 return 0;
1803 }
1804
1805 /* DMA page allocation helpers. */
1806 static int dma_alloc_pages(struct hdac_bus *bus,
1807 int type,
1808 size_t size,
1809 struct snd_dma_buffer *buf)
1810 {
1811 struct azx *chip = bus_to_azx(bus);
1812 int err;
1813
1814 err = snd_dma_alloc_pages(type,
1815 bus->dev,
1816 size, buf);
1817 if (err < 0)
1818 return err;
1819 mark_pages_wc(chip, buf, true);
1820 return 0;
1821 }
1822
1823 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1824 {
1825 struct azx *chip = bus_to_azx(bus);
1826
1827 mark_pages_wc(chip, buf, false);
1828 snd_dma_free_pages(buf);
1829 }
1830
1831 static int substream_alloc_pages(struct azx *chip,
1832 struct snd_pcm_substream *substream,
1833 size_t size)
1834 {
1835 struct azx_dev *azx_dev = get_azx_dev(substream);
1836 int ret;
1837
1838 mark_runtime_wc(chip, azx_dev, substream, false);
1839 ret = snd_pcm_lib_malloc_pages(substream, size);
1840 if (ret < 0)
1841 return ret;
1842 mark_runtime_wc(chip, azx_dev, substream, true);
1843 return 0;
1844 }
1845
1846 static int substream_free_pages(struct azx *chip,
1847 struct snd_pcm_substream *substream)
1848 {
1849 struct azx_dev *azx_dev = get_azx_dev(substream);
1850 mark_runtime_wc(chip, azx_dev, substream, false);
1851 return snd_pcm_lib_free_pages(substream);
1852 }
1853
1854 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1855 struct vm_area_struct *area)
1856 {
1857 #ifdef CONFIG_X86
1858 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1859 struct azx *chip = apcm->chip;
1860 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1861 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1862 #endif
1863 }
1864
1865 static const struct hdac_io_ops pci_hda_io_ops = {
1866 .reg_writel = pci_azx_writel,
1867 .reg_readl = pci_azx_readl,
1868 .reg_writew = pci_azx_writew,
1869 .reg_readw = pci_azx_readw,
1870 .reg_writeb = pci_azx_writeb,
1871 .reg_readb = pci_azx_readb,
1872 .dma_alloc_pages = dma_alloc_pages,
1873 .dma_free_pages = dma_free_pages,
1874 };
1875
1876 static const struct hda_controller_ops pci_hda_ops = {
1877 .disable_msi_reset_irq = disable_msi_reset_irq,
1878 .substream_alloc_pages = substream_alloc_pages,
1879 .substream_free_pages = substream_free_pages,
1880 .pcm_mmap_prepare = pcm_mmap_prepare,
1881 .position_check = azx_position_check,
1882 .link_power = azx_intel_link_power,
1883 };
1884
1885 static int azx_probe(struct pci_dev *pci,
1886 const struct pci_device_id *pci_id)
1887 {
1888 static int dev;
1889 struct snd_card *card;
1890 struct hda_intel *hda;
1891 struct azx *chip;
1892 bool schedule_probe;
1893 int err;
1894
1895 if (dev >= SNDRV_CARDS)
1896 return -ENODEV;
1897 if (!enable[dev]) {
1898 dev++;
1899 return -ENOENT;
1900 }
1901
1902 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1903 0, &card);
1904 if (err < 0) {
1905 dev_err(&pci->dev, "Error creating card!\n");
1906 return err;
1907 }
1908
1909 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1910 if (err < 0)
1911 goto out_free;
1912 card->private_data = chip;
1913 hda = container_of(chip, struct hda_intel, chip);
1914
1915 pci_set_drvdata(pci, card);
1916
1917 err = register_vga_switcheroo(chip);
1918 if (err < 0) {
1919 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1920 goto out_free;
1921 }
1922
1923 if (check_hdmi_disabled(pci)) {
1924 dev_info(card->dev, "VGA controller is disabled\n");
1925 dev_info(card->dev, "Delaying initialization\n");
1926 chip->disabled = true;
1927 }
1928
1929 schedule_probe = !chip->disabled;
1930
1931 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1932 if (patch[dev] && *patch[dev]) {
1933 dev_info(card->dev, "Applying patch firmware '%s'\n",
1934 patch[dev]);
1935 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1936 &pci->dev, GFP_KERNEL, card,
1937 azx_firmware_cb);
1938 if (err < 0)
1939 goto out_free;
1940 schedule_probe = false; /* continued in azx_firmware_cb() */
1941 }
1942 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1943
1944 #ifndef CONFIG_SND_HDA_I915
1945 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1946 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1947 #endif
1948
1949 if (schedule_probe)
1950 schedule_work(&hda->probe_work);
1951
1952 dev++;
1953 if (chip->disabled)
1954 complete_all(&hda->probe_wait);
1955 return 0;
1956
1957 out_free:
1958 snd_card_free(card);
1959 return err;
1960 }
1961
1962 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1963 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1964 [AZX_DRIVER_NVIDIA] = 8,
1965 [AZX_DRIVER_TERA] = 1,
1966 };
1967
1968 static int azx_probe_continue(struct azx *chip)
1969 {
1970 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1971 struct hdac_bus *bus = azx_bus(chip);
1972 struct pci_dev *pci = chip->pci;
1973 int dev = chip->dev_index;
1974 int err;
1975
1976 hda->probe_continued = 1;
1977
1978 /* Request display power well for the HDA controller or codec. For
1979 * Haswell/Broadwell, both the display HDA controller and codec need
1980 * this power. For other platforms, like Baytrail/Braswell, only the
1981 * display codec needs the power and it can be released after probe.
1982 */
1983 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1984 /* HSW/BDW controllers need this power */
1985 if (CONTROLLER_IN_GPU(pci))
1986 hda->need_i915_power = 1;
1987
1988 err = snd_hdac_i915_init(bus);
1989 if (err < 0) {
1990 /* if the controller is bound only with HDMI/DP
1991 * (for HSW and BDW), we need to abort the probe;
1992 * for other chips, still continue probing as other
1993 * codecs can be on the same link.
1994 */
1995 if (CONTROLLER_IN_GPU(pci))
1996 goto out_free;
1997 else
1998 goto skip_i915;
1999 }
2000
2001 err = snd_hdac_display_power(bus, true);
2002 if (err < 0) {
2003 dev_err(chip->card->dev,
2004 "Cannot turn on display power on i915\n");
2005 goto i915_power_fail;
2006 }
2007 }
2008
2009 skip_i915:
2010 err = azx_first_init(chip);
2011 if (err < 0)
2012 goto out_free;
2013
2014 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2015 chip->beep_mode = beep_mode[dev];
2016 #endif
2017
2018 /* create codec instances */
2019 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2020 if (err < 0)
2021 goto out_free;
2022
2023 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2024 if (chip->fw) {
2025 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2026 chip->fw->data);
2027 if (err < 0)
2028 goto out_free;
2029 #ifndef CONFIG_PM
2030 release_firmware(chip->fw); /* no longer needed */
2031 chip->fw = NULL;
2032 #endif
2033 }
2034 #endif
2035 if ((probe_only[dev] & 1) == 0) {
2036 err = azx_codec_configure(chip);
2037 if (err < 0)
2038 goto out_free;
2039 }
2040
2041 err = snd_card_register(chip->card);
2042 if (err < 0)
2043 goto out_free;
2044
2045 chip->running = 1;
2046 azx_add_card_list(chip);
2047 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2048 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2049 pm_runtime_put_noidle(&pci->dev);
2050
2051 out_free:
2052 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2053 && !hda->need_i915_power)
2054 snd_hdac_display_power(bus, false);
2055
2056 i915_power_fail:
2057 if (err < 0)
2058 hda->init_failed = 1;
2059 complete_all(&hda->probe_wait);
2060 return err;
2061 }
2062
2063 static void azx_remove(struct pci_dev *pci)
2064 {
2065 struct snd_card *card = pci_get_drvdata(pci);
2066
2067 if (card)
2068 snd_card_free(card);
2069 }
2070
2071 static void azx_shutdown(struct pci_dev *pci)
2072 {
2073 struct snd_card *card = pci_get_drvdata(pci);
2074 struct azx *chip;
2075
2076 if (!card)
2077 return;
2078 chip = card->private_data;
2079 if (chip && chip->running)
2080 azx_stop_chip(chip);
2081 }
2082
2083 /* PCI IDs */
2084 static const struct pci_device_id azx_ids[] = {
2085 /* CPT */
2086 { PCI_DEVICE(0x8086, 0x1c20),
2087 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2088 /* PBG */
2089 { PCI_DEVICE(0x8086, 0x1d20),
2090 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2091 /* Panther Point */
2092 { PCI_DEVICE(0x8086, 0x1e20),
2093 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2094 /* Lynx Point */
2095 { PCI_DEVICE(0x8086, 0x8c20),
2096 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2097 /* 9 Series */
2098 { PCI_DEVICE(0x8086, 0x8ca0),
2099 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2100 /* Wellsburg */
2101 { PCI_DEVICE(0x8086, 0x8d20),
2102 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2103 { PCI_DEVICE(0x8086, 0x8d21),
2104 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2105 /* Lynx Point-LP */
2106 { PCI_DEVICE(0x8086, 0x9c20),
2107 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2108 /* Lynx Point-LP */
2109 { PCI_DEVICE(0x8086, 0x9c21),
2110 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2111 /* Wildcat Point-LP */
2112 { PCI_DEVICE(0x8086, 0x9ca0),
2113 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2114 /* Sunrise Point */
2115 { PCI_DEVICE(0x8086, 0xa170),
2116 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2117 /* Sunrise Point-LP */
2118 { PCI_DEVICE(0x8086, 0x9d70),
2119 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2120 /* Haswell */
2121 { PCI_DEVICE(0x8086, 0x0a0c),
2122 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2123 { PCI_DEVICE(0x8086, 0x0c0c),
2124 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2125 { PCI_DEVICE(0x8086, 0x0d0c),
2126 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2127 /* Broadwell */
2128 { PCI_DEVICE(0x8086, 0x160c),
2129 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2130 /* 5 Series/3400 */
2131 { PCI_DEVICE(0x8086, 0x3b56),
2132 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2133 /* Poulsbo */
2134 { PCI_DEVICE(0x8086, 0x811b),
2135 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2136 /* Oaktrail */
2137 { PCI_DEVICE(0x8086, 0x080a),
2138 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2139 /* BayTrail */
2140 { PCI_DEVICE(0x8086, 0x0f04),
2141 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2142 /* Braswell */
2143 { PCI_DEVICE(0x8086, 0x2284),
2144 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2145 /* ICH6 */
2146 { PCI_DEVICE(0x8086, 0x2668),
2147 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2148 /* ICH7 */
2149 { PCI_DEVICE(0x8086, 0x27d8),
2150 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2151 /* ESB2 */
2152 { PCI_DEVICE(0x8086, 0x269a),
2153 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2154 /* ICH8 */
2155 { PCI_DEVICE(0x8086, 0x284b),
2156 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2157 /* ICH9 */
2158 { PCI_DEVICE(0x8086, 0x293e),
2159 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2160 /* ICH9 */
2161 { PCI_DEVICE(0x8086, 0x293f),
2162 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2163 /* ICH10 */
2164 { PCI_DEVICE(0x8086, 0x3a3e),
2165 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2166 /* ICH10 */
2167 { PCI_DEVICE(0x8086, 0x3a6e),
2168 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2169 /* Generic Intel */
2170 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2171 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2172 .class_mask = 0xffffff,
2173 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2174 /* ATI SB 450/600/700/800/900 */
2175 { PCI_DEVICE(0x1002, 0x437b),
2176 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2177 { PCI_DEVICE(0x1002, 0x4383),
2178 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2179 /* AMD Hudson */
2180 { PCI_DEVICE(0x1022, 0x780d),
2181 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2182 /* ATI HDMI */
2183 { PCI_DEVICE(0x1002, 0x1308),
2184 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2185 { PCI_DEVICE(0x1002, 0x793b),
2186 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2187 { PCI_DEVICE(0x1002, 0x7919),
2188 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2189 { PCI_DEVICE(0x1002, 0x960f),
2190 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2191 { PCI_DEVICE(0x1002, 0x970f),
2192 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2193 { PCI_DEVICE(0x1002, 0x9840),
2194 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2195 { PCI_DEVICE(0x1002, 0xaa00),
2196 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2197 { PCI_DEVICE(0x1002, 0xaa08),
2198 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2199 { PCI_DEVICE(0x1002, 0xaa10),
2200 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2201 { PCI_DEVICE(0x1002, 0xaa18),
2202 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2203 { PCI_DEVICE(0x1002, 0xaa20),
2204 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2205 { PCI_DEVICE(0x1002, 0xaa28),
2206 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2207 { PCI_DEVICE(0x1002, 0xaa30),
2208 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209 { PCI_DEVICE(0x1002, 0xaa38),
2210 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2211 { PCI_DEVICE(0x1002, 0xaa40),
2212 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213 { PCI_DEVICE(0x1002, 0xaa48),
2214 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215 { PCI_DEVICE(0x1002, 0xaa50),
2216 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2217 { PCI_DEVICE(0x1002, 0xaa58),
2218 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219 { PCI_DEVICE(0x1002, 0xaa60),
2220 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221 { PCI_DEVICE(0x1002, 0xaa68),
2222 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223 { PCI_DEVICE(0x1002, 0xaa80),
2224 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2225 { PCI_DEVICE(0x1002, 0xaa88),
2226 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2227 { PCI_DEVICE(0x1002, 0xaa90),
2228 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2229 { PCI_DEVICE(0x1002, 0xaa98),
2230 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2231 { PCI_DEVICE(0x1002, 0x9902),
2232 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2233 { PCI_DEVICE(0x1002, 0xaaa0),
2234 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2235 { PCI_DEVICE(0x1002, 0xaaa8),
2236 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2237 { PCI_DEVICE(0x1002, 0xaab0),
2238 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2239 { PCI_DEVICE(0x1002, 0xaac8),
2240 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2241 /* VIA VT8251/VT8237A */
2242 { PCI_DEVICE(0x1106, 0x3288),
2243 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2244 /* VIA GFX VT7122/VX900 */
2245 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2246 /* VIA GFX VT6122/VX11 */
2247 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2248 /* SIS966 */
2249 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2250 /* ULI M5461 */
2251 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2252 /* NVIDIA MCP */
2253 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2254 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2255 .class_mask = 0xffffff,
2256 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2257 /* Teradici */
2258 { PCI_DEVICE(0x6549, 0x1200),
2259 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2260 { PCI_DEVICE(0x6549, 0x2200),
2261 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2262 /* Creative X-Fi (CA0110-IBG) */
2263 /* CTHDA chips */
2264 { PCI_DEVICE(0x1102, 0x0010),
2265 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2266 { PCI_DEVICE(0x1102, 0x0012),
2267 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2268 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2269 /* the following entry conflicts with snd-ctxfi driver,
2270 * as ctxfi driver mutates from HD-audio to native mode with
2271 * a special command sequence.
2272 */
2273 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2274 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2275 .class_mask = 0xffffff,
2276 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2277 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2278 #else
2279 /* this entry seems still valid -- i.e. without emu20kx chip */
2280 { PCI_DEVICE(0x1102, 0x0009),
2281 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2282 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2283 #endif
2284 /* CM8888 */
2285 { PCI_DEVICE(0x13f6, 0x5011),
2286 .driver_data = AZX_DRIVER_CMEDIA |
2287 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2288 /* Vortex86MX */
2289 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2290 /* VMware HDAudio */
2291 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2292 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2293 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2294 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2295 .class_mask = 0xffffff,
2296 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2297 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2298 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2299 .class_mask = 0xffffff,
2300 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2301 { 0, }
2302 };
2303 MODULE_DEVICE_TABLE(pci, azx_ids);
2304
2305 /* pci_driver definition */
2306 static struct pci_driver azx_driver = {
2307 .name = KBUILD_MODNAME,
2308 .id_table = azx_ids,
2309 .probe = azx_probe,
2310 .remove = azx_remove,
2311 .shutdown = azx_shutdown,
2312 .driver = {
2313 .pm = AZX_PM_OPS,
2314 },
2315 };
2316
2317 module_pci_driver(azx_driver);
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