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[mirror_ubuntu-bionic-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #ifdef CONFIG_X86
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
53 #endif
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include "hda_codec.h"
57
58
59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62 static char *model[SNDRV_CARDS];
63 static int position_fix[SNDRV_CARDS];
64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
66 static int probe_only[SNDRV_CARDS];
67 static bool single_cmd;
68 static int enable_msi = -1;
69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
70 static char *patch[SNDRV_CARDS];
71 #endif
72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75 #endif
76
77 module_param_array(index, int, NULL, 0444);
78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79 module_param_array(id, charp, NULL, 0444);
80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81 module_param_array(enable, bool, NULL, 0444);
82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83 module_param_array(model, charp, NULL, 0444);
84 MODULE_PARM_DESC(model, "Use the given board model.");
85 module_param_array(position_fix, int, NULL, 0444);
86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
88 module_param_array(bdl_pos_adj, int, NULL, 0644);
89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90 module_param_array(probe_mask, int, NULL, 0444);
91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
92 module_param_array(probe_only, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
94 module_param(single_cmd, bool, 0444);
95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97 module_param(enable_msi, bint, 0444);
98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
100 module_param_array(patch, charp, NULL, 0444);
101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102 #endif
103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
104 module_param_array(beep_mode, int, NULL, 0444);
105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107 #endif
108
109 #ifdef CONFIG_SND_HDA_POWER_SAVE
110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111 module_param(power_save, int, 0644);
112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
114
115 /* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
119 static bool power_save_controller = 1;
120 module_param(power_save_controller, bool, 0644);
121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122 #endif
123
124 static int align_buffer_size = -1;
125 module_param(align_buffer_size, bint, 0644);
126 MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
129 #ifdef CONFIG_X86
130 static bool hda_snoop = true;
131 module_param_named(snoop, hda_snoop, bool, 0444);
132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133 #define azx_snoop(chip) (chip)->snoop
134 #else
135 #define hda_snoop true
136 #define azx_snoop(chip) true
137 #endif
138
139
140 MODULE_LICENSE("GPL");
141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
143 "{Intel, ICH7},"
144 "{Intel, ESB2},"
145 "{Intel, ICH8},"
146 "{Intel, ICH9},"
147 "{Intel, ICH10},"
148 "{Intel, PCH},"
149 "{Intel, CPT},"
150 "{Intel, PPT},"
151 "{Intel, LPT},"
152 "{Intel, PBG},"
153 "{Intel, SCH},"
154 "{ATI, SB450},"
155 "{ATI, SB600},"
156 "{ATI, RS600},"
157 "{ATI, RS690},"
158 "{ATI, RS780},"
159 "{ATI, R600},"
160 "{ATI, RV630},"
161 "{ATI, RV610},"
162 "{ATI, RV670},"
163 "{ATI, RV635},"
164 "{ATI, RV620},"
165 "{ATI, RV770},"
166 "{VIA, VT8251},"
167 "{VIA, VT8237A},"
168 "{SiS, SIS966},"
169 "{ULI, M5461}}");
170 MODULE_DESCRIPTION("Intel HDA driver");
171
172 #ifdef CONFIG_SND_VERBOSE_PRINTK
173 #define SFX /* nop */
174 #else
175 #define SFX "hda-intel: "
176 #endif
177
178 /*
179 * registers
180 */
181 #define ICH6_REG_GCAP 0x00
182 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
183 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
184 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
185 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
186 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
187 #define ICH6_REG_VMIN 0x02
188 #define ICH6_REG_VMAJ 0x03
189 #define ICH6_REG_OUTPAY 0x04
190 #define ICH6_REG_INPAY 0x06
191 #define ICH6_REG_GCTL 0x08
192 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
193 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
194 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
195 #define ICH6_REG_WAKEEN 0x0c
196 #define ICH6_REG_STATESTS 0x0e
197 #define ICH6_REG_GSTS 0x10
198 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
199 #define ICH6_REG_INTCTL 0x20
200 #define ICH6_REG_INTSTS 0x24
201 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
202 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
203 #define ICH6_REG_SSYNC 0x38
204 #define ICH6_REG_CORBLBASE 0x40
205 #define ICH6_REG_CORBUBASE 0x44
206 #define ICH6_REG_CORBWP 0x48
207 #define ICH6_REG_CORBRP 0x4a
208 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
209 #define ICH6_REG_CORBCTL 0x4c
210 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
211 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
212 #define ICH6_REG_CORBSTS 0x4d
213 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
214 #define ICH6_REG_CORBSIZE 0x4e
215
216 #define ICH6_REG_RIRBLBASE 0x50
217 #define ICH6_REG_RIRBUBASE 0x54
218 #define ICH6_REG_RIRBWP 0x58
219 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
220 #define ICH6_REG_RINTCNT 0x5a
221 #define ICH6_REG_RIRBCTL 0x5c
222 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
223 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
224 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
225 #define ICH6_REG_RIRBSTS 0x5d
226 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
227 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
228 #define ICH6_REG_RIRBSIZE 0x5e
229
230 #define ICH6_REG_IC 0x60
231 #define ICH6_REG_IR 0x64
232 #define ICH6_REG_IRS 0x68
233 #define ICH6_IRS_VALID (1<<1)
234 #define ICH6_IRS_BUSY (1<<0)
235
236 #define ICH6_REG_DPLBASE 0x70
237 #define ICH6_REG_DPUBASE 0x74
238 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
239
240 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
241 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
242
243 /* stream register offsets from stream base */
244 #define ICH6_REG_SD_CTL 0x00
245 #define ICH6_REG_SD_STS 0x03
246 #define ICH6_REG_SD_LPIB 0x04
247 #define ICH6_REG_SD_CBL 0x08
248 #define ICH6_REG_SD_LVI 0x0c
249 #define ICH6_REG_SD_FIFOW 0x0e
250 #define ICH6_REG_SD_FIFOSIZE 0x10
251 #define ICH6_REG_SD_FORMAT 0x12
252 #define ICH6_REG_SD_BDLPL 0x18
253 #define ICH6_REG_SD_BDLPU 0x1c
254
255 /* PCI space */
256 #define ICH6_PCIREG_TCSEL 0x44
257
258 /*
259 * other constants
260 */
261
262 /* max number of SDs */
263 /* ICH, ATI and VIA have 4 playback and 4 capture */
264 #define ICH6_NUM_CAPTURE 4
265 #define ICH6_NUM_PLAYBACK 4
266
267 /* ULI has 6 playback and 5 capture */
268 #define ULI_NUM_CAPTURE 5
269 #define ULI_NUM_PLAYBACK 6
270
271 /* ATI HDMI has 1 playback and 0 capture */
272 #define ATIHDMI_NUM_CAPTURE 0
273 #define ATIHDMI_NUM_PLAYBACK 1
274
275 /* TERA has 4 playback and 3 capture */
276 #define TERA_NUM_CAPTURE 3
277 #define TERA_NUM_PLAYBACK 4
278
279 /* this number is statically defined for simplicity */
280 #define MAX_AZX_DEV 16
281
282 /* max number of fragments - we may use more if allocating more pages for BDL */
283 #define BDL_SIZE 4096
284 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
285 #define AZX_MAX_FRAG 32
286 /* max buffer size - no h/w limit, you can increase as you like */
287 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
288
289 /* RIRB int mask: overrun[2], response[0] */
290 #define RIRB_INT_RESPONSE 0x01
291 #define RIRB_INT_OVERRUN 0x04
292 #define RIRB_INT_MASK 0x05
293
294 /* STATESTS int mask: S3,SD2,SD1,SD0 */
295 #define AZX_MAX_CODECS 8
296 #define AZX_DEFAULT_CODECS 4
297 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
298
299 /* SD_CTL bits */
300 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
301 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
302 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
303 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
304 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
305 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
306 #define SD_CTL_STREAM_TAG_SHIFT 20
307
308 /* SD_CTL and SD_STS */
309 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
310 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
311 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
312 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
313 SD_INT_COMPLETE)
314
315 /* SD_STS */
316 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
317
318 /* INTCTL and INTSTS */
319 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
320 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
321 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
322
323 /* below are so far hardcoded - should read registers in future */
324 #define ICH6_MAX_CORB_ENTRIES 256
325 #define ICH6_MAX_RIRB_ENTRIES 256
326
327 /* position fix mode */
328 enum {
329 POS_FIX_AUTO,
330 POS_FIX_LPIB,
331 POS_FIX_POSBUF,
332 POS_FIX_VIACOMBO,
333 POS_FIX_COMBO,
334 };
335
336 /* Defines for ATI HD Audio support in SB450 south bridge */
337 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
338 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
339
340 /* Defines for Nvidia HDA support */
341 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
342 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
343 #define NVIDIA_HDA_ISTRM_COH 0x4d
344 #define NVIDIA_HDA_OSTRM_COH 0x4c
345 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
346
347 /* Defines for Intel SCH HDA snoop control */
348 #define INTEL_SCH_HDA_DEVC 0x78
349 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
350
351 /* Define IN stream 0 FIFO size offset in VIA controller */
352 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
353 /* Define VIA HD Audio Device ID*/
354 #define VIA_HDAC_DEVICE_ID 0x3288
355
356 /* HD Audio class code */
357 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
358
359 /*
360 */
361
362 struct azx_dev {
363 struct snd_dma_buffer bdl; /* BDL buffer */
364 u32 *posbuf; /* position buffer pointer */
365
366 unsigned int bufsize; /* size of the play buffer in bytes */
367 unsigned int period_bytes; /* size of the period in bytes */
368 unsigned int frags; /* number for period in the play buffer */
369 unsigned int fifo_size; /* FIFO size */
370 unsigned long start_wallclk; /* start + minimum wallclk */
371 unsigned long period_wallclk; /* wallclk for period */
372
373 void __iomem *sd_addr; /* stream descriptor pointer */
374
375 u32 sd_int_sta_mask; /* stream int status mask */
376
377 /* pcm support */
378 struct snd_pcm_substream *substream; /* assigned substream,
379 * set in PCM open
380 */
381 unsigned int format_val; /* format value to be set in the
382 * controller and the codec
383 */
384 unsigned char stream_tag; /* assigned stream */
385 unsigned char index; /* stream index */
386 int assigned_key; /* last device# key assigned to */
387
388 unsigned int opened :1;
389 unsigned int running :1;
390 unsigned int irq_pending :1;
391 /*
392 * For VIA:
393 * A flag to ensure DMA position is 0
394 * when link position is not greater than FIFO size
395 */
396 unsigned int insufficient :1;
397 unsigned int wc_marked:1;
398 };
399
400 /* CORB/RIRB */
401 struct azx_rb {
402 u32 *buf; /* CORB/RIRB buffer
403 * Each CORB entry is 4byte, RIRB is 8byte
404 */
405 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
406 /* for RIRB */
407 unsigned short rp, wp; /* read/write pointers */
408 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
409 u32 res[AZX_MAX_CODECS]; /* last read value */
410 };
411
412 struct azx_pcm {
413 struct azx *chip;
414 struct snd_pcm *pcm;
415 struct hda_codec *codec;
416 struct hda_pcm_stream *hinfo[2];
417 struct list_head list;
418 };
419
420 struct azx {
421 struct snd_card *card;
422 struct pci_dev *pci;
423 int dev_index;
424
425 /* chip type specific */
426 int driver_type;
427 unsigned int driver_caps;
428 int playback_streams;
429 int playback_index_offset;
430 int capture_streams;
431 int capture_index_offset;
432 int num_streams;
433
434 /* pci resources */
435 unsigned long addr;
436 void __iomem *remap_addr;
437 int irq;
438
439 /* locks */
440 spinlock_t reg_lock;
441 struct mutex open_mutex;
442
443 /* streams (x num_streams) */
444 struct azx_dev *azx_dev;
445
446 /* PCM */
447 struct list_head pcm_list; /* azx_pcm list */
448
449 /* HD codec */
450 unsigned short codec_mask;
451 int codec_probe_mask; /* copied from probe_mask option */
452 struct hda_bus *bus;
453 unsigned int beep_mode;
454
455 /* CORB/RIRB */
456 struct azx_rb corb;
457 struct azx_rb rirb;
458
459 /* CORB/RIRB and position buffers */
460 struct snd_dma_buffer rb;
461 struct snd_dma_buffer posbuf;
462
463 /* flags */
464 int position_fix[2]; /* for both playback/capture streams */
465 int poll_count;
466 unsigned int running :1;
467 unsigned int initialized :1;
468 unsigned int single_cmd :1;
469 unsigned int polling_mode :1;
470 unsigned int msi :1;
471 unsigned int irq_pending_warned :1;
472 unsigned int probing :1; /* codec probing phase */
473 unsigned int snoop:1;
474 unsigned int align_buffer_size:1;
475
476 /* for debugging */
477 unsigned int last_cmd[AZX_MAX_CODECS];
478
479 /* for pending irqs */
480 struct work_struct irq_pending_work;
481
482 /* reboot notifier (for mysterious hangup problem at power-down) */
483 struct notifier_block reboot_notifier;
484 };
485
486 /* driver types */
487 enum {
488 AZX_DRIVER_ICH,
489 AZX_DRIVER_PCH,
490 AZX_DRIVER_SCH,
491 AZX_DRIVER_ATI,
492 AZX_DRIVER_ATIHDMI,
493 AZX_DRIVER_ATIHDMI_NS,
494 AZX_DRIVER_VIA,
495 AZX_DRIVER_SIS,
496 AZX_DRIVER_ULI,
497 AZX_DRIVER_NVIDIA,
498 AZX_DRIVER_TERA,
499 AZX_DRIVER_CTX,
500 AZX_DRIVER_GENERIC,
501 AZX_NUM_DRIVERS, /* keep this as last entry */
502 };
503
504 /* driver quirks (capabilities) */
505 /* bits 0-7 are used for indicating driver type */
506 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
507 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
508 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
509 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
510 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
511 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
512 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
513 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
514 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
515 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
516 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
517 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
518 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
519 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
520 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
521
522 /* quirks for ATI SB / AMD Hudson */
523 #define AZX_DCAPS_PRESET_ATI_SB \
524 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
525 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
526
527 /* quirks for ATI/AMD HDMI */
528 #define AZX_DCAPS_PRESET_ATI_HDMI \
529 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
530
531 /* quirks for Nvidia */
532 #define AZX_DCAPS_PRESET_NVIDIA \
533 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
534 AZX_DCAPS_ALIGN_BUFSIZE)
535
536 static char *driver_short_names[] __devinitdata = {
537 [AZX_DRIVER_ICH] = "HDA Intel",
538 [AZX_DRIVER_PCH] = "HDA Intel PCH",
539 [AZX_DRIVER_SCH] = "HDA Intel MID",
540 [AZX_DRIVER_ATI] = "HDA ATI SB",
541 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
542 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
543 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
544 [AZX_DRIVER_SIS] = "HDA SIS966",
545 [AZX_DRIVER_ULI] = "HDA ULI M5461",
546 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
547 [AZX_DRIVER_TERA] = "HDA Teradici",
548 [AZX_DRIVER_CTX] = "HDA Creative",
549 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
550 };
551
552 /*
553 * macros for easy use
554 */
555 #define azx_writel(chip,reg,value) \
556 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
557 #define azx_readl(chip,reg) \
558 readl((chip)->remap_addr + ICH6_REG_##reg)
559 #define azx_writew(chip,reg,value) \
560 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
561 #define azx_readw(chip,reg) \
562 readw((chip)->remap_addr + ICH6_REG_##reg)
563 #define azx_writeb(chip,reg,value) \
564 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
565 #define azx_readb(chip,reg) \
566 readb((chip)->remap_addr + ICH6_REG_##reg)
567
568 #define azx_sd_writel(dev,reg,value) \
569 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
570 #define azx_sd_readl(dev,reg) \
571 readl((dev)->sd_addr + ICH6_REG_##reg)
572 #define azx_sd_writew(dev,reg,value) \
573 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
574 #define azx_sd_readw(dev,reg) \
575 readw((dev)->sd_addr + ICH6_REG_##reg)
576 #define azx_sd_writeb(dev,reg,value) \
577 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
578 #define azx_sd_readb(dev,reg) \
579 readb((dev)->sd_addr + ICH6_REG_##reg)
580
581 /* for pcm support */
582 #define get_azx_dev(substream) (substream->runtime->private_data)
583
584 #ifdef CONFIG_X86
585 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
586 {
587 if (azx_snoop(chip))
588 return;
589 if (addr && size) {
590 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
591 if (on)
592 set_memory_wc((unsigned long)addr, pages);
593 else
594 set_memory_wb((unsigned long)addr, pages);
595 }
596 }
597
598 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
599 bool on)
600 {
601 __mark_pages_wc(chip, buf->area, buf->bytes, on);
602 }
603 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
604 struct snd_pcm_runtime *runtime, bool on)
605 {
606 if (azx_dev->wc_marked != on) {
607 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
608 azx_dev->wc_marked = on;
609 }
610 }
611 #else
612 /* NOP for other archs */
613 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
614 bool on)
615 {
616 }
617 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
618 struct snd_pcm_runtime *runtime, bool on)
619 {
620 }
621 #endif
622
623 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
624 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
625 /*
626 * Interface for HD codec
627 */
628
629 /*
630 * CORB / RIRB interface
631 */
632 static int azx_alloc_cmd_io(struct azx *chip)
633 {
634 int err;
635
636 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
637 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
638 snd_dma_pci_data(chip->pci),
639 PAGE_SIZE, &chip->rb);
640 if (err < 0) {
641 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
642 return err;
643 }
644 mark_pages_wc(chip, &chip->rb, true);
645 return 0;
646 }
647
648 static void azx_init_cmd_io(struct azx *chip)
649 {
650 spin_lock_irq(&chip->reg_lock);
651 /* CORB set up */
652 chip->corb.addr = chip->rb.addr;
653 chip->corb.buf = (u32 *)chip->rb.area;
654 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
655 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
656
657 /* set the corb size to 256 entries (ULI requires explicitly) */
658 azx_writeb(chip, CORBSIZE, 0x02);
659 /* set the corb write pointer to 0 */
660 azx_writew(chip, CORBWP, 0);
661 /* reset the corb hw read pointer */
662 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
663 /* enable corb dma */
664 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
665
666 /* RIRB set up */
667 chip->rirb.addr = chip->rb.addr + 2048;
668 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
669 chip->rirb.wp = chip->rirb.rp = 0;
670 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
671 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
672 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
673
674 /* set the rirb size to 256 entries (ULI requires explicitly) */
675 azx_writeb(chip, RIRBSIZE, 0x02);
676 /* reset the rirb hw write pointer */
677 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
678 /* set N=1, get RIRB response interrupt for new entry */
679 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
680 azx_writew(chip, RINTCNT, 0xc0);
681 else
682 azx_writew(chip, RINTCNT, 1);
683 /* enable rirb dma and response irq */
684 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
685 spin_unlock_irq(&chip->reg_lock);
686 }
687
688 static void azx_free_cmd_io(struct azx *chip)
689 {
690 spin_lock_irq(&chip->reg_lock);
691 /* disable ringbuffer DMAs */
692 azx_writeb(chip, RIRBCTL, 0);
693 azx_writeb(chip, CORBCTL, 0);
694 spin_unlock_irq(&chip->reg_lock);
695 }
696
697 static unsigned int azx_command_addr(u32 cmd)
698 {
699 unsigned int addr = cmd >> 28;
700
701 if (addr >= AZX_MAX_CODECS) {
702 snd_BUG();
703 addr = 0;
704 }
705
706 return addr;
707 }
708
709 static unsigned int azx_response_addr(u32 res)
710 {
711 unsigned int addr = res & 0xf;
712
713 if (addr >= AZX_MAX_CODECS) {
714 snd_BUG();
715 addr = 0;
716 }
717
718 return addr;
719 }
720
721 /* send a command */
722 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
723 {
724 struct azx *chip = bus->private_data;
725 unsigned int addr = azx_command_addr(val);
726 unsigned int wp;
727
728 spin_lock_irq(&chip->reg_lock);
729
730 /* add command to corb */
731 wp = azx_readb(chip, CORBWP);
732 wp++;
733 wp %= ICH6_MAX_CORB_ENTRIES;
734
735 chip->rirb.cmds[addr]++;
736 chip->corb.buf[wp] = cpu_to_le32(val);
737 azx_writel(chip, CORBWP, wp);
738
739 spin_unlock_irq(&chip->reg_lock);
740
741 return 0;
742 }
743
744 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
745
746 /* retrieve RIRB entry - called from interrupt handler */
747 static void azx_update_rirb(struct azx *chip)
748 {
749 unsigned int rp, wp;
750 unsigned int addr;
751 u32 res, res_ex;
752
753 wp = azx_readb(chip, RIRBWP);
754 if (wp == chip->rirb.wp)
755 return;
756 chip->rirb.wp = wp;
757
758 while (chip->rirb.rp != wp) {
759 chip->rirb.rp++;
760 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
761
762 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
763 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
764 res = le32_to_cpu(chip->rirb.buf[rp]);
765 addr = azx_response_addr(res_ex);
766 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
767 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
768 else if (chip->rirb.cmds[addr]) {
769 chip->rirb.res[addr] = res;
770 smp_wmb();
771 chip->rirb.cmds[addr]--;
772 } else
773 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
774 "last cmd=%#08x\n",
775 res, res_ex,
776 chip->last_cmd[addr]);
777 }
778 }
779
780 /* receive a response */
781 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
782 unsigned int addr)
783 {
784 struct azx *chip = bus->private_data;
785 unsigned long timeout;
786 int do_poll = 0;
787
788 again:
789 timeout = jiffies + msecs_to_jiffies(1000);
790 for (;;) {
791 if (chip->polling_mode || do_poll) {
792 spin_lock_irq(&chip->reg_lock);
793 azx_update_rirb(chip);
794 spin_unlock_irq(&chip->reg_lock);
795 }
796 if (!chip->rirb.cmds[addr]) {
797 smp_rmb();
798 bus->rirb_error = 0;
799
800 if (!do_poll)
801 chip->poll_count = 0;
802 return chip->rirb.res[addr]; /* the last value */
803 }
804 if (time_after(jiffies, timeout))
805 break;
806 if (bus->needs_damn_long_delay)
807 msleep(2); /* temporary workaround */
808 else {
809 udelay(10);
810 cond_resched();
811 }
812 }
813
814 if (!chip->polling_mode && chip->poll_count < 2) {
815 snd_printdd(SFX "azx_get_response timeout, "
816 "polling the codec once: last cmd=0x%08x\n",
817 chip->last_cmd[addr]);
818 do_poll = 1;
819 chip->poll_count++;
820 goto again;
821 }
822
823
824 if (!chip->polling_mode) {
825 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
826 "switching to polling mode: last cmd=0x%08x\n",
827 chip->last_cmd[addr]);
828 chip->polling_mode = 1;
829 goto again;
830 }
831
832 if (chip->msi) {
833 snd_printk(KERN_WARNING SFX "No response from codec, "
834 "disabling MSI: last cmd=0x%08x\n",
835 chip->last_cmd[addr]);
836 free_irq(chip->irq, chip);
837 chip->irq = -1;
838 pci_disable_msi(chip->pci);
839 chip->msi = 0;
840 if (azx_acquire_irq(chip, 1) < 0) {
841 bus->rirb_error = 1;
842 return -1;
843 }
844 goto again;
845 }
846
847 if (chip->probing) {
848 /* If this critical timeout happens during the codec probing
849 * phase, this is likely an access to a non-existing codec
850 * slot. Better to return an error and reset the system.
851 */
852 return -1;
853 }
854
855 /* a fatal communication error; need either to reset or to fallback
856 * to the single_cmd mode
857 */
858 bus->rirb_error = 1;
859 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
860 bus->response_reset = 1;
861 return -1; /* give a chance to retry */
862 }
863
864 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
865 "switching to single_cmd mode: last cmd=0x%08x\n",
866 chip->last_cmd[addr]);
867 chip->single_cmd = 1;
868 bus->response_reset = 0;
869 /* release CORB/RIRB */
870 azx_free_cmd_io(chip);
871 /* disable unsolicited responses */
872 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
873 return -1;
874 }
875
876 /*
877 * Use the single immediate command instead of CORB/RIRB for simplicity
878 *
879 * Note: according to Intel, this is not preferred use. The command was
880 * intended for the BIOS only, and may get confused with unsolicited
881 * responses. So, we shouldn't use it for normal operation from the
882 * driver.
883 * I left the codes, however, for debugging/testing purposes.
884 */
885
886 /* receive a response */
887 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
888 {
889 int timeout = 50;
890
891 while (timeout--) {
892 /* check IRV busy bit */
893 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
894 /* reuse rirb.res as the response return value */
895 chip->rirb.res[addr] = azx_readl(chip, IR);
896 return 0;
897 }
898 udelay(1);
899 }
900 if (printk_ratelimit())
901 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
902 azx_readw(chip, IRS));
903 chip->rirb.res[addr] = -1;
904 return -EIO;
905 }
906
907 /* send a command */
908 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
909 {
910 struct azx *chip = bus->private_data;
911 unsigned int addr = azx_command_addr(val);
912 int timeout = 50;
913
914 bus->rirb_error = 0;
915 while (timeout--) {
916 /* check ICB busy bit */
917 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
918 /* Clear IRV valid bit */
919 azx_writew(chip, IRS, azx_readw(chip, IRS) |
920 ICH6_IRS_VALID);
921 azx_writel(chip, IC, val);
922 azx_writew(chip, IRS, azx_readw(chip, IRS) |
923 ICH6_IRS_BUSY);
924 return azx_single_wait_for_response(chip, addr);
925 }
926 udelay(1);
927 }
928 if (printk_ratelimit())
929 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
930 azx_readw(chip, IRS), val);
931 return -EIO;
932 }
933
934 /* receive a response */
935 static unsigned int azx_single_get_response(struct hda_bus *bus,
936 unsigned int addr)
937 {
938 struct azx *chip = bus->private_data;
939 return chip->rirb.res[addr];
940 }
941
942 /*
943 * The below are the main callbacks from hda_codec.
944 *
945 * They are just the skeleton to call sub-callbacks according to the
946 * current setting of chip->single_cmd.
947 */
948
949 /* send a command */
950 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
951 {
952 struct azx *chip = bus->private_data;
953
954 chip->last_cmd[azx_command_addr(val)] = val;
955 if (chip->single_cmd)
956 return azx_single_send_cmd(bus, val);
957 else
958 return azx_corb_send_cmd(bus, val);
959 }
960
961 /* get a response */
962 static unsigned int azx_get_response(struct hda_bus *bus,
963 unsigned int addr)
964 {
965 struct azx *chip = bus->private_data;
966 if (chip->single_cmd)
967 return azx_single_get_response(bus, addr);
968 else
969 return azx_rirb_get_response(bus, addr);
970 }
971
972 #ifdef CONFIG_SND_HDA_POWER_SAVE
973 static void azx_power_notify(struct hda_bus *bus);
974 #endif
975
976 /* reset codec link */
977 static int azx_reset(struct azx *chip, int full_reset)
978 {
979 int count;
980
981 if (!full_reset)
982 goto __skip;
983
984 /* clear STATESTS */
985 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
986
987 /* reset controller */
988 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
989
990 count = 50;
991 while (azx_readb(chip, GCTL) && --count)
992 msleep(1);
993
994 /* delay for >= 100us for codec PLL to settle per spec
995 * Rev 0.9 section 5.5.1
996 */
997 msleep(1);
998
999 /* Bring controller out of reset */
1000 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1001
1002 count = 50;
1003 while (!azx_readb(chip, GCTL) && --count)
1004 msleep(1);
1005
1006 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1007 msleep(1);
1008
1009 __skip:
1010 /* check to see if controller is ready */
1011 if (!azx_readb(chip, GCTL)) {
1012 snd_printd(SFX "azx_reset: controller not ready!\n");
1013 return -EBUSY;
1014 }
1015
1016 /* Accept unsolicited responses */
1017 if (!chip->single_cmd)
1018 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1019 ICH6_GCTL_UNSOL);
1020
1021 /* detect codecs */
1022 if (!chip->codec_mask) {
1023 chip->codec_mask = azx_readw(chip, STATESTS);
1024 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1025 }
1026
1027 return 0;
1028 }
1029
1030
1031 /*
1032 * Lowlevel interface
1033 */
1034
1035 /* enable interrupts */
1036 static void azx_int_enable(struct azx *chip)
1037 {
1038 /* enable controller CIE and GIE */
1039 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1040 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1041 }
1042
1043 /* disable interrupts */
1044 static void azx_int_disable(struct azx *chip)
1045 {
1046 int i;
1047
1048 /* disable interrupts in stream descriptor */
1049 for (i = 0; i < chip->num_streams; i++) {
1050 struct azx_dev *azx_dev = &chip->azx_dev[i];
1051 azx_sd_writeb(azx_dev, SD_CTL,
1052 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1053 }
1054
1055 /* disable SIE for all streams */
1056 azx_writeb(chip, INTCTL, 0);
1057
1058 /* disable controller CIE and GIE */
1059 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1060 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1061 }
1062
1063 /* clear interrupts */
1064 static void azx_int_clear(struct azx *chip)
1065 {
1066 int i;
1067
1068 /* clear stream status */
1069 for (i = 0; i < chip->num_streams; i++) {
1070 struct azx_dev *azx_dev = &chip->azx_dev[i];
1071 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1072 }
1073
1074 /* clear STATESTS */
1075 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1076
1077 /* clear rirb status */
1078 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1079
1080 /* clear int status */
1081 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1082 }
1083
1084 /* start a stream */
1085 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1086 {
1087 /*
1088 * Before stream start, initialize parameter
1089 */
1090 azx_dev->insufficient = 1;
1091
1092 /* enable SIE */
1093 azx_writel(chip, INTCTL,
1094 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1095 /* set DMA start and interrupt mask */
1096 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1097 SD_CTL_DMA_START | SD_INT_MASK);
1098 }
1099
1100 /* stop DMA */
1101 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1102 {
1103 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1104 ~(SD_CTL_DMA_START | SD_INT_MASK));
1105 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1106 }
1107
1108 /* stop a stream */
1109 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1110 {
1111 azx_stream_clear(chip, azx_dev);
1112 /* disable SIE */
1113 azx_writel(chip, INTCTL,
1114 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1115 }
1116
1117
1118 /*
1119 * reset and start the controller registers
1120 */
1121 static void azx_init_chip(struct azx *chip, int full_reset)
1122 {
1123 if (chip->initialized)
1124 return;
1125
1126 /* reset controller */
1127 azx_reset(chip, full_reset);
1128
1129 /* initialize interrupts */
1130 azx_int_clear(chip);
1131 azx_int_enable(chip);
1132
1133 /* initialize the codec command I/O */
1134 if (!chip->single_cmd)
1135 azx_init_cmd_io(chip);
1136
1137 /* program the position buffer */
1138 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1139 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1140
1141 chip->initialized = 1;
1142 }
1143
1144 /*
1145 * initialize the PCI registers
1146 */
1147 /* update bits in a PCI register byte */
1148 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1149 unsigned char mask, unsigned char val)
1150 {
1151 unsigned char data;
1152
1153 pci_read_config_byte(pci, reg, &data);
1154 data &= ~mask;
1155 data |= (val & mask);
1156 pci_write_config_byte(pci, reg, data);
1157 }
1158
1159 static void azx_init_pci(struct azx *chip)
1160 {
1161 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1162 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1163 * Ensuring these bits are 0 clears playback static on some HD Audio
1164 * codecs.
1165 * The PCI register TCSEL is defined in the Intel manuals.
1166 */
1167 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1168 snd_printdd(SFX "Clearing TCSEL\n");
1169 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1170 }
1171
1172 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1173 * we need to enable snoop.
1174 */
1175 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1176 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1177 update_pci_byte(chip->pci,
1178 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1179 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1180 }
1181
1182 /* For NVIDIA HDA, enable snoop */
1183 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1184 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1185 update_pci_byte(chip->pci,
1186 NVIDIA_HDA_TRANSREG_ADDR,
1187 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1188 update_pci_byte(chip->pci,
1189 NVIDIA_HDA_ISTRM_COH,
1190 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1191 update_pci_byte(chip->pci,
1192 NVIDIA_HDA_OSTRM_COH,
1193 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1194 }
1195
1196 /* Enable SCH/PCH snoop if needed */
1197 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1198 unsigned short snoop;
1199 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1200 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1201 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1202 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1203 if (!azx_snoop(chip))
1204 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1205 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1206 pci_read_config_word(chip->pci,
1207 INTEL_SCH_HDA_DEVC, &snoop);
1208 }
1209 snd_printdd(SFX "SCH snoop: %s\n",
1210 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1211 ? "Disabled" : "Enabled");
1212 }
1213 }
1214
1215
1216 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1217
1218 /*
1219 * interrupt handler
1220 */
1221 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1222 {
1223 struct azx *chip = dev_id;
1224 struct azx_dev *azx_dev;
1225 u32 status;
1226 u8 sd_status;
1227 int i, ok;
1228
1229 spin_lock(&chip->reg_lock);
1230
1231 status = azx_readl(chip, INTSTS);
1232 if (status == 0) {
1233 spin_unlock(&chip->reg_lock);
1234 return IRQ_NONE;
1235 }
1236
1237 for (i = 0; i < chip->num_streams; i++) {
1238 azx_dev = &chip->azx_dev[i];
1239 if (status & azx_dev->sd_int_sta_mask) {
1240 sd_status = azx_sd_readb(azx_dev, SD_STS);
1241 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1242 if (!azx_dev->substream || !azx_dev->running ||
1243 !(sd_status & SD_INT_COMPLETE))
1244 continue;
1245 /* check whether this IRQ is really acceptable */
1246 ok = azx_position_ok(chip, azx_dev);
1247 if (ok == 1) {
1248 azx_dev->irq_pending = 0;
1249 spin_unlock(&chip->reg_lock);
1250 snd_pcm_period_elapsed(azx_dev->substream);
1251 spin_lock(&chip->reg_lock);
1252 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1253 /* bogus IRQ, process it later */
1254 azx_dev->irq_pending = 1;
1255 queue_work(chip->bus->workq,
1256 &chip->irq_pending_work);
1257 }
1258 }
1259 }
1260
1261 /* clear rirb int */
1262 status = azx_readb(chip, RIRBSTS);
1263 if (status & RIRB_INT_MASK) {
1264 if (status & RIRB_INT_RESPONSE) {
1265 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1266 udelay(80);
1267 azx_update_rirb(chip);
1268 }
1269 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1270 }
1271
1272 #if 0
1273 /* clear state status int */
1274 if (azx_readb(chip, STATESTS) & 0x04)
1275 azx_writeb(chip, STATESTS, 0x04);
1276 #endif
1277 spin_unlock(&chip->reg_lock);
1278
1279 return IRQ_HANDLED;
1280 }
1281
1282
1283 /*
1284 * set up a BDL entry
1285 */
1286 static int setup_bdle(struct snd_pcm_substream *substream,
1287 struct azx_dev *azx_dev, u32 **bdlp,
1288 int ofs, int size, int with_ioc)
1289 {
1290 u32 *bdl = *bdlp;
1291
1292 while (size > 0) {
1293 dma_addr_t addr;
1294 int chunk;
1295
1296 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1297 return -EINVAL;
1298
1299 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1300 /* program the address field of the BDL entry */
1301 bdl[0] = cpu_to_le32((u32)addr);
1302 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1303 /* program the size field of the BDL entry */
1304 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1305 bdl[2] = cpu_to_le32(chunk);
1306 /* program the IOC to enable interrupt
1307 * only when the whole fragment is processed
1308 */
1309 size -= chunk;
1310 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1311 bdl += 4;
1312 azx_dev->frags++;
1313 ofs += chunk;
1314 }
1315 *bdlp = bdl;
1316 return ofs;
1317 }
1318
1319 /*
1320 * set up BDL entries
1321 */
1322 static int azx_setup_periods(struct azx *chip,
1323 struct snd_pcm_substream *substream,
1324 struct azx_dev *azx_dev)
1325 {
1326 u32 *bdl;
1327 int i, ofs, periods, period_bytes;
1328 int pos_adj;
1329
1330 /* reset BDL address */
1331 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1332 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1333
1334 period_bytes = azx_dev->period_bytes;
1335 periods = azx_dev->bufsize / period_bytes;
1336
1337 /* program the initial BDL entries */
1338 bdl = (u32 *)azx_dev->bdl.area;
1339 ofs = 0;
1340 azx_dev->frags = 0;
1341 pos_adj = bdl_pos_adj[chip->dev_index];
1342 if (pos_adj > 0) {
1343 struct snd_pcm_runtime *runtime = substream->runtime;
1344 int pos_align = pos_adj;
1345 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1346 if (!pos_adj)
1347 pos_adj = pos_align;
1348 else
1349 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1350 pos_align;
1351 pos_adj = frames_to_bytes(runtime, pos_adj);
1352 if (pos_adj >= period_bytes) {
1353 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1354 bdl_pos_adj[chip->dev_index]);
1355 pos_adj = 0;
1356 } else {
1357 ofs = setup_bdle(substream, azx_dev,
1358 &bdl, ofs, pos_adj,
1359 !substream->runtime->no_period_wakeup);
1360 if (ofs < 0)
1361 goto error;
1362 }
1363 } else
1364 pos_adj = 0;
1365 for (i = 0; i < periods; i++) {
1366 if (i == periods - 1 && pos_adj)
1367 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1368 period_bytes - pos_adj, 0);
1369 else
1370 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1371 period_bytes,
1372 !substream->runtime->no_period_wakeup);
1373 if (ofs < 0)
1374 goto error;
1375 }
1376 return 0;
1377
1378 error:
1379 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1380 azx_dev->bufsize, period_bytes);
1381 return -EINVAL;
1382 }
1383
1384 /* reset stream */
1385 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1386 {
1387 unsigned char val;
1388 int timeout;
1389
1390 azx_stream_clear(chip, azx_dev);
1391
1392 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1393 SD_CTL_STREAM_RESET);
1394 udelay(3);
1395 timeout = 300;
1396 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1397 --timeout)
1398 ;
1399 val &= ~SD_CTL_STREAM_RESET;
1400 azx_sd_writeb(azx_dev, SD_CTL, val);
1401 udelay(3);
1402
1403 timeout = 300;
1404 /* waiting for hardware to report that the stream is out of reset */
1405 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1406 --timeout)
1407 ;
1408
1409 /* reset first position - may not be synced with hw at this time */
1410 *azx_dev->posbuf = 0;
1411 }
1412
1413 /*
1414 * set up the SD for streaming
1415 */
1416 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1417 {
1418 unsigned int val;
1419 /* make sure the run bit is zero for SD */
1420 azx_stream_clear(chip, azx_dev);
1421 /* program the stream_tag */
1422 val = azx_sd_readl(azx_dev, SD_CTL);
1423 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1424 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1425 if (!azx_snoop(chip))
1426 val |= SD_CTL_TRAFFIC_PRIO;
1427 azx_sd_writel(azx_dev, SD_CTL, val);
1428
1429 /* program the length of samples in cyclic buffer */
1430 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1431
1432 /* program the stream format */
1433 /* this value needs to be the same as the one programmed */
1434 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1435
1436 /* program the stream LVI (last valid index) of the BDL */
1437 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1438
1439 /* program the BDL address */
1440 /* lower BDL address */
1441 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1442 /* upper BDL address */
1443 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1444
1445 /* enable the position buffer */
1446 if (chip->position_fix[0] != POS_FIX_LPIB ||
1447 chip->position_fix[1] != POS_FIX_LPIB) {
1448 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1449 azx_writel(chip, DPLBASE,
1450 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1451 }
1452
1453 /* set the interrupt enable bits in the descriptor control register */
1454 azx_sd_writel(azx_dev, SD_CTL,
1455 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1456
1457 return 0;
1458 }
1459
1460 /*
1461 * Probe the given codec address
1462 */
1463 static int probe_codec(struct azx *chip, int addr)
1464 {
1465 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1466 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1467 unsigned int res;
1468
1469 mutex_lock(&chip->bus->cmd_mutex);
1470 chip->probing = 1;
1471 azx_send_cmd(chip->bus, cmd);
1472 res = azx_get_response(chip->bus, addr);
1473 chip->probing = 0;
1474 mutex_unlock(&chip->bus->cmd_mutex);
1475 if (res == -1)
1476 return -EIO;
1477 snd_printdd(SFX "codec #%d probed OK\n", addr);
1478 return 0;
1479 }
1480
1481 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1482 struct hda_pcm *cpcm);
1483 static void azx_stop_chip(struct azx *chip);
1484
1485 static void azx_bus_reset(struct hda_bus *bus)
1486 {
1487 struct azx *chip = bus->private_data;
1488
1489 bus->in_reset = 1;
1490 azx_stop_chip(chip);
1491 azx_init_chip(chip, 1);
1492 #ifdef CONFIG_PM
1493 if (chip->initialized) {
1494 struct azx_pcm *p;
1495 list_for_each_entry(p, &chip->pcm_list, list)
1496 snd_pcm_suspend_all(p->pcm);
1497 snd_hda_suspend(chip->bus);
1498 snd_hda_resume(chip->bus);
1499 }
1500 #endif
1501 bus->in_reset = 0;
1502 }
1503
1504 /*
1505 * Codec initialization
1506 */
1507
1508 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1509 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1510 [AZX_DRIVER_NVIDIA] = 8,
1511 [AZX_DRIVER_TERA] = 1,
1512 };
1513
1514 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1515 {
1516 struct hda_bus_template bus_temp;
1517 int c, codecs, err;
1518 int max_slots;
1519
1520 memset(&bus_temp, 0, sizeof(bus_temp));
1521 bus_temp.private_data = chip;
1522 bus_temp.modelname = model;
1523 bus_temp.pci = chip->pci;
1524 bus_temp.ops.command = azx_send_cmd;
1525 bus_temp.ops.get_response = azx_get_response;
1526 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1527 bus_temp.ops.bus_reset = azx_bus_reset;
1528 #ifdef CONFIG_SND_HDA_POWER_SAVE
1529 bus_temp.power_save = &power_save;
1530 bus_temp.ops.pm_notify = azx_power_notify;
1531 #endif
1532
1533 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1534 if (err < 0)
1535 return err;
1536
1537 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1538 snd_printd(SFX "Enable delay in RIRB handling\n");
1539 chip->bus->needs_damn_long_delay = 1;
1540 }
1541
1542 codecs = 0;
1543 max_slots = azx_max_codecs[chip->driver_type];
1544 if (!max_slots)
1545 max_slots = AZX_DEFAULT_CODECS;
1546
1547 /* First try to probe all given codec slots */
1548 for (c = 0; c < max_slots; c++) {
1549 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1550 if (probe_codec(chip, c) < 0) {
1551 /* Some BIOSen give you wrong codec addresses
1552 * that don't exist
1553 */
1554 snd_printk(KERN_WARNING SFX
1555 "Codec #%d probe error; "
1556 "disabling it...\n", c);
1557 chip->codec_mask &= ~(1 << c);
1558 /* More badly, accessing to a non-existing
1559 * codec often screws up the controller chip,
1560 * and disturbs the further communications.
1561 * Thus if an error occurs during probing,
1562 * better to reset the controller chip to
1563 * get back to the sanity state.
1564 */
1565 azx_stop_chip(chip);
1566 azx_init_chip(chip, 1);
1567 }
1568 }
1569 }
1570
1571 /* AMD chipsets often cause the communication stalls upon certain
1572 * sequence like the pin-detection. It seems that forcing the synced
1573 * access works around the stall. Grrr...
1574 */
1575 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1576 snd_printd(SFX "Enable sync_write for stable communication\n");
1577 chip->bus->sync_write = 1;
1578 chip->bus->allow_bus_reset = 1;
1579 }
1580
1581 /* Then create codec instances */
1582 for (c = 0; c < max_slots; c++) {
1583 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1584 struct hda_codec *codec;
1585 err = snd_hda_codec_new(chip->bus, c, &codec);
1586 if (err < 0)
1587 continue;
1588 codec->beep_mode = chip->beep_mode;
1589 codecs++;
1590 }
1591 }
1592 if (!codecs) {
1593 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1594 return -ENXIO;
1595 }
1596 return 0;
1597 }
1598
1599 /* configure each codec instance */
1600 static int __devinit azx_codec_configure(struct azx *chip)
1601 {
1602 struct hda_codec *codec;
1603 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1604 snd_hda_codec_configure(codec);
1605 }
1606 return 0;
1607 }
1608
1609
1610 /*
1611 * PCM support
1612 */
1613
1614 /* assign a stream for the PCM */
1615 static inline struct azx_dev *
1616 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1617 {
1618 int dev, i, nums;
1619 struct azx_dev *res = NULL;
1620 /* make a non-zero unique key for the substream */
1621 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1622 (substream->stream + 1);
1623
1624 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1625 dev = chip->playback_index_offset;
1626 nums = chip->playback_streams;
1627 } else {
1628 dev = chip->capture_index_offset;
1629 nums = chip->capture_streams;
1630 }
1631 for (i = 0; i < nums; i++, dev++)
1632 if (!chip->azx_dev[dev].opened) {
1633 res = &chip->azx_dev[dev];
1634 if (res->assigned_key == key)
1635 break;
1636 }
1637 if (res) {
1638 res->opened = 1;
1639 res->assigned_key = key;
1640 }
1641 return res;
1642 }
1643
1644 /* release the assigned stream */
1645 static inline void azx_release_device(struct azx_dev *azx_dev)
1646 {
1647 azx_dev->opened = 0;
1648 }
1649
1650 static struct snd_pcm_hardware azx_pcm_hw = {
1651 .info = (SNDRV_PCM_INFO_MMAP |
1652 SNDRV_PCM_INFO_INTERLEAVED |
1653 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1654 SNDRV_PCM_INFO_MMAP_VALID |
1655 /* No full-resume yet implemented */
1656 /* SNDRV_PCM_INFO_RESUME |*/
1657 SNDRV_PCM_INFO_PAUSE |
1658 SNDRV_PCM_INFO_SYNC_START |
1659 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1660 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1661 .rates = SNDRV_PCM_RATE_48000,
1662 .rate_min = 48000,
1663 .rate_max = 48000,
1664 .channels_min = 2,
1665 .channels_max = 2,
1666 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1667 .period_bytes_min = 128,
1668 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1669 .periods_min = 2,
1670 .periods_max = AZX_MAX_FRAG,
1671 .fifo_size = 0,
1672 };
1673
1674 static int azx_pcm_open(struct snd_pcm_substream *substream)
1675 {
1676 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1677 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1678 struct azx *chip = apcm->chip;
1679 struct azx_dev *azx_dev;
1680 struct snd_pcm_runtime *runtime = substream->runtime;
1681 unsigned long flags;
1682 int err;
1683 int buff_step;
1684
1685 mutex_lock(&chip->open_mutex);
1686 azx_dev = azx_assign_device(chip, substream);
1687 if (azx_dev == NULL) {
1688 mutex_unlock(&chip->open_mutex);
1689 return -EBUSY;
1690 }
1691 runtime->hw = azx_pcm_hw;
1692 runtime->hw.channels_min = hinfo->channels_min;
1693 runtime->hw.channels_max = hinfo->channels_max;
1694 runtime->hw.formats = hinfo->formats;
1695 runtime->hw.rates = hinfo->rates;
1696 snd_pcm_limit_hw_rates(runtime);
1697 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1698 if (chip->align_buffer_size)
1699 /* constrain buffer sizes to be multiple of 128
1700 bytes. This is more efficient in terms of memory
1701 access but isn't required by the HDA spec and
1702 prevents users from specifying exact period/buffer
1703 sizes. For example for 44.1kHz, a period size set
1704 to 20ms will be rounded to 19.59ms. */
1705 buff_step = 128;
1706 else
1707 /* Don't enforce steps on buffer sizes, still need to
1708 be multiple of 4 bytes (HDA spec). Tested on Intel
1709 HDA controllers, may not work on all devices where
1710 option needs to be disabled */
1711 buff_step = 4;
1712
1713 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1714 buff_step);
1715 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1716 buff_step);
1717 snd_hda_power_up(apcm->codec);
1718 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1719 if (err < 0) {
1720 azx_release_device(azx_dev);
1721 snd_hda_power_down(apcm->codec);
1722 mutex_unlock(&chip->open_mutex);
1723 return err;
1724 }
1725 snd_pcm_limit_hw_rates(runtime);
1726 /* sanity check */
1727 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1728 snd_BUG_ON(!runtime->hw.channels_max) ||
1729 snd_BUG_ON(!runtime->hw.formats) ||
1730 snd_BUG_ON(!runtime->hw.rates)) {
1731 azx_release_device(azx_dev);
1732 hinfo->ops.close(hinfo, apcm->codec, substream);
1733 snd_hda_power_down(apcm->codec);
1734 mutex_unlock(&chip->open_mutex);
1735 return -EINVAL;
1736 }
1737 spin_lock_irqsave(&chip->reg_lock, flags);
1738 azx_dev->substream = substream;
1739 azx_dev->running = 0;
1740 spin_unlock_irqrestore(&chip->reg_lock, flags);
1741
1742 runtime->private_data = azx_dev;
1743 snd_pcm_set_sync(substream);
1744 mutex_unlock(&chip->open_mutex);
1745 return 0;
1746 }
1747
1748 static int azx_pcm_close(struct snd_pcm_substream *substream)
1749 {
1750 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1751 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1752 struct azx *chip = apcm->chip;
1753 struct azx_dev *azx_dev = get_azx_dev(substream);
1754 unsigned long flags;
1755
1756 mutex_lock(&chip->open_mutex);
1757 spin_lock_irqsave(&chip->reg_lock, flags);
1758 azx_dev->substream = NULL;
1759 azx_dev->running = 0;
1760 spin_unlock_irqrestore(&chip->reg_lock, flags);
1761 azx_release_device(azx_dev);
1762 hinfo->ops.close(hinfo, apcm->codec, substream);
1763 snd_hda_power_down(apcm->codec);
1764 mutex_unlock(&chip->open_mutex);
1765 return 0;
1766 }
1767
1768 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1769 struct snd_pcm_hw_params *hw_params)
1770 {
1771 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1772 struct azx *chip = apcm->chip;
1773 struct snd_pcm_runtime *runtime = substream->runtime;
1774 struct azx_dev *azx_dev = get_azx_dev(substream);
1775 int ret;
1776
1777 mark_runtime_wc(chip, azx_dev, runtime, false);
1778 azx_dev->bufsize = 0;
1779 azx_dev->period_bytes = 0;
1780 azx_dev->format_val = 0;
1781 ret = snd_pcm_lib_malloc_pages(substream,
1782 params_buffer_bytes(hw_params));
1783 if (ret < 0)
1784 return ret;
1785 mark_runtime_wc(chip, azx_dev, runtime, true);
1786 return ret;
1787 }
1788
1789 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1790 {
1791 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1792 struct azx_dev *azx_dev = get_azx_dev(substream);
1793 struct azx *chip = apcm->chip;
1794 struct snd_pcm_runtime *runtime = substream->runtime;
1795 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1796
1797 /* reset BDL address */
1798 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1799 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1800 azx_sd_writel(azx_dev, SD_CTL, 0);
1801 azx_dev->bufsize = 0;
1802 azx_dev->period_bytes = 0;
1803 azx_dev->format_val = 0;
1804
1805 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1806
1807 mark_runtime_wc(chip, azx_dev, runtime, false);
1808 return snd_pcm_lib_free_pages(substream);
1809 }
1810
1811 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1812 {
1813 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1814 struct azx *chip = apcm->chip;
1815 struct azx_dev *azx_dev = get_azx_dev(substream);
1816 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1817 struct snd_pcm_runtime *runtime = substream->runtime;
1818 unsigned int bufsize, period_bytes, format_val, stream_tag;
1819 int err;
1820 struct hda_spdif_out *spdif =
1821 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1822 unsigned short ctls = spdif ? spdif->ctls : 0;
1823
1824 azx_stream_reset(chip, azx_dev);
1825 format_val = snd_hda_calc_stream_format(runtime->rate,
1826 runtime->channels,
1827 runtime->format,
1828 hinfo->maxbps,
1829 ctls);
1830 if (!format_val) {
1831 snd_printk(KERN_ERR SFX
1832 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1833 runtime->rate, runtime->channels, runtime->format);
1834 return -EINVAL;
1835 }
1836
1837 bufsize = snd_pcm_lib_buffer_bytes(substream);
1838 period_bytes = snd_pcm_lib_period_bytes(substream);
1839
1840 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1841 bufsize, format_val);
1842
1843 if (bufsize != azx_dev->bufsize ||
1844 period_bytes != azx_dev->period_bytes ||
1845 format_val != azx_dev->format_val) {
1846 azx_dev->bufsize = bufsize;
1847 azx_dev->period_bytes = period_bytes;
1848 azx_dev->format_val = format_val;
1849 err = azx_setup_periods(chip, substream, azx_dev);
1850 if (err < 0)
1851 return err;
1852 }
1853
1854 /* wallclk has 24Mhz clock source */
1855 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1856 runtime->rate) * 1000);
1857 azx_setup_controller(chip, azx_dev);
1858 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1859 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1860 else
1861 azx_dev->fifo_size = 0;
1862
1863 stream_tag = azx_dev->stream_tag;
1864 /* CA-IBG chips need the playback stream starting from 1 */
1865 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1866 stream_tag > chip->capture_streams)
1867 stream_tag -= chip->capture_streams;
1868 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1869 azx_dev->format_val, substream);
1870 }
1871
1872 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1873 {
1874 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1875 struct azx *chip = apcm->chip;
1876 struct azx_dev *azx_dev;
1877 struct snd_pcm_substream *s;
1878 int rstart = 0, start, nsync = 0, sbits = 0;
1879 int nwait, timeout;
1880
1881 switch (cmd) {
1882 case SNDRV_PCM_TRIGGER_START:
1883 rstart = 1;
1884 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1885 case SNDRV_PCM_TRIGGER_RESUME:
1886 start = 1;
1887 break;
1888 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1889 case SNDRV_PCM_TRIGGER_SUSPEND:
1890 case SNDRV_PCM_TRIGGER_STOP:
1891 start = 0;
1892 break;
1893 default:
1894 return -EINVAL;
1895 }
1896
1897 snd_pcm_group_for_each_entry(s, substream) {
1898 if (s->pcm->card != substream->pcm->card)
1899 continue;
1900 azx_dev = get_azx_dev(s);
1901 sbits |= 1 << azx_dev->index;
1902 nsync++;
1903 snd_pcm_trigger_done(s, substream);
1904 }
1905
1906 spin_lock(&chip->reg_lock);
1907 if (nsync > 1) {
1908 /* first, set SYNC bits of corresponding streams */
1909 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1910 azx_writel(chip, OLD_SSYNC,
1911 azx_readl(chip, OLD_SSYNC) | sbits);
1912 else
1913 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1914 }
1915 snd_pcm_group_for_each_entry(s, substream) {
1916 if (s->pcm->card != substream->pcm->card)
1917 continue;
1918 azx_dev = get_azx_dev(s);
1919 if (start) {
1920 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1921 if (!rstart)
1922 azx_dev->start_wallclk -=
1923 azx_dev->period_wallclk;
1924 azx_stream_start(chip, azx_dev);
1925 } else {
1926 azx_stream_stop(chip, azx_dev);
1927 }
1928 azx_dev->running = start;
1929 }
1930 spin_unlock(&chip->reg_lock);
1931 if (start) {
1932 if (nsync == 1)
1933 return 0;
1934 /* wait until all FIFOs get ready */
1935 for (timeout = 5000; timeout; timeout--) {
1936 nwait = 0;
1937 snd_pcm_group_for_each_entry(s, substream) {
1938 if (s->pcm->card != substream->pcm->card)
1939 continue;
1940 azx_dev = get_azx_dev(s);
1941 if (!(azx_sd_readb(azx_dev, SD_STS) &
1942 SD_STS_FIFO_READY))
1943 nwait++;
1944 }
1945 if (!nwait)
1946 break;
1947 cpu_relax();
1948 }
1949 } else {
1950 /* wait until all RUN bits are cleared */
1951 for (timeout = 5000; timeout; timeout--) {
1952 nwait = 0;
1953 snd_pcm_group_for_each_entry(s, substream) {
1954 if (s->pcm->card != substream->pcm->card)
1955 continue;
1956 azx_dev = get_azx_dev(s);
1957 if (azx_sd_readb(azx_dev, SD_CTL) &
1958 SD_CTL_DMA_START)
1959 nwait++;
1960 }
1961 if (!nwait)
1962 break;
1963 cpu_relax();
1964 }
1965 }
1966 if (nsync > 1) {
1967 spin_lock(&chip->reg_lock);
1968 /* reset SYNC bits */
1969 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1970 azx_writel(chip, OLD_SSYNC,
1971 azx_readl(chip, OLD_SSYNC) & ~sbits);
1972 else
1973 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1974 spin_unlock(&chip->reg_lock);
1975 }
1976 return 0;
1977 }
1978
1979 /* get the current DMA position with correction on VIA chips */
1980 static unsigned int azx_via_get_position(struct azx *chip,
1981 struct azx_dev *azx_dev)
1982 {
1983 unsigned int link_pos, mini_pos, bound_pos;
1984 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1985 unsigned int fifo_size;
1986
1987 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1988 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1989 /* Playback, no problem using link position */
1990 return link_pos;
1991 }
1992
1993 /* Capture */
1994 /* For new chipset,
1995 * use mod to get the DMA position just like old chipset
1996 */
1997 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1998 mod_dma_pos %= azx_dev->period_bytes;
1999
2000 /* azx_dev->fifo_size can't get FIFO size of in stream.
2001 * Get from base address + offset.
2002 */
2003 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2004
2005 if (azx_dev->insufficient) {
2006 /* Link position never gather than FIFO size */
2007 if (link_pos <= fifo_size)
2008 return 0;
2009
2010 azx_dev->insufficient = 0;
2011 }
2012
2013 if (link_pos <= fifo_size)
2014 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2015 else
2016 mini_pos = link_pos - fifo_size;
2017
2018 /* Find nearest previous boudary */
2019 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2020 mod_link_pos = link_pos % azx_dev->period_bytes;
2021 if (mod_link_pos >= fifo_size)
2022 bound_pos = link_pos - mod_link_pos;
2023 else if (mod_dma_pos >= mod_mini_pos)
2024 bound_pos = mini_pos - mod_mini_pos;
2025 else {
2026 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2027 if (bound_pos >= azx_dev->bufsize)
2028 bound_pos = 0;
2029 }
2030
2031 /* Calculate real DMA position we want */
2032 return bound_pos + mod_dma_pos;
2033 }
2034
2035 static unsigned int azx_get_position(struct azx *chip,
2036 struct azx_dev *azx_dev,
2037 bool with_check)
2038 {
2039 unsigned int pos;
2040 int stream = azx_dev->substream->stream;
2041
2042 switch (chip->position_fix[stream]) {
2043 case POS_FIX_LPIB:
2044 /* read LPIB */
2045 pos = azx_sd_readl(azx_dev, SD_LPIB);
2046 break;
2047 case POS_FIX_VIACOMBO:
2048 pos = azx_via_get_position(chip, azx_dev);
2049 break;
2050 default:
2051 /* use the position buffer */
2052 pos = le32_to_cpu(*azx_dev->posbuf);
2053 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2054 if (!pos || pos == (u32)-1) {
2055 printk(KERN_WARNING
2056 "hda-intel: Invalid position buffer, "
2057 "using LPIB read method instead.\n");
2058 chip->position_fix[stream] = POS_FIX_LPIB;
2059 pos = azx_sd_readl(azx_dev, SD_LPIB);
2060 } else
2061 chip->position_fix[stream] = POS_FIX_POSBUF;
2062 }
2063 break;
2064 }
2065
2066 if (pos >= azx_dev->bufsize)
2067 pos = 0;
2068 return pos;
2069 }
2070
2071 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2072 {
2073 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2074 struct azx *chip = apcm->chip;
2075 struct azx_dev *azx_dev = get_azx_dev(substream);
2076 return bytes_to_frames(substream->runtime,
2077 azx_get_position(chip, azx_dev, false));
2078 }
2079
2080 /*
2081 * Check whether the current DMA position is acceptable for updating
2082 * periods. Returns non-zero if it's OK.
2083 *
2084 * Many HD-audio controllers appear pretty inaccurate about
2085 * the update-IRQ timing. The IRQ is issued before actually the
2086 * data is processed. So, we need to process it afterwords in a
2087 * workqueue.
2088 */
2089 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2090 {
2091 u32 wallclk;
2092 unsigned int pos;
2093 int stream;
2094
2095 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2096 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2097 return -1; /* bogus (too early) interrupt */
2098
2099 stream = azx_dev->substream->stream;
2100 pos = azx_get_position(chip, azx_dev, true);
2101
2102 if (WARN_ONCE(!azx_dev->period_bytes,
2103 "hda-intel: zero azx_dev->period_bytes"))
2104 return -1; /* this shouldn't happen! */
2105 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2106 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2107 /* NG - it's below the first next period boundary */
2108 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2109 azx_dev->start_wallclk += wallclk;
2110 return 1; /* OK, it's fine */
2111 }
2112
2113 /*
2114 * The work for pending PCM period updates.
2115 */
2116 static void azx_irq_pending_work(struct work_struct *work)
2117 {
2118 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2119 int i, pending, ok;
2120
2121 if (!chip->irq_pending_warned) {
2122 printk(KERN_WARNING
2123 "hda-intel: IRQ timing workaround is activated "
2124 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2125 chip->card->number);
2126 chip->irq_pending_warned = 1;
2127 }
2128
2129 for (;;) {
2130 pending = 0;
2131 spin_lock_irq(&chip->reg_lock);
2132 for (i = 0; i < chip->num_streams; i++) {
2133 struct azx_dev *azx_dev = &chip->azx_dev[i];
2134 if (!azx_dev->irq_pending ||
2135 !azx_dev->substream ||
2136 !azx_dev->running)
2137 continue;
2138 ok = azx_position_ok(chip, azx_dev);
2139 if (ok > 0) {
2140 azx_dev->irq_pending = 0;
2141 spin_unlock(&chip->reg_lock);
2142 snd_pcm_period_elapsed(azx_dev->substream);
2143 spin_lock(&chip->reg_lock);
2144 } else if (ok < 0) {
2145 pending = 0; /* too early */
2146 } else
2147 pending++;
2148 }
2149 spin_unlock_irq(&chip->reg_lock);
2150 if (!pending)
2151 return;
2152 msleep(1);
2153 }
2154 }
2155
2156 /* clear irq_pending flags and assure no on-going workq */
2157 static void azx_clear_irq_pending(struct azx *chip)
2158 {
2159 int i;
2160
2161 spin_lock_irq(&chip->reg_lock);
2162 for (i = 0; i < chip->num_streams; i++)
2163 chip->azx_dev[i].irq_pending = 0;
2164 spin_unlock_irq(&chip->reg_lock);
2165 }
2166
2167 #ifdef CONFIG_X86
2168 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2169 struct vm_area_struct *area)
2170 {
2171 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2172 struct azx *chip = apcm->chip;
2173 if (!azx_snoop(chip))
2174 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2175 return snd_pcm_lib_default_mmap(substream, area);
2176 }
2177 #else
2178 #define azx_pcm_mmap NULL
2179 #endif
2180
2181 static struct snd_pcm_ops azx_pcm_ops = {
2182 .open = azx_pcm_open,
2183 .close = azx_pcm_close,
2184 .ioctl = snd_pcm_lib_ioctl,
2185 .hw_params = azx_pcm_hw_params,
2186 .hw_free = azx_pcm_hw_free,
2187 .prepare = azx_pcm_prepare,
2188 .trigger = azx_pcm_trigger,
2189 .pointer = azx_pcm_pointer,
2190 .mmap = azx_pcm_mmap,
2191 .page = snd_pcm_sgbuf_ops_page,
2192 };
2193
2194 static void azx_pcm_free(struct snd_pcm *pcm)
2195 {
2196 struct azx_pcm *apcm = pcm->private_data;
2197 if (apcm) {
2198 list_del(&apcm->list);
2199 kfree(apcm);
2200 }
2201 }
2202
2203 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2204
2205 static int
2206 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2207 struct hda_pcm *cpcm)
2208 {
2209 struct azx *chip = bus->private_data;
2210 struct snd_pcm *pcm;
2211 struct azx_pcm *apcm;
2212 int pcm_dev = cpcm->device;
2213 unsigned int size;
2214 int s, err;
2215
2216 list_for_each_entry(apcm, &chip->pcm_list, list) {
2217 if (apcm->pcm->device == pcm_dev) {
2218 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2219 return -EBUSY;
2220 }
2221 }
2222 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2223 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2224 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2225 &pcm);
2226 if (err < 0)
2227 return err;
2228 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2229 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2230 if (apcm == NULL)
2231 return -ENOMEM;
2232 apcm->chip = chip;
2233 apcm->pcm = pcm;
2234 apcm->codec = codec;
2235 pcm->private_data = apcm;
2236 pcm->private_free = azx_pcm_free;
2237 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2238 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2239 list_add_tail(&apcm->list, &chip->pcm_list);
2240 cpcm->pcm = pcm;
2241 for (s = 0; s < 2; s++) {
2242 apcm->hinfo[s] = &cpcm->stream[s];
2243 if (cpcm->stream[s].substreams)
2244 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2245 }
2246 /* buffer pre-allocation */
2247 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2248 if (size > MAX_PREALLOC_SIZE)
2249 size = MAX_PREALLOC_SIZE;
2250 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2251 snd_dma_pci_data(chip->pci),
2252 size, MAX_PREALLOC_SIZE);
2253 return 0;
2254 }
2255
2256 /*
2257 * mixer creation - all stuff is implemented in hda module
2258 */
2259 static int __devinit azx_mixer_create(struct azx *chip)
2260 {
2261 return snd_hda_build_controls(chip->bus);
2262 }
2263
2264
2265 /*
2266 * initialize SD streams
2267 */
2268 static int __devinit azx_init_stream(struct azx *chip)
2269 {
2270 int i;
2271
2272 /* initialize each stream (aka device)
2273 * assign the starting bdl address to each stream (device)
2274 * and initialize
2275 */
2276 for (i = 0; i < chip->num_streams; i++) {
2277 struct azx_dev *azx_dev = &chip->azx_dev[i];
2278 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2279 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2280 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2281 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2282 azx_dev->sd_int_sta_mask = 1 << i;
2283 /* stream tag: must be non-zero and unique */
2284 azx_dev->index = i;
2285 azx_dev->stream_tag = i + 1;
2286 }
2287
2288 return 0;
2289 }
2290
2291 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2292 {
2293 if (request_irq(chip->pci->irq, azx_interrupt,
2294 chip->msi ? 0 : IRQF_SHARED,
2295 KBUILD_MODNAME, chip)) {
2296 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2297 "disabling device\n", chip->pci->irq);
2298 if (do_disconnect)
2299 snd_card_disconnect(chip->card);
2300 return -1;
2301 }
2302 chip->irq = chip->pci->irq;
2303 pci_intx(chip->pci, !chip->msi);
2304 return 0;
2305 }
2306
2307
2308 static void azx_stop_chip(struct azx *chip)
2309 {
2310 if (!chip->initialized)
2311 return;
2312
2313 /* disable interrupts */
2314 azx_int_disable(chip);
2315 azx_int_clear(chip);
2316
2317 /* disable CORB/RIRB */
2318 azx_free_cmd_io(chip);
2319
2320 /* disable position buffer */
2321 azx_writel(chip, DPLBASE, 0);
2322 azx_writel(chip, DPUBASE, 0);
2323
2324 chip->initialized = 0;
2325 }
2326
2327 #ifdef CONFIG_SND_HDA_POWER_SAVE
2328 /* power-up/down the controller */
2329 static void azx_power_notify(struct hda_bus *bus)
2330 {
2331 struct azx *chip = bus->private_data;
2332 struct hda_codec *c;
2333 int power_on = 0;
2334
2335 list_for_each_entry(c, &bus->codec_list, list) {
2336 if (c->power_on) {
2337 power_on = 1;
2338 break;
2339 }
2340 }
2341 if (power_on)
2342 azx_init_chip(chip, 1);
2343 else if (chip->running && power_save_controller &&
2344 !bus->power_keep_link_on)
2345 azx_stop_chip(chip);
2346 }
2347 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2348
2349 #ifdef CONFIG_PM
2350 /*
2351 * power management
2352 */
2353
2354 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2355 {
2356 struct snd_card *card = pci_get_drvdata(pci);
2357 struct azx *chip = card->private_data;
2358 struct azx_pcm *p;
2359
2360 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2361 azx_clear_irq_pending(chip);
2362 list_for_each_entry(p, &chip->pcm_list, list)
2363 snd_pcm_suspend_all(p->pcm);
2364 if (chip->initialized)
2365 snd_hda_suspend(chip->bus);
2366 azx_stop_chip(chip);
2367 if (chip->irq >= 0) {
2368 free_irq(chip->irq, chip);
2369 chip->irq = -1;
2370 }
2371 if (chip->msi)
2372 pci_disable_msi(chip->pci);
2373 pci_disable_device(pci);
2374 pci_save_state(pci);
2375 pci_set_power_state(pci, pci_choose_state(pci, state));
2376 return 0;
2377 }
2378
2379 static int azx_resume(struct pci_dev *pci)
2380 {
2381 struct snd_card *card = pci_get_drvdata(pci);
2382 struct azx *chip = card->private_data;
2383
2384 pci_set_power_state(pci, PCI_D0);
2385 pci_restore_state(pci);
2386 if (pci_enable_device(pci) < 0) {
2387 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2388 "disabling device\n");
2389 snd_card_disconnect(card);
2390 return -EIO;
2391 }
2392 pci_set_master(pci);
2393 if (chip->msi)
2394 if (pci_enable_msi(pci) < 0)
2395 chip->msi = 0;
2396 if (azx_acquire_irq(chip, 1) < 0)
2397 return -EIO;
2398 azx_init_pci(chip);
2399
2400 azx_init_chip(chip, 1);
2401
2402 snd_hda_resume(chip->bus);
2403 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2404 return 0;
2405 }
2406 #endif /* CONFIG_PM */
2407
2408
2409 /*
2410 * reboot notifier for hang-up problem at power-down
2411 */
2412 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2413 {
2414 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2415 snd_hda_bus_reboot_notify(chip->bus);
2416 azx_stop_chip(chip);
2417 return NOTIFY_OK;
2418 }
2419
2420 static void azx_notifier_register(struct azx *chip)
2421 {
2422 chip->reboot_notifier.notifier_call = azx_halt;
2423 register_reboot_notifier(&chip->reboot_notifier);
2424 }
2425
2426 static void azx_notifier_unregister(struct azx *chip)
2427 {
2428 if (chip->reboot_notifier.notifier_call)
2429 unregister_reboot_notifier(&chip->reboot_notifier);
2430 }
2431
2432 /*
2433 * destructor
2434 */
2435 static int azx_free(struct azx *chip)
2436 {
2437 int i;
2438
2439 azx_notifier_unregister(chip);
2440
2441 if (chip->initialized) {
2442 azx_clear_irq_pending(chip);
2443 for (i = 0; i < chip->num_streams; i++)
2444 azx_stream_stop(chip, &chip->azx_dev[i]);
2445 azx_stop_chip(chip);
2446 }
2447
2448 if (chip->irq >= 0)
2449 free_irq(chip->irq, (void*)chip);
2450 if (chip->msi)
2451 pci_disable_msi(chip->pci);
2452 if (chip->remap_addr)
2453 iounmap(chip->remap_addr);
2454
2455 if (chip->azx_dev) {
2456 for (i = 0; i < chip->num_streams; i++)
2457 if (chip->azx_dev[i].bdl.area) {
2458 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2459 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2460 }
2461 }
2462 if (chip->rb.area) {
2463 mark_pages_wc(chip, &chip->rb, false);
2464 snd_dma_free_pages(&chip->rb);
2465 }
2466 if (chip->posbuf.area) {
2467 mark_pages_wc(chip, &chip->posbuf, false);
2468 snd_dma_free_pages(&chip->posbuf);
2469 }
2470 pci_release_regions(chip->pci);
2471 pci_disable_device(chip->pci);
2472 kfree(chip->azx_dev);
2473 kfree(chip);
2474
2475 return 0;
2476 }
2477
2478 static int azx_dev_free(struct snd_device *device)
2479 {
2480 return azx_free(device->device_data);
2481 }
2482
2483 /*
2484 * white/black-listing for position_fix
2485 */
2486 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2487 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2488 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2489 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2490 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2491 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2492 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2493 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2494 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2495 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2496 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2497 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2498 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2499 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2500 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2501 {}
2502 };
2503
2504 static int __devinit check_position_fix(struct azx *chip, int fix)
2505 {
2506 const struct snd_pci_quirk *q;
2507
2508 switch (fix) {
2509 case POS_FIX_LPIB:
2510 case POS_FIX_POSBUF:
2511 case POS_FIX_VIACOMBO:
2512 case POS_FIX_COMBO:
2513 return fix;
2514 }
2515
2516 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2517 if (q) {
2518 printk(KERN_INFO
2519 "hda_intel: position_fix set to %d "
2520 "for device %04x:%04x\n",
2521 q->value, q->subvendor, q->subdevice);
2522 return q->value;
2523 }
2524
2525 /* Check VIA/ATI HD Audio Controller exist */
2526 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2527 snd_printd(SFX "Using VIACOMBO position fix\n");
2528 return POS_FIX_VIACOMBO;
2529 }
2530 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2531 snd_printd(SFX "Using LPIB position fix\n");
2532 return POS_FIX_LPIB;
2533 }
2534 return POS_FIX_AUTO;
2535 }
2536
2537 /*
2538 * black-lists for probe_mask
2539 */
2540 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2541 /* Thinkpad often breaks the controller communication when accessing
2542 * to the non-working (or non-existing) modem codec slot.
2543 */
2544 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2545 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2546 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2547 /* broken BIOS */
2548 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2549 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2550 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2551 /* forced codec slots */
2552 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2553 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2554 {}
2555 };
2556
2557 #define AZX_FORCE_CODEC_MASK 0x100
2558
2559 static void __devinit check_probe_mask(struct azx *chip, int dev)
2560 {
2561 const struct snd_pci_quirk *q;
2562
2563 chip->codec_probe_mask = probe_mask[dev];
2564 if (chip->codec_probe_mask == -1) {
2565 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2566 if (q) {
2567 printk(KERN_INFO
2568 "hda_intel: probe_mask set to 0x%x "
2569 "for device %04x:%04x\n",
2570 q->value, q->subvendor, q->subdevice);
2571 chip->codec_probe_mask = q->value;
2572 }
2573 }
2574
2575 /* check forced option */
2576 if (chip->codec_probe_mask != -1 &&
2577 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2578 chip->codec_mask = chip->codec_probe_mask & 0xff;
2579 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2580 chip->codec_mask);
2581 }
2582 }
2583
2584 /*
2585 * white/black-list for enable_msi
2586 */
2587 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2588 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2589 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2590 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2591 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2592 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2593 {}
2594 };
2595
2596 static void __devinit check_msi(struct azx *chip)
2597 {
2598 const struct snd_pci_quirk *q;
2599
2600 if (enable_msi >= 0) {
2601 chip->msi = !!enable_msi;
2602 return;
2603 }
2604 chip->msi = 1; /* enable MSI as default */
2605 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2606 if (q) {
2607 printk(KERN_INFO
2608 "hda_intel: msi for device %04x:%04x set to %d\n",
2609 q->subvendor, q->subdevice, q->value);
2610 chip->msi = q->value;
2611 return;
2612 }
2613
2614 /* NVidia chipsets seem to cause troubles with MSI */
2615 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2616 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2617 chip->msi = 0;
2618 }
2619 }
2620
2621 /* check the snoop mode availability */
2622 static void __devinit azx_check_snoop_available(struct azx *chip)
2623 {
2624 bool snoop = chip->snoop;
2625
2626 switch (chip->driver_type) {
2627 case AZX_DRIVER_VIA:
2628 /* force to non-snoop mode for a new VIA controller
2629 * when BIOS is set
2630 */
2631 if (snoop) {
2632 u8 val;
2633 pci_read_config_byte(chip->pci, 0x42, &val);
2634 if (!(val & 0x80) && chip->pci->revision == 0x30)
2635 snoop = false;
2636 }
2637 break;
2638 case AZX_DRIVER_ATIHDMI_NS:
2639 /* new ATI HDMI requires non-snoop */
2640 snoop = false;
2641 break;
2642 }
2643
2644 if (snoop != chip->snoop) {
2645 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2646 snoop ? "snoop" : "non-snoop");
2647 chip->snoop = snoop;
2648 }
2649 }
2650
2651 /*
2652 * constructor
2653 */
2654 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2655 int dev, unsigned int driver_caps,
2656 struct azx **rchip)
2657 {
2658 struct azx *chip;
2659 int i, err;
2660 unsigned short gcap;
2661 static struct snd_device_ops ops = {
2662 .dev_free = azx_dev_free,
2663 };
2664
2665 *rchip = NULL;
2666
2667 err = pci_enable_device(pci);
2668 if (err < 0)
2669 return err;
2670
2671 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2672 if (!chip) {
2673 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2674 pci_disable_device(pci);
2675 return -ENOMEM;
2676 }
2677
2678 spin_lock_init(&chip->reg_lock);
2679 mutex_init(&chip->open_mutex);
2680 chip->card = card;
2681 chip->pci = pci;
2682 chip->irq = -1;
2683 chip->driver_caps = driver_caps;
2684 chip->driver_type = driver_caps & 0xff;
2685 check_msi(chip);
2686 chip->dev_index = dev;
2687 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2688 INIT_LIST_HEAD(&chip->pcm_list);
2689
2690 chip->position_fix[0] = chip->position_fix[1] =
2691 check_position_fix(chip, position_fix[dev]);
2692 /* combo mode uses LPIB for playback */
2693 if (chip->position_fix[0] == POS_FIX_COMBO) {
2694 chip->position_fix[0] = POS_FIX_LPIB;
2695 chip->position_fix[1] = POS_FIX_AUTO;
2696 }
2697
2698 check_probe_mask(chip, dev);
2699
2700 chip->single_cmd = single_cmd;
2701 chip->snoop = hda_snoop;
2702 azx_check_snoop_available(chip);
2703
2704 if (bdl_pos_adj[dev] < 0) {
2705 switch (chip->driver_type) {
2706 case AZX_DRIVER_ICH:
2707 case AZX_DRIVER_PCH:
2708 bdl_pos_adj[dev] = 1;
2709 break;
2710 default:
2711 bdl_pos_adj[dev] = 32;
2712 break;
2713 }
2714 }
2715
2716 #if BITS_PER_LONG != 64
2717 /* Fix up base address on ULI M5461 */
2718 if (chip->driver_type == AZX_DRIVER_ULI) {
2719 u16 tmp3;
2720 pci_read_config_word(pci, 0x40, &tmp3);
2721 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2722 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2723 }
2724 #endif
2725
2726 err = pci_request_regions(pci, "ICH HD audio");
2727 if (err < 0) {
2728 kfree(chip);
2729 pci_disable_device(pci);
2730 return err;
2731 }
2732
2733 chip->addr = pci_resource_start(pci, 0);
2734 chip->remap_addr = pci_ioremap_bar(pci, 0);
2735 if (chip->remap_addr == NULL) {
2736 snd_printk(KERN_ERR SFX "ioremap error\n");
2737 err = -ENXIO;
2738 goto errout;
2739 }
2740
2741 if (chip->msi)
2742 if (pci_enable_msi(pci) < 0)
2743 chip->msi = 0;
2744
2745 if (azx_acquire_irq(chip, 0) < 0) {
2746 err = -EBUSY;
2747 goto errout;
2748 }
2749
2750 pci_set_master(pci);
2751 synchronize_irq(chip->irq);
2752
2753 gcap = azx_readw(chip, GCAP);
2754 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2755
2756 /* disable SB600 64bit support for safety */
2757 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2758 struct pci_dev *p_smbus;
2759 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2760 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2761 NULL);
2762 if (p_smbus) {
2763 if (p_smbus->revision < 0x30)
2764 gcap &= ~ICH6_GCAP_64OK;
2765 pci_dev_put(p_smbus);
2766 }
2767 }
2768
2769 /* disable 64bit DMA address on some devices */
2770 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2771 snd_printd(SFX "Disabling 64bit DMA\n");
2772 gcap &= ~ICH6_GCAP_64OK;
2773 }
2774
2775 /* disable buffer size rounding to 128-byte multiples if supported */
2776 if (align_buffer_size >= 0)
2777 chip->align_buffer_size = !!align_buffer_size;
2778 else {
2779 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2780 chip->align_buffer_size = 0;
2781 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
2782 chip->align_buffer_size = 1;
2783 else
2784 chip->align_buffer_size = 1;
2785 }
2786
2787 /* allow 64bit DMA address if supported by H/W */
2788 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2789 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2790 else {
2791 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2792 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2793 }
2794
2795 /* read number of streams from GCAP register instead of using
2796 * hardcoded value
2797 */
2798 chip->capture_streams = (gcap >> 8) & 0x0f;
2799 chip->playback_streams = (gcap >> 12) & 0x0f;
2800 if (!chip->playback_streams && !chip->capture_streams) {
2801 /* gcap didn't give any info, switching to old method */
2802
2803 switch (chip->driver_type) {
2804 case AZX_DRIVER_ULI:
2805 chip->playback_streams = ULI_NUM_PLAYBACK;
2806 chip->capture_streams = ULI_NUM_CAPTURE;
2807 break;
2808 case AZX_DRIVER_ATIHDMI:
2809 case AZX_DRIVER_ATIHDMI_NS:
2810 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2811 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2812 break;
2813 case AZX_DRIVER_GENERIC:
2814 default:
2815 chip->playback_streams = ICH6_NUM_PLAYBACK;
2816 chip->capture_streams = ICH6_NUM_CAPTURE;
2817 break;
2818 }
2819 }
2820 chip->capture_index_offset = 0;
2821 chip->playback_index_offset = chip->capture_streams;
2822 chip->num_streams = chip->playback_streams + chip->capture_streams;
2823 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2824 GFP_KERNEL);
2825 if (!chip->azx_dev) {
2826 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2827 goto errout;
2828 }
2829
2830 for (i = 0; i < chip->num_streams; i++) {
2831 /* allocate memory for the BDL for each stream */
2832 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2833 snd_dma_pci_data(chip->pci),
2834 BDL_SIZE, &chip->azx_dev[i].bdl);
2835 if (err < 0) {
2836 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2837 goto errout;
2838 }
2839 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2840 }
2841 /* allocate memory for the position buffer */
2842 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2843 snd_dma_pci_data(chip->pci),
2844 chip->num_streams * 8, &chip->posbuf);
2845 if (err < 0) {
2846 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2847 goto errout;
2848 }
2849 mark_pages_wc(chip, &chip->posbuf, true);
2850 /* allocate CORB/RIRB */
2851 err = azx_alloc_cmd_io(chip);
2852 if (err < 0)
2853 goto errout;
2854
2855 /* initialize streams */
2856 azx_init_stream(chip);
2857
2858 /* initialize chip */
2859 azx_init_pci(chip);
2860 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2861
2862 /* codec detection */
2863 if (!chip->codec_mask) {
2864 snd_printk(KERN_ERR SFX "no codecs found!\n");
2865 err = -ENODEV;
2866 goto errout;
2867 }
2868
2869 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2870 if (err <0) {
2871 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2872 goto errout;
2873 }
2874
2875 strcpy(card->driver, "HDA-Intel");
2876 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2877 sizeof(card->shortname));
2878 snprintf(card->longname, sizeof(card->longname),
2879 "%s at 0x%lx irq %i",
2880 card->shortname, chip->addr, chip->irq);
2881
2882 *rchip = chip;
2883 return 0;
2884
2885 errout:
2886 azx_free(chip);
2887 return err;
2888 }
2889
2890 static void power_down_all_codecs(struct azx *chip)
2891 {
2892 #ifdef CONFIG_SND_HDA_POWER_SAVE
2893 /* The codecs were powered up in snd_hda_codec_new().
2894 * Now all initialization done, so turn them down if possible
2895 */
2896 struct hda_codec *codec;
2897 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2898 snd_hda_power_down(codec);
2899 }
2900 #endif
2901 }
2902
2903 static int __devinit azx_probe(struct pci_dev *pci,
2904 const struct pci_device_id *pci_id)
2905 {
2906 static int dev;
2907 struct snd_card *card;
2908 struct azx *chip;
2909 int err;
2910
2911 if (dev >= SNDRV_CARDS)
2912 return -ENODEV;
2913 if (!enable[dev]) {
2914 dev++;
2915 return -ENOENT;
2916 }
2917
2918 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2919 if (err < 0) {
2920 snd_printk(KERN_ERR SFX "Error creating card!\n");
2921 return err;
2922 }
2923
2924 /* set this here since it's referred in snd_hda_load_patch() */
2925 snd_card_set_dev(card, &pci->dev);
2926
2927 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2928 if (err < 0)
2929 goto out_free;
2930 card->private_data = chip;
2931
2932 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2933 chip->beep_mode = beep_mode[dev];
2934 #endif
2935
2936 /* create codec instances */
2937 err = azx_codec_create(chip, model[dev]);
2938 if (err < 0)
2939 goto out_free;
2940 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2941 if (patch[dev] && *patch[dev]) {
2942 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2943 patch[dev]);
2944 err = snd_hda_load_patch(chip->bus, patch[dev]);
2945 if (err < 0)
2946 goto out_free;
2947 }
2948 #endif
2949 if ((probe_only[dev] & 1) == 0) {
2950 err = azx_codec_configure(chip);
2951 if (err < 0)
2952 goto out_free;
2953 }
2954
2955 /* create PCM streams */
2956 err = snd_hda_build_pcms(chip->bus);
2957 if (err < 0)
2958 goto out_free;
2959
2960 /* create mixer controls */
2961 err = azx_mixer_create(chip);
2962 if (err < 0)
2963 goto out_free;
2964
2965 err = snd_card_register(card);
2966 if (err < 0)
2967 goto out_free;
2968
2969 pci_set_drvdata(pci, card);
2970 chip->running = 1;
2971 power_down_all_codecs(chip);
2972 azx_notifier_register(chip);
2973
2974 dev++;
2975 return err;
2976 out_free:
2977 snd_card_free(card);
2978 return err;
2979 }
2980
2981 static void __devexit azx_remove(struct pci_dev *pci)
2982 {
2983 snd_card_free(pci_get_drvdata(pci));
2984 pci_set_drvdata(pci, NULL);
2985 }
2986
2987 /* PCI IDs */
2988 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2989 /* CPT */
2990 { PCI_DEVICE(0x8086, 0x1c20),
2991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2992 AZX_DCAPS_BUFSIZE },
2993 /* PBG */
2994 { PCI_DEVICE(0x8086, 0x1d20),
2995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2996 AZX_DCAPS_BUFSIZE},
2997 /* Panther Point */
2998 { PCI_DEVICE(0x8086, 0x1e20),
2999 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3000 AZX_DCAPS_BUFSIZE},
3001 /* Lynx Point */
3002 { PCI_DEVICE(0x8086, 0x8c20),
3003 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3004 AZX_DCAPS_BUFSIZE},
3005 /* SCH */
3006 { PCI_DEVICE(0x8086, 0x811b),
3007 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3008 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3009 { PCI_DEVICE(0x8086, 0x080a),
3010 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3011 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3012 /* ICH */
3013 { PCI_DEVICE(0x8086, 0x2668),
3014 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3015 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3016 { PCI_DEVICE(0x8086, 0x27d8),
3017 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3018 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3019 { PCI_DEVICE(0x8086, 0x269a),
3020 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3021 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3022 { PCI_DEVICE(0x8086, 0x284b),
3023 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3024 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3025 { PCI_DEVICE(0x8086, 0x293e),
3026 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3027 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3028 { PCI_DEVICE(0x8086, 0x293f),
3029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3030 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3031 { PCI_DEVICE(0x8086, 0x3a3e),
3032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3033 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3034 { PCI_DEVICE(0x8086, 0x3a6e),
3035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3036 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3037 /* Generic Intel */
3038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3039 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3040 .class_mask = 0xffffff,
3041 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3042 /* ATI SB 450/600/700/800/900 */
3043 { PCI_DEVICE(0x1002, 0x437b),
3044 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3045 { PCI_DEVICE(0x1002, 0x4383),
3046 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3047 /* AMD Hudson */
3048 { PCI_DEVICE(0x1022, 0x780d),
3049 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3050 /* ATI HDMI */
3051 { PCI_DEVICE(0x1002, 0x793b),
3052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3053 { PCI_DEVICE(0x1002, 0x7919),
3054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3055 { PCI_DEVICE(0x1002, 0x960f),
3056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3057 { PCI_DEVICE(0x1002, 0x970f),
3058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3059 { PCI_DEVICE(0x1002, 0xaa00),
3060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3061 { PCI_DEVICE(0x1002, 0xaa08),
3062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3063 { PCI_DEVICE(0x1002, 0xaa10),
3064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3065 { PCI_DEVICE(0x1002, 0xaa18),
3066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3067 { PCI_DEVICE(0x1002, 0xaa20),
3068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3069 { PCI_DEVICE(0x1002, 0xaa28),
3070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3071 { PCI_DEVICE(0x1002, 0xaa30),
3072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3073 { PCI_DEVICE(0x1002, 0xaa38),
3074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3075 { PCI_DEVICE(0x1002, 0xaa40),
3076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3077 { PCI_DEVICE(0x1002, 0xaa48),
3078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3079 { PCI_DEVICE(0x1002, 0x9902),
3080 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3081 { PCI_DEVICE(0x1002, 0xaaa0),
3082 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3083 { PCI_DEVICE(0x1002, 0xaaa8),
3084 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3085 { PCI_DEVICE(0x1002, 0xaab0),
3086 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3087 /* VIA VT8251/VT8237A */
3088 { PCI_DEVICE(0x1106, 0x3288),
3089 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3090 /* SIS966 */
3091 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3092 /* ULI M5461 */
3093 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3094 /* NVIDIA MCP */
3095 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3096 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3097 .class_mask = 0xffffff,
3098 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3099 /* Teradici */
3100 { PCI_DEVICE(0x6549, 0x1200),
3101 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3102 /* Creative X-Fi (CA0110-IBG) */
3103 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3104 /* the following entry conflicts with snd-ctxfi driver,
3105 * as ctxfi driver mutates from HD-audio to native mode with
3106 * a special command sequence.
3107 */
3108 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3109 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3110 .class_mask = 0xffffff,
3111 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3112 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3113 #else
3114 /* this entry seems still valid -- i.e. without emu20kx chip */
3115 { PCI_DEVICE(0x1102, 0x0009),
3116 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3117 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3118 #endif
3119 /* Vortex86MX */
3120 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3121 /* VMware HDAudio */
3122 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3123 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3124 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3125 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3126 .class_mask = 0xffffff,
3127 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3128 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3129 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3130 .class_mask = 0xffffff,
3131 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3132 { 0, }
3133 };
3134 MODULE_DEVICE_TABLE(pci, azx_ids);
3135
3136 /* pci_driver definition */
3137 static struct pci_driver azx_driver = {
3138 .name = KBUILD_MODNAME,
3139 .id_table = azx_ids,
3140 .probe = azx_probe,
3141 .remove = __devexit_p(azx_remove),
3142 #ifdef CONFIG_PM
3143 .suspend = azx_suspend,
3144 .resume = azx_resume,
3145 #endif
3146 };
3147
3148 module_pci_driver(azx_driver);
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