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[mirror_ubuntu-eoan-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_intel.h"
66
67 /* position fix mode */
68 enum {
69 POS_FIX_AUTO,
70 POS_FIX_LPIB,
71 POS_FIX_POSBUF,
72 POS_FIX_VIACOMBO,
73 POS_FIX_COMBO,
74 };
75
76 /* Defines for ATI HD Audio support in SB450 south bridge */
77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
79
80 /* Defines for Nvidia HDA support */
81 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
82 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
83 #define NVIDIA_HDA_ISTRM_COH 0x4d
84 #define NVIDIA_HDA_OSTRM_COH 0x4c
85 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
86
87 /* Defines for Intel SCH HDA snoop control */
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* Define IN stream 0 FIFO size offset in VIA controller */
92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
93 /* Define VIA HD Audio Device ID*/
94 #define VIA_HDAC_DEVICE_ID 0x3288
95
96 /* max number of SDs */
97 /* ICH, ATI and VIA have 4 playback and 4 capture */
98 #define ICH6_NUM_CAPTURE 4
99 #define ICH6_NUM_PLAYBACK 4
100
101 /* ULI has 6 playback and 5 capture */
102 #define ULI_NUM_CAPTURE 5
103 #define ULI_NUM_PLAYBACK 6
104
105 /* ATI HDMI may have up to 8 playbacks and 0 capture */
106 #define ATIHDMI_NUM_CAPTURE 0
107 #define ATIHDMI_NUM_PLAYBACK 8
108
109 /* TERA has 4 playback and 3 capture */
110 #define TERA_NUM_CAPTURE 3
111 #define TERA_NUM_PLAYBACK 4
112
113
114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
117 static char *model[SNDRV_CARDS];
118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_only[SNDRV_CARDS];
122 static int jackpoll_ms[SNDRV_CARDS];
123 static bool single_cmd;
124 static int enable_msi = -1;
125 #ifdef CONFIG_SND_HDA_PATCH_LOADER
126 static char *patch[SNDRV_CARDS];
127 #endif
128 #ifdef CONFIG_SND_HDA_INPUT_BEEP
129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
130 CONFIG_SND_HDA_INPUT_BEEP_MODE};
131 #endif
132
133 module_param_array(index, int, NULL, 0444);
134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
135 module_param_array(id, charp, NULL, 0444);
136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
137 module_param_array(enable, bool, NULL, 0444);
138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
139 module_param_array(model, charp, NULL, 0444);
140 MODULE_PARM_DESC(model, "Use the given board model.");
141 module_param_array(position_fix, int, NULL, 0444);
142 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
144 module_param_array(bdl_pos_adj, int, NULL, 0644);
145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
146 module_param_array(probe_mask, int, NULL, 0444);
147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
148 module_param_array(probe_only, int, NULL, 0444);
149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
150 module_param_array(jackpoll_ms, int, NULL, 0444);
151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
152 module_param(single_cmd, bool, 0444);
153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
154 "(for debugging only).");
155 module_param(enable_msi, bint, 0444);
156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
158 module_param_array(patch, charp, NULL, 0444);
159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
160 #endif
161 #ifdef CONFIG_SND_HDA_INPUT_BEEP
162 module_param_array(beep_mode, bool, NULL, 0444);
163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
164 "(0=off, 1=on) (default=1).");
165 #endif
166
167 #ifdef CONFIG_PM
168 static int param_set_xint(const char *val, const struct kernel_param *kp);
169 static struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172 };
173 #define param_check_xint param_check_int
174
175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
176 module_param(power_save, xint, 0644);
177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
179
180 /* reset the HD-audio controller in power save mode.
181 * this may give more power-saving, but will take longer time to
182 * wake up.
183 */
184 static bool power_save_controller = 1;
185 module_param(power_save_controller, bool, 0644);
186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
187 #else
188 #define power_save 0
189 #endif /* CONFIG_PM */
190
191 static int align_buffer_size = -1;
192 module_param(align_buffer_size, bint, 0644);
193 MODULE_PARM_DESC(align_buffer_size,
194 "Force buffer and period sizes to be multiple of 128 bytes.");
195
196 #ifdef CONFIG_X86
197 static int hda_snoop = -1;
198 module_param_named(snoop, hda_snoop, bint, 0444);
199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
200 #else
201 #define hda_snoop true
202 #endif
203
204
205 MODULE_LICENSE("GPL");
206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
207 "{Intel, ICH6M},"
208 "{Intel, ICH7},"
209 "{Intel, ESB2},"
210 "{Intel, ICH8},"
211 "{Intel, ICH9},"
212 "{Intel, ICH10},"
213 "{Intel, PCH},"
214 "{Intel, CPT},"
215 "{Intel, PPT},"
216 "{Intel, LPT},"
217 "{Intel, LPT_LP},"
218 "{Intel, WPT_LP},"
219 "{Intel, SPT},"
220 "{Intel, SPT_LP},"
221 "{Intel, HPT},"
222 "{Intel, PBG},"
223 "{Intel, SCH},"
224 "{ATI, SB450},"
225 "{ATI, SB600},"
226 "{ATI, RS600},"
227 "{ATI, RS690},"
228 "{ATI, RS780},"
229 "{ATI, R600},"
230 "{ATI, RV630},"
231 "{ATI, RV610},"
232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
236 "{VIA, VT8251},"
237 "{VIA, VT8237A},"
238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
240 MODULE_DESCRIPTION("Intel HDA driver");
241
242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
244 #define SUPPORT_VGA_SWITCHEROO
245 #endif
246 #endif
247
248
249 /*
250 */
251
252 /* driver types */
253 enum {
254 AZX_DRIVER_ICH,
255 AZX_DRIVER_PCH,
256 AZX_DRIVER_SCH,
257 AZX_DRIVER_HDMI,
258 AZX_DRIVER_ATI,
259 AZX_DRIVER_ATIHDMI,
260 AZX_DRIVER_ATIHDMI_NS,
261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
264 AZX_DRIVER_NVIDIA,
265 AZX_DRIVER_TERA,
266 AZX_DRIVER_CTX,
267 AZX_DRIVER_CTHDA,
268 AZX_DRIVER_CMEDIA,
269 AZX_DRIVER_GENERIC,
270 AZX_NUM_DRIVERS, /* keep this as last entry */
271 };
272
273 #define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
277 /* quirks for old Intel chipsets */
278 #define AZX_DCAPS_INTEL_ICH \
279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
280
281 /* quirks for Intel PCH */
282 #define AZX_DCAPS_INTEL_PCH_NOPM \
283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
285
286 #define AZX_DCAPS_INTEL_PCH \
287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
288
289 #define AZX_DCAPS_INTEL_HASWELL \
290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
292 AZX_DCAPS_SNOOP_TYPE(SCH))
293
294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
295 #define AZX_DCAPS_INTEL_BROADWELL \
296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
299
300 #define AZX_DCAPS_INTEL_BRASWELL \
301 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
302
303 #define AZX_DCAPS_INTEL_SKYLAKE \
304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
305 AZX_DCAPS_I915_POWERWELL)
306
307 /* quirks for ATI SB / AMD Hudson */
308 #define AZX_DCAPS_PRESET_ATI_SB \
309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
310 AZX_DCAPS_SNOOP_TYPE(ATI))
311
312 /* quirks for ATI/AMD HDMI */
313 #define AZX_DCAPS_PRESET_ATI_HDMI \
314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
315 AZX_DCAPS_NO_MSI64)
316
317 /* quirks for ATI HDMI with snoop off */
318 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
319 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
320
321 /* quirks for Nvidia */
322 #define AZX_DCAPS_PRESET_NVIDIA \
323 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
324 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
325 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
326
327 #define AZX_DCAPS_PRESET_CTHDA \
328 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
329 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
330
331 /*
332 * VGA-switcher support
333 */
334 #ifdef SUPPORT_VGA_SWITCHEROO
335 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
336 #else
337 #define use_vga_switcheroo(chip) 0
338 #endif
339
340 static char *driver_short_names[] = {
341 [AZX_DRIVER_ICH] = "HDA Intel",
342 [AZX_DRIVER_PCH] = "HDA Intel PCH",
343 [AZX_DRIVER_SCH] = "HDA Intel MID",
344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
345 [AZX_DRIVER_ATI] = "HDA ATI SB",
346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
348 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
349 [AZX_DRIVER_SIS] = "HDA SIS966",
350 [AZX_DRIVER_ULI] = "HDA ULI M5461",
351 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
352 [AZX_DRIVER_TERA] = "HDA Teradici",
353 [AZX_DRIVER_CTX] = "HDA Creative",
354 [AZX_DRIVER_CTHDA] = "HDA Creative",
355 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
356 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
357 };
358
359 #ifdef CONFIG_X86
360 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
361 {
362 int pages;
363
364 if (azx_snoop(chip))
365 return;
366 if (!dmab || !dmab->area || !dmab->bytes)
367 return;
368
369 #ifdef CONFIG_SND_DMA_SGBUF
370 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
371 struct snd_sg_buf *sgbuf = dmab->private_data;
372 if (chip->driver_type == AZX_DRIVER_CMEDIA)
373 return; /* deal with only CORB/RIRB buffers */
374 if (on)
375 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
376 else
377 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
378 return;
379 }
380 #endif
381
382 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
383 if (on)
384 set_memory_wc((unsigned long)dmab->area, pages);
385 else
386 set_memory_wb((unsigned long)dmab->area, pages);
387 }
388
389 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
390 bool on)
391 {
392 __mark_pages_wc(chip, buf, on);
393 }
394 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
395 struct snd_pcm_substream *substream, bool on)
396 {
397 if (azx_dev->wc_marked != on) {
398 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
399 azx_dev->wc_marked = on;
400 }
401 }
402 #else
403 /* NOP for other archs */
404 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
405 bool on)
406 {
407 }
408 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
409 struct snd_pcm_substream *substream, bool on)
410 {
411 }
412 #endif
413
414 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
415
416 /*
417 * initialize the PCI registers
418 */
419 /* update bits in a PCI register byte */
420 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
421 unsigned char mask, unsigned char val)
422 {
423 unsigned char data;
424
425 pci_read_config_byte(pci, reg, &data);
426 data &= ~mask;
427 data |= (val & mask);
428 pci_write_config_byte(pci, reg, data);
429 }
430
431 static void azx_init_pci(struct azx *chip)
432 {
433 int snoop_type = azx_get_snoop_type(chip);
434
435 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
436 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
437 * Ensuring these bits are 0 clears playback static on some HD Audio
438 * codecs.
439 * The PCI register TCSEL is defined in the Intel manuals.
440 */
441 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
442 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
443 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
444 }
445
446 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
447 * we need to enable snoop.
448 */
449 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
450 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
451 azx_snoop(chip));
452 update_pci_byte(chip->pci,
453 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
454 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
455 }
456
457 /* For NVIDIA HDA, enable snoop */
458 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
459 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
460 azx_snoop(chip));
461 update_pci_byte(chip->pci,
462 NVIDIA_HDA_TRANSREG_ADDR,
463 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
464 update_pci_byte(chip->pci,
465 NVIDIA_HDA_ISTRM_COH,
466 0x01, NVIDIA_HDA_ENABLE_COHBIT);
467 update_pci_byte(chip->pci,
468 NVIDIA_HDA_OSTRM_COH,
469 0x01, NVIDIA_HDA_ENABLE_COHBIT);
470 }
471
472 /* Enable SCH/PCH snoop if needed */
473 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
474 unsigned short snoop;
475 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
476 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
477 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
478 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
479 if (!azx_snoop(chip))
480 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
481 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
482 pci_read_config_word(chip->pci,
483 INTEL_SCH_HDA_DEVC, &snoop);
484 }
485 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
486 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
487 "Disabled" : "Enabled");
488 }
489 }
490
491 /* calculate runtime delay from LPIB */
492 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
493 unsigned int pos)
494 {
495 struct snd_pcm_substream *substream = azx_dev->core.substream;
496 int stream = substream->stream;
497 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
498 int delay;
499
500 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
501 delay = pos - lpib_pos;
502 else
503 delay = lpib_pos - pos;
504 if (delay < 0) {
505 if (delay >= azx_dev->core.delay_negative_threshold)
506 delay = 0;
507 else
508 delay += azx_dev->core.bufsize;
509 }
510
511 if (delay >= azx_dev->core.period_bytes) {
512 dev_info(chip->card->dev,
513 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
514 delay, azx_dev->core.period_bytes);
515 delay = 0;
516 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
517 chip->get_delay[stream] = NULL;
518 }
519
520 return bytes_to_frames(substream->runtime, delay);
521 }
522
523 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
524
525 /* called from IRQ */
526 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
527 {
528 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
529 int ok;
530
531 ok = azx_position_ok(chip, azx_dev);
532 if (ok == 1) {
533 azx_dev->irq_pending = 0;
534 return ok;
535 } else if (ok == 0) {
536 /* bogus IRQ, process it later */
537 azx_dev->irq_pending = 1;
538 schedule_work(&hda->irq_pending_work);
539 }
540 return 0;
541 }
542
543 /*
544 * Check whether the current DMA position is acceptable for updating
545 * periods. Returns non-zero if it's OK.
546 *
547 * Many HD-audio controllers appear pretty inaccurate about
548 * the update-IRQ timing. The IRQ is issued before actually the
549 * data is processed. So, we need to process it afterwords in a
550 * workqueue.
551 */
552 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
553 {
554 struct snd_pcm_substream *substream = azx_dev->core.substream;
555 int stream = substream->stream;
556 u32 wallclk;
557 unsigned int pos;
558
559 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
560 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
561 return -1; /* bogus (too early) interrupt */
562
563 if (chip->get_position[stream])
564 pos = chip->get_position[stream](chip, azx_dev);
565 else { /* use the position buffer as default */
566 pos = azx_get_pos_posbuf(chip, azx_dev);
567 if (!pos || pos == (u32)-1) {
568 dev_info(chip->card->dev,
569 "Invalid position buffer, using LPIB read method instead.\n");
570 chip->get_position[stream] = azx_get_pos_lpib;
571 if (chip->get_position[0] == azx_get_pos_lpib &&
572 chip->get_position[1] == azx_get_pos_lpib)
573 azx_bus(chip)->use_posbuf = false;
574 pos = azx_get_pos_lpib(chip, azx_dev);
575 chip->get_delay[stream] = NULL;
576 } else {
577 chip->get_position[stream] = azx_get_pos_posbuf;
578 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
579 chip->get_delay[stream] = azx_get_delay_from_lpib;
580 }
581 }
582
583 if (pos >= azx_dev->core.bufsize)
584 pos = 0;
585
586 if (WARN_ONCE(!azx_dev->core.period_bytes,
587 "hda-intel: zero azx_dev->period_bytes"))
588 return -1; /* this shouldn't happen! */
589 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
590 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
591 /* NG - it's below the first next period boundary */
592 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
593 azx_dev->core.start_wallclk += wallclk;
594 return 1; /* OK, it's fine */
595 }
596
597 /*
598 * The work for pending PCM period updates.
599 */
600 static void azx_irq_pending_work(struct work_struct *work)
601 {
602 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
603 struct azx *chip = &hda->chip;
604 struct hdac_bus *bus = azx_bus(chip);
605 struct hdac_stream *s;
606 int pending, ok;
607
608 if (!hda->irq_pending_warned) {
609 dev_info(chip->card->dev,
610 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
611 chip->card->number);
612 hda->irq_pending_warned = 1;
613 }
614
615 for (;;) {
616 pending = 0;
617 spin_lock_irq(&chip->reg_lock);
618 list_for_each_entry(s, &bus->stream_list, list) {
619 struct azx_dev *azx_dev = stream_to_azx_dev(s);
620 if (!azx_dev->irq_pending ||
621 !s->substream ||
622 !s->running)
623 continue;
624 ok = azx_position_ok(chip, azx_dev);
625 if (ok > 0) {
626 azx_dev->irq_pending = 0;
627 spin_unlock(&chip->reg_lock);
628 snd_pcm_period_elapsed(s->substream);
629 spin_lock(&chip->reg_lock);
630 } else if (ok < 0) {
631 pending = 0; /* too early */
632 } else
633 pending++;
634 }
635 spin_unlock_irq(&chip->reg_lock);
636 if (!pending)
637 return;
638 msleep(1);
639 }
640 }
641
642 /* clear irq_pending flags and assure no on-going workq */
643 static void azx_clear_irq_pending(struct azx *chip)
644 {
645 struct hdac_bus *bus = azx_bus(chip);
646 struct hdac_stream *s;
647
648 spin_lock_irq(&chip->reg_lock);
649 list_for_each_entry(s, &bus->stream_list, list) {
650 struct azx_dev *azx_dev = stream_to_azx_dev(s);
651 azx_dev->irq_pending = 0;
652 }
653 spin_unlock_irq(&chip->reg_lock);
654 }
655
656 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
657 {
658 if (request_irq(chip->pci->irq, azx_interrupt,
659 chip->msi ? 0 : IRQF_SHARED,
660 KBUILD_MODNAME, chip)) {
661 dev_err(chip->card->dev,
662 "unable to grab IRQ %d, disabling device\n",
663 chip->pci->irq);
664 if (do_disconnect)
665 snd_card_disconnect(chip->card);
666 return -1;
667 }
668 chip->irq = chip->pci->irq;
669 pci_intx(chip->pci, !chip->msi);
670 return 0;
671 }
672
673 /* get the current DMA position with correction on VIA chips */
674 static unsigned int azx_via_get_position(struct azx *chip,
675 struct azx_dev *azx_dev)
676 {
677 unsigned int link_pos, mini_pos, bound_pos;
678 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
679 unsigned int fifo_size;
680
681 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
682 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
683 /* Playback, no problem using link position */
684 return link_pos;
685 }
686
687 /* Capture */
688 /* For new chipset,
689 * use mod to get the DMA position just like old chipset
690 */
691 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
692 mod_dma_pos %= azx_dev->core.period_bytes;
693
694 /* azx_dev->fifo_size can't get FIFO size of in stream.
695 * Get from base address + offset.
696 */
697 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
698
699 if (azx_dev->insufficient) {
700 /* Link position never gather than FIFO size */
701 if (link_pos <= fifo_size)
702 return 0;
703
704 azx_dev->insufficient = 0;
705 }
706
707 if (link_pos <= fifo_size)
708 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
709 else
710 mini_pos = link_pos - fifo_size;
711
712 /* Find nearest previous boudary */
713 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
714 mod_link_pos = link_pos % azx_dev->core.period_bytes;
715 if (mod_link_pos >= fifo_size)
716 bound_pos = link_pos - mod_link_pos;
717 else if (mod_dma_pos >= mod_mini_pos)
718 bound_pos = mini_pos - mod_mini_pos;
719 else {
720 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
721 if (bound_pos >= azx_dev->core.bufsize)
722 bound_pos = 0;
723 }
724
725 /* Calculate real DMA position we want */
726 return bound_pos + mod_dma_pos;
727 }
728
729 #ifdef CONFIG_PM
730 static DEFINE_MUTEX(card_list_lock);
731 static LIST_HEAD(card_list);
732
733 static void azx_add_card_list(struct azx *chip)
734 {
735 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
736 mutex_lock(&card_list_lock);
737 list_add(&hda->list, &card_list);
738 mutex_unlock(&card_list_lock);
739 }
740
741 static void azx_del_card_list(struct azx *chip)
742 {
743 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
744 mutex_lock(&card_list_lock);
745 list_del_init(&hda->list);
746 mutex_unlock(&card_list_lock);
747 }
748
749 /* trigger power-save check at writing parameter */
750 static int param_set_xint(const char *val, const struct kernel_param *kp)
751 {
752 struct hda_intel *hda;
753 struct azx *chip;
754 int prev = power_save;
755 int ret = param_set_int(val, kp);
756
757 if (ret || prev == power_save)
758 return ret;
759
760 mutex_lock(&card_list_lock);
761 list_for_each_entry(hda, &card_list, list) {
762 chip = &hda->chip;
763 if (!chip->bus || chip->disabled)
764 continue;
765 snd_hda_set_power_save(chip->bus, power_save * 1000);
766 }
767 mutex_unlock(&card_list_lock);
768 return 0;
769 }
770 #else
771 #define azx_add_card_list(chip) /* NOP */
772 #define azx_del_card_list(chip) /* NOP */
773 #endif /* CONFIG_PM */
774
775 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
776 /*
777 * power management
778 */
779 static int azx_suspend(struct device *dev)
780 {
781 struct snd_card *card = dev_get_drvdata(dev);
782 struct azx *chip;
783 struct hda_intel *hda;
784
785 if (!card)
786 return 0;
787
788 chip = card->private_data;
789 hda = container_of(chip, struct hda_intel, chip);
790 if (chip->disabled || hda->init_failed)
791 return 0;
792
793 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
794 azx_clear_irq_pending(chip);
795 azx_stop_chip(chip);
796 azx_enter_link_reset(chip);
797 if (chip->irq >= 0) {
798 free_irq(chip->irq, chip);
799 chip->irq = -1;
800 }
801
802 if (chip->msi)
803 pci_disable_msi(chip->pci);
804 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
805 hda_display_power(hda, false);
806 return 0;
807 }
808
809 static int azx_resume(struct device *dev)
810 {
811 struct pci_dev *pci = to_pci_dev(dev);
812 struct snd_card *card = dev_get_drvdata(dev);
813 struct azx *chip;
814 struct hda_intel *hda;
815
816 if (!card)
817 return 0;
818
819 chip = card->private_data;
820 hda = container_of(chip, struct hda_intel, chip);
821 if (chip->disabled || hda->init_failed)
822 return 0;
823
824 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
825 hda_display_power(hda, true);
826 haswell_set_bclk(hda);
827 }
828 if (chip->msi)
829 if (pci_enable_msi(pci) < 0)
830 chip->msi = 0;
831 if (azx_acquire_irq(chip, 1) < 0)
832 return -EIO;
833 azx_init_pci(chip);
834
835 azx_init_chip(chip, true);
836
837 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
838 return 0;
839 }
840 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
841
842 #ifdef CONFIG_PM
843 static int azx_runtime_suspend(struct device *dev)
844 {
845 struct snd_card *card = dev_get_drvdata(dev);
846 struct azx *chip;
847 struct hda_intel *hda;
848
849 if (!card)
850 return 0;
851
852 chip = card->private_data;
853 hda = container_of(chip, struct hda_intel, chip);
854 if (chip->disabled || hda->init_failed)
855 return 0;
856
857 if (!azx_has_pm_runtime(chip))
858 return 0;
859
860 /* enable controller wake up event */
861 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
862 STATESTS_INT_MASK);
863
864 azx_stop_chip(chip);
865 azx_enter_link_reset(chip);
866 azx_clear_irq_pending(chip);
867 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
868 hda_display_power(hda, false);
869
870 return 0;
871 }
872
873 static int azx_runtime_resume(struct device *dev)
874 {
875 struct snd_card *card = dev_get_drvdata(dev);
876 struct azx *chip;
877 struct hda_intel *hda;
878 struct hda_bus *bus;
879 struct hda_codec *codec;
880 int status;
881
882 if (!card)
883 return 0;
884
885 chip = card->private_data;
886 hda = container_of(chip, struct hda_intel, chip);
887 if (chip->disabled || hda->init_failed)
888 return 0;
889
890 if (!azx_has_pm_runtime(chip))
891 return 0;
892
893 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
894 hda_display_power(hda, true);
895 haswell_set_bclk(hda);
896 }
897
898 /* Read STATESTS before controller reset */
899 status = azx_readw(chip, STATESTS);
900
901 azx_init_pci(chip);
902 azx_init_chip(chip, true);
903
904 bus = chip->bus;
905 if (status && bus) {
906 list_for_each_codec(codec, bus)
907 if (status & (1 << codec->addr))
908 schedule_delayed_work(&codec->jackpoll_work,
909 codec->jackpoll_interval);
910 }
911
912 /* disable controller Wake Up event*/
913 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
914 ~STATESTS_INT_MASK);
915
916 return 0;
917 }
918
919 static int azx_runtime_idle(struct device *dev)
920 {
921 struct snd_card *card = dev_get_drvdata(dev);
922 struct azx *chip;
923 struct hda_intel *hda;
924
925 if (!card)
926 return 0;
927
928 chip = card->private_data;
929 hda = container_of(chip, struct hda_intel, chip);
930 if (chip->disabled || hda->init_failed)
931 return 0;
932
933 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
934 chip->bus->core.codec_powered)
935 return -EBUSY;
936
937 return 0;
938 }
939
940 static const struct dev_pm_ops azx_pm = {
941 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
942 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
943 };
944
945 #define AZX_PM_OPS &azx_pm
946 #else
947 #define AZX_PM_OPS NULL
948 #endif /* CONFIG_PM */
949
950
951 static int azx_probe_continue(struct azx *chip);
952
953 #ifdef SUPPORT_VGA_SWITCHEROO
954 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
955
956 static void azx_vs_set_state(struct pci_dev *pci,
957 enum vga_switcheroo_state state)
958 {
959 struct snd_card *card = pci_get_drvdata(pci);
960 struct azx *chip = card->private_data;
961 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
962 bool disabled;
963
964 wait_for_completion(&hda->probe_wait);
965 if (hda->init_failed)
966 return;
967
968 disabled = (state == VGA_SWITCHEROO_OFF);
969 if (chip->disabled == disabled)
970 return;
971
972 if (!chip->bus) {
973 chip->disabled = disabled;
974 if (!disabled) {
975 dev_info(chip->card->dev,
976 "Start delayed initialization\n");
977 if (azx_probe_continue(chip) < 0) {
978 dev_err(chip->card->dev, "initialization error\n");
979 hda->init_failed = true;
980 }
981 }
982 } else {
983 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
984 disabled ? "Disabling" : "Enabling");
985 if (disabled) {
986 pm_runtime_put_sync_suspend(card->dev);
987 azx_suspend(card->dev);
988 /* when we get suspended by vga switcheroo we end up in D3cold,
989 * however we have no ACPI handle, so pci/acpi can't put us there,
990 * put ourselves there */
991 pci->current_state = PCI_D3cold;
992 chip->disabled = true;
993 if (snd_hda_lock_devices(chip->bus))
994 dev_warn(chip->card->dev,
995 "Cannot lock devices!\n");
996 } else {
997 snd_hda_unlock_devices(chip->bus);
998 pm_runtime_get_noresume(card->dev);
999 chip->disabled = false;
1000 azx_resume(card->dev);
1001 }
1002 }
1003 }
1004
1005 static bool azx_vs_can_switch(struct pci_dev *pci)
1006 {
1007 struct snd_card *card = pci_get_drvdata(pci);
1008 struct azx *chip = card->private_data;
1009 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1010
1011 wait_for_completion(&hda->probe_wait);
1012 if (hda->init_failed)
1013 return false;
1014 if (chip->disabled || !chip->bus)
1015 return true;
1016 if (snd_hda_lock_devices(chip->bus))
1017 return false;
1018 snd_hda_unlock_devices(chip->bus);
1019 return true;
1020 }
1021
1022 static void init_vga_switcheroo(struct azx *chip)
1023 {
1024 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1025 struct pci_dev *p = get_bound_vga(chip->pci);
1026 if (p) {
1027 dev_info(chip->card->dev,
1028 "Handle VGA-switcheroo audio client\n");
1029 hda->use_vga_switcheroo = 1;
1030 pci_dev_put(p);
1031 }
1032 }
1033
1034 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1035 .set_gpu_state = azx_vs_set_state,
1036 .can_switch = azx_vs_can_switch,
1037 };
1038
1039 static int register_vga_switcheroo(struct azx *chip)
1040 {
1041 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1042 int err;
1043
1044 if (!hda->use_vga_switcheroo)
1045 return 0;
1046 /* FIXME: currently only handling DIS controller
1047 * is there any machine with two switchable HDMI audio controllers?
1048 */
1049 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1050 VGA_SWITCHEROO_DIS,
1051 chip->bus != NULL);
1052 if (err < 0)
1053 return err;
1054 hda->vga_switcheroo_registered = 1;
1055
1056 /* register as an optimus hdmi audio power domain */
1057 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1058 &hda->hdmi_pm_domain);
1059 return 0;
1060 }
1061 #else
1062 #define init_vga_switcheroo(chip) /* NOP */
1063 #define register_vga_switcheroo(chip) 0
1064 #define check_hdmi_disabled(pci) false
1065 #endif /* SUPPORT_VGA_SWITCHER */
1066
1067 /*
1068 * destructor
1069 */
1070 static int azx_free(struct azx *chip)
1071 {
1072 struct pci_dev *pci = chip->pci;
1073 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1074
1075 if (azx_has_pm_runtime(chip) && chip->running)
1076 pm_runtime_get_noresume(&pci->dev);
1077
1078 azx_del_card_list(chip);
1079
1080 hda->init_failed = 1; /* to be sure */
1081 complete_all(&hda->probe_wait);
1082
1083 if (use_vga_switcheroo(hda)) {
1084 if (chip->disabled && chip->bus)
1085 snd_hda_unlock_devices(chip->bus);
1086 if (hda->vga_switcheroo_registered)
1087 vga_switcheroo_unregister_client(chip->pci);
1088 }
1089
1090 if (chip->initialized) {
1091 azx_clear_irq_pending(chip);
1092 azx_stop_all_streams(chip);
1093 azx_stop_chip(chip);
1094 }
1095
1096 if (chip->irq >= 0)
1097 free_irq(chip->irq, (void*)chip);
1098 if (chip->msi)
1099 pci_disable_msi(chip->pci);
1100 iounmap(chip->remap_addr);
1101
1102 azx_free_stream_pages(chip);
1103 if (chip->region_requested)
1104 pci_release_regions(chip->pci);
1105 pci_disable_device(chip->pci);
1106 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1107 release_firmware(chip->fw);
1108 #endif
1109 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1110 hda_display_power(hda, false);
1111 hda_i915_exit(hda);
1112 }
1113 kfree(hda);
1114
1115 return 0;
1116 }
1117
1118 static int azx_dev_free(struct snd_device *device)
1119 {
1120 return azx_free(device->device_data);
1121 }
1122
1123 #ifdef SUPPORT_VGA_SWITCHEROO
1124 /*
1125 * Check of disabled HDMI controller by vga-switcheroo
1126 */
1127 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1128 {
1129 struct pci_dev *p;
1130
1131 /* check only discrete GPU */
1132 switch (pci->vendor) {
1133 case PCI_VENDOR_ID_ATI:
1134 case PCI_VENDOR_ID_AMD:
1135 case PCI_VENDOR_ID_NVIDIA:
1136 if (pci->devfn == 1) {
1137 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1138 pci->bus->number, 0);
1139 if (p) {
1140 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1141 return p;
1142 pci_dev_put(p);
1143 }
1144 }
1145 break;
1146 }
1147 return NULL;
1148 }
1149
1150 static bool check_hdmi_disabled(struct pci_dev *pci)
1151 {
1152 bool vga_inactive = false;
1153 struct pci_dev *p = get_bound_vga(pci);
1154
1155 if (p) {
1156 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1157 vga_inactive = true;
1158 pci_dev_put(p);
1159 }
1160 return vga_inactive;
1161 }
1162 #endif /* SUPPORT_VGA_SWITCHEROO */
1163
1164 /*
1165 * white/black-listing for position_fix
1166 */
1167 static struct snd_pci_quirk position_fix_list[] = {
1168 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1169 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1170 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1171 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1172 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1173 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1174 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1175 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1176 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1177 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1178 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1179 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1180 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1181 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1182 {}
1183 };
1184
1185 static int check_position_fix(struct azx *chip, int fix)
1186 {
1187 const struct snd_pci_quirk *q;
1188
1189 switch (fix) {
1190 case POS_FIX_AUTO:
1191 case POS_FIX_LPIB:
1192 case POS_FIX_POSBUF:
1193 case POS_FIX_VIACOMBO:
1194 case POS_FIX_COMBO:
1195 return fix;
1196 }
1197
1198 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1199 if (q) {
1200 dev_info(chip->card->dev,
1201 "position_fix set to %d for device %04x:%04x\n",
1202 q->value, q->subvendor, q->subdevice);
1203 return q->value;
1204 }
1205
1206 /* Check VIA/ATI HD Audio Controller exist */
1207 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1208 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1209 return POS_FIX_VIACOMBO;
1210 }
1211 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1212 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1213 return POS_FIX_LPIB;
1214 }
1215 return POS_FIX_AUTO;
1216 }
1217
1218 static void assign_position_fix(struct azx *chip, int fix)
1219 {
1220 static azx_get_pos_callback_t callbacks[] = {
1221 [POS_FIX_AUTO] = NULL,
1222 [POS_FIX_LPIB] = azx_get_pos_lpib,
1223 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1224 [POS_FIX_VIACOMBO] = azx_via_get_position,
1225 [POS_FIX_COMBO] = azx_get_pos_lpib,
1226 };
1227
1228 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1229
1230 /* combo mode uses LPIB only for playback */
1231 if (fix == POS_FIX_COMBO)
1232 chip->get_position[1] = NULL;
1233
1234 if (fix == POS_FIX_POSBUF &&
1235 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1236 chip->get_delay[0] = chip->get_delay[1] =
1237 azx_get_delay_from_lpib;
1238 }
1239
1240 }
1241
1242 /*
1243 * black-lists for probe_mask
1244 */
1245 static struct snd_pci_quirk probe_mask_list[] = {
1246 /* Thinkpad often breaks the controller communication when accessing
1247 * to the non-working (or non-existing) modem codec slot.
1248 */
1249 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1250 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1251 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1252 /* broken BIOS */
1253 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1254 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1255 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1256 /* forced codec slots */
1257 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1258 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1259 /* WinFast VP200 H (Teradici) user reported broken communication */
1260 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1261 {}
1262 };
1263
1264 #define AZX_FORCE_CODEC_MASK 0x100
1265
1266 static void check_probe_mask(struct azx *chip, int dev)
1267 {
1268 const struct snd_pci_quirk *q;
1269
1270 chip->codec_probe_mask = probe_mask[dev];
1271 if (chip->codec_probe_mask == -1) {
1272 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1273 if (q) {
1274 dev_info(chip->card->dev,
1275 "probe_mask set to 0x%x for device %04x:%04x\n",
1276 q->value, q->subvendor, q->subdevice);
1277 chip->codec_probe_mask = q->value;
1278 }
1279 }
1280
1281 /* check forced option */
1282 if (chip->codec_probe_mask != -1 &&
1283 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1284 chip->codec_mask = chip->codec_probe_mask & 0xff;
1285 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1286 chip->codec_mask);
1287 }
1288 }
1289
1290 /*
1291 * white/black-list for enable_msi
1292 */
1293 static struct snd_pci_quirk msi_black_list[] = {
1294 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1295 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1296 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1297 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1298 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1299 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1300 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1301 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1302 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1303 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1304 {}
1305 };
1306
1307 static void check_msi(struct azx *chip)
1308 {
1309 const struct snd_pci_quirk *q;
1310
1311 if (enable_msi >= 0) {
1312 chip->msi = !!enable_msi;
1313 return;
1314 }
1315 chip->msi = 1; /* enable MSI as default */
1316 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1317 if (q) {
1318 dev_info(chip->card->dev,
1319 "msi for device %04x:%04x set to %d\n",
1320 q->subvendor, q->subdevice, q->value);
1321 chip->msi = q->value;
1322 return;
1323 }
1324
1325 /* NVidia chipsets seem to cause troubles with MSI */
1326 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1327 dev_info(chip->card->dev, "Disabling MSI\n");
1328 chip->msi = 0;
1329 }
1330 }
1331
1332 /* check the snoop mode availability */
1333 static void azx_check_snoop_available(struct azx *chip)
1334 {
1335 int snoop = hda_snoop;
1336
1337 if (snoop >= 0) {
1338 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1339 snoop ? "snoop" : "non-snoop");
1340 chip->snoop = snoop;
1341 return;
1342 }
1343
1344 snoop = true;
1345 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1346 chip->driver_type == AZX_DRIVER_VIA) {
1347 /* force to non-snoop mode for a new VIA controller
1348 * when BIOS is set
1349 */
1350 u8 val;
1351 pci_read_config_byte(chip->pci, 0x42, &val);
1352 if (!(val & 0x80) && chip->pci->revision == 0x30)
1353 snoop = false;
1354 }
1355
1356 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1357 snoop = false;
1358
1359 chip->snoop = snoop;
1360 if (!snoop)
1361 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1362 }
1363
1364 static void azx_probe_work(struct work_struct *work)
1365 {
1366 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1367 azx_probe_continue(&hda->chip);
1368 }
1369
1370 /*
1371 * constructor
1372 */
1373 static const struct hdac_io_ops pci_hda_io_ops;
1374 static const struct hda_controller_ops pci_hda_ops;
1375
1376 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1377 int dev, unsigned int driver_caps,
1378 struct azx **rchip)
1379 {
1380 static struct snd_device_ops ops = {
1381 .dev_free = azx_dev_free,
1382 };
1383 struct hda_intel *hda;
1384 struct azx *chip;
1385 int err;
1386
1387 *rchip = NULL;
1388
1389 err = pci_enable_device(pci);
1390 if (err < 0)
1391 return err;
1392
1393 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1394 if (!hda) {
1395 pci_disable_device(pci);
1396 return -ENOMEM;
1397 }
1398
1399 chip = &hda->chip;
1400 spin_lock_init(&chip->reg_lock);
1401 mutex_init(&chip->open_mutex);
1402 chip->card = card;
1403 chip->pci = pci;
1404 chip->ops = &pci_hda_ops;
1405 chip->io_ops = &pci_hda_io_ops;
1406 chip->irq = -1;
1407 chip->driver_caps = driver_caps;
1408 chip->driver_type = driver_caps & 0xff;
1409 check_msi(chip);
1410 chip->dev_index = dev;
1411 chip->jackpoll_ms = jackpoll_ms;
1412 INIT_LIST_HEAD(&chip->pcm_list);
1413 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1414 INIT_LIST_HEAD(&hda->list);
1415 init_vga_switcheroo(chip);
1416 init_completion(&hda->probe_wait);
1417
1418 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1419
1420 check_probe_mask(chip, dev);
1421
1422 chip->single_cmd = single_cmd;
1423 azx_check_snoop_available(chip);
1424
1425 if (bdl_pos_adj[dev] < 0) {
1426 switch (chip->driver_type) {
1427 case AZX_DRIVER_ICH:
1428 case AZX_DRIVER_PCH:
1429 bdl_pos_adj[dev] = 1;
1430 break;
1431 default:
1432 bdl_pos_adj[dev] = 32;
1433 break;
1434 }
1435 }
1436 chip->bdl_pos_adj = bdl_pos_adj;
1437
1438 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1439 if (err < 0) {
1440 dev_err(card->dev, "Error creating device [card]!\n");
1441 azx_free(chip);
1442 return err;
1443 }
1444
1445 /* continue probing in work context as may trigger request module */
1446 INIT_WORK(&hda->probe_work, azx_probe_work);
1447
1448 *rchip = chip;
1449
1450 return 0;
1451 }
1452
1453 static int azx_first_init(struct azx *chip)
1454 {
1455 int dev = chip->dev_index;
1456 struct pci_dev *pci = chip->pci;
1457 struct snd_card *card = chip->card;
1458 int err;
1459 unsigned short gcap;
1460 unsigned int dma_bits = 64;
1461
1462 #if BITS_PER_LONG != 64
1463 /* Fix up base address on ULI M5461 */
1464 if (chip->driver_type == AZX_DRIVER_ULI) {
1465 u16 tmp3;
1466 pci_read_config_word(pci, 0x40, &tmp3);
1467 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1468 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1469 }
1470 #endif
1471
1472 err = pci_request_regions(pci, "ICH HD audio");
1473 if (err < 0)
1474 return err;
1475 chip->region_requested = 1;
1476
1477 chip->addr = pci_resource_start(pci, 0);
1478 chip->remap_addr = pci_ioremap_bar(pci, 0);
1479 if (chip->remap_addr == NULL) {
1480 dev_err(card->dev, "ioremap error\n");
1481 return -ENXIO;
1482 }
1483 azx_bus(chip)->remap_addr = chip->remap_addr; /* FIXME */
1484
1485 if (chip->msi) {
1486 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1487 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1488 pci->no_64bit_msi = true;
1489 }
1490 if (pci_enable_msi(pci) < 0)
1491 chip->msi = 0;
1492 }
1493
1494 if (azx_acquire_irq(chip, 0) < 0)
1495 return -EBUSY;
1496
1497 pci_set_master(pci);
1498 synchronize_irq(chip->irq);
1499
1500 gcap = azx_readw(chip, GCAP);
1501 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1502
1503 /* AMD devices support 40 or 48bit DMA, take the safe one */
1504 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1505 dma_bits = 40;
1506
1507 /* disable SB600 64bit support for safety */
1508 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1509 struct pci_dev *p_smbus;
1510 dma_bits = 40;
1511 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1512 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1513 NULL);
1514 if (p_smbus) {
1515 if (p_smbus->revision < 0x30)
1516 gcap &= ~AZX_GCAP_64OK;
1517 pci_dev_put(p_smbus);
1518 }
1519 }
1520
1521 /* disable 64bit DMA address on some devices */
1522 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1523 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1524 gcap &= ~AZX_GCAP_64OK;
1525 }
1526
1527 /* disable buffer size rounding to 128-byte multiples if supported */
1528 if (align_buffer_size >= 0)
1529 chip->align_buffer_size = !!align_buffer_size;
1530 else {
1531 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1532 chip->align_buffer_size = 0;
1533 else
1534 chip->align_buffer_size = 1;
1535 }
1536
1537 /* allow 64bit DMA address if supported by H/W */
1538 if (!(gcap & AZX_GCAP_64OK))
1539 dma_bits = 32;
1540 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1541 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1542 } else {
1543 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1544 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1545 }
1546
1547 /* read number of streams from GCAP register instead of using
1548 * hardcoded value
1549 */
1550 chip->capture_streams = (gcap >> 8) & 0x0f;
1551 chip->playback_streams = (gcap >> 12) & 0x0f;
1552 if (!chip->playback_streams && !chip->capture_streams) {
1553 /* gcap didn't give any info, switching to old method */
1554
1555 switch (chip->driver_type) {
1556 case AZX_DRIVER_ULI:
1557 chip->playback_streams = ULI_NUM_PLAYBACK;
1558 chip->capture_streams = ULI_NUM_CAPTURE;
1559 break;
1560 case AZX_DRIVER_ATIHDMI:
1561 case AZX_DRIVER_ATIHDMI_NS:
1562 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1563 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1564 break;
1565 case AZX_DRIVER_GENERIC:
1566 default:
1567 chip->playback_streams = ICH6_NUM_PLAYBACK;
1568 chip->capture_streams = ICH6_NUM_CAPTURE;
1569 break;
1570 }
1571 }
1572 chip->capture_index_offset = 0;
1573 chip->playback_index_offset = chip->capture_streams;
1574 chip->num_streams = chip->playback_streams + chip->capture_streams;
1575
1576 err = azx_alloc_stream_pages(chip);
1577 if (err < 0)
1578 return err;
1579
1580 /* initialize streams */
1581 azx_init_stream(chip);
1582
1583 /* initialize chip */
1584 azx_init_pci(chip);
1585
1586 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1587 struct hda_intel *hda;
1588
1589 hda = container_of(chip, struct hda_intel, chip);
1590 haswell_set_bclk(hda);
1591 }
1592
1593 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1594
1595 /* codec detection */
1596 if (!chip->codec_mask) {
1597 dev_err(card->dev, "no codecs found!\n");
1598 return -ENODEV;
1599 }
1600
1601 strcpy(card->driver, "HDA-Intel");
1602 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1603 sizeof(card->shortname));
1604 snprintf(card->longname, sizeof(card->longname),
1605 "%s at 0x%lx irq %i",
1606 card->shortname, chip->addr, chip->irq);
1607
1608 return 0;
1609 }
1610
1611 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1612 /* callback from request_firmware_nowait() */
1613 static void azx_firmware_cb(const struct firmware *fw, void *context)
1614 {
1615 struct snd_card *card = context;
1616 struct azx *chip = card->private_data;
1617 struct pci_dev *pci = chip->pci;
1618
1619 if (!fw) {
1620 dev_err(card->dev, "Cannot load firmware, aborting\n");
1621 goto error;
1622 }
1623
1624 chip->fw = fw;
1625 if (!chip->disabled) {
1626 /* continue probing */
1627 if (azx_probe_continue(chip))
1628 goto error;
1629 }
1630 return; /* OK */
1631
1632 error:
1633 snd_card_free(card);
1634 pci_set_drvdata(pci, NULL);
1635 }
1636 #endif
1637
1638 /*
1639 * HDA controller ops.
1640 */
1641
1642 /* PCI register access. */
1643 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1644 {
1645 writel(value, addr);
1646 }
1647
1648 static u32 pci_azx_readl(u32 __iomem *addr)
1649 {
1650 return readl(addr);
1651 }
1652
1653 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1654 {
1655 writew(value, addr);
1656 }
1657
1658 static u16 pci_azx_readw(u16 __iomem *addr)
1659 {
1660 return readw(addr);
1661 }
1662
1663 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1664 {
1665 writeb(value, addr);
1666 }
1667
1668 static u8 pci_azx_readb(u8 __iomem *addr)
1669 {
1670 return readb(addr);
1671 }
1672
1673 static int disable_msi_reset_irq(struct azx *chip)
1674 {
1675 int err;
1676
1677 free_irq(chip->irq, chip);
1678 chip->irq = -1;
1679 pci_disable_msi(chip->pci);
1680 chip->msi = 0;
1681 err = azx_acquire_irq(chip, 1);
1682 if (err < 0)
1683 return err;
1684
1685 return 0;
1686 }
1687
1688 /* DMA page allocation helpers. */
1689 static int dma_alloc_pages(struct hdac_bus *bus,
1690 int type,
1691 size_t size,
1692 struct snd_dma_buffer *buf)
1693 {
1694 struct azx *chip = to_hda_bus(bus)->private_data;
1695 int err;
1696
1697 err = snd_dma_alloc_pages(type,
1698 bus->dev,
1699 size, buf);
1700 if (err < 0)
1701 return err;
1702 mark_pages_wc(chip, buf, true);
1703 return 0;
1704 }
1705
1706 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1707 {
1708 struct azx *chip = to_hda_bus(bus)->private_data;
1709
1710 mark_pages_wc(chip, buf, false);
1711 snd_dma_free_pages(buf);
1712 }
1713
1714 static int substream_alloc_pages(struct azx *chip,
1715 struct snd_pcm_substream *substream,
1716 size_t size)
1717 {
1718 struct azx_dev *azx_dev = get_azx_dev(substream);
1719 int ret;
1720
1721 mark_runtime_wc(chip, azx_dev, substream, false);
1722 azx_dev->core.bufsize = 0;
1723 azx_dev->core.period_bytes = 0;
1724 azx_dev->core.format_val = 0;
1725 ret = snd_pcm_lib_malloc_pages(substream, size);
1726 if (ret < 0)
1727 return ret;
1728 mark_runtime_wc(chip, azx_dev, substream, true);
1729 return 0;
1730 }
1731
1732 static int substream_free_pages(struct azx *chip,
1733 struct snd_pcm_substream *substream)
1734 {
1735 struct azx_dev *azx_dev = get_azx_dev(substream);
1736 mark_runtime_wc(chip, azx_dev, substream, false);
1737 return snd_pcm_lib_free_pages(substream);
1738 }
1739
1740 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1741 struct vm_area_struct *area)
1742 {
1743 #ifdef CONFIG_X86
1744 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1745 struct azx *chip = apcm->chip;
1746 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1747 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1748 #endif
1749 }
1750
1751 static const struct hdac_io_ops pci_hda_io_ops = {
1752 .reg_writel = pci_azx_writel,
1753 .reg_readl = pci_azx_readl,
1754 .reg_writew = pci_azx_writew,
1755 .reg_readw = pci_azx_readw,
1756 .reg_writeb = pci_azx_writeb,
1757 .reg_readb = pci_azx_readb,
1758 .dma_alloc_pages = dma_alloc_pages,
1759 .dma_free_pages = dma_free_pages,
1760 };
1761
1762 static const struct hda_controller_ops pci_hda_ops = {
1763 .disable_msi_reset_irq = disable_msi_reset_irq,
1764 .substream_alloc_pages = substream_alloc_pages,
1765 .substream_free_pages = substream_free_pages,
1766 .pcm_mmap_prepare = pcm_mmap_prepare,
1767 .position_check = azx_position_check,
1768 };
1769
1770 static int azx_probe(struct pci_dev *pci,
1771 const struct pci_device_id *pci_id)
1772 {
1773 static int dev;
1774 struct snd_card *card;
1775 struct hda_intel *hda;
1776 struct azx *chip;
1777 bool schedule_probe;
1778 int err;
1779
1780 if (dev >= SNDRV_CARDS)
1781 return -ENODEV;
1782 if (!enable[dev]) {
1783 dev++;
1784 return -ENOENT;
1785 }
1786
1787 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1788 0, &card);
1789 if (err < 0) {
1790 dev_err(&pci->dev, "Error creating card!\n");
1791 return err;
1792 }
1793
1794 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1795 if (err < 0)
1796 goto out_free;
1797 card->private_data = chip;
1798 hda = container_of(chip, struct hda_intel, chip);
1799
1800 pci_set_drvdata(pci, card);
1801
1802 err = register_vga_switcheroo(chip);
1803 if (err < 0) {
1804 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1805 goto out_free;
1806 }
1807
1808 if (check_hdmi_disabled(pci)) {
1809 dev_info(card->dev, "VGA controller is disabled\n");
1810 dev_info(card->dev, "Delaying initialization\n");
1811 chip->disabled = true;
1812 }
1813
1814 schedule_probe = !chip->disabled;
1815
1816 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1817 if (patch[dev] && *patch[dev]) {
1818 dev_info(card->dev, "Applying patch firmware '%s'\n",
1819 patch[dev]);
1820 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1821 &pci->dev, GFP_KERNEL, card,
1822 azx_firmware_cb);
1823 if (err < 0)
1824 goto out_free;
1825 schedule_probe = false; /* continued in azx_firmware_cb() */
1826 }
1827 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1828
1829 #ifndef CONFIG_SND_HDA_I915
1830 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1831 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1832 #endif
1833
1834 if (schedule_probe)
1835 schedule_work(&hda->probe_work);
1836
1837 dev++;
1838 if (chip->disabled)
1839 complete_all(&hda->probe_wait);
1840 return 0;
1841
1842 out_free:
1843 snd_card_free(card);
1844 return err;
1845 }
1846
1847 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1848 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1849 [AZX_DRIVER_NVIDIA] = 8,
1850 [AZX_DRIVER_TERA] = 1,
1851 };
1852
1853 static int azx_probe_continue(struct azx *chip)
1854 {
1855 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1856 struct pci_dev *pci = chip->pci;
1857 int dev = chip->dev_index;
1858 int err;
1859
1860 /* Request power well for Haswell HDA controller and codec */
1861 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1862 #ifdef CONFIG_SND_HDA_I915
1863 err = hda_i915_init(hda);
1864 if (err < 0)
1865 goto out_free;
1866 err = hda_display_power(hda, true);
1867 if (err < 0) {
1868 dev_err(chip->card->dev,
1869 "Cannot turn on display power on i915\n");
1870 goto out_free;
1871 }
1872 #endif
1873 }
1874
1875 err = azx_bus_create(chip, model[dev]);
1876 if (err < 0)
1877 goto out_free;
1878
1879 err = azx_first_init(chip);
1880 if (err < 0)
1881 goto out_free;
1882
1883 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1884 chip->beep_mode = beep_mode[dev];
1885 #endif
1886
1887 /* create codec instances */
1888 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
1889 if (err < 0)
1890 goto out_free;
1891
1892 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1893 if (chip->fw) {
1894 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1895 chip->fw->data);
1896 if (err < 0)
1897 goto out_free;
1898 #ifndef CONFIG_PM
1899 release_firmware(chip->fw); /* no longer needed */
1900 chip->fw = NULL;
1901 #endif
1902 }
1903 #endif
1904 if ((probe_only[dev] & 1) == 0) {
1905 err = azx_codec_configure(chip);
1906 if (err < 0)
1907 goto out_free;
1908 }
1909
1910 err = snd_card_register(chip->card);
1911 if (err < 0)
1912 goto out_free;
1913
1914 chip->running = 1;
1915 azx_add_card_list(chip);
1916 snd_hda_set_power_save(chip->bus, power_save * 1000);
1917 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
1918 pm_runtime_put_noidle(&pci->dev);
1919
1920 out_free:
1921 if (err < 0)
1922 hda->init_failed = 1;
1923 complete_all(&hda->probe_wait);
1924 return err;
1925 }
1926
1927 static void azx_remove(struct pci_dev *pci)
1928 {
1929 struct snd_card *card = pci_get_drvdata(pci);
1930
1931 if (card)
1932 snd_card_free(card);
1933 }
1934
1935 static void azx_shutdown(struct pci_dev *pci)
1936 {
1937 struct snd_card *card = pci_get_drvdata(pci);
1938 struct azx *chip;
1939
1940 if (!card)
1941 return;
1942 chip = card->private_data;
1943 if (chip && chip->running)
1944 azx_stop_chip(chip);
1945 }
1946
1947 /* PCI IDs */
1948 static const struct pci_device_id azx_ids[] = {
1949 /* CPT */
1950 { PCI_DEVICE(0x8086, 0x1c20),
1951 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1952 /* PBG */
1953 { PCI_DEVICE(0x8086, 0x1d20),
1954 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1955 /* Panther Point */
1956 { PCI_DEVICE(0x8086, 0x1e20),
1957 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1958 /* Lynx Point */
1959 { PCI_DEVICE(0x8086, 0x8c20),
1960 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1961 /* 9 Series */
1962 { PCI_DEVICE(0x8086, 0x8ca0),
1963 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1964 /* Wellsburg */
1965 { PCI_DEVICE(0x8086, 0x8d20),
1966 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1967 { PCI_DEVICE(0x8086, 0x8d21),
1968 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1969 /* Lynx Point-LP */
1970 { PCI_DEVICE(0x8086, 0x9c20),
1971 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1972 /* Lynx Point-LP */
1973 { PCI_DEVICE(0x8086, 0x9c21),
1974 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1975 /* Wildcat Point-LP */
1976 { PCI_DEVICE(0x8086, 0x9ca0),
1977 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1978 /* Sunrise Point */
1979 { PCI_DEVICE(0x8086, 0xa170),
1980 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
1981 /* Sunrise Point-LP */
1982 { PCI_DEVICE(0x8086, 0x9d70),
1983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
1984 /* Haswell */
1985 { PCI_DEVICE(0x8086, 0x0a0c),
1986 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1987 { PCI_DEVICE(0x8086, 0x0c0c),
1988 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1989 { PCI_DEVICE(0x8086, 0x0d0c),
1990 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1991 /* Broadwell */
1992 { PCI_DEVICE(0x8086, 0x160c),
1993 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
1994 /* 5 Series/3400 */
1995 { PCI_DEVICE(0x8086, 0x3b56),
1996 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1997 /* Poulsbo */
1998 { PCI_DEVICE(0x8086, 0x811b),
1999 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2000 /* Oaktrail */
2001 { PCI_DEVICE(0x8086, 0x080a),
2002 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2003 /* BayTrail */
2004 { PCI_DEVICE(0x8086, 0x0f04),
2005 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2006 /* Braswell */
2007 { PCI_DEVICE(0x8086, 0x2284),
2008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2009 /* ICH6 */
2010 { PCI_DEVICE(0x8086, 0x2668),
2011 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2012 /* ICH7 */
2013 { PCI_DEVICE(0x8086, 0x27d8),
2014 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2015 /* ESB2 */
2016 { PCI_DEVICE(0x8086, 0x269a),
2017 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2018 /* ICH8 */
2019 { PCI_DEVICE(0x8086, 0x284b),
2020 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2021 /* ICH9 */
2022 { PCI_DEVICE(0x8086, 0x293e),
2023 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2024 /* ICH9 */
2025 { PCI_DEVICE(0x8086, 0x293f),
2026 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2027 /* ICH10 */
2028 { PCI_DEVICE(0x8086, 0x3a3e),
2029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2030 /* ICH10 */
2031 { PCI_DEVICE(0x8086, 0x3a6e),
2032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2033 /* Generic Intel */
2034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2035 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2036 .class_mask = 0xffffff,
2037 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2038 /* ATI SB 450/600/700/800/900 */
2039 { PCI_DEVICE(0x1002, 0x437b),
2040 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2041 { PCI_DEVICE(0x1002, 0x4383),
2042 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2043 /* AMD Hudson */
2044 { PCI_DEVICE(0x1022, 0x780d),
2045 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2046 /* ATI HDMI */
2047 { PCI_DEVICE(0x1002, 0x793b),
2048 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2049 { PCI_DEVICE(0x1002, 0x7919),
2050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2051 { PCI_DEVICE(0x1002, 0x960f),
2052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2053 { PCI_DEVICE(0x1002, 0x970f),
2054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2055 { PCI_DEVICE(0x1002, 0xaa00),
2056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2057 { PCI_DEVICE(0x1002, 0xaa08),
2058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2059 { PCI_DEVICE(0x1002, 0xaa10),
2060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2061 { PCI_DEVICE(0x1002, 0xaa18),
2062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2063 { PCI_DEVICE(0x1002, 0xaa20),
2064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2065 { PCI_DEVICE(0x1002, 0xaa28),
2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2067 { PCI_DEVICE(0x1002, 0xaa30),
2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2069 { PCI_DEVICE(0x1002, 0xaa38),
2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2071 { PCI_DEVICE(0x1002, 0xaa40),
2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2073 { PCI_DEVICE(0x1002, 0xaa48),
2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2075 { PCI_DEVICE(0x1002, 0xaa50),
2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2077 { PCI_DEVICE(0x1002, 0xaa58),
2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2079 { PCI_DEVICE(0x1002, 0xaa60),
2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2081 { PCI_DEVICE(0x1002, 0xaa68),
2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2083 { PCI_DEVICE(0x1002, 0xaa80),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0xaa88),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0xaa90),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2089 { PCI_DEVICE(0x1002, 0xaa98),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0x9902),
2092 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2093 { PCI_DEVICE(0x1002, 0xaaa0),
2094 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2095 { PCI_DEVICE(0x1002, 0xaaa8),
2096 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2097 { PCI_DEVICE(0x1002, 0xaab0),
2098 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2099 /* VIA VT8251/VT8237A */
2100 { PCI_DEVICE(0x1106, 0x3288),
2101 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2102 /* VIA GFX VT7122/VX900 */
2103 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2104 /* VIA GFX VT6122/VX11 */
2105 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2106 /* SIS966 */
2107 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2108 /* ULI M5461 */
2109 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2110 /* NVIDIA MCP */
2111 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2112 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2113 .class_mask = 0xffffff,
2114 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2115 /* Teradici */
2116 { PCI_DEVICE(0x6549, 0x1200),
2117 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2118 { PCI_DEVICE(0x6549, 0x2200),
2119 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2120 /* Creative X-Fi (CA0110-IBG) */
2121 /* CTHDA chips */
2122 { PCI_DEVICE(0x1102, 0x0010),
2123 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2124 { PCI_DEVICE(0x1102, 0x0012),
2125 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2126 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2127 /* the following entry conflicts with snd-ctxfi driver,
2128 * as ctxfi driver mutates from HD-audio to native mode with
2129 * a special command sequence.
2130 */
2131 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2132 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2133 .class_mask = 0xffffff,
2134 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2135 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2136 #else
2137 /* this entry seems still valid -- i.e. without emu20kx chip */
2138 { PCI_DEVICE(0x1102, 0x0009),
2139 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2140 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2141 #endif
2142 /* CM8888 */
2143 { PCI_DEVICE(0x13f6, 0x5011),
2144 .driver_data = AZX_DRIVER_CMEDIA |
2145 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2146 /* Vortex86MX */
2147 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2148 /* VMware HDAudio */
2149 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2150 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2151 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2152 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2153 .class_mask = 0xffffff,
2154 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2155 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2156 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2157 .class_mask = 0xffffff,
2158 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2159 { 0, }
2160 };
2161 MODULE_DEVICE_TABLE(pci, azx_ids);
2162
2163 /* pci_driver definition */
2164 static struct pci_driver azx_driver = {
2165 .name = KBUILD_MODNAME,
2166 .id_table = azx_ids,
2167 .probe = azx_probe,
2168 .remove = azx_remove,
2169 .shutdown = azx_shutdown,
2170 .driver = {
2171 .pm = AZX_PM_OPS,
2172 },
2173 };
2174
2175 module_pci_driver(azx_driver);
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