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ALSA: hda/intel: stop probe if DMICS are detected on Skylake+ platforms
[mirror_ubuntu-eoan-kernel.git] / sound / pci / hda / hda_intel.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38
39 #ifdef CONFIG_X86
40 /* for snoop control */
41 #include <asm/pgtable.h>
42 #include <asm/set_memory.h>
43 #include <asm/cpufeature.h>
44 #endif
45 #include <sound/core.h>
46 #include <sound/initval.h>
47 #include <sound/hdaudio.h>
48 #include <sound/hda_i915.h>
49 #include <sound/intel-nhlt.h>
50 #include <linux/vgaarb.h>
51 #include <linux/vga_switcheroo.h>
52 #include <linux/firmware.h>
53 #include <sound/hda_codec.h>
54 #include "hda_controller.h"
55 #include "hda_intel.h"
56
57 #define CREATE_TRACE_POINTS
58 #include "hda_intel_trace.h"
59
60 /* position fix mode */
61 enum {
62 POS_FIX_AUTO,
63 POS_FIX_LPIB,
64 POS_FIX_POSBUF,
65 POS_FIX_VIACOMBO,
66 POS_FIX_COMBO,
67 POS_FIX_SKL,
68 POS_FIX_FIFO,
69 };
70
71 /* Defines for ATI HD Audio support in SB450 south bridge */
72 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
73 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
74
75 /* Defines for Nvidia HDA support */
76 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
77 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
78 #define NVIDIA_HDA_ISTRM_COH 0x4d
79 #define NVIDIA_HDA_OSTRM_COH 0x4c
80 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
81
82 /* Defines for Intel SCH HDA snoop control */
83 #define INTEL_HDA_CGCTL 0x48
84 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
85 #define INTEL_SCH_HDA_DEVC 0x78
86 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
87
88 /* Define IN stream 0 FIFO size offset in VIA controller */
89 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
90 /* Define VIA HD Audio Device ID*/
91 #define VIA_HDAC_DEVICE_ID 0x3288
92
93 /* max number of SDs */
94 /* ICH, ATI and VIA have 4 playback and 4 capture */
95 #define ICH6_NUM_CAPTURE 4
96 #define ICH6_NUM_PLAYBACK 4
97
98 /* ULI has 6 playback and 5 capture */
99 #define ULI_NUM_CAPTURE 5
100 #define ULI_NUM_PLAYBACK 6
101
102 /* ATI HDMI may have up to 8 playbacks and 0 capture */
103 #define ATIHDMI_NUM_CAPTURE 0
104 #define ATIHDMI_NUM_PLAYBACK 8
105
106 /* TERA has 4 playback and 3 capture */
107 #define TERA_NUM_CAPTURE 3
108 #define TERA_NUM_PLAYBACK 4
109
110
111 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
112 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
113 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
114 static char *model[SNDRV_CARDS];
115 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
118 static int probe_only[SNDRV_CARDS];
119 static int jackpoll_ms[SNDRV_CARDS];
120 static int single_cmd = -1;
121 static int enable_msi = -1;
122 #ifdef CONFIG_SND_HDA_PATCH_LOADER
123 static char *patch[SNDRV_CARDS];
124 #endif
125 #ifdef CONFIG_SND_HDA_INPUT_BEEP
126 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
127 CONFIG_SND_HDA_INPUT_BEEP_MODE};
128 #endif
129 static bool dmic_detect = IS_ENABLED(CONFIG_SND_HDA_INTEL_DETECT_DMIC);
130
131 module_param_array(index, int, NULL, 0444);
132 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
133 module_param_array(id, charp, NULL, 0444);
134 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
135 module_param_array(enable, bool, NULL, 0444);
136 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
137 module_param_array(model, charp, NULL, 0444);
138 MODULE_PARM_DESC(model, "Use the given board model.");
139 module_param_array(position_fix, int, NULL, 0444);
140 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
141 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
142 module_param_array(bdl_pos_adj, int, NULL, 0644);
143 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
144 module_param_array(probe_mask, int, NULL, 0444);
145 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
146 module_param_array(probe_only, int, NULL, 0444);
147 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
148 module_param_array(jackpoll_ms, int, NULL, 0444);
149 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
150 module_param(single_cmd, bint, 0444);
151 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
152 "(for debugging only).");
153 module_param(enable_msi, bint, 0444);
154 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
155 #ifdef CONFIG_SND_HDA_PATCH_LOADER
156 module_param_array(patch, charp, NULL, 0444);
157 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
158 #endif
159 #ifdef CONFIG_SND_HDA_INPUT_BEEP
160 module_param_array(beep_mode, bool, NULL, 0444);
161 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
162 "(0=off, 1=on) (default=1).");
163 #endif
164 module_param(dmic_detect, bool, 0444);
165 MODULE_PARM_DESC(dmic_detect, "DMIC detect on SKL+ platforms");
166
167 #ifdef CONFIG_PM
168 static int param_set_xint(const char *val, const struct kernel_param *kp);
169 static const struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172 };
173 #define param_check_xint param_check_int
174
175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
176 module_param(power_save, xint, 0644);
177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
179
180 static bool pm_blacklist = true;
181 module_param(pm_blacklist, bool, 0644);
182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist");
183
184 /* reset the HD-audio controller in power save mode.
185 * this may give more power-saving, but will take longer time to
186 * wake up.
187 */
188 static bool power_save_controller = 1;
189 module_param(power_save_controller, bool, 0644);
190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
191 #else
192 #define power_save 0
193 #endif /* CONFIG_PM */
194
195 static int align_buffer_size = -1;
196 module_param(align_buffer_size, bint, 0644);
197 MODULE_PARM_DESC(align_buffer_size,
198 "Force buffer and period sizes to be multiple of 128 bytes.");
199
200 #ifdef CONFIG_X86
201 static int hda_snoop = -1;
202 module_param_named(snoop, hda_snoop, bint, 0444);
203 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
204 #else
205 #define hda_snoop true
206 #endif
207
208
209 MODULE_LICENSE("GPL");
210 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
211 "{Intel, ICH6M},"
212 "{Intel, ICH7},"
213 "{Intel, ESB2},"
214 "{Intel, ICH8},"
215 "{Intel, ICH9},"
216 "{Intel, ICH10},"
217 "{Intel, PCH},"
218 "{Intel, CPT},"
219 "{Intel, PPT},"
220 "{Intel, LPT},"
221 "{Intel, LPT_LP},"
222 "{Intel, WPT_LP},"
223 "{Intel, SPT},"
224 "{Intel, SPT_LP},"
225 "{Intel, HPT},"
226 "{Intel, PBG},"
227 "{Intel, SCH},"
228 "{ATI, SB450},"
229 "{ATI, SB600},"
230 "{ATI, RS600},"
231 "{ATI, RS690},"
232 "{ATI, RS780},"
233 "{ATI, R600},"
234 "{ATI, RV630},"
235 "{ATI, RV610},"
236 "{ATI, RV670},"
237 "{ATI, RV635},"
238 "{ATI, RV620},"
239 "{ATI, RV770},"
240 "{VIA, VT8251},"
241 "{VIA, VT8237A},"
242 "{SiS, SIS966},"
243 "{ULI, M5461}}");
244 MODULE_DESCRIPTION("Intel HDA driver");
245
246 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
247 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
248 #define SUPPORT_VGA_SWITCHEROO
249 #endif
250 #endif
251
252
253 /*
254 */
255
256 /* driver types */
257 enum {
258 AZX_DRIVER_ICH,
259 AZX_DRIVER_PCH,
260 AZX_DRIVER_SCH,
261 AZX_DRIVER_SKL,
262 AZX_DRIVER_HDMI,
263 AZX_DRIVER_ATI,
264 AZX_DRIVER_ATIHDMI,
265 AZX_DRIVER_ATIHDMI_NS,
266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
269 AZX_DRIVER_NVIDIA,
270 AZX_DRIVER_TERA,
271 AZX_DRIVER_CTX,
272 AZX_DRIVER_CTHDA,
273 AZX_DRIVER_CMEDIA,
274 AZX_DRIVER_GENERIC,
275 AZX_NUM_DRIVERS, /* keep this as last entry */
276 };
277
278 #define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
282 /* quirks for old Intel chipsets */
283 #define AZX_DCAPS_INTEL_ICH \
284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\
285 AZX_DCAPS_SYNC_WRITE)
286
287 /* quirks for Intel PCH */
288 #define AZX_DCAPS_INTEL_PCH_BASE \
289 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
290 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
291
292 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
293 #define AZX_DCAPS_INTEL_PCH_NOPM \
294 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
295
296 /* PCH for HSW/BDW; with runtime PM */
297 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
298 #define AZX_DCAPS_INTEL_PCH \
299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
300
301 /* HSW HDMI */
302 #define AZX_DCAPS_INTEL_HASWELL \
303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
305 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
306
307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
308 #define AZX_DCAPS_INTEL_BROADWELL \
309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
311 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE)
312
313 #define AZX_DCAPS_INTEL_BAYTRAIL \
314 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
315
316 #define AZX_DCAPS_INTEL_BRASWELL \
317 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
318 AZX_DCAPS_I915_COMPONENT)
319
320 #define AZX_DCAPS_INTEL_SKYLAKE \
321 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
322 AZX_DCAPS_SYNC_WRITE |\
323 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
324
325 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
326
327 /* quirks for ATI SB / AMD Hudson */
328 #define AZX_DCAPS_PRESET_ATI_SB \
329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
331
332 /* quirks for ATI/AMD HDMI */
333 #define AZX_DCAPS_PRESET_ATI_HDMI \
334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
336
337 /* quirks for ATI HDMI with snoop off */
338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
341 /* quirks for AMD SB */
342 #define AZX_DCAPS_PRESET_AMD_SB \
343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\
344 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME)
345
346 /* quirks for Nvidia */
347 #define AZX_DCAPS_PRESET_NVIDIA \
348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
349 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
350
351 #define AZX_DCAPS_PRESET_CTHDA \
352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
353 AZX_DCAPS_NO_64BIT |\
354 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
355
356 /*
357 * vga_switcheroo support
358 */
359 #ifdef SUPPORT_VGA_SWITCHEROO
360 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
361 #define needs_eld_notify_link(chip) ((chip)->need_eld_notify_link)
362 #else
363 #define use_vga_switcheroo(chip) 0
364 #define needs_eld_notify_link(chip) false
365 #endif
366
367 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
368 ((pci)->device == 0x0c0c) || \
369 ((pci)->device == 0x0d0c) || \
370 ((pci)->device == 0x160c))
371
372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
373 #define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)
374 #define IS_CNL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9dc8)
375
376 static char *driver_short_names[] = {
377 [AZX_DRIVER_ICH] = "HDA Intel",
378 [AZX_DRIVER_PCH] = "HDA Intel PCH",
379 [AZX_DRIVER_SCH] = "HDA Intel MID",
380 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
381 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
382 [AZX_DRIVER_ATI] = "HDA ATI SB",
383 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
384 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
389 [AZX_DRIVER_TERA] = "HDA Teradici",
390 [AZX_DRIVER_CTX] = "HDA Creative",
391 [AZX_DRIVER_CTHDA] = "HDA Creative",
392 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
394 };
395
396 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
397 static void set_default_power_save(struct azx *chip);
398
399 /*
400 * initialize the PCI registers
401 */
402 /* update bits in a PCI register byte */
403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
404 unsigned char mask, unsigned char val)
405 {
406 unsigned char data;
407
408 pci_read_config_byte(pci, reg, &data);
409 data &= ~mask;
410 data |= (val & mask);
411 pci_write_config_byte(pci, reg, data);
412 }
413
414 static void azx_init_pci(struct azx *chip)
415 {
416 int snoop_type = azx_get_snoop_type(chip);
417
418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
420 * Ensuring these bits are 0 clears playback static on some HD Audio
421 * codecs.
422 * The PCI register TCSEL is defined in the Intel manuals.
423 */
424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
425 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
427 }
428
429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
430 * we need to enable snoop.
431 */
432 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
434 azx_snoop(chip));
435 update_pci_byte(chip->pci,
436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
438 }
439
440 /* For NVIDIA HDA, enable snoop */
441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
443 azx_snoop(chip));
444 update_pci_byte(chip->pci,
445 NVIDIA_HDA_TRANSREG_ADDR,
446 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
447 update_pci_byte(chip->pci,
448 NVIDIA_HDA_ISTRM_COH,
449 0x01, NVIDIA_HDA_ENABLE_COHBIT);
450 update_pci_byte(chip->pci,
451 NVIDIA_HDA_OSTRM_COH,
452 0x01, NVIDIA_HDA_ENABLE_COHBIT);
453 }
454
455 /* Enable SCH/PCH snoop if needed */
456 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
457 unsigned short snoop;
458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
462 if (!azx_snoop(chip))
463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
465 pci_read_config_word(chip->pci,
466 INTEL_SCH_HDA_DEVC, &snoop);
467 }
468 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
470 "Disabled" : "Enabled");
471 }
472 }
473
474 /*
475 * In BXT-P A0, HD-Audio DMA requests is later than expected,
476 * and makes an audio stream sensitive to system latencies when
477 * 24/32 bits are playing.
478 * Adjusting threshold of DMA fifo to force the DMA request
479 * sooner to improve latency tolerance at the expense of power.
480 */
481 static void bxt_reduce_dma_latency(struct azx *chip)
482 {
483 u32 val;
484
485 val = azx_readl(chip, VS_EM4L);
486 val &= (0x3 << 20);
487 azx_writel(chip, VS_EM4L, val);
488 }
489
490 /*
491 * ML_LCAP bits:
492 * bit 0: 6 MHz Supported
493 * bit 1: 12 MHz Supported
494 * bit 2: 24 MHz Supported
495 * bit 3: 48 MHz Supported
496 * bit 4: 96 MHz Supported
497 * bit 5: 192 MHz Supported
498 */
499 static int intel_get_lctl_scf(struct azx *chip)
500 {
501 struct hdac_bus *bus = azx_bus(chip);
502 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
503 u32 val, t;
504 int i;
505
506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
507
508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
509 t = preferred_bits[i];
510 if (val & (1 << t))
511 return t;
512 }
513
514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
515 return 0;
516 }
517
518 static int intel_ml_lctl_set_power(struct azx *chip, int state)
519 {
520 struct hdac_bus *bus = azx_bus(chip);
521 u32 val;
522 int timeout;
523
524 /*
525 * the codecs are sharing the first link setting by default
526 * If other links are enabled for stream, they need similar fix
527 */
528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
529 val &= ~AZX_MLCTL_SPA;
530 val |= state << AZX_MLCTL_SPA_SHIFT;
531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
532 /* wait for CPA */
533 timeout = 50;
534 while (timeout) {
535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
537 return 0;
538 timeout--;
539 udelay(10);
540 }
541
542 return -1;
543 }
544
545 static void intel_init_lctl(struct azx *chip)
546 {
547 struct hdac_bus *bus = azx_bus(chip);
548 u32 val;
549 int ret;
550
551 /* 0. check lctl register value is correct or not */
552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
553 /* if SCF is already set, let's use it */
554 if ((val & ML_LCTL_SCF_MASK) != 0)
555 return;
556
557 /*
558 * Before operating on SPA, CPA must match SPA.
559 * Any deviation may result in undefined behavior.
560 */
561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
563 return;
564
565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
566 ret = intel_ml_lctl_set_power(chip, 0);
567 udelay(100);
568 if (ret)
569 goto set_spa;
570
571 /* 2. update SCF to select a properly audio clock*/
572 val &= ~ML_LCTL_SCF_MASK;
573 val |= intel_get_lctl_scf(chip);
574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
575
576 set_spa:
577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
578 intel_ml_lctl_set_power(chip, 1);
579 udelay(100);
580 }
581
582 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
583 {
584 struct hdac_bus *bus = azx_bus(chip);
585 struct pci_dev *pci = chip->pci;
586 u32 val;
587
588 snd_hdac_set_codec_wakeup(bus, true);
589 if (chip->driver_type == AZX_DRIVER_SKL) {
590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
593 }
594 azx_init_chip(chip, full_reset);
595 if (chip->driver_type == AZX_DRIVER_SKL) {
596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
597 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
599 }
600
601 snd_hdac_set_codec_wakeup(bus, false);
602
603 /* reduce dma latency to avoid noise */
604 if (IS_BXT(pci))
605 bxt_reduce_dma_latency(chip);
606
607 if (bus->mlcap != NULL)
608 intel_init_lctl(chip);
609 }
610
611 /* calculate runtime delay from LPIB */
612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
613 unsigned int pos)
614 {
615 struct snd_pcm_substream *substream = azx_dev->core.substream;
616 int stream = substream->stream;
617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
618 int delay;
619
620 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
621 delay = pos - lpib_pos;
622 else
623 delay = lpib_pos - pos;
624 if (delay < 0) {
625 if (delay >= azx_dev->core.delay_negative_threshold)
626 delay = 0;
627 else
628 delay += azx_dev->core.bufsize;
629 }
630
631 if (delay >= azx_dev->core.period_bytes) {
632 dev_info(chip->card->dev,
633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
634 delay, azx_dev->core.period_bytes);
635 delay = 0;
636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
637 chip->get_delay[stream] = NULL;
638 }
639
640 return bytes_to_frames(substream->runtime, delay);
641 }
642
643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
644
645 /* called from IRQ */
646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
647 {
648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
649 int ok;
650
651 ok = azx_position_ok(chip, azx_dev);
652 if (ok == 1) {
653 azx_dev->irq_pending = 0;
654 return ok;
655 } else if (ok == 0) {
656 /* bogus IRQ, process it later */
657 azx_dev->irq_pending = 1;
658 schedule_work(&hda->irq_pending_work);
659 }
660 return 0;
661 }
662
663 #define display_power(chip, enable) \
664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
665
666 /*
667 * Check whether the current DMA position is acceptable for updating
668 * periods. Returns non-zero if it's OK.
669 *
670 * Many HD-audio controllers appear pretty inaccurate about
671 * the update-IRQ timing. The IRQ is issued before actually the
672 * data is processed. So, we need to process it afterwords in a
673 * workqueue.
674 */
675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
676 {
677 struct snd_pcm_substream *substream = azx_dev->core.substream;
678 int stream = substream->stream;
679 u32 wallclk;
680 unsigned int pos;
681
682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
684 return -1; /* bogus (too early) interrupt */
685
686 if (chip->get_position[stream])
687 pos = chip->get_position[stream](chip, azx_dev);
688 else { /* use the position buffer as default */
689 pos = azx_get_pos_posbuf(chip, azx_dev);
690 if (!pos || pos == (u32)-1) {
691 dev_info(chip->card->dev,
692 "Invalid position buffer, using LPIB read method instead.\n");
693 chip->get_position[stream] = azx_get_pos_lpib;
694 if (chip->get_position[0] == azx_get_pos_lpib &&
695 chip->get_position[1] == azx_get_pos_lpib)
696 azx_bus(chip)->use_posbuf = false;
697 pos = azx_get_pos_lpib(chip, azx_dev);
698 chip->get_delay[stream] = NULL;
699 } else {
700 chip->get_position[stream] = azx_get_pos_posbuf;
701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
702 chip->get_delay[stream] = azx_get_delay_from_lpib;
703 }
704 }
705
706 if (pos >= azx_dev->core.bufsize)
707 pos = 0;
708
709 if (WARN_ONCE(!azx_dev->core.period_bytes,
710 "hda-intel: zero azx_dev->period_bytes"))
711 return -1; /* this shouldn't happen! */
712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
714 /* NG - it's below the first next period boundary */
715 return chip->bdl_pos_adj ? 0 : -1;
716 azx_dev->core.start_wallclk += wallclk;
717 return 1; /* OK, it's fine */
718 }
719
720 /*
721 * The work for pending PCM period updates.
722 */
723 static void azx_irq_pending_work(struct work_struct *work)
724 {
725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
726 struct azx *chip = &hda->chip;
727 struct hdac_bus *bus = azx_bus(chip);
728 struct hdac_stream *s;
729 int pending, ok;
730
731 if (!hda->irq_pending_warned) {
732 dev_info(chip->card->dev,
733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
734 chip->card->number);
735 hda->irq_pending_warned = 1;
736 }
737
738 for (;;) {
739 pending = 0;
740 spin_lock_irq(&bus->reg_lock);
741 list_for_each_entry(s, &bus->stream_list, list) {
742 struct azx_dev *azx_dev = stream_to_azx_dev(s);
743 if (!azx_dev->irq_pending ||
744 !s->substream ||
745 !s->running)
746 continue;
747 ok = azx_position_ok(chip, azx_dev);
748 if (ok > 0) {
749 azx_dev->irq_pending = 0;
750 spin_unlock(&bus->reg_lock);
751 snd_pcm_period_elapsed(s->substream);
752 spin_lock(&bus->reg_lock);
753 } else if (ok < 0) {
754 pending = 0; /* too early */
755 } else
756 pending++;
757 }
758 spin_unlock_irq(&bus->reg_lock);
759 if (!pending)
760 return;
761 msleep(1);
762 }
763 }
764
765 /* clear irq_pending flags and assure no on-going workq */
766 static void azx_clear_irq_pending(struct azx *chip)
767 {
768 struct hdac_bus *bus = azx_bus(chip);
769 struct hdac_stream *s;
770
771 spin_lock_irq(&bus->reg_lock);
772 list_for_each_entry(s, &bus->stream_list, list) {
773 struct azx_dev *azx_dev = stream_to_azx_dev(s);
774 azx_dev->irq_pending = 0;
775 }
776 spin_unlock_irq(&bus->reg_lock);
777 }
778
779 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
780 {
781 struct hdac_bus *bus = azx_bus(chip);
782
783 if (request_irq(chip->pci->irq, azx_interrupt,
784 chip->msi ? 0 : IRQF_SHARED,
785 chip->card->irq_descr, chip)) {
786 dev_err(chip->card->dev,
787 "unable to grab IRQ %d, disabling device\n",
788 chip->pci->irq);
789 if (do_disconnect)
790 snd_card_disconnect(chip->card);
791 return -1;
792 }
793 bus->irq = chip->pci->irq;
794 pci_intx(chip->pci, !chip->msi);
795 return 0;
796 }
797
798 /* get the current DMA position with correction on VIA chips */
799 static unsigned int azx_via_get_position(struct azx *chip,
800 struct azx_dev *azx_dev)
801 {
802 unsigned int link_pos, mini_pos, bound_pos;
803 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
804 unsigned int fifo_size;
805
806 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
807 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
808 /* Playback, no problem using link position */
809 return link_pos;
810 }
811
812 /* Capture */
813 /* For new chipset,
814 * use mod to get the DMA position just like old chipset
815 */
816 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
817 mod_dma_pos %= azx_dev->core.period_bytes;
818
819 /* azx_dev->fifo_size can't get FIFO size of in stream.
820 * Get from base address + offset.
821 */
822 fifo_size = readw(azx_bus(chip)->remap_addr +
823 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
824
825 if (azx_dev->insufficient) {
826 /* Link position never gather than FIFO size */
827 if (link_pos <= fifo_size)
828 return 0;
829
830 azx_dev->insufficient = 0;
831 }
832
833 if (link_pos <= fifo_size)
834 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
835 else
836 mini_pos = link_pos - fifo_size;
837
838 /* Find nearest previous boudary */
839 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
840 mod_link_pos = link_pos % azx_dev->core.period_bytes;
841 if (mod_link_pos >= fifo_size)
842 bound_pos = link_pos - mod_link_pos;
843 else if (mod_dma_pos >= mod_mini_pos)
844 bound_pos = mini_pos - mod_mini_pos;
845 else {
846 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
847 if (bound_pos >= azx_dev->core.bufsize)
848 bound_pos = 0;
849 }
850
851 /* Calculate real DMA position we want */
852 return bound_pos + mod_dma_pos;
853 }
854
855 #define AMD_FIFO_SIZE 32
856
857 /* get the current DMA position with FIFO size correction */
858 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
859 {
860 struct snd_pcm_substream *substream = azx_dev->core.substream;
861 struct snd_pcm_runtime *runtime = substream->runtime;
862 unsigned int pos, delay;
863
864 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
865 if (!runtime)
866 return pos;
867
868 runtime->delay = AMD_FIFO_SIZE;
869 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
870 if (azx_dev->insufficient) {
871 if (pos < delay) {
872 delay = pos;
873 runtime->delay = bytes_to_frames(runtime, pos);
874 } else {
875 azx_dev->insufficient = 0;
876 }
877 }
878
879 /* correct the DMA position for capture stream */
880 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
881 if (pos < delay)
882 pos += azx_dev->core.bufsize;
883 pos -= delay;
884 }
885
886 return pos;
887 }
888
889 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
890 unsigned int pos)
891 {
892 struct snd_pcm_substream *substream = azx_dev->core.substream;
893
894 /* just read back the calculated value in the above */
895 return substream->runtime->delay;
896 }
897
898 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
899 struct azx_dev *azx_dev)
900 {
901 return _snd_hdac_chip_readl(azx_bus(chip),
902 AZX_REG_VS_SDXDPIB_XBASE +
903 (AZX_REG_VS_SDXDPIB_XINTERVAL *
904 azx_dev->core.index));
905 }
906
907 /* get the current DMA position with correction on SKL+ chips */
908 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
909 {
910 /* DPIB register gives a more accurate position for playback */
911 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
912 return azx_skl_get_dpib_pos(chip, azx_dev);
913
914 /* For capture, we need to read posbuf, but it requires a delay
915 * for the possible boundary overlap; the read of DPIB fetches the
916 * actual posbuf
917 */
918 udelay(20);
919 azx_skl_get_dpib_pos(chip, azx_dev);
920 return azx_get_pos_posbuf(chip, azx_dev);
921 }
922
923 #ifdef CONFIG_PM
924 static DEFINE_MUTEX(card_list_lock);
925 static LIST_HEAD(card_list);
926
927 static void azx_add_card_list(struct azx *chip)
928 {
929 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
930 mutex_lock(&card_list_lock);
931 list_add(&hda->list, &card_list);
932 mutex_unlock(&card_list_lock);
933 }
934
935 static void azx_del_card_list(struct azx *chip)
936 {
937 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
938 mutex_lock(&card_list_lock);
939 list_del_init(&hda->list);
940 mutex_unlock(&card_list_lock);
941 }
942
943 /* trigger power-save check at writing parameter */
944 static int param_set_xint(const char *val, const struct kernel_param *kp)
945 {
946 struct hda_intel *hda;
947 struct azx *chip;
948 int prev = power_save;
949 int ret = param_set_int(val, kp);
950
951 if (ret || prev == power_save)
952 return ret;
953
954 mutex_lock(&card_list_lock);
955 list_for_each_entry(hda, &card_list, list) {
956 chip = &hda->chip;
957 if (!hda->probe_continued || chip->disabled)
958 continue;
959 snd_hda_set_power_save(&chip->bus, power_save * 1000);
960 }
961 mutex_unlock(&card_list_lock);
962 return 0;
963 }
964
965 /*
966 * power management
967 */
968 static bool azx_is_pm_ready(struct snd_card *card)
969 {
970 struct azx *chip;
971 struct hda_intel *hda;
972
973 if (!card)
974 return false;
975 chip = card->private_data;
976 hda = container_of(chip, struct hda_intel, chip);
977 if (chip->disabled || hda->init_failed || !chip->running)
978 return false;
979 return true;
980 }
981
982 static void __azx_runtime_suspend(struct azx *chip)
983 {
984 azx_stop_chip(chip);
985 azx_enter_link_reset(chip);
986 azx_clear_irq_pending(chip);
987 display_power(chip, false);
988 }
989
990 static void __azx_runtime_resume(struct azx *chip, bool from_rt)
991 {
992 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
993 struct hdac_bus *bus = azx_bus(chip);
994 struct hda_codec *codec;
995 int status;
996
997 display_power(chip, true);
998 if (hda->need_i915_power)
999 snd_hdac_i915_set_bclk(bus);
1000
1001 /* Read STATESTS before controller reset */
1002 status = azx_readw(chip, STATESTS);
1003
1004 azx_init_pci(chip);
1005 hda_intel_init_chip(chip, true);
1006
1007 if (status && from_rt) {
1008 list_for_each_codec(codec, &chip->bus)
1009 if (status & (1 << codec->addr))
1010 schedule_delayed_work(&codec->jackpoll_work,
1011 codec->jackpoll_interval);
1012 }
1013
1014 /* power down again for link-controlled chips */
1015 if (!hda->need_i915_power)
1016 display_power(chip, false);
1017 }
1018
1019 #ifdef CONFIG_PM_SLEEP
1020 static int azx_suspend(struct device *dev)
1021 {
1022 struct snd_card *card = dev_get_drvdata(dev);
1023 struct azx *chip;
1024 struct hdac_bus *bus;
1025
1026 if (!azx_is_pm_ready(card))
1027 return 0;
1028
1029 chip = card->private_data;
1030 bus = azx_bus(chip);
1031 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1032 __azx_runtime_suspend(chip);
1033 if (bus->irq >= 0) {
1034 free_irq(bus->irq, chip);
1035 bus->irq = -1;
1036 }
1037
1038 if (chip->msi)
1039 pci_disable_msi(chip->pci);
1040
1041 trace_azx_suspend(chip);
1042 return 0;
1043 }
1044
1045 static int azx_resume(struct device *dev)
1046 {
1047 struct snd_card *card = dev_get_drvdata(dev);
1048 struct azx *chip;
1049
1050 if (!azx_is_pm_ready(card))
1051 return 0;
1052
1053 chip = card->private_data;
1054 if (chip->msi)
1055 if (pci_enable_msi(chip->pci) < 0)
1056 chip->msi = 0;
1057 if (azx_acquire_irq(chip, 1) < 0)
1058 return -EIO;
1059 __azx_runtime_resume(chip, false);
1060 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1061
1062 trace_azx_resume(chip);
1063 return 0;
1064 }
1065
1066 /* put codec down to D3 at hibernation for Intel SKL+;
1067 * otherwise BIOS may still access the codec and screw up the driver
1068 */
1069 static int azx_freeze_noirq(struct device *dev)
1070 {
1071 struct snd_card *card = dev_get_drvdata(dev);
1072 struct azx *chip = card->private_data;
1073 struct pci_dev *pci = to_pci_dev(dev);
1074
1075 if (chip->driver_type == AZX_DRIVER_SKL)
1076 pci_set_power_state(pci, PCI_D3hot);
1077
1078 return 0;
1079 }
1080
1081 static int azx_thaw_noirq(struct device *dev)
1082 {
1083 struct snd_card *card = dev_get_drvdata(dev);
1084 struct azx *chip = card->private_data;
1085 struct pci_dev *pci = to_pci_dev(dev);
1086
1087 if (chip->driver_type == AZX_DRIVER_SKL)
1088 pci_set_power_state(pci, PCI_D0);
1089
1090 return 0;
1091 }
1092 #endif /* CONFIG_PM_SLEEP */
1093
1094 static int azx_runtime_suspend(struct device *dev)
1095 {
1096 struct snd_card *card = dev_get_drvdata(dev);
1097 struct azx *chip;
1098
1099 if (!azx_is_pm_ready(card))
1100 return 0;
1101 chip = card->private_data;
1102 if (!azx_has_pm_runtime(chip))
1103 return 0;
1104
1105 /* enable controller wake up event */
1106 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1107 STATESTS_INT_MASK);
1108
1109 __azx_runtime_suspend(chip);
1110 trace_azx_runtime_suspend(chip);
1111 return 0;
1112 }
1113
1114 static int azx_runtime_resume(struct device *dev)
1115 {
1116 struct snd_card *card = dev_get_drvdata(dev);
1117 struct azx *chip;
1118
1119 if (!azx_is_pm_ready(card))
1120 return 0;
1121 chip = card->private_data;
1122 if (!azx_has_pm_runtime(chip))
1123 return 0;
1124 __azx_runtime_resume(chip, true);
1125
1126 /* disable controller Wake Up event*/
1127 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1128 ~STATESTS_INT_MASK);
1129
1130 trace_azx_runtime_resume(chip);
1131 return 0;
1132 }
1133
1134 static int azx_runtime_idle(struct device *dev)
1135 {
1136 struct snd_card *card = dev_get_drvdata(dev);
1137 struct azx *chip;
1138 struct hda_intel *hda;
1139
1140 if (!card)
1141 return 0;
1142
1143 chip = card->private_data;
1144 hda = container_of(chip, struct hda_intel, chip);
1145 if (chip->disabled || hda->init_failed)
1146 return 0;
1147
1148 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1149 azx_bus(chip)->codec_powered || !chip->running)
1150 return -EBUSY;
1151
1152 /* ELD notification gets broken when HD-audio bus is off */
1153 if (needs_eld_notify_link(hda))
1154 return -EBUSY;
1155
1156 return 0;
1157 }
1158
1159 static const struct dev_pm_ops azx_pm = {
1160 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1161 #ifdef CONFIG_PM_SLEEP
1162 .freeze_noirq = azx_freeze_noirq,
1163 .thaw_noirq = azx_thaw_noirq,
1164 #endif
1165 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1166 };
1167
1168 #define AZX_PM_OPS &azx_pm
1169 #else
1170 #define azx_add_card_list(chip) /* NOP */
1171 #define azx_del_card_list(chip) /* NOP */
1172 #define AZX_PM_OPS NULL
1173 #endif /* CONFIG_PM */
1174
1175
1176 static int azx_probe_continue(struct azx *chip);
1177
1178 #ifdef SUPPORT_VGA_SWITCHEROO
1179 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1180
1181 static void azx_vs_set_state(struct pci_dev *pci,
1182 enum vga_switcheroo_state state)
1183 {
1184 struct snd_card *card = pci_get_drvdata(pci);
1185 struct azx *chip = card->private_data;
1186 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1187 struct hda_codec *codec;
1188 bool disabled;
1189
1190 wait_for_completion(&hda->probe_wait);
1191 if (hda->init_failed)
1192 return;
1193
1194 disabled = (state == VGA_SWITCHEROO_OFF);
1195 if (chip->disabled == disabled)
1196 return;
1197
1198 if (!hda->probe_continued) {
1199 chip->disabled = disabled;
1200 if (!disabled) {
1201 dev_info(chip->card->dev,
1202 "Start delayed initialization\n");
1203 if (azx_probe_continue(chip) < 0) {
1204 dev_err(chip->card->dev, "initialization error\n");
1205 hda->init_failed = true;
1206 }
1207 }
1208 } else {
1209 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1210 disabled ? "Disabling" : "Enabling");
1211 if (disabled) {
1212 list_for_each_codec(codec, &chip->bus) {
1213 pm_runtime_suspend(hda_codec_dev(codec));
1214 pm_runtime_disable(hda_codec_dev(codec));
1215 }
1216 pm_runtime_suspend(card->dev);
1217 pm_runtime_disable(card->dev);
1218 /* when we get suspended by vga_switcheroo we end up in D3cold,
1219 * however we have no ACPI handle, so pci/acpi can't put us there,
1220 * put ourselves there */
1221 pci->current_state = PCI_D3cold;
1222 chip->disabled = true;
1223 if (snd_hda_lock_devices(&chip->bus))
1224 dev_warn(chip->card->dev,
1225 "Cannot lock devices!\n");
1226 } else {
1227 snd_hda_unlock_devices(&chip->bus);
1228 chip->disabled = false;
1229 pm_runtime_enable(card->dev);
1230 list_for_each_codec(codec, &chip->bus) {
1231 pm_runtime_enable(hda_codec_dev(codec));
1232 pm_runtime_resume(hda_codec_dev(codec));
1233 }
1234 }
1235 }
1236 }
1237
1238 static bool azx_vs_can_switch(struct pci_dev *pci)
1239 {
1240 struct snd_card *card = pci_get_drvdata(pci);
1241 struct azx *chip = card->private_data;
1242 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1243
1244 wait_for_completion(&hda->probe_wait);
1245 if (hda->init_failed)
1246 return false;
1247 if (chip->disabled || !hda->probe_continued)
1248 return true;
1249 if (snd_hda_lock_devices(&chip->bus))
1250 return false;
1251 snd_hda_unlock_devices(&chip->bus);
1252 return true;
1253 }
1254
1255 /*
1256 * The discrete GPU cannot power down unless the HDA controller runtime
1257 * suspends, so activate runtime PM on codecs even if power_save == 0.
1258 */
1259 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1260 {
1261 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1262 struct hda_codec *codec;
1263
1264 if (hda->use_vga_switcheroo && !hda->need_eld_notify_link) {
1265 list_for_each_codec(codec, &chip->bus)
1266 codec->auto_runtime_pm = 1;
1267 /* reset the power save setup */
1268 if (chip->running)
1269 set_default_power_save(chip);
1270 }
1271 }
1272
1273 static void azx_vs_gpu_bound(struct pci_dev *pci,
1274 enum vga_switcheroo_client_id client_id)
1275 {
1276 struct snd_card *card = pci_get_drvdata(pci);
1277 struct azx *chip = card->private_data;
1278 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1279
1280 if (client_id == VGA_SWITCHEROO_DIS)
1281 hda->need_eld_notify_link = 0;
1282 setup_vga_switcheroo_runtime_pm(chip);
1283 }
1284
1285 static void init_vga_switcheroo(struct azx *chip)
1286 {
1287 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1288 struct pci_dev *p = get_bound_vga(chip->pci);
1289 struct pci_dev *parent;
1290 if (p) {
1291 dev_info(chip->card->dev,
1292 "Handle vga_switcheroo audio client\n");
1293 hda->use_vga_switcheroo = 1;
1294
1295 /* cleared in either gpu_bound op or codec probe, or when its
1296 * upstream port has _PR3 (i.e. dGPU).
1297 */
1298 parent = pci_upstream_bridge(p);
1299 hda->need_eld_notify_link = parent ? !pci_pr3_present(parent) : 1;
1300 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1301 pci_dev_put(p);
1302 }
1303 }
1304
1305 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1306 .set_gpu_state = azx_vs_set_state,
1307 .can_switch = azx_vs_can_switch,
1308 .gpu_bound = azx_vs_gpu_bound,
1309 };
1310
1311 static int register_vga_switcheroo(struct azx *chip)
1312 {
1313 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1314 struct pci_dev *p;
1315 int err;
1316
1317 if (!hda->use_vga_switcheroo)
1318 return 0;
1319
1320 p = get_bound_vga(chip->pci);
1321 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1322 pci_dev_put(p);
1323
1324 if (err < 0)
1325 return err;
1326 hda->vga_switcheroo_registered = 1;
1327
1328 return 0;
1329 }
1330 #else
1331 #define init_vga_switcheroo(chip) /* NOP */
1332 #define register_vga_switcheroo(chip) 0
1333 #define check_hdmi_disabled(pci) false
1334 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1335 #endif /* SUPPORT_VGA_SWITCHER */
1336
1337 /*
1338 * destructor
1339 */
1340 static int azx_free(struct azx *chip)
1341 {
1342 struct pci_dev *pci = chip->pci;
1343 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1344 struct hdac_bus *bus = azx_bus(chip);
1345
1346 if (azx_has_pm_runtime(chip) && chip->running)
1347 pm_runtime_get_noresume(&pci->dev);
1348 chip->running = 0;
1349
1350 azx_del_card_list(chip);
1351
1352 hda->init_failed = 1; /* to be sure */
1353 complete_all(&hda->probe_wait);
1354
1355 if (use_vga_switcheroo(hda)) {
1356 if (chip->disabled && hda->probe_continued)
1357 snd_hda_unlock_devices(&chip->bus);
1358 if (hda->vga_switcheroo_registered)
1359 vga_switcheroo_unregister_client(chip->pci);
1360 }
1361
1362 if (bus->chip_init) {
1363 azx_clear_irq_pending(chip);
1364 azx_stop_all_streams(chip);
1365 azx_stop_chip(chip);
1366 }
1367
1368 if (bus->irq >= 0)
1369 free_irq(bus->irq, (void*)chip);
1370 if (chip->msi)
1371 pci_disable_msi(chip->pci);
1372 iounmap(bus->remap_addr);
1373
1374 azx_free_stream_pages(chip);
1375 azx_free_streams(chip);
1376 snd_hdac_bus_exit(bus);
1377
1378 if (chip->region_requested)
1379 pci_release_regions(chip->pci);
1380
1381 pci_disable_device(chip->pci);
1382 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1383 release_firmware(chip->fw);
1384 #endif
1385 display_power(chip, false);
1386
1387 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1388 snd_hdac_i915_exit(bus);
1389 kfree(hda);
1390
1391 return 0;
1392 }
1393
1394 static int azx_dev_disconnect(struct snd_device *device)
1395 {
1396 struct azx *chip = device->device_data;
1397 struct hdac_bus *bus = azx_bus(chip);
1398
1399 chip->bus.shutdown = 1;
1400 cancel_work_sync(&bus->unsol_work);
1401
1402 return 0;
1403 }
1404
1405 static int azx_dev_free(struct snd_device *device)
1406 {
1407 return azx_free(device->device_data);
1408 }
1409
1410 #ifdef SUPPORT_VGA_SWITCHEROO
1411 /*
1412 * Check of disabled HDMI controller by vga_switcheroo
1413 */
1414 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1415 {
1416 struct pci_dev *p;
1417
1418 /* check only discrete GPU */
1419 switch (pci->vendor) {
1420 case PCI_VENDOR_ID_ATI:
1421 case PCI_VENDOR_ID_AMD:
1422 case PCI_VENDOR_ID_NVIDIA:
1423 if (pci->devfn == 1) {
1424 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1425 pci->bus->number, 0);
1426 if (p) {
1427 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1428 return p;
1429 pci_dev_put(p);
1430 }
1431 }
1432 break;
1433 }
1434 return NULL;
1435 }
1436
1437 static bool check_hdmi_disabled(struct pci_dev *pci)
1438 {
1439 bool vga_inactive = false;
1440 struct pci_dev *p = get_bound_vga(pci);
1441
1442 if (p) {
1443 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1444 vga_inactive = true;
1445 pci_dev_put(p);
1446 }
1447 return vga_inactive;
1448 }
1449 #endif /* SUPPORT_VGA_SWITCHEROO */
1450
1451 /*
1452 * white/black-listing for position_fix
1453 */
1454 static struct snd_pci_quirk position_fix_list[] = {
1455 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1456 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1457 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1458 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1459 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1460 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1461 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1462 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1463 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1464 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1465 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1466 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1467 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1468 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1469 {}
1470 };
1471
1472 static int check_position_fix(struct azx *chip, int fix)
1473 {
1474 const struct snd_pci_quirk *q;
1475
1476 switch (fix) {
1477 case POS_FIX_AUTO:
1478 case POS_FIX_LPIB:
1479 case POS_FIX_POSBUF:
1480 case POS_FIX_VIACOMBO:
1481 case POS_FIX_COMBO:
1482 case POS_FIX_SKL:
1483 case POS_FIX_FIFO:
1484 return fix;
1485 }
1486
1487 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1488 if (q) {
1489 dev_info(chip->card->dev,
1490 "position_fix set to %d for device %04x:%04x\n",
1491 q->value, q->subvendor, q->subdevice);
1492 return q->value;
1493 }
1494
1495 /* Check VIA/ATI HD Audio Controller exist */
1496 if (chip->driver_type == AZX_DRIVER_VIA) {
1497 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1498 return POS_FIX_VIACOMBO;
1499 }
1500 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1501 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1502 return POS_FIX_FIFO;
1503 }
1504 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1505 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1506 return POS_FIX_LPIB;
1507 }
1508 if (chip->driver_type == AZX_DRIVER_SKL) {
1509 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1510 return POS_FIX_SKL;
1511 }
1512 return POS_FIX_AUTO;
1513 }
1514
1515 static void assign_position_fix(struct azx *chip, int fix)
1516 {
1517 static azx_get_pos_callback_t callbacks[] = {
1518 [POS_FIX_AUTO] = NULL,
1519 [POS_FIX_LPIB] = azx_get_pos_lpib,
1520 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1521 [POS_FIX_VIACOMBO] = azx_via_get_position,
1522 [POS_FIX_COMBO] = azx_get_pos_lpib,
1523 [POS_FIX_SKL] = azx_get_pos_skl,
1524 [POS_FIX_FIFO] = azx_get_pos_fifo,
1525 };
1526
1527 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1528
1529 /* combo mode uses LPIB only for playback */
1530 if (fix == POS_FIX_COMBO)
1531 chip->get_position[1] = NULL;
1532
1533 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1534 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1535 chip->get_delay[0] = chip->get_delay[1] =
1536 azx_get_delay_from_lpib;
1537 }
1538
1539 if (fix == POS_FIX_FIFO)
1540 chip->get_delay[0] = chip->get_delay[1] =
1541 azx_get_delay_from_fifo;
1542 }
1543
1544 /*
1545 * black-lists for probe_mask
1546 */
1547 static struct snd_pci_quirk probe_mask_list[] = {
1548 /* Thinkpad often breaks the controller communication when accessing
1549 * to the non-working (or non-existing) modem codec slot.
1550 */
1551 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1552 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1553 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1554 /* broken BIOS */
1555 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1556 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1557 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1558 /* forced codec slots */
1559 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1560 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1561 /* WinFast VP200 H (Teradici) user reported broken communication */
1562 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1563 {}
1564 };
1565
1566 #define AZX_FORCE_CODEC_MASK 0x100
1567
1568 static void check_probe_mask(struct azx *chip, int dev)
1569 {
1570 const struct snd_pci_quirk *q;
1571
1572 chip->codec_probe_mask = probe_mask[dev];
1573 if (chip->codec_probe_mask == -1) {
1574 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1575 if (q) {
1576 dev_info(chip->card->dev,
1577 "probe_mask set to 0x%x for device %04x:%04x\n",
1578 q->value, q->subvendor, q->subdevice);
1579 chip->codec_probe_mask = q->value;
1580 }
1581 }
1582
1583 /* check forced option */
1584 if (chip->codec_probe_mask != -1 &&
1585 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1586 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1587 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1588 (int)azx_bus(chip)->codec_mask);
1589 }
1590 }
1591
1592 /*
1593 * white/black-list for enable_msi
1594 */
1595 static struct snd_pci_quirk msi_black_list[] = {
1596 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1597 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1598 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1599 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1600 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1601 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1602 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1603 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1604 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1605 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1606 {}
1607 };
1608
1609 static void check_msi(struct azx *chip)
1610 {
1611 const struct snd_pci_quirk *q;
1612
1613 if (enable_msi >= 0) {
1614 chip->msi = !!enable_msi;
1615 return;
1616 }
1617 chip->msi = 1; /* enable MSI as default */
1618 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1619 if (q) {
1620 dev_info(chip->card->dev,
1621 "msi for device %04x:%04x set to %d\n",
1622 q->subvendor, q->subdevice, q->value);
1623 chip->msi = q->value;
1624 return;
1625 }
1626
1627 /* NVidia chipsets seem to cause troubles with MSI */
1628 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1629 dev_info(chip->card->dev, "Disabling MSI\n");
1630 chip->msi = 0;
1631 }
1632 }
1633
1634 /* check the snoop mode availability */
1635 static void azx_check_snoop_available(struct azx *chip)
1636 {
1637 int snoop = hda_snoop;
1638
1639 if (snoop >= 0) {
1640 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1641 snoop ? "snoop" : "non-snoop");
1642 chip->snoop = snoop;
1643 chip->uc_buffer = !snoop;
1644 return;
1645 }
1646
1647 snoop = true;
1648 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1649 chip->driver_type == AZX_DRIVER_VIA) {
1650 /* force to non-snoop mode for a new VIA controller
1651 * when BIOS is set
1652 */
1653 u8 val;
1654 pci_read_config_byte(chip->pci, 0x42, &val);
1655 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1656 chip->pci->revision == 0x20))
1657 snoop = false;
1658 }
1659
1660 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1661 snoop = false;
1662
1663 chip->snoop = snoop;
1664 if (!snoop) {
1665 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1666 /* C-Media requires non-cached pages only for CORB/RIRB */
1667 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1668 chip->uc_buffer = true;
1669 }
1670 }
1671
1672 static void azx_probe_work(struct work_struct *work)
1673 {
1674 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1675 azx_probe_continue(&hda->chip);
1676 }
1677
1678 static int default_bdl_pos_adj(struct azx *chip)
1679 {
1680 /* some exceptions: Atoms seem problematic with value 1 */
1681 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1682 switch (chip->pci->device) {
1683 case 0x0f04: /* Baytrail */
1684 case 0x2284: /* Braswell */
1685 return 32;
1686 }
1687 }
1688
1689 switch (chip->driver_type) {
1690 case AZX_DRIVER_ICH:
1691 case AZX_DRIVER_PCH:
1692 return 1;
1693 default:
1694 return 32;
1695 }
1696 }
1697
1698 /*
1699 * constructor
1700 */
1701 static const struct hdac_io_ops pci_hda_io_ops;
1702 static const struct hda_controller_ops pci_hda_ops;
1703
1704 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1705 int dev, unsigned int driver_caps,
1706 struct azx **rchip)
1707 {
1708 static struct snd_device_ops ops = {
1709 .dev_disconnect = azx_dev_disconnect,
1710 .dev_free = azx_dev_free,
1711 };
1712 struct hda_intel *hda;
1713 struct azx *chip;
1714 int err;
1715
1716 *rchip = NULL;
1717
1718 err = pci_enable_device(pci);
1719 if (err < 0)
1720 return err;
1721
1722 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1723 if (!hda) {
1724 pci_disable_device(pci);
1725 return -ENOMEM;
1726 }
1727
1728 chip = &hda->chip;
1729 mutex_init(&chip->open_mutex);
1730 chip->card = card;
1731 chip->pci = pci;
1732 chip->ops = &pci_hda_ops;
1733 chip->driver_caps = driver_caps;
1734 chip->driver_type = driver_caps & 0xff;
1735 check_msi(chip);
1736 chip->dev_index = dev;
1737 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1738 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1739 INIT_LIST_HEAD(&chip->pcm_list);
1740 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1741 INIT_LIST_HEAD(&hda->list);
1742 init_vga_switcheroo(chip);
1743 init_completion(&hda->probe_wait);
1744
1745 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1746
1747 check_probe_mask(chip, dev);
1748
1749 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1750 chip->fallback_to_single_cmd = 1;
1751 else /* explicitly set to single_cmd or not */
1752 chip->single_cmd = single_cmd;
1753
1754 azx_check_snoop_available(chip);
1755
1756 if (bdl_pos_adj[dev] < 0)
1757 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1758 else
1759 chip->bdl_pos_adj = bdl_pos_adj[dev];
1760
1761 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1762 if (err < 0) {
1763 kfree(hda);
1764 pci_disable_device(pci);
1765 return err;
1766 }
1767
1768 /* Workaround for a communication error on CFL (bko#199007) and CNL */
1769 if (IS_CFL(pci) || IS_CNL(pci))
1770 azx_bus(chip)->polling_mode = 1;
1771
1772 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1773 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1774 chip->bus.needs_damn_long_delay = 1;
1775 }
1776
1777 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1778 if (err < 0) {
1779 dev_err(card->dev, "Error creating device [card]!\n");
1780 azx_free(chip);
1781 return err;
1782 }
1783
1784 /* continue probing in work context as may trigger request module */
1785 INIT_WORK(&hda->probe_work, azx_probe_work);
1786
1787 *rchip = chip;
1788
1789 return 0;
1790 }
1791
1792 static int azx_first_init(struct azx *chip)
1793 {
1794 int dev = chip->dev_index;
1795 struct pci_dev *pci = chip->pci;
1796 struct snd_card *card = chip->card;
1797 struct hdac_bus *bus = azx_bus(chip);
1798 int err;
1799 unsigned short gcap;
1800 unsigned int dma_bits = 64;
1801
1802 #if BITS_PER_LONG != 64
1803 /* Fix up base address on ULI M5461 */
1804 if (chip->driver_type == AZX_DRIVER_ULI) {
1805 u16 tmp3;
1806 pci_read_config_word(pci, 0x40, &tmp3);
1807 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1808 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1809 }
1810 #endif
1811
1812 err = pci_request_regions(pci, "ICH HD audio");
1813 if (err < 0)
1814 return err;
1815 chip->region_requested = 1;
1816
1817 bus->addr = pci_resource_start(pci, 0);
1818 bus->remap_addr = pci_ioremap_bar(pci, 0);
1819 if (bus->remap_addr == NULL) {
1820 dev_err(card->dev, "ioremap error\n");
1821 return -ENXIO;
1822 }
1823
1824 if (chip->driver_type == AZX_DRIVER_SKL)
1825 snd_hdac_bus_parse_capabilities(bus);
1826
1827 /*
1828 * Some Intel CPUs has always running timer (ART) feature and
1829 * controller may have Global time sync reporting capability, so
1830 * check both of these before declaring synchronized time reporting
1831 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1832 */
1833 chip->gts_present = false;
1834
1835 #ifdef CONFIG_X86
1836 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1837 chip->gts_present = true;
1838 #endif
1839
1840 if (chip->msi) {
1841 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1842 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1843 pci->no_64bit_msi = true;
1844 }
1845 if (pci_enable_msi(pci) < 0)
1846 chip->msi = 0;
1847 }
1848
1849 pci_set_master(pci);
1850 synchronize_irq(bus->irq);
1851
1852 gcap = azx_readw(chip, GCAP);
1853 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1854
1855 /* AMD devices support 40 or 48bit DMA, take the safe one */
1856 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1857 dma_bits = 40;
1858
1859 /* disable SB600 64bit support for safety */
1860 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1861 struct pci_dev *p_smbus;
1862 dma_bits = 40;
1863 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1864 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1865 NULL);
1866 if (p_smbus) {
1867 if (p_smbus->revision < 0x30)
1868 gcap &= ~AZX_GCAP_64OK;
1869 pci_dev_put(p_smbus);
1870 }
1871 }
1872
1873 /* NVidia hardware normally only supports up to 40 bits of DMA */
1874 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1875 dma_bits = 40;
1876
1877 /* disable 64bit DMA address on some devices */
1878 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1879 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1880 gcap &= ~AZX_GCAP_64OK;
1881 }
1882
1883 /* disable buffer size rounding to 128-byte multiples if supported */
1884 if (align_buffer_size >= 0)
1885 chip->align_buffer_size = !!align_buffer_size;
1886 else {
1887 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1888 chip->align_buffer_size = 0;
1889 else
1890 chip->align_buffer_size = 1;
1891 }
1892
1893 /* allow 64bit DMA address if supported by H/W */
1894 if (!(gcap & AZX_GCAP_64OK))
1895 dma_bits = 32;
1896 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1897 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1898 } else {
1899 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1900 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1901 }
1902
1903 /* read number of streams from GCAP register instead of using
1904 * hardcoded value
1905 */
1906 chip->capture_streams = (gcap >> 8) & 0x0f;
1907 chip->playback_streams = (gcap >> 12) & 0x0f;
1908 if (!chip->playback_streams && !chip->capture_streams) {
1909 /* gcap didn't give any info, switching to old method */
1910
1911 switch (chip->driver_type) {
1912 case AZX_DRIVER_ULI:
1913 chip->playback_streams = ULI_NUM_PLAYBACK;
1914 chip->capture_streams = ULI_NUM_CAPTURE;
1915 break;
1916 case AZX_DRIVER_ATIHDMI:
1917 case AZX_DRIVER_ATIHDMI_NS:
1918 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1919 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1920 break;
1921 case AZX_DRIVER_GENERIC:
1922 default:
1923 chip->playback_streams = ICH6_NUM_PLAYBACK;
1924 chip->capture_streams = ICH6_NUM_CAPTURE;
1925 break;
1926 }
1927 }
1928 chip->capture_index_offset = 0;
1929 chip->playback_index_offset = chip->capture_streams;
1930 chip->num_streams = chip->playback_streams + chip->capture_streams;
1931
1932 /* sanity check for the SDxCTL.STRM field overflow */
1933 if (chip->num_streams > 15 &&
1934 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1935 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1936 "forcing separate stream tags", chip->num_streams);
1937 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1938 }
1939
1940 /* initialize streams */
1941 err = azx_init_streams(chip);
1942 if (err < 0)
1943 return err;
1944
1945 err = azx_alloc_stream_pages(chip);
1946 if (err < 0)
1947 return err;
1948
1949 /* initialize chip */
1950 azx_init_pci(chip);
1951
1952 snd_hdac_i915_set_bclk(bus);
1953
1954 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1955
1956 /* codec detection */
1957 if (!azx_bus(chip)->codec_mask) {
1958 dev_err(card->dev, "no codecs found!\n");
1959 return -ENODEV;
1960 }
1961
1962 if (azx_acquire_irq(chip, 0) < 0)
1963 return -EBUSY;
1964
1965 strcpy(card->driver, "HDA-Intel");
1966 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1967 sizeof(card->shortname));
1968 snprintf(card->longname, sizeof(card->longname),
1969 "%s at 0x%lx irq %i",
1970 card->shortname, bus->addr, bus->irq);
1971
1972 return 0;
1973 }
1974
1975 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1976 /* callback from request_firmware_nowait() */
1977 static void azx_firmware_cb(const struct firmware *fw, void *context)
1978 {
1979 struct snd_card *card = context;
1980 struct azx *chip = card->private_data;
1981 struct pci_dev *pci = chip->pci;
1982
1983 if (!fw) {
1984 dev_err(card->dev, "Cannot load firmware, aborting\n");
1985 goto error;
1986 }
1987
1988 chip->fw = fw;
1989 if (!chip->disabled) {
1990 /* continue probing */
1991 if (azx_probe_continue(chip))
1992 goto error;
1993 }
1994 return; /* OK */
1995
1996 error:
1997 snd_card_free(card);
1998 pci_set_drvdata(pci, NULL);
1999 }
2000 #endif
2001
2002 /*
2003 * HDA controller ops.
2004 */
2005
2006 /* PCI register access. */
2007 static void pci_azx_writel(u32 value, u32 __iomem *addr)
2008 {
2009 writel(value, addr);
2010 }
2011
2012 static u32 pci_azx_readl(u32 __iomem *addr)
2013 {
2014 return readl(addr);
2015 }
2016
2017 static void pci_azx_writew(u16 value, u16 __iomem *addr)
2018 {
2019 writew(value, addr);
2020 }
2021
2022 static u16 pci_azx_readw(u16 __iomem *addr)
2023 {
2024 return readw(addr);
2025 }
2026
2027 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2028 {
2029 writeb(value, addr);
2030 }
2031
2032 static u8 pci_azx_readb(u8 __iomem *addr)
2033 {
2034 return readb(addr);
2035 }
2036
2037 static int disable_msi_reset_irq(struct azx *chip)
2038 {
2039 struct hdac_bus *bus = azx_bus(chip);
2040 int err;
2041
2042 free_irq(bus->irq, chip);
2043 bus->irq = -1;
2044 pci_disable_msi(chip->pci);
2045 chip->msi = 0;
2046 err = azx_acquire_irq(chip, 1);
2047 if (err < 0)
2048 return err;
2049
2050 return 0;
2051 }
2052
2053 /* DMA page allocation helpers. */
2054 static int dma_alloc_pages(struct hdac_bus *bus,
2055 int type,
2056 size_t size,
2057 struct snd_dma_buffer *buf)
2058 {
2059 struct azx *chip = bus_to_azx(bus);
2060
2061 if (!azx_snoop(chip) && type == SNDRV_DMA_TYPE_DEV)
2062 type = SNDRV_DMA_TYPE_DEV_UC;
2063 return snd_dma_alloc_pages(type, bus->dev, size, buf);
2064 }
2065
2066 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2067 {
2068 snd_dma_free_pages(buf);
2069 }
2070
2071 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2072 struct vm_area_struct *area)
2073 {
2074 #ifdef CONFIG_X86
2075 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2076 struct azx *chip = apcm->chip;
2077 if (chip->uc_buffer)
2078 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2079 #endif
2080 }
2081
2082 static const struct hdac_io_ops pci_hda_io_ops = {
2083 .reg_writel = pci_azx_writel,
2084 .reg_readl = pci_azx_readl,
2085 .reg_writew = pci_azx_writew,
2086 .reg_readw = pci_azx_readw,
2087 .reg_writeb = pci_azx_writeb,
2088 .reg_readb = pci_azx_readb,
2089 .dma_alloc_pages = dma_alloc_pages,
2090 .dma_free_pages = dma_free_pages,
2091 };
2092
2093 static const struct hda_controller_ops pci_hda_ops = {
2094 .disable_msi_reset_irq = disable_msi_reset_irq,
2095 .pcm_mmap_prepare = pcm_mmap_prepare,
2096 .position_check = azx_position_check,
2097 };
2098
2099 static int azx_check_dmic(struct pci_dev *pci, struct azx *chip)
2100 {
2101 struct nhlt_acpi_table *nhlt;
2102 int ret = 0;
2103
2104 if (chip->driver_type == AZX_DRIVER_SKL &&
2105 pci->class != 0x040300) {
2106 nhlt = intel_nhlt_init(&pci->dev);
2107 if (nhlt) {
2108 if (intel_nhlt_get_dmic_geo(&pci->dev, nhlt)) {
2109 ret = -ENODEV;
2110 dev_info(&pci->dev, "Digital mics found on Skylake+ platform, aborting probe\n");
2111 }
2112 intel_nhlt_free(nhlt);
2113 }
2114 }
2115 return ret;
2116 }
2117
2118 static int azx_probe(struct pci_dev *pci,
2119 const struct pci_device_id *pci_id)
2120 {
2121 static int dev;
2122 struct snd_card *card;
2123 struct hda_intel *hda;
2124 struct azx *chip;
2125 bool schedule_probe;
2126 int err;
2127
2128 if (dev >= SNDRV_CARDS)
2129 return -ENODEV;
2130 if (!enable[dev]) {
2131 dev++;
2132 return -ENOENT;
2133 }
2134
2135 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2136 0, &card);
2137 if (err < 0) {
2138 dev_err(&pci->dev, "Error creating card!\n");
2139 return err;
2140 }
2141
2142 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2143 if (err < 0)
2144 goto out_free;
2145 card->private_data = chip;
2146 hda = container_of(chip, struct hda_intel, chip);
2147
2148 /*
2149 * stop probe if digital microphones detected on Skylake+ platform
2150 * with the DSP enabled. This is an opt-in behavior defined at build
2151 * time or at run-time with a module parameter
2152 */
2153 if (dmic_detect) {
2154 err = azx_check_dmic(pci, chip);
2155 if (err < 0)
2156 goto out_free;
2157 }
2158
2159 pci_set_drvdata(pci, card);
2160
2161 err = register_vga_switcheroo(chip);
2162 if (err < 0) {
2163 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2164 goto out_free;
2165 }
2166
2167 if (check_hdmi_disabled(pci)) {
2168 dev_info(card->dev, "VGA controller is disabled\n");
2169 dev_info(card->dev, "Delaying initialization\n");
2170 chip->disabled = true;
2171 }
2172
2173 schedule_probe = !chip->disabled;
2174
2175 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2176 if (patch[dev] && *patch[dev]) {
2177 dev_info(card->dev, "Applying patch firmware '%s'\n",
2178 patch[dev]);
2179 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2180 &pci->dev, GFP_KERNEL, card,
2181 azx_firmware_cb);
2182 if (err < 0)
2183 goto out_free;
2184 schedule_probe = false; /* continued in azx_firmware_cb() */
2185 }
2186 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2187
2188 #ifndef CONFIG_SND_HDA_I915
2189 if (CONTROLLER_IN_GPU(pci))
2190 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2191 #endif
2192
2193 if (schedule_probe)
2194 schedule_work(&hda->probe_work);
2195
2196 dev++;
2197 if (chip->disabled)
2198 complete_all(&hda->probe_wait);
2199 return 0;
2200
2201 out_free:
2202 snd_card_free(card);
2203 return err;
2204 }
2205
2206 #ifdef CONFIG_PM
2207 /* On some boards setting power_save to a non 0 value leads to clicking /
2208 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2209 * figure out how to avoid these sounds, but that is not always feasible.
2210 * So we keep a list of devices where we disable powersaving as its known
2211 * to causes problems on these devices.
2212 */
2213 static struct snd_pci_quirk power_save_blacklist[] = {
2214 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2215 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2216 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2217 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2218 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2219 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2220 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2221 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2222 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */
2223 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0),
2224 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2225 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2226 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2227 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2228 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2229 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2230 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2231 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2232 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2233 /* https://bugs.launchpad.net/bugs/1821663 */
2234 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2235 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2236 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2237 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2238 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2239 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2240 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2241 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2242 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2243 /* https://bugs.launchpad.net/bugs/1821663 */
2244 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2245 {}
2246 };
2247 #endif /* CONFIG_PM */
2248
2249 static void set_default_power_save(struct azx *chip)
2250 {
2251 int val = power_save;
2252
2253 #ifdef CONFIG_PM
2254 if (pm_blacklist) {
2255 const struct snd_pci_quirk *q;
2256
2257 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
2258 if (q && val) {
2259 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
2260 q->subvendor, q->subdevice);
2261 val = 0;
2262 }
2263 }
2264 #endif /* CONFIG_PM */
2265 snd_hda_set_power_save(&chip->bus, val * 1000);
2266 }
2267
2268 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2269 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2270 [AZX_DRIVER_NVIDIA] = 8,
2271 [AZX_DRIVER_TERA] = 1,
2272 };
2273
2274 static int azx_probe_continue(struct azx *chip)
2275 {
2276 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2277 struct hdac_bus *bus = azx_bus(chip);
2278 struct pci_dev *pci = chip->pci;
2279 int dev = chip->dev_index;
2280 int err;
2281
2282 to_hda_bus(bus)->bus_probing = 1;
2283 hda->probe_continued = 1;
2284
2285 /* bind with i915 if needed */
2286 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2287 err = snd_hdac_i915_init(bus);
2288 if (err < 0) {
2289 /* if the controller is bound only with HDMI/DP
2290 * (for HSW and BDW), we need to abort the probe;
2291 * for other chips, still continue probing as other
2292 * codecs can be on the same link.
2293 */
2294 if (CONTROLLER_IN_GPU(pci)) {
2295 dev_err(chip->card->dev,
2296 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2297 goto out_free;
2298 } else {
2299 /* don't bother any longer */
2300 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2301 }
2302 }
2303
2304 /* HSW/BDW controllers need this power */
2305 if (CONTROLLER_IN_GPU(pci))
2306 hda->need_i915_power = 1;
2307 }
2308
2309 /* Request display power well for the HDA controller or codec. For
2310 * Haswell/Broadwell, both the display HDA controller and codec need
2311 * this power. For other platforms, like Baytrail/Braswell, only the
2312 * display codec needs the power and it can be released after probe.
2313 */
2314 display_power(chip, true);
2315
2316 err = azx_first_init(chip);
2317 if (err < 0)
2318 goto out_free;
2319
2320 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2321 chip->beep_mode = beep_mode[dev];
2322 #endif
2323
2324 /* create codec instances */
2325 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2326 if (err < 0)
2327 goto out_free;
2328
2329 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2330 if (chip->fw) {
2331 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2332 chip->fw->data);
2333 if (err < 0)
2334 goto out_free;
2335 #ifndef CONFIG_PM
2336 release_firmware(chip->fw); /* no longer needed */
2337 chip->fw = NULL;
2338 #endif
2339 }
2340 #endif
2341 if ((probe_only[dev] & 1) == 0) {
2342 err = azx_codec_configure(chip);
2343 if (err < 0)
2344 goto out_free;
2345 }
2346
2347 err = snd_card_register(chip->card);
2348 if (err < 0)
2349 goto out_free;
2350
2351 setup_vga_switcheroo_runtime_pm(chip);
2352
2353 chip->running = 1;
2354 azx_add_card_list(chip);
2355
2356 set_default_power_save(chip);
2357
2358 if (azx_has_pm_runtime(chip))
2359 pm_runtime_put_autosuspend(&pci->dev);
2360
2361 out_free:
2362 if (err < 0 || !hda->need_i915_power)
2363 display_power(chip, false);
2364 if (err < 0)
2365 hda->init_failed = 1;
2366 complete_all(&hda->probe_wait);
2367 to_hda_bus(bus)->bus_probing = 0;
2368 return err;
2369 }
2370
2371 static void azx_remove(struct pci_dev *pci)
2372 {
2373 struct snd_card *card = pci_get_drvdata(pci);
2374 struct azx *chip;
2375 struct hda_intel *hda;
2376
2377 if (card) {
2378 /* cancel the pending probing work */
2379 chip = card->private_data;
2380 hda = container_of(chip, struct hda_intel, chip);
2381 /* FIXME: below is an ugly workaround.
2382 * Both device_release_driver() and driver_probe_device()
2383 * take *both* the device's and its parent's lock before
2384 * calling the remove() and probe() callbacks. The codec
2385 * probe takes the locks of both the codec itself and its
2386 * parent, i.e. the PCI controller dev. Meanwhile, when
2387 * the PCI controller is unbound, it takes its lock, too
2388 * ==> ouch, a deadlock!
2389 * As a workaround, we unlock temporarily here the controller
2390 * device during cancel_work_sync() call.
2391 */
2392 device_unlock(&pci->dev);
2393 cancel_work_sync(&hda->probe_work);
2394 device_lock(&pci->dev);
2395
2396 snd_card_free(card);
2397 }
2398 }
2399
2400 static void azx_shutdown(struct pci_dev *pci)
2401 {
2402 struct snd_card *card = pci_get_drvdata(pci);
2403 struct azx *chip;
2404
2405 if (!card)
2406 return;
2407 chip = card->private_data;
2408 if (chip && chip->running)
2409 azx_stop_chip(chip);
2410 }
2411
2412 /* PCI IDs */
2413 static const struct pci_device_id azx_ids[] = {
2414 /* CPT */
2415 { PCI_DEVICE(0x8086, 0x1c20),
2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2417 /* PBG */
2418 { PCI_DEVICE(0x8086, 0x1d20),
2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2420 /* Panther Point */
2421 { PCI_DEVICE(0x8086, 0x1e20),
2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2423 /* Lynx Point */
2424 { PCI_DEVICE(0x8086, 0x8c20),
2425 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2426 /* 9 Series */
2427 { PCI_DEVICE(0x8086, 0x8ca0),
2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2429 /* Wellsburg */
2430 { PCI_DEVICE(0x8086, 0x8d20),
2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2432 { PCI_DEVICE(0x8086, 0x8d21),
2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2434 /* Lewisburg */
2435 { PCI_DEVICE(0x8086, 0xa1f0),
2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2437 { PCI_DEVICE(0x8086, 0xa270),
2438 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2439 /* Lynx Point-LP */
2440 { PCI_DEVICE(0x8086, 0x9c20),
2441 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2442 /* Lynx Point-LP */
2443 { PCI_DEVICE(0x8086, 0x9c21),
2444 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2445 /* Wildcat Point-LP */
2446 { PCI_DEVICE(0x8086, 0x9ca0),
2447 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2448 /* Sunrise Point */
2449 { PCI_DEVICE(0x8086, 0xa170),
2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2451 /* Sunrise Point-LP */
2452 { PCI_DEVICE(0x8086, 0x9d70),
2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2454 /* Kabylake */
2455 { PCI_DEVICE(0x8086, 0xa171),
2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2457 /* Kabylake-LP */
2458 { PCI_DEVICE(0x8086, 0x9d71),
2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2460 /* Kabylake-H */
2461 { PCI_DEVICE(0x8086, 0xa2f0),
2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2463 /* Coffelake */
2464 { PCI_DEVICE(0x8086, 0xa348),
2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2466 /* Cannonlake */
2467 { PCI_DEVICE(0x8086, 0x9dc8),
2468 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2469 /* CometLake-LP */
2470 { PCI_DEVICE(0x8086, 0x02C8),
2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2472 /* CometLake-H */
2473 { PCI_DEVICE(0x8086, 0x06C8),
2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2475 /* CometLake-S */
2476 { PCI_DEVICE(0x8086, 0xa3f0),
2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2478 /* Icelake */
2479 { PCI_DEVICE(0x8086, 0x34c8),
2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2481 /* Jasperlake */
2482 { PCI_DEVICE(0x8086, 0x38c8),
2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2484 /* Tigerlake */
2485 { PCI_DEVICE(0x8086, 0xa0c8),
2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2487 /* Elkhart Lake */
2488 { PCI_DEVICE(0x8086, 0x4b55),
2489 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2490 /* Broxton-P(Apollolake) */
2491 { PCI_DEVICE(0x8086, 0x5a98),
2492 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2493 /* Broxton-T */
2494 { PCI_DEVICE(0x8086, 0x1a98),
2495 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2496 /* Gemini-Lake */
2497 { PCI_DEVICE(0x8086, 0x3198),
2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2499 /* Haswell */
2500 { PCI_DEVICE(0x8086, 0x0a0c),
2501 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2502 { PCI_DEVICE(0x8086, 0x0c0c),
2503 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2504 { PCI_DEVICE(0x8086, 0x0d0c),
2505 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2506 /* Broadwell */
2507 { PCI_DEVICE(0x8086, 0x160c),
2508 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2509 /* 5 Series/3400 */
2510 { PCI_DEVICE(0x8086, 0x3b56),
2511 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2512 /* Poulsbo */
2513 { PCI_DEVICE(0x8086, 0x811b),
2514 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2515 /* Oaktrail */
2516 { PCI_DEVICE(0x8086, 0x080a),
2517 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2518 /* BayTrail */
2519 { PCI_DEVICE(0x8086, 0x0f04),
2520 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2521 /* Braswell */
2522 { PCI_DEVICE(0x8086, 0x2284),
2523 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2524 /* ICH6 */
2525 { PCI_DEVICE(0x8086, 0x2668),
2526 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2527 /* ICH7 */
2528 { PCI_DEVICE(0x8086, 0x27d8),
2529 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2530 /* ESB2 */
2531 { PCI_DEVICE(0x8086, 0x269a),
2532 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2533 /* ICH8 */
2534 { PCI_DEVICE(0x8086, 0x284b),
2535 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2536 /* ICH9 */
2537 { PCI_DEVICE(0x8086, 0x293e),
2538 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2539 /* ICH9 */
2540 { PCI_DEVICE(0x8086, 0x293f),
2541 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2542 /* ICH10 */
2543 { PCI_DEVICE(0x8086, 0x3a3e),
2544 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2545 /* ICH10 */
2546 { PCI_DEVICE(0x8086, 0x3a6e),
2547 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2548 /* Generic Intel */
2549 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2550 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2551 .class_mask = 0xffffff,
2552 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2553 /* ATI SB 450/600/700/800/900 */
2554 { PCI_DEVICE(0x1002, 0x437b),
2555 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2556 { PCI_DEVICE(0x1002, 0x4383),
2557 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2558 /* AMD Hudson */
2559 { PCI_DEVICE(0x1022, 0x780d),
2560 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2561 /* AMD, X370 & co */
2562 { PCI_DEVICE(0x1022, 0x1457),
2563 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2564 /* AMD, X570 & co */
2565 { PCI_DEVICE(0x1022, 0x1487),
2566 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2567 /* AMD Stoney */
2568 { PCI_DEVICE(0x1022, 0x157a),
2569 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2570 AZX_DCAPS_PM_RUNTIME },
2571 /* AMD Raven */
2572 { PCI_DEVICE(0x1022, 0x15e3),
2573 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2574 /* ATI HDMI */
2575 { PCI_DEVICE(0x1002, 0x0002),
2576 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2577 { PCI_DEVICE(0x1002, 0x1308),
2578 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2579 { PCI_DEVICE(0x1002, 0x157a),
2580 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2581 { PCI_DEVICE(0x1002, 0x15b3),
2582 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2583 { PCI_DEVICE(0x1002, 0x793b),
2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2585 { PCI_DEVICE(0x1002, 0x7919),
2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2587 { PCI_DEVICE(0x1002, 0x960f),
2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2589 { PCI_DEVICE(0x1002, 0x970f),
2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2591 { PCI_DEVICE(0x1002, 0x9840),
2592 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2593 { PCI_DEVICE(0x1002, 0xaa00),
2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2595 { PCI_DEVICE(0x1002, 0xaa08),
2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2597 { PCI_DEVICE(0x1002, 0xaa10),
2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2599 { PCI_DEVICE(0x1002, 0xaa18),
2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2601 { PCI_DEVICE(0x1002, 0xaa20),
2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2603 { PCI_DEVICE(0x1002, 0xaa28),
2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2605 { PCI_DEVICE(0x1002, 0xaa30),
2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2607 { PCI_DEVICE(0x1002, 0xaa38),
2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2609 { PCI_DEVICE(0x1002, 0xaa40),
2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2611 { PCI_DEVICE(0x1002, 0xaa48),
2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2613 { PCI_DEVICE(0x1002, 0xaa50),
2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2615 { PCI_DEVICE(0x1002, 0xaa58),
2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2617 { PCI_DEVICE(0x1002, 0xaa60),
2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2619 { PCI_DEVICE(0x1002, 0xaa68),
2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2621 { PCI_DEVICE(0x1002, 0xaa80),
2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2623 { PCI_DEVICE(0x1002, 0xaa88),
2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2625 { PCI_DEVICE(0x1002, 0xaa90),
2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627 { PCI_DEVICE(0x1002, 0xaa98),
2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629 { PCI_DEVICE(0x1002, 0x9902),
2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2631 { PCI_DEVICE(0x1002, 0xaaa0),
2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2633 { PCI_DEVICE(0x1002, 0xaaa8),
2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2635 { PCI_DEVICE(0x1002, 0xaab0),
2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2637 { PCI_DEVICE(0x1002, 0xaac0),
2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2639 { PCI_DEVICE(0x1002, 0xaac8),
2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2641 { PCI_DEVICE(0x1002, 0xaad8),
2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2643 { PCI_DEVICE(0x1002, 0xaae8),
2644 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2645 { PCI_DEVICE(0x1002, 0xaae0),
2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2647 { PCI_DEVICE(0x1002, 0xaaf0),
2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2649 /* VIA VT8251/VT8237A */
2650 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2651 /* VIA GFX VT7122/VX900 */
2652 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2653 /* VIA GFX VT6122/VX11 */
2654 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2655 /* SIS966 */
2656 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2657 /* ULI M5461 */
2658 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2659 /* NVIDIA MCP */
2660 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2661 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2662 .class_mask = 0xffffff,
2663 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2664 /* Teradici */
2665 { PCI_DEVICE(0x6549, 0x1200),
2666 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2667 { PCI_DEVICE(0x6549, 0x2200),
2668 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2669 /* Creative X-Fi (CA0110-IBG) */
2670 /* CTHDA chips */
2671 { PCI_DEVICE(0x1102, 0x0010),
2672 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2673 { PCI_DEVICE(0x1102, 0x0012),
2674 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2675 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2676 /* the following entry conflicts with snd-ctxfi driver,
2677 * as ctxfi driver mutates from HD-audio to native mode with
2678 * a special command sequence.
2679 */
2680 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2681 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2682 .class_mask = 0xffffff,
2683 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2684 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2685 #else
2686 /* this entry seems still valid -- i.e. without emu20kx chip */
2687 { PCI_DEVICE(0x1102, 0x0009),
2688 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2689 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2690 #endif
2691 /* CM8888 */
2692 { PCI_DEVICE(0x13f6, 0x5011),
2693 .driver_data = AZX_DRIVER_CMEDIA |
2694 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2695 /* Vortex86MX */
2696 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2697 /* VMware HDAudio */
2698 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2699 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2700 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2701 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2702 .class_mask = 0xffffff,
2703 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2704 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2705 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2706 .class_mask = 0xffffff,
2707 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2708 { 0, }
2709 };
2710 MODULE_DEVICE_TABLE(pci, azx_ids);
2711
2712 /* pci_driver definition */
2713 static struct pci_driver azx_driver = {
2714 .name = KBUILD_MODNAME,
2715 .id_table = azx_ids,
2716 .probe = azx_probe,
2717 .remove = azx_remove,
2718 .shutdown = azx_shutdown,
2719 .driver = {
2720 .pm = AZX_PM_OPS,
2721 },
2722 };
2723
2724 module_pci_driver(azx_driver);
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