3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
55 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
56 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
57 static char *model
[SNDRV_CARDS
];
58 static int position_fix
[SNDRV_CARDS
];
59 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
60 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
61 static int probe_only
[SNDRV_CARDS
];
62 static int single_cmd
;
63 static int enable_msi
;
65 module_param_array(index
, int, NULL
, 0444);
66 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
67 module_param_array(id
, charp
, NULL
, 0444);
68 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
69 module_param_array(enable
, bool, NULL
, 0444);
70 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
71 module_param_array(model
, charp
, NULL
, 0444);
72 MODULE_PARM_DESC(model
, "Use the given board model.");
73 module_param_array(position_fix
, int, NULL
, 0444);
74 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer "
75 "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
78 module_param_array(probe_mask
, int, NULL
, 0444);
79 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only
, bool, NULL
, 0444);
81 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
82 module_param(single_cmd
, bool, 0444);
83 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
84 "(for debugging only).");
85 module_param(enable_msi
, int, 0444);
86 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
90 module_param(power_save
, int, 0644);
91 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
94 /* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
98 static int power_save_controller
= 1;
99 module_param(power_save_controller
, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
129 MODULE_DESCRIPTION("Intel HDA driver");
131 #ifdef CONFIG_SND_VERBOSE_PRINTK
132 #define SFX /* nop */
134 #define SFX "hda-intel: "
140 #define ICH6_REG_GCAP 0x00
141 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
142 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
143 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
144 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
145 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
146 #define ICH6_REG_VMIN 0x02
147 #define ICH6_REG_VMAJ 0x03
148 #define ICH6_REG_OUTPAY 0x04
149 #define ICH6_REG_INPAY 0x06
150 #define ICH6_REG_GCTL 0x08
151 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
152 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
153 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
154 #define ICH6_REG_WAKEEN 0x0c
155 #define ICH6_REG_STATESTS 0x0e
156 #define ICH6_REG_GSTS 0x10
157 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
158 #define ICH6_REG_INTCTL 0x20
159 #define ICH6_REG_INTSTS 0x24
160 #define ICH6_REG_WALCLK 0x30
161 #define ICH6_REG_SYNC 0x34
162 #define ICH6_REG_CORBLBASE 0x40
163 #define ICH6_REG_CORBUBASE 0x44
164 #define ICH6_REG_CORBWP 0x48
165 #define ICH6_REG_CORBRP 0x4a
166 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
167 #define ICH6_REG_CORBCTL 0x4c
168 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
169 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
170 #define ICH6_REG_CORBSTS 0x4d
171 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
172 #define ICH6_REG_CORBSIZE 0x4e
174 #define ICH6_REG_RIRBLBASE 0x50
175 #define ICH6_REG_RIRBUBASE 0x54
176 #define ICH6_REG_RIRBWP 0x58
177 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
178 #define ICH6_REG_RINTCNT 0x5a
179 #define ICH6_REG_RIRBCTL 0x5c
180 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
181 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
182 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
183 #define ICH6_REG_RIRBSTS 0x5d
184 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
185 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
186 #define ICH6_REG_RIRBSIZE 0x5e
188 #define ICH6_REG_IC 0x60
189 #define ICH6_REG_IR 0x64
190 #define ICH6_REG_IRS 0x68
191 #define ICH6_IRS_VALID (1<<1)
192 #define ICH6_IRS_BUSY (1<<0)
194 #define ICH6_REG_DPLBASE 0x70
195 #define ICH6_REG_DPUBASE 0x74
196 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
199 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
201 /* stream register offsets from stream base */
202 #define ICH6_REG_SD_CTL 0x00
203 #define ICH6_REG_SD_STS 0x03
204 #define ICH6_REG_SD_LPIB 0x04
205 #define ICH6_REG_SD_CBL 0x08
206 #define ICH6_REG_SD_LVI 0x0c
207 #define ICH6_REG_SD_FIFOW 0x0e
208 #define ICH6_REG_SD_FIFOSIZE 0x10
209 #define ICH6_REG_SD_FORMAT 0x12
210 #define ICH6_REG_SD_BDLPL 0x18
211 #define ICH6_REG_SD_BDLPU 0x1c
214 #define ICH6_PCIREG_TCSEL 0x44
220 /* max number of SDs */
221 /* ICH, ATI and VIA have 4 playback and 4 capture */
222 #define ICH6_NUM_CAPTURE 4
223 #define ICH6_NUM_PLAYBACK 4
225 /* ULI has 6 playback and 5 capture */
226 #define ULI_NUM_CAPTURE 5
227 #define ULI_NUM_PLAYBACK 6
229 /* ATI HDMI has 1 playback and 0 capture */
230 #define ATIHDMI_NUM_CAPTURE 0
231 #define ATIHDMI_NUM_PLAYBACK 1
233 /* TERA has 4 playback and 3 capture */
234 #define TERA_NUM_CAPTURE 3
235 #define TERA_NUM_PLAYBACK 4
237 /* this number is statically defined for simplicity */
238 #define MAX_AZX_DEV 16
240 /* max number of fragments - we may use more if allocating more pages for BDL */
241 #define BDL_SIZE 4096
242 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
243 #define AZX_MAX_FRAG 32
244 /* max buffer size - no h/w limit, you can increase as you like */
245 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
246 /* max number of PCM devics per card */
247 #define AZX_MAX_PCMS 8
249 /* RIRB int mask: overrun[2], response[0] */
250 #define RIRB_INT_RESPONSE 0x01
251 #define RIRB_INT_OVERRUN 0x04
252 #define RIRB_INT_MASK 0x05
254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
255 #define AZX_MAX_CODECS 4
256 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
259 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
260 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
261 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
262 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
263 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
264 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
265 #define SD_CTL_STREAM_TAG_SHIFT 20
267 /* SD_CTL and SD_STS */
268 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
269 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
270 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
271 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
275 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
277 /* INTCTL and INTSTS */
278 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
279 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
280 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
282 /* below are so far hardcoded - should read registers in future */
283 #define ICH6_MAX_CORB_ENTRIES 256
284 #define ICH6_MAX_RIRB_ENTRIES 256
286 /* position fix mode */
293 /* Defines for ATI HD Audio support in SB450 south bridge */
294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
297 /* Defines for Nvidia HDA support */
298 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
299 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
300 #define NVIDIA_HDA_ISTRM_COH 0x4d
301 #define NVIDIA_HDA_OSTRM_COH 0x4c
302 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
304 /* Defines for Intel SCH HDA snoop control */
305 #define INTEL_SCH_HDA_DEVC 0x78
306 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
308 /* Define IN stream 0 FIFO size offset in VIA controller */
309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
310 /* Define VIA HD Audio Device ID*/
311 #define VIA_HDAC_DEVICE_ID 0x3288
313 /* HD Audio class code */
314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
320 struct snd_dma_buffer bdl
; /* BDL buffer */
321 u32
*posbuf
; /* position buffer pointer */
323 unsigned int bufsize
; /* size of the play buffer in bytes */
324 unsigned int period_bytes
; /* size of the period in bytes */
325 unsigned int frags
; /* number for period in the play buffer */
326 unsigned int fifo_size
; /* FIFO size */
327 unsigned long start_jiffies
; /* start + minimum jiffies */
328 unsigned long min_jiffies
; /* minimum jiffies before position is valid */
330 void __iomem
*sd_addr
; /* stream descriptor pointer */
332 u32 sd_int_sta_mask
; /* stream int status mask */
335 struct snd_pcm_substream
*substream
; /* assigned substream,
338 unsigned int format_val
; /* format value to be set in the
339 * controller and the codec
341 unsigned char stream_tag
; /* assigned stream */
342 unsigned char index
; /* stream index */
344 unsigned int opened
:1;
345 unsigned int running
:1;
346 unsigned int irq_pending
:1;
347 unsigned int start_flag
: 1; /* stream full start flag */
350 * A flag to ensure DMA position is 0
351 * when link position is not greater than FIFO size
353 unsigned int insufficient
:1;
358 u32
*buf
; /* CORB/RIRB buffer
359 * Each CORB entry is 4byte, RIRB is 8byte
361 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
363 unsigned short rp
, wp
; /* read/write pointers */
364 int cmds
[AZX_MAX_CODECS
]; /* number of pending requests */
365 u32 res
[AZX_MAX_CODECS
]; /* last read value */
369 struct snd_card
*card
;
373 /* chip type specific */
375 int playback_streams
;
376 int playback_index_offset
;
378 int capture_index_offset
;
383 void __iomem
*remap_addr
;
388 struct mutex open_mutex
;
390 /* streams (x num_streams) */
391 struct azx_dev
*azx_dev
;
394 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
397 unsigned short codec_mask
;
398 int codec_probe_mask
; /* copied from probe_mask option */
405 /* CORB/RIRB and position buffers */
406 struct snd_dma_buffer rb
;
407 struct snd_dma_buffer posbuf
;
411 unsigned int running
:1;
412 unsigned int initialized
:1;
413 unsigned int single_cmd
:1;
414 unsigned int polling_mode
:1;
416 unsigned int irq_pending_warned
:1;
417 unsigned int via_dmapos_patch
:1; /* enable DMA-position fix for VIA */
418 unsigned int probing
:1; /* codec probing phase */
421 unsigned int last_cmd
; /* last issued command (to sync) */
423 /* for pending irqs */
424 struct work_struct irq_pending_work
;
426 /* reboot notifier (for mysterious hangup problem at power-down) */
427 struct notifier_block reboot_notifier
;
442 AZX_NUM_DRIVERS
, /* keep this as last entry */
445 static char *driver_short_names
[] __devinitdata
= {
446 [AZX_DRIVER_ICH
] = "HDA Intel",
447 [AZX_DRIVER_SCH
] = "HDA Intel MID",
448 [AZX_DRIVER_ATI
] = "HDA ATI SB",
449 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
450 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
451 [AZX_DRIVER_SIS
] = "HDA SIS966",
452 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
453 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
454 [AZX_DRIVER_TERA
] = "HDA Teradici",
455 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
459 * macros for easy use
461 #define azx_writel(chip,reg,value) \
462 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
463 #define azx_readl(chip,reg) \
464 readl((chip)->remap_addr + ICH6_REG_##reg)
465 #define azx_writew(chip,reg,value) \
466 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
467 #define azx_readw(chip,reg) \
468 readw((chip)->remap_addr + ICH6_REG_##reg)
469 #define azx_writeb(chip,reg,value) \
470 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
471 #define azx_readb(chip,reg) \
472 readb((chip)->remap_addr + ICH6_REG_##reg)
474 #define azx_sd_writel(dev,reg,value) \
475 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
476 #define azx_sd_readl(dev,reg) \
477 readl((dev)->sd_addr + ICH6_REG_##reg)
478 #define azx_sd_writew(dev,reg,value) \
479 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
480 #define azx_sd_readw(dev,reg) \
481 readw((dev)->sd_addr + ICH6_REG_##reg)
482 #define azx_sd_writeb(dev,reg,value) \
483 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
484 #define azx_sd_readb(dev,reg) \
485 readb((dev)->sd_addr + ICH6_REG_##reg)
487 /* for pcm support */
488 #define get_azx_dev(substream) (substream->runtime->private_data)
490 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
493 * Interface for HD codec
497 * CORB / RIRB interface
499 static int azx_alloc_cmd_io(struct azx
*chip
)
503 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
504 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
505 snd_dma_pci_data(chip
->pci
),
506 PAGE_SIZE
, &chip
->rb
);
508 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
514 static void azx_init_cmd_io(struct azx
*chip
)
516 spin_lock_irq(&chip
->reg_lock
);
518 chip
->corb
.addr
= chip
->rb
.addr
;
519 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
520 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
521 azx_writel(chip
, CORBUBASE
, upper_32_bits(chip
->corb
.addr
));
523 /* set the corb size to 256 entries (ULI requires explicitly) */
524 azx_writeb(chip
, CORBSIZE
, 0x02);
525 /* set the corb write pointer to 0 */
526 azx_writew(chip
, CORBWP
, 0);
527 /* reset the corb hw read pointer */
528 azx_writew(chip
, CORBRP
, ICH6_CORBRP_RST
);
529 /* enable corb dma */
530 azx_writeb(chip
, CORBCTL
, ICH6_CORBCTL_RUN
);
533 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
534 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
535 chip
->rirb
.wp
= chip
->rirb
.rp
= 0;
536 memset(chip
->rirb
.cmds
, 0, sizeof(chip
->rirb
.cmds
));
537 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
538 azx_writel(chip
, RIRBUBASE
, upper_32_bits(chip
->rirb
.addr
));
540 /* set the rirb size to 256 entries (ULI requires explicitly) */
541 azx_writeb(chip
, RIRBSIZE
, 0x02);
542 /* reset the rirb hw write pointer */
543 azx_writew(chip
, RIRBWP
, ICH6_RIRBWP_RST
);
544 /* set N=1, get RIRB response interrupt for new entry */
545 azx_writew(chip
, RINTCNT
, 1);
546 /* enable rirb dma and response irq */
547 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
548 spin_unlock_irq(&chip
->reg_lock
);
551 static void azx_free_cmd_io(struct azx
*chip
)
553 spin_lock_irq(&chip
->reg_lock
);
554 /* disable ringbuffer DMAs */
555 azx_writeb(chip
, RIRBCTL
, 0);
556 azx_writeb(chip
, CORBCTL
, 0);
557 spin_unlock_irq(&chip
->reg_lock
);
560 static unsigned int azx_command_addr(u32 cmd
)
562 unsigned int addr
= cmd
>> 28;
564 if (addr
>= AZX_MAX_CODECS
) {
572 static unsigned int azx_response_addr(u32 res
)
574 unsigned int addr
= res
& 0xf;
576 if (addr
>= AZX_MAX_CODECS
) {
585 static int azx_corb_send_cmd(struct hda_bus
*bus
, u32 val
)
587 struct azx
*chip
= bus
->private_data
;
588 unsigned int addr
= azx_command_addr(val
);
591 spin_lock_irq(&chip
->reg_lock
);
593 /* add command to corb */
594 wp
= azx_readb(chip
, CORBWP
);
596 wp
%= ICH6_MAX_CORB_ENTRIES
;
598 chip
->rirb
.cmds
[addr
]++;
599 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
600 azx_writel(chip
, CORBWP
, wp
);
602 spin_unlock_irq(&chip
->reg_lock
);
607 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
609 /* retrieve RIRB entry - called from interrupt handler */
610 static void azx_update_rirb(struct azx
*chip
)
616 wp
= azx_readb(chip
, RIRBWP
);
617 if (wp
== chip
->rirb
.wp
)
621 while (chip
->rirb
.rp
!= wp
) {
623 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
625 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
626 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
627 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
628 addr
= azx_response_addr(res_ex
);
629 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
630 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
631 else if (chip
->rirb
.cmds
[addr
]) {
632 chip
->rirb
.res
[addr
] = res
;
634 chip
->rirb
.cmds
[addr
]--;
639 /* receive a response */
640 static unsigned int azx_rirb_get_response(struct hda_bus
*bus
,
643 struct azx
*chip
= bus
->private_data
;
644 unsigned long timeout
;
647 timeout
= jiffies
+ msecs_to_jiffies(1000);
649 if (chip
->polling_mode
) {
650 spin_lock_irq(&chip
->reg_lock
);
651 azx_update_rirb(chip
);
652 spin_unlock_irq(&chip
->reg_lock
);
654 if (!chip
->rirb
.cmds
[addr
]) {
657 return chip
->rirb
.res
[addr
]; /* the last value */
659 if (time_after(jiffies
, timeout
))
661 if (bus
->needs_damn_long_delay
)
662 msleep(2); /* temporary workaround */
670 snd_printk(KERN_WARNING SFX
"No response from codec, "
671 "disabling MSI: last cmd=0x%08x\n", chip
->last_cmd
);
672 free_irq(chip
->irq
, chip
);
674 pci_disable_msi(chip
->pci
);
676 if (azx_acquire_irq(chip
, 1) < 0) {
683 if (!chip
->polling_mode
) {
684 snd_printk(KERN_WARNING SFX
"azx_get_response timeout, "
685 "switching to polling mode: last cmd=0x%08x\n",
687 chip
->polling_mode
= 1;
692 /* If this critical timeout happens during the codec probing
693 * phase, this is likely an access to a non-existing codec
694 * slot. Better to return an error and reset the system.
699 /* a fatal communication error; need either to reset or to fallback
700 * to the single_cmd mode
703 if (bus
->allow_bus_reset
&& !bus
->response_reset
&& !bus
->in_reset
) {
704 bus
->response_reset
= 1;
705 return -1; /* give a chance to retry */
708 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
709 "switching to single_cmd mode: last cmd=0x%08x\n",
711 chip
->single_cmd
= 1;
712 bus
->response_reset
= 0;
713 /* re-initialize CORB/RIRB */
714 azx_free_cmd_io(chip
);
715 azx_init_cmd_io(chip
);
720 * Use the single immediate command instead of CORB/RIRB for simplicity
722 * Note: according to Intel, this is not preferred use. The command was
723 * intended for the BIOS only, and may get confused with unsolicited
724 * responses. So, we shouldn't use it for normal operation from the
726 * I left the codes, however, for debugging/testing purposes.
729 /* receive a response */
730 static int azx_single_wait_for_response(struct azx
*chip
, unsigned int addr
)
735 /* check IRV busy bit */
736 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
) {
737 /* reuse rirb.res as the response return value */
738 chip
->rirb
.res
[addr
] = azx_readl(chip
, IR
);
743 if (printk_ratelimit())
744 snd_printd(SFX
"get_response timeout: IRS=0x%x\n",
745 azx_readw(chip
, IRS
));
746 chip
->rirb
.res
[addr
] = -1;
751 static int azx_single_send_cmd(struct hda_bus
*bus
, u32 val
)
753 struct azx
*chip
= bus
->private_data
;
754 unsigned int addr
= azx_command_addr(val
);
759 /* check ICB busy bit */
760 if (!((azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
))) {
761 /* Clear IRV valid bit */
762 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
764 azx_writel(chip
, IC
, val
);
765 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
767 return azx_single_wait_for_response(chip
, addr
);
771 if (printk_ratelimit())
772 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
773 azx_readw(chip
, IRS
), val
);
777 /* receive a response */
778 static unsigned int azx_single_get_response(struct hda_bus
*bus
,
781 struct azx
*chip
= bus
->private_data
;
782 return chip
->rirb
.res
[addr
];
786 * The below are the main callbacks from hda_codec.
788 * They are just the skeleton to call sub-callbacks according to the
789 * current setting of chip->single_cmd.
793 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
)
795 struct azx
*chip
= bus
->private_data
;
797 chip
->last_cmd
= val
;
798 if (chip
->single_cmd
)
799 return azx_single_send_cmd(bus
, val
);
801 return azx_corb_send_cmd(bus
, val
);
805 static unsigned int azx_get_response(struct hda_bus
*bus
,
808 struct azx
*chip
= bus
->private_data
;
809 if (chip
->single_cmd
)
810 return azx_single_get_response(bus
, addr
);
812 return azx_rirb_get_response(bus
, addr
);
815 #ifdef CONFIG_SND_HDA_POWER_SAVE
816 static void azx_power_notify(struct hda_bus
*bus
);
819 /* reset codec link */
820 static int azx_reset(struct azx
*chip
)
825 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
827 /* reset controller */
828 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
831 while (azx_readb(chip
, GCTL
) && --count
)
834 /* delay for >= 100us for codec PLL to settle per spec
835 * Rev 0.9 section 5.5.1
839 /* Bring controller out of reset */
840 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
843 while (!azx_readb(chip
, GCTL
) && --count
)
846 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
849 /* check to see if controller is ready */
850 if (!azx_readb(chip
, GCTL
)) {
851 snd_printd(SFX
"azx_reset: controller not ready!\n");
855 /* Accept unsolicited responses */
856 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UNSOL
);
859 if (!chip
->codec_mask
) {
860 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
861 snd_printdd(SFX
"codec_mask = 0x%x\n", chip
->codec_mask
);
872 /* enable interrupts */
873 static void azx_int_enable(struct azx
*chip
)
875 /* enable controller CIE and GIE */
876 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
877 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
880 /* disable interrupts */
881 static void azx_int_disable(struct azx
*chip
)
885 /* disable interrupts in stream descriptor */
886 for (i
= 0; i
< chip
->num_streams
; i
++) {
887 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
888 azx_sd_writeb(azx_dev
, SD_CTL
,
889 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
892 /* disable SIE for all streams */
893 azx_writeb(chip
, INTCTL
, 0);
895 /* disable controller CIE and GIE */
896 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
897 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
900 /* clear interrupts */
901 static void azx_int_clear(struct azx
*chip
)
905 /* clear stream status */
906 for (i
= 0; i
< chip
->num_streams
; i
++) {
907 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
908 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
912 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
914 /* clear rirb status */
915 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
917 /* clear int status */
918 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
922 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
925 * Before stream start, initialize parameter
927 azx_dev
->insufficient
= 1;
930 azx_writeb(chip
, INTCTL
,
931 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
932 /* set DMA start and interrupt mask */
933 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
934 SD_CTL_DMA_START
| SD_INT_MASK
);
938 static void azx_stream_clear(struct azx
*chip
, struct azx_dev
*azx_dev
)
940 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
941 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
942 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
946 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
948 azx_stream_clear(chip
, azx_dev
);
950 azx_writeb(chip
, INTCTL
,
951 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
956 * reset and start the controller registers
958 static void azx_init_chip(struct azx
*chip
)
960 if (chip
->initialized
)
963 /* reset controller */
966 /* initialize interrupts */
968 azx_int_enable(chip
);
970 /* initialize the codec command I/O */
971 azx_init_cmd_io(chip
);
973 /* program the position buffer */
974 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
975 azx_writel(chip
, DPUBASE
, upper_32_bits(chip
->posbuf
.addr
));
977 chip
->initialized
= 1;
981 * initialize the PCI registers
983 /* update bits in a PCI register byte */
984 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
985 unsigned char mask
, unsigned char val
)
989 pci_read_config_byte(pci
, reg
, &data
);
991 data
|= (val
& mask
);
992 pci_write_config_byte(pci
, reg
, data
);
995 static void azx_init_pci(struct azx
*chip
)
997 unsigned short snoop
;
999 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1000 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1001 * Ensuring these bits are 0 clears playback static on some HD Audio
1004 update_pci_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, 0x07, 0);
1006 switch (chip
->driver_type
) {
1007 case AZX_DRIVER_ATI
:
1008 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1009 update_pci_byte(chip
->pci
,
1010 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
1011 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
1013 case AZX_DRIVER_NVIDIA
:
1014 /* For NVIDIA HDA, enable snoop */
1015 update_pci_byte(chip
->pci
,
1016 NVIDIA_HDA_TRANSREG_ADDR
,
1017 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
1018 update_pci_byte(chip
->pci
,
1019 NVIDIA_HDA_ISTRM_COH
,
1020 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1021 update_pci_byte(chip
->pci
,
1022 NVIDIA_HDA_OSTRM_COH
,
1023 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1025 case AZX_DRIVER_SCH
:
1026 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
1027 if (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) {
1028 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
,
1029 snoop
& (~INTEL_SCH_HDA_DEVC_NOSNOOP
));
1030 pci_read_config_word(chip
->pci
,
1031 INTEL_SCH_HDA_DEVC
, &snoop
);
1032 snd_printdd(SFX
"HDA snoop disabled, enabling ... %s\n",
1033 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)
1042 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
1047 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
1049 struct azx
*chip
= dev_id
;
1050 struct azx_dev
*azx_dev
;
1054 spin_lock(&chip
->reg_lock
);
1056 status
= azx_readl(chip
, INTSTS
);
1058 spin_unlock(&chip
->reg_lock
);
1062 for (i
= 0; i
< chip
->num_streams
; i
++) {
1063 azx_dev
= &chip
->azx_dev
[i
];
1064 if (status
& azx_dev
->sd_int_sta_mask
) {
1065 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
1066 if (!azx_dev
->substream
|| !azx_dev
->running
)
1068 /* check whether this IRQ is really acceptable */
1069 ok
= azx_position_ok(chip
, azx_dev
);
1071 azx_dev
->irq_pending
= 0;
1072 spin_unlock(&chip
->reg_lock
);
1073 snd_pcm_period_elapsed(azx_dev
->substream
);
1074 spin_lock(&chip
->reg_lock
);
1075 } else if (ok
== 0 && chip
->bus
&& chip
->bus
->workq
) {
1076 /* bogus IRQ, process it later */
1077 azx_dev
->irq_pending
= 1;
1078 queue_work(chip
->bus
->workq
,
1079 &chip
->irq_pending_work
);
1084 /* clear rirb int */
1085 status
= azx_readb(chip
, RIRBSTS
);
1086 if (status
& RIRB_INT_MASK
) {
1087 if (status
& RIRB_INT_RESPONSE
)
1088 azx_update_rirb(chip
);
1089 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1093 /* clear state status int */
1094 if (azx_readb(chip
, STATESTS
) & 0x04)
1095 azx_writeb(chip
, STATESTS
, 0x04);
1097 spin_unlock(&chip
->reg_lock
);
1104 * set up a BDL entry
1106 static int setup_bdle(struct snd_pcm_substream
*substream
,
1107 struct azx_dev
*azx_dev
, u32
**bdlp
,
1108 int ofs
, int size
, int with_ioc
)
1116 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
1119 addr
= snd_pcm_sgbuf_get_addr(substream
, ofs
);
1120 /* program the address field of the BDL entry */
1121 bdl
[0] = cpu_to_le32((u32
)addr
);
1122 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
1123 /* program the size field of the BDL entry */
1124 chunk
= snd_pcm_sgbuf_get_chunk_size(substream
, ofs
, size
);
1125 bdl
[2] = cpu_to_le32(chunk
);
1126 /* program the IOC to enable interrupt
1127 * only when the whole fragment is processed
1130 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
1140 * set up BDL entries
1142 static int azx_setup_periods(struct azx
*chip
,
1143 struct snd_pcm_substream
*substream
,
1144 struct azx_dev
*azx_dev
)
1147 int i
, ofs
, periods
, period_bytes
;
1150 /* reset BDL address */
1151 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1152 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1154 period_bytes
= azx_dev
->period_bytes
;
1155 periods
= azx_dev
->bufsize
/ period_bytes
;
1157 /* program the initial BDL entries */
1158 bdl
= (u32
*)azx_dev
->bdl
.area
;
1161 pos_adj
= bdl_pos_adj
[chip
->dev_index
];
1163 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1164 int pos_align
= pos_adj
;
1165 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
1167 pos_adj
= pos_align
;
1169 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
1171 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
1172 if (pos_adj
>= period_bytes
) {
1173 snd_printk(KERN_WARNING SFX
"Too big adjustment %d\n",
1174 bdl_pos_adj
[chip
->dev_index
]);
1177 ofs
= setup_bdle(substream
, azx_dev
,
1178 &bdl
, ofs
, pos_adj
, 1);
1184 for (i
= 0; i
< periods
; i
++) {
1185 if (i
== periods
- 1 && pos_adj
)
1186 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1187 period_bytes
- pos_adj
, 0);
1189 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1197 snd_printk(KERN_ERR SFX
"Too many BDL entries: buffer=%d, period=%d\n",
1198 azx_dev
->bufsize
, period_bytes
);
1203 static void azx_stream_reset(struct azx
*chip
, struct azx_dev
*azx_dev
)
1208 azx_stream_clear(chip
, azx_dev
);
1210 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
1211 SD_CTL_STREAM_RESET
);
1214 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1217 val
&= ~SD_CTL_STREAM_RESET
;
1218 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
1222 /* waiting for hardware to report that the stream is out of reset */
1223 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1227 /* reset first position - may not be synced with hw at this time */
1228 *azx_dev
->posbuf
= 0;
1232 * set up the SD for streaming
1234 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
1236 /* make sure the run bit is zero for SD */
1237 azx_stream_clear(chip
, azx_dev
);
1238 /* program the stream_tag */
1239 azx_sd_writel(azx_dev
, SD_CTL
,
1240 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
)|
1241 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
1243 /* program the length of samples in cyclic buffer */
1244 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
1246 /* program the stream format */
1247 /* this value needs to be the same as the one programmed */
1248 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
1250 /* program the stream LVI (last valid index) of the BDL */
1251 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
1253 /* program the BDL address */
1254 /* lower BDL address */
1255 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
1256 /* upper BDL address */
1257 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32_bits(azx_dev
->bdl
.addr
));
1259 /* enable the position buffer */
1260 if (chip
->position_fix
== POS_FIX_POSBUF
||
1261 chip
->position_fix
== POS_FIX_AUTO
||
1262 chip
->via_dmapos_patch
) {
1263 if (!(azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
1264 azx_writel(chip
, DPLBASE
,
1265 (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
1268 /* set the interrupt enable bits in the descriptor control register */
1269 azx_sd_writel(azx_dev
, SD_CTL
,
1270 azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
1276 * Probe the given codec address
1278 static int probe_codec(struct azx
*chip
, int addr
)
1280 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
1281 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
1284 mutex_lock(&chip
->bus
->cmd_mutex
);
1286 azx_send_cmd(chip
->bus
, cmd
);
1287 res
= azx_get_response(chip
->bus
, addr
);
1289 mutex_unlock(&chip
->bus
->cmd_mutex
);
1292 snd_printdd(SFX
"codec #%d probed OK\n", addr
);
1296 static int azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1297 struct hda_pcm
*cpcm
);
1298 static void azx_stop_chip(struct azx
*chip
);
1300 static void azx_bus_reset(struct hda_bus
*bus
)
1302 struct azx
*chip
= bus
->private_data
;
1305 azx_stop_chip(chip
);
1306 azx_init_chip(chip
);
1308 if (chip
->initialized
) {
1311 for (i
= 0; i
< AZX_MAX_PCMS
; i
++)
1312 snd_pcm_suspend_all(chip
->pcm
[i
]);
1313 snd_hda_suspend(chip
->bus
);
1314 snd_hda_resume(chip
->bus
);
1321 * Codec initialization
1324 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1325 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] __devinitdata
= {
1326 [AZX_DRIVER_TERA
] = 1,
1329 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
,
1332 struct hda_bus_template bus_temp
;
1336 memset(&bus_temp
, 0, sizeof(bus_temp
));
1337 bus_temp
.private_data
= chip
;
1338 bus_temp
.modelname
= model
;
1339 bus_temp
.pci
= chip
->pci
;
1340 bus_temp
.ops
.command
= azx_send_cmd
;
1341 bus_temp
.ops
.get_response
= azx_get_response
;
1342 bus_temp
.ops
.attach_pcm
= azx_attach_pcm_stream
;
1343 bus_temp
.ops
.bus_reset
= azx_bus_reset
;
1344 #ifdef CONFIG_SND_HDA_POWER_SAVE
1345 bus_temp
.power_save
= &power_save
;
1346 bus_temp
.ops
.pm_notify
= azx_power_notify
;
1349 err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
);
1353 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
)
1354 chip
->bus
->needs_damn_long_delay
= 1;
1357 max_slots
= azx_max_codecs
[chip
->driver_type
];
1359 max_slots
= AZX_MAX_CODECS
;
1361 /* First try to probe all given codec slots */
1362 for (c
= 0; c
< max_slots
; c
++) {
1363 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1364 if (probe_codec(chip
, c
) < 0) {
1365 /* Some BIOSen give you wrong codec addresses
1368 snd_printk(KERN_WARNING SFX
1369 "Codec #%d probe error; "
1370 "disabling it...\n", c
);
1371 chip
->codec_mask
&= ~(1 << c
);
1372 /* More badly, accessing to a non-existing
1373 * codec often screws up the controller chip,
1374 * and distrubs the further communications.
1375 * Thus if an error occurs during probing,
1376 * better to reset the controller chip to
1377 * get back to the sanity state.
1379 azx_stop_chip(chip
);
1380 azx_init_chip(chip
);
1385 /* Then create codec instances */
1386 for (c
= 0; c
< max_slots
; c
++) {
1387 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1388 struct hda_codec
*codec
;
1389 err
= snd_hda_codec_new(chip
->bus
, c
, !no_init
, &codec
);
1396 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1408 /* assign a stream for the PCM */
1409 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
1412 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1413 dev
= chip
->playback_index_offset
;
1414 nums
= chip
->playback_streams
;
1416 dev
= chip
->capture_index_offset
;
1417 nums
= chip
->capture_streams
;
1419 for (i
= 0; i
< nums
; i
++, dev
++)
1420 if (!chip
->azx_dev
[dev
].opened
) {
1421 chip
->azx_dev
[dev
].opened
= 1;
1422 return &chip
->azx_dev
[dev
];
1427 /* release the assigned stream */
1428 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1430 azx_dev
->opened
= 0;
1433 static struct snd_pcm_hardware azx_pcm_hw
= {
1434 .info
= (SNDRV_PCM_INFO_MMAP
|
1435 SNDRV_PCM_INFO_INTERLEAVED
|
1436 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1437 SNDRV_PCM_INFO_MMAP_VALID
|
1438 /* No full-resume yet implemented */
1439 /* SNDRV_PCM_INFO_RESUME |*/
1440 SNDRV_PCM_INFO_PAUSE
|
1441 SNDRV_PCM_INFO_SYNC_START
),
1442 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1443 .rates
= SNDRV_PCM_RATE_48000
,
1448 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1449 .period_bytes_min
= 128,
1450 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1452 .periods_max
= AZX_MAX_FRAG
,
1458 struct hda_codec
*codec
;
1459 struct hda_pcm_stream
*hinfo
[2];
1462 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1464 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1465 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1466 struct azx
*chip
= apcm
->chip
;
1467 struct azx_dev
*azx_dev
;
1468 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1469 unsigned long flags
;
1472 mutex_lock(&chip
->open_mutex
);
1473 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1474 if (azx_dev
== NULL
) {
1475 mutex_unlock(&chip
->open_mutex
);
1478 runtime
->hw
= azx_pcm_hw
;
1479 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1480 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1481 runtime
->hw
.formats
= hinfo
->formats
;
1482 runtime
->hw
.rates
= hinfo
->rates
;
1483 snd_pcm_limit_hw_rates(runtime
);
1484 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1485 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1487 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1489 snd_hda_power_up(apcm
->codec
);
1490 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
1492 azx_release_device(azx_dev
);
1493 snd_hda_power_down(apcm
->codec
);
1494 mutex_unlock(&chip
->open_mutex
);
1497 snd_pcm_limit_hw_rates(runtime
);
1499 if (snd_BUG_ON(!runtime
->hw
.channels_min
) ||
1500 snd_BUG_ON(!runtime
->hw
.channels_max
) ||
1501 snd_BUG_ON(!runtime
->hw
.formats
) ||
1502 snd_BUG_ON(!runtime
->hw
.rates
)) {
1503 azx_release_device(azx_dev
);
1504 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1505 snd_hda_power_down(apcm
->codec
);
1506 mutex_unlock(&chip
->open_mutex
);
1509 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1510 azx_dev
->substream
= substream
;
1511 azx_dev
->running
= 0;
1512 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1514 runtime
->private_data
= azx_dev
;
1515 snd_pcm_set_sync(substream
);
1516 mutex_unlock(&chip
->open_mutex
);
1520 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1522 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1523 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1524 struct azx
*chip
= apcm
->chip
;
1525 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1526 unsigned long flags
;
1528 mutex_lock(&chip
->open_mutex
);
1529 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1530 azx_dev
->substream
= NULL
;
1531 azx_dev
->running
= 0;
1532 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1533 azx_release_device(azx_dev
);
1534 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1535 snd_hda_power_down(apcm
->codec
);
1536 mutex_unlock(&chip
->open_mutex
);
1540 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
1541 struct snd_pcm_hw_params
*hw_params
)
1543 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1545 azx_dev
->bufsize
= 0;
1546 azx_dev
->period_bytes
= 0;
1547 azx_dev
->format_val
= 0;
1548 return snd_pcm_lib_malloc_pages(substream
,
1549 params_buffer_bytes(hw_params
));
1552 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1554 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1555 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1556 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1558 /* reset BDL address */
1559 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1560 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1561 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1562 azx_dev
->bufsize
= 0;
1563 azx_dev
->period_bytes
= 0;
1564 azx_dev
->format_val
= 0;
1566 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1568 return snd_pcm_lib_free_pages(substream
);
1571 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1573 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1574 struct azx
*chip
= apcm
->chip
;
1575 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1576 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1577 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1578 unsigned int bufsize
, period_bytes
, format_val
;
1581 azx_stream_reset(chip
, azx_dev
);
1582 format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1587 snd_printk(KERN_ERR SFX
1588 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1589 runtime
->rate
, runtime
->channels
, runtime
->format
);
1593 bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1594 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1596 snd_printdd(SFX
"azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1597 bufsize
, format_val
);
1599 if (bufsize
!= azx_dev
->bufsize
||
1600 period_bytes
!= azx_dev
->period_bytes
||
1601 format_val
!= azx_dev
->format_val
) {
1602 azx_dev
->bufsize
= bufsize
;
1603 azx_dev
->period_bytes
= period_bytes
;
1604 azx_dev
->format_val
= format_val
;
1605 err
= azx_setup_periods(chip
, substream
, azx_dev
);
1610 azx_dev
->min_jiffies
= (runtime
->period_size
* HZ
) /
1611 (runtime
->rate
* 2);
1612 azx_setup_controller(chip
, azx_dev
);
1613 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1614 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1616 azx_dev
->fifo_size
= 0;
1618 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1619 azx_dev
->format_val
, substream
);
1622 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1624 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1625 struct azx
*chip
= apcm
->chip
;
1626 struct azx_dev
*azx_dev
;
1627 struct snd_pcm_substream
*s
;
1628 int rstart
= 0, start
, nsync
= 0, sbits
= 0;
1632 case SNDRV_PCM_TRIGGER_START
:
1634 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1635 case SNDRV_PCM_TRIGGER_RESUME
:
1638 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1639 case SNDRV_PCM_TRIGGER_SUSPEND
:
1640 case SNDRV_PCM_TRIGGER_STOP
:
1647 snd_pcm_group_for_each_entry(s
, substream
) {
1648 if (s
->pcm
->card
!= substream
->pcm
->card
)
1650 azx_dev
= get_azx_dev(s
);
1651 sbits
|= 1 << azx_dev
->index
;
1653 snd_pcm_trigger_done(s
, substream
);
1656 spin_lock(&chip
->reg_lock
);
1658 /* first, set SYNC bits of corresponding streams */
1659 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) | sbits
);
1661 snd_pcm_group_for_each_entry(s
, substream
) {
1662 if (s
->pcm
->card
!= substream
->pcm
->card
)
1664 azx_dev
= get_azx_dev(s
);
1666 azx_dev
->start_flag
= 1;
1667 azx_dev
->start_jiffies
= jiffies
+ azx_dev
->min_jiffies
;
1670 azx_stream_start(chip
, azx_dev
);
1672 azx_stream_stop(chip
, azx_dev
);
1673 azx_dev
->running
= start
;
1675 spin_unlock(&chip
->reg_lock
);
1679 /* wait until all FIFOs get ready */
1680 for (timeout
= 5000; timeout
; timeout
--) {
1682 snd_pcm_group_for_each_entry(s
, substream
) {
1683 if (s
->pcm
->card
!= substream
->pcm
->card
)
1685 azx_dev
= get_azx_dev(s
);
1686 if (!(azx_sd_readb(azx_dev
, SD_STS
) &
1695 /* wait until all RUN bits are cleared */
1696 for (timeout
= 5000; timeout
; timeout
--) {
1698 snd_pcm_group_for_each_entry(s
, substream
) {
1699 if (s
->pcm
->card
!= substream
->pcm
->card
)
1701 azx_dev
= get_azx_dev(s
);
1702 if (azx_sd_readb(azx_dev
, SD_CTL
) &
1712 spin_lock(&chip
->reg_lock
);
1713 /* reset SYNC bits */
1714 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) & ~sbits
);
1715 spin_unlock(&chip
->reg_lock
);
1720 /* get the current DMA position with correction on VIA chips */
1721 static unsigned int azx_via_get_position(struct azx
*chip
,
1722 struct azx_dev
*azx_dev
)
1724 unsigned int link_pos
, mini_pos
, bound_pos
;
1725 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
1726 unsigned int fifo_size
;
1728 link_pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1729 if (azx_dev
->index
>= 4) {
1730 /* Playback, no problem using link position */
1736 * use mod to get the DMA position just like old chipset
1738 mod_dma_pos
= le32_to_cpu(*azx_dev
->posbuf
);
1739 mod_dma_pos
%= azx_dev
->period_bytes
;
1741 /* azx_dev->fifo_size can't get FIFO size of in stream.
1742 * Get from base address + offset.
1744 fifo_size
= readw(chip
->remap_addr
+ VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
1746 if (azx_dev
->insufficient
) {
1747 /* Link position never gather than FIFO size */
1748 if (link_pos
<= fifo_size
)
1751 azx_dev
->insufficient
= 0;
1754 if (link_pos
<= fifo_size
)
1755 mini_pos
= azx_dev
->bufsize
+ link_pos
- fifo_size
;
1757 mini_pos
= link_pos
- fifo_size
;
1759 /* Find nearest previous boudary */
1760 mod_mini_pos
= mini_pos
% azx_dev
->period_bytes
;
1761 mod_link_pos
= link_pos
% azx_dev
->period_bytes
;
1762 if (mod_link_pos
>= fifo_size
)
1763 bound_pos
= link_pos
- mod_link_pos
;
1764 else if (mod_dma_pos
>= mod_mini_pos
)
1765 bound_pos
= mini_pos
- mod_mini_pos
;
1767 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->period_bytes
;
1768 if (bound_pos
>= azx_dev
->bufsize
)
1772 /* Calculate real DMA position we want */
1773 return bound_pos
+ mod_dma_pos
;
1776 static unsigned int azx_get_position(struct azx
*chip
,
1777 struct azx_dev
*azx_dev
)
1781 if (chip
->via_dmapos_patch
)
1782 pos
= azx_via_get_position(chip
, azx_dev
);
1783 else if (chip
->position_fix
== POS_FIX_POSBUF
||
1784 chip
->position_fix
== POS_FIX_AUTO
) {
1785 /* use the position buffer */
1786 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1789 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1791 if (pos
>= azx_dev
->bufsize
)
1796 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1798 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1799 struct azx
*chip
= apcm
->chip
;
1800 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1801 return bytes_to_frames(substream
->runtime
,
1802 azx_get_position(chip
, azx_dev
));
1806 * Check whether the current DMA position is acceptable for updating
1807 * periods. Returns non-zero if it's OK.
1809 * Many HD-audio controllers appear pretty inaccurate about
1810 * the update-IRQ timing. The IRQ is issued before actually the
1811 * data is processed. So, we need to process it afterwords in a
1814 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
1818 if (azx_dev
->start_flag
&&
1819 time_before_eq(jiffies
, azx_dev
->start_jiffies
))
1820 return -1; /* bogus (too early) interrupt */
1821 azx_dev
->start_flag
= 0;
1823 pos
= azx_get_position(chip
, azx_dev
);
1824 if (chip
->position_fix
== POS_FIX_AUTO
) {
1827 "hda-intel: Invalid position buffer, "
1828 "using LPIB read method instead.\n");
1829 chip
->position_fix
= POS_FIX_LPIB
;
1830 pos
= azx_get_position(chip
, azx_dev
);
1832 chip
->position_fix
= POS_FIX_POSBUF
;
1835 if (!bdl_pos_adj
[chip
->dev_index
])
1836 return 1; /* no delayed ack */
1837 if (pos
% azx_dev
->period_bytes
> azx_dev
->period_bytes
/ 2)
1838 return 0; /* NG - it's below the period boundary */
1839 return 1; /* OK, it's fine */
1843 * The work for pending PCM period updates.
1845 static void azx_irq_pending_work(struct work_struct
*work
)
1847 struct azx
*chip
= container_of(work
, struct azx
, irq_pending_work
);
1850 if (!chip
->irq_pending_warned
) {
1852 "hda-intel: IRQ timing workaround is activated "
1853 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1854 chip
->card
->number
);
1855 chip
->irq_pending_warned
= 1;
1860 spin_lock_irq(&chip
->reg_lock
);
1861 for (i
= 0; i
< chip
->num_streams
; i
++) {
1862 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1863 if (!azx_dev
->irq_pending
||
1864 !azx_dev
->substream
||
1867 if (azx_position_ok(chip
, azx_dev
)) {
1868 azx_dev
->irq_pending
= 0;
1869 spin_unlock(&chip
->reg_lock
);
1870 snd_pcm_period_elapsed(azx_dev
->substream
);
1871 spin_lock(&chip
->reg_lock
);
1875 spin_unlock_irq(&chip
->reg_lock
);
1882 /* clear irq_pending flags and assure no on-going workq */
1883 static void azx_clear_irq_pending(struct azx
*chip
)
1887 spin_lock_irq(&chip
->reg_lock
);
1888 for (i
= 0; i
< chip
->num_streams
; i
++)
1889 chip
->azx_dev
[i
].irq_pending
= 0;
1890 spin_unlock_irq(&chip
->reg_lock
);
1893 static struct snd_pcm_ops azx_pcm_ops
= {
1894 .open
= azx_pcm_open
,
1895 .close
= azx_pcm_close
,
1896 .ioctl
= snd_pcm_lib_ioctl
,
1897 .hw_params
= azx_pcm_hw_params
,
1898 .hw_free
= azx_pcm_hw_free
,
1899 .prepare
= azx_pcm_prepare
,
1900 .trigger
= azx_pcm_trigger
,
1901 .pointer
= azx_pcm_pointer
,
1902 .page
= snd_pcm_sgbuf_ops_page
,
1905 static void azx_pcm_free(struct snd_pcm
*pcm
)
1907 struct azx_pcm
*apcm
= pcm
->private_data
;
1909 apcm
->chip
->pcm
[pcm
->device
] = NULL
;
1915 azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1916 struct hda_pcm
*cpcm
)
1918 struct azx
*chip
= bus
->private_data
;
1919 struct snd_pcm
*pcm
;
1920 struct azx_pcm
*apcm
;
1921 int pcm_dev
= cpcm
->device
;
1924 if (pcm_dev
>= AZX_MAX_PCMS
) {
1925 snd_printk(KERN_ERR SFX
"Invalid PCM device number %d\n",
1929 if (chip
->pcm
[pcm_dev
]) {
1930 snd_printk(KERN_ERR SFX
"PCM %d already exists\n", pcm_dev
);
1933 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1934 cpcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].substreams
,
1935 cpcm
->stream
[SNDRV_PCM_STREAM_CAPTURE
].substreams
,
1939 strlcpy(pcm
->name
, cpcm
->name
, sizeof(pcm
->name
));
1940 apcm
= kzalloc(sizeof(*apcm
), GFP_KERNEL
);
1944 apcm
->codec
= codec
;
1945 pcm
->private_data
= apcm
;
1946 pcm
->private_free
= azx_pcm_free
;
1947 if (cpcm
->pcm_type
== HDA_PCM_TYPE_MODEM
)
1948 pcm
->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1949 chip
->pcm
[pcm_dev
] = pcm
;
1951 for (s
= 0; s
< 2; s
++) {
1952 apcm
->hinfo
[s
] = &cpcm
->stream
[s
];
1953 if (cpcm
->stream
[s
].substreams
)
1954 snd_pcm_set_ops(pcm
, s
, &azx_pcm_ops
);
1956 /* buffer pre-allocation */
1957 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV_SG
,
1958 snd_dma_pci_data(chip
->pci
),
1959 1024 * 64, 32 * 1024 * 1024);
1964 * mixer creation - all stuff is implemented in hda module
1966 static int __devinit
azx_mixer_create(struct azx
*chip
)
1968 return snd_hda_build_controls(chip
->bus
);
1973 * initialize SD streams
1975 static int __devinit
azx_init_stream(struct azx
*chip
)
1979 /* initialize each stream (aka device)
1980 * assign the starting bdl address to each stream (device)
1983 for (i
= 0; i
< chip
->num_streams
; i
++) {
1984 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1985 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
1986 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1987 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1988 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1989 azx_dev
->sd_int_sta_mask
= 1 << i
;
1990 /* stream tag: must be non-zero and unique */
1992 azx_dev
->stream_tag
= i
+ 1;
1998 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
2000 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
2001 chip
->msi
? 0 : IRQF_SHARED
,
2002 "HDA Intel", chip
)) {
2003 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
2004 "disabling device\n", chip
->pci
->irq
);
2006 snd_card_disconnect(chip
->card
);
2009 chip
->irq
= chip
->pci
->irq
;
2010 pci_intx(chip
->pci
, !chip
->msi
);
2015 static void azx_stop_chip(struct azx
*chip
)
2017 if (!chip
->initialized
)
2020 /* disable interrupts */
2021 azx_int_disable(chip
);
2022 azx_int_clear(chip
);
2024 /* disable CORB/RIRB */
2025 azx_free_cmd_io(chip
);
2027 /* disable position buffer */
2028 azx_writel(chip
, DPLBASE
, 0);
2029 azx_writel(chip
, DPUBASE
, 0);
2031 chip
->initialized
= 0;
2034 #ifdef CONFIG_SND_HDA_POWER_SAVE
2035 /* power-up/down the controller */
2036 static void azx_power_notify(struct hda_bus
*bus
)
2038 struct azx
*chip
= bus
->private_data
;
2039 struct hda_codec
*c
;
2042 list_for_each_entry(c
, &bus
->codec_list
, list
) {
2049 azx_init_chip(chip
);
2050 else if (chip
->running
&& power_save_controller
)
2051 azx_stop_chip(chip
);
2053 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2060 static int snd_hda_codecs_inuse(struct hda_bus
*bus
)
2062 struct hda_codec
*codec
;
2064 list_for_each_entry(codec
, &bus
->codec_list
, list
) {
2065 if (snd_hda_codec_needs_resume(codec
))
2071 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
2073 struct snd_card
*card
= pci_get_drvdata(pci
);
2074 struct azx
*chip
= card
->private_data
;
2077 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
2078 azx_clear_irq_pending(chip
);
2079 for (i
= 0; i
< AZX_MAX_PCMS
; i
++)
2080 snd_pcm_suspend_all(chip
->pcm
[i
]);
2081 if (chip
->initialized
)
2082 snd_hda_suspend(chip
->bus
);
2083 azx_stop_chip(chip
);
2084 if (chip
->irq
>= 0) {
2085 free_irq(chip
->irq
, chip
);
2089 pci_disable_msi(chip
->pci
);
2090 pci_disable_device(pci
);
2091 pci_save_state(pci
);
2092 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
2096 static int azx_resume(struct pci_dev
*pci
)
2098 struct snd_card
*card
= pci_get_drvdata(pci
);
2099 struct azx
*chip
= card
->private_data
;
2101 pci_set_power_state(pci
, PCI_D0
);
2102 pci_restore_state(pci
);
2103 if (pci_enable_device(pci
) < 0) {
2104 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
2105 "disabling device\n");
2106 snd_card_disconnect(card
);
2109 pci_set_master(pci
);
2111 if (pci_enable_msi(pci
) < 0)
2113 if (azx_acquire_irq(chip
, 1) < 0)
2117 if (snd_hda_codecs_inuse(chip
->bus
))
2118 azx_init_chip(chip
);
2120 snd_hda_resume(chip
->bus
);
2121 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2124 #endif /* CONFIG_PM */
2128 * reboot notifier for hang-up problem at power-down
2130 static int azx_halt(struct notifier_block
*nb
, unsigned long event
, void *buf
)
2132 struct azx
*chip
= container_of(nb
, struct azx
, reboot_notifier
);
2133 azx_stop_chip(chip
);
2137 static void azx_notifier_register(struct azx
*chip
)
2139 chip
->reboot_notifier
.notifier_call
= azx_halt
;
2140 register_reboot_notifier(&chip
->reboot_notifier
);
2143 static void azx_notifier_unregister(struct azx
*chip
)
2145 if (chip
->reboot_notifier
.notifier_call
)
2146 unregister_reboot_notifier(&chip
->reboot_notifier
);
2152 static int azx_free(struct azx
*chip
)
2156 azx_notifier_unregister(chip
);
2158 if (chip
->initialized
) {
2159 azx_clear_irq_pending(chip
);
2160 for (i
= 0; i
< chip
->num_streams
; i
++)
2161 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
2162 azx_stop_chip(chip
);
2166 free_irq(chip
->irq
, (void*)chip
);
2168 pci_disable_msi(chip
->pci
);
2169 if (chip
->remap_addr
)
2170 iounmap(chip
->remap_addr
);
2172 if (chip
->azx_dev
) {
2173 for (i
= 0; i
< chip
->num_streams
; i
++)
2174 if (chip
->azx_dev
[i
].bdl
.area
)
2175 snd_dma_free_pages(&chip
->azx_dev
[i
].bdl
);
2178 snd_dma_free_pages(&chip
->rb
);
2179 if (chip
->posbuf
.area
)
2180 snd_dma_free_pages(&chip
->posbuf
);
2181 pci_release_regions(chip
->pci
);
2182 pci_disable_device(chip
->pci
);
2183 kfree(chip
->azx_dev
);
2189 static int azx_dev_free(struct snd_device
*device
)
2191 return azx_free(device
->device_data
);
2195 * white/black-listing for position_fix
2197 static struct snd_pci_quirk position_fix_list
[] __devinitdata
= {
2198 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
2199 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
2200 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
2204 static int __devinit
check_position_fix(struct azx
*chip
, int fix
)
2206 const struct snd_pci_quirk
*q
;
2210 case POS_FIX_POSBUF
:
2214 /* Check VIA/ATI HD Audio Controller exist */
2215 switch (chip
->driver_type
) {
2216 case AZX_DRIVER_VIA
:
2217 case AZX_DRIVER_ATI
:
2218 chip
->via_dmapos_patch
= 1;
2219 /* Use link position directly, avoid any transfer problem. */
2220 return POS_FIX_LPIB
;
2222 chip
->via_dmapos_patch
= 0;
2224 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
2227 "hda_intel: position_fix set to %d "
2228 "for device %04x:%04x\n",
2229 q
->value
, q
->subvendor
, q
->subdevice
);
2232 return POS_FIX_AUTO
;
2236 * black-lists for probe_mask
2238 static struct snd_pci_quirk probe_mask_list
[] __devinitdata
= {
2239 /* Thinkpad often breaks the controller communication when accessing
2240 * to the non-working (or non-existing) modem codec slot.
2242 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2243 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2244 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2246 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2247 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2248 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2249 /* forced codec slots */
2250 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2251 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2255 #define AZX_FORCE_CODEC_MASK 0x100
2257 static void __devinit
check_probe_mask(struct azx
*chip
, int dev
)
2259 const struct snd_pci_quirk
*q
;
2261 chip
->codec_probe_mask
= probe_mask
[dev
];
2262 if (chip
->codec_probe_mask
== -1) {
2263 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
2266 "hda_intel: probe_mask set to 0x%x "
2267 "for device %04x:%04x\n",
2268 q
->value
, q
->subvendor
, q
->subdevice
);
2269 chip
->codec_probe_mask
= q
->value
;
2273 /* check forced option */
2274 if (chip
->codec_probe_mask
!= -1 &&
2275 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
2276 chip
->codec_mask
= chip
->codec_probe_mask
& 0xff;
2277 printk(KERN_INFO
"hda_intel: codec_mask forced to 0x%x\n",
2286 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
2287 int dev
, int driver_type
,
2292 unsigned short gcap
;
2293 static struct snd_device_ops ops
= {
2294 .dev_free
= azx_dev_free
,
2299 err
= pci_enable_device(pci
);
2303 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
2305 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
2306 pci_disable_device(pci
);
2310 spin_lock_init(&chip
->reg_lock
);
2311 mutex_init(&chip
->open_mutex
);
2315 chip
->driver_type
= driver_type
;
2316 chip
->msi
= enable_msi
;
2317 chip
->dev_index
= dev
;
2318 INIT_WORK(&chip
->irq_pending_work
, azx_irq_pending_work
);
2320 chip
->position_fix
= check_position_fix(chip
, position_fix
[dev
]);
2321 check_probe_mask(chip
, dev
);
2323 chip
->single_cmd
= single_cmd
;
2325 if (bdl_pos_adj
[dev
] < 0) {
2326 switch (chip
->driver_type
) {
2327 case AZX_DRIVER_ICH
:
2328 bdl_pos_adj
[dev
] = 1;
2331 bdl_pos_adj
[dev
] = 32;
2336 #if BITS_PER_LONG != 64
2337 /* Fix up base address on ULI M5461 */
2338 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
2340 pci_read_config_word(pci
, 0x40, &tmp3
);
2341 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
2342 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
2346 err
= pci_request_regions(pci
, "ICH HD audio");
2349 pci_disable_device(pci
);
2353 chip
->addr
= pci_resource_start(pci
, 0);
2354 chip
->remap_addr
= pci_ioremap_bar(pci
, 0);
2355 if (chip
->remap_addr
== NULL
) {
2356 snd_printk(KERN_ERR SFX
"ioremap error\n");
2362 if (pci_enable_msi(pci
) < 0)
2365 if (azx_acquire_irq(chip
, 0) < 0) {
2370 pci_set_master(pci
);
2371 synchronize_irq(chip
->irq
);
2373 gcap
= azx_readw(chip
, GCAP
);
2374 snd_printdd(SFX
"chipset global capabilities = 0x%x\n", gcap
);
2376 /* disable SB600 64bit support for safety */
2377 if ((chip
->driver_type
== AZX_DRIVER_ATI
) ||
2378 (chip
->driver_type
== AZX_DRIVER_ATIHDMI
)) {
2379 struct pci_dev
*p_smbus
;
2380 p_smbus
= pci_get_device(PCI_VENDOR_ID_ATI
,
2381 PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2384 if (p_smbus
->revision
< 0x30)
2385 gcap
&= ~ICH6_GCAP_64OK
;
2386 pci_dev_put(p_smbus
);
2390 /* allow 64bit DMA address if supported by H/W */
2391 if ((gcap
& ICH6_GCAP_64OK
) && !pci_set_dma_mask(pci
, DMA_BIT_MASK(64)))
2392 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(64));
2394 pci_set_dma_mask(pci
, DMA_BIT_MASK(32));
2395 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(32));
2398 /* read number of streams from GCAP register instead of using
2401 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
2402 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
2403 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
2404 /* gcap didn't give any info, switching to old method */
2406 switch (chip
->driver_type
) {
2407 case AZX_DRIVER_ULI
:
2408 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
2409 chip
->capture_streams
= ULI_NUM_CAPTURE
;
2411 case AZX_DRIVER_ATIHDMI
:
2412 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
2413 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
2415 case AZX_DRIVER_GENERIC
:
2417 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
2418 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
2422 chip
->capture_index_offset
= 0;
2423 chip
->playback_index_offset
= chip
->capture_streams
;
2424 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
2425 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
),
2427 if (!chip
->azx_dev
) {
2428 snd_printk(KERN_ERR SFX
"cannot malloc azx_dev\n");
2432 for (i
= 0; i
< chip
->num_streams
; i
++) {
2433 /* allocate memory for the BDL for each stream */
2434 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2435 snd_dma_pci_data(chip
->pci
),
2436 BDL_SIZE
, &chip
->azx_dev
[i
].bdl
);
2438 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
2442 /* allocate memory for the position buffer */
2443 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2444 snd_dma_pci_data(chip
->pci
),
2445 chip
->num_streams
* 8, &chip
->posbuf
);
2447 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
2450 /* allocate CORB/RIRB */
2451 err
= azx_alloc_cmd_io(chip
);
2455 /* initialize streams */
2456 azx_init_stream(chip
);
2458 /* initialize chip */
2460 azx_init_chip(chip
);
2462 /* codec detection */
2463 if (!chip
->codec_mask
) {
2464 snd_printk(KERN_ERR SFX
"no codecs found!\n");
2469 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
2471 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
2475 strcpy(card
->driver
, "HDA-Intel");
2476 strlcpy(card
->shortname
, driver_short_names
[chip
->driver_type
],
2477 sizeof(card
->shortname
));
2478 snprintf(card
->longname
, sizeof(card
->longname
),
2479 "%s at 0x%lx irq %i",
2480 card
->shortname
, chip
->addr
, chip
->irq
);
2490 static void power_down_all_codecs(struct azx
*chip
)
2492 #ifdef CONFIG_SND_HDA_POWER_SAVE
2493 /* The codecs were powered up in snd_hda_codec_new().
2494 * Now all initialization done, so turn them down if possible
2496 struct hda_codec
*codec
;
2497 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
2498 snd_hda_power_down(codec
);
2503 static int __devinit
azx_probe(struct pci_dev
*pci
,
2504 const struct pci_device_id
*pci_id
)
2507 struct snd_card
*card
;
2511 if (dev
>= SNDRV_CARDS
)
2518 err
= snd_card_create(index
[dev
], id
[dev
], THIS_MODULE
, 0, &card
);
2520 snd_printk(KERN_ERR SFX
"Error creating card!\n");
2524 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2527 card
->private_data
= chip
;
2529 /* create codec instances */
2530 err
= azx_codec_create(chip
, model
[dev
], probe_only
[dev
]);
2534 /* create PCM streams */
2535 err
= snd_hda_build_pcms(chip
->bus
);
2539 /* create mixer controls */
2540 err
= azx_mixer_create(chip
);
2544 snd_card_set_dev(card
, &pci
->dev
);
2546 err
= snd_card_register(card
);
2550 pci_set_drvdata(pci
, card
);
2552 power_down_all_codecs(chip
);
2553 azx_notifier_register(chip
);
2558 snd_card_free(card
);
2562 static void __devexit
azx_remove(struct pci_dev
*pci
)
2564 snd_card_free(pci_get_drvdata(pci
));
2565 pci_set_drvdata(pci
, NULL
);
2569 static struct pci_device_id azx_ids
[] = {
2571 { PCI_DEVICE(0x8086, 0x2668), .driver_data
= AZX_DRIVER_ICH
},
2572 { PCI_DEVICE(0x8086, 0x27d8), .driver_data
= AZX_DRIVER_ICH
},
2573 { PCI_DEVICE(0x8086, 0x269a), .driver_data
= AZX_DRIVER_ICH
},
2574 { PCI_DEVICE(0x8086, 0x284b), .driver_data
= AZX_DRIVER_ICH
},
2575 { PCI_DEVICE(0x8086, 0x2911), .driver_data
= AZX_DRIVER_ICH
},
2576 { PCI_DEVICE(0x8086, 0x293e), .driver_data
= AZX_DRIVER_ICH
},
2577 { PCI_DEVICE(0x8086, 0x293f), .driver_data
= AZX_DRIVER_ICH
},
2578 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data
= AZX_DRIVER_ICH
},
2579 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data
= AZX_DRIVER_ICH
},
2581 { PCI_DEVICE(0x8086, 0x3b56), .driver_data
= AZX_DRIVER_ICH
},
2583 { PCI_DEVICE(0x8086, 0x811b), .driver_data
= AZX_DRIVER_SCH
},
2584 /* ATI SB 450/600 */
2585 { PCI_DEVICE(0x1002, 0x437b), .driver_data
= AZX_DRIVER_ATI
},
2586 { PCI_DEVICE(0x1002, 0x4383), .driver_data
= AZX_DRIVER_ATI
},
2588 { PCI_DEVICE(0x1002, 0x793b), .driver_data
= AZX_DRIVER_ATIHDMI
},
2589 { PCI_DEVICE(0x1002, 0x7919), .driver_data
= AZX_DRIVER_ATIHDMI
},
2590 { PCI_DEVICE(0x1002, 0x960f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2591 { PCI_DEVICE(0x1002, 0x970f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2592 { PCI_DEVICE(0x1002, 0xaa00), .driver_data
= AZX_DRIVER_ATIHDMI
},
2593 { PCI_DEVICE(0x1002, 0xaa08), .driver_data
= AZX_DRIVER_ATIHDMI
},
2594 { PCI_DEVICE(0x1002, 0xaa10), .driver_data
= AZX_DRIVER_ATIHDMI
},
2595 { PCI_DEVICE(0x1002, 0xaa18), .driver_data
= AZX_DRIVER_ATIHDMI
},
2596 { PCI_DEVICE(0x1002, 0xaa20), .driver_data
= AZX_DRIVER_ATIHDMI
},
2597 { PCI_DEVICE(0x1002, 0xaa28), .driver_data
= AZX_DRIVER_ATIHDMI
},
2598 { PCI_DEVICE(0x1002, 0xaa30), .driver_data
= AZX_DRIVER_ATIHDMI
},
2599 { PCI_DEVICE(0x1002, 0xaa38), .driver_data
= AZX_DRIVER_ATIHDMI
},
2600 { PCI_DEVICE(0x1002, 0xaa40), .driver_data
= AZX_DRIVER_ATIHDMI
},
2601 { PCI_DEVICE(0x1002, 0xaa48), .driver_data
= AZX_DRIVER_ATIHDMI
},
2602 /* VIA VT8251/VT8237A */
2603 { PCI_DEVICE(0x1106, 0x3288), .driver_data
= AZX_DRIVER_VIA
},
2605 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
2607 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
2609 { PCI_DEVICE(0x10de, 0x026c), .driver_data
= AZX_DRIVER_NVIDIA
},
2610 { PCI_DEVICE(0x10de, 0x0371), .driver_data
= AZX_DRIVER_NVIDIA
},
2611 { PCI_DEVICE(0x10de, 0x03e4), .driver_data
= AZX_DRIVER_NVIDIA
},
2612 { PCI_DEVICE(0x10de, 0x03f0), .driver_data
= AZX_DRIVER_NVIDIA
},
2613 { PCI_DEVICE(0x10de, 0x044a), .driver_data
= AZX_DRIVER_NVIDIA
},
2614 { PCI_DEVICE(0x10de, 0x044b), .driver_data
= AZX_DRIVER_NVIDIA
},
2615 { PCI_DEVICE(0x10de, 0x055c), .driver_data
= AZX_DRIVER_NVIDIA
},
2616 { PCI_DEVICE(0x10de, 0x055d), .driver_data
= AZX_DRIVER_NVIDIA
},
2617 { PCI_DEVICE(0x10de, 0x0774), .driver_data
= AZX_DRIVER_NVIDIA
},
2618 { PCI_DEVICE(0x10de, 0x0775), .driver_data
= AZX_DRIVER_NVIDIA
},
2619 { PCI_DEVICE(0x10de, 0x0776), .driver_data
= AZX_DRIVER_NVIDIA
},
2620 { PCI_DEVICE(0x10de, 0x0777), .driver_data
= AZX_DRIVER_NVIDIA
},
2621 { PCI_DEVICE(0x10de, 0x07fc), .driver_data
= AZX_DRIVER_NVIDIA
},
2622 { PCI_DEVICE(0x10de, 0x07fd), .driver_data
= AZX_DRIVER_NVIDIA
},
2623 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data
= AZX_DRIVER_NVIDIA
},
2624 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data
= AZX_DRIVER_NVIDIA
},
2625 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data
= AZX_DRIVER_NVIDIA
},
2626 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data
= AZX_DRIVER_NVIDIA
},
2627 { PCI_DEVICE(0x10de, 0x0d94), .driver_data
= AZX_DRIVER_NVIDIA
},
2628 { PCI_DEVICE(0x10de, 0x0d95), .driver_data
= AZX_DRIVER_NVIDIA
},
2629 { PCI_DEVICE(0x10de, 0x0d96), .driver_data
= AZX_DRIVER_NVIDIA
},
2630 { PCI_DEVICE(0x10de, 0x0d97), .driver_data
= AZX_DRIVER_NVIDIA
},
2632 { PCI_DEVICE(0x6549, 0x1200), .driver_data
= AZX_DRIVER_TERA
},
2633 /* Creative X-Fi (CA0110-IBG) */
2634 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2635 /* the following entry conflicts with snd-ctxfi driver,
2636 * as ctxfi driver mutates from HD-audio to native mode with
2637 * a special command sequence.
2639 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE
, PCI_ANY_ID
),
2640 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2641 .class_mask
= 0xffffff,
2642 .driver_data
= AZX_DRIVER_GENERIC
},
2644 /* this entry seems still valid -- i.e. without emu20kx chip */
2645 { PCI_DEVICE(0x1102, 0x0009), .driver_data
= AZX_DRIVER_GENERIC
},
2647 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2648 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
2649 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2650 .class_mask
= 0xffffff,
2651 .driver_data
= AZX_DRIVER_GENERIC
},
2654 MODULE_DEVICE_TABLE(pci
, azx_ids
);
2656 /* pci_driver definition */
2657 static struct pci_driver driver
= {
2658 .name
= "HDA Intel",
2659 .id_table
= azx_ids
,
2661 .remove
= __devexit_p(azx_remove
),
2663 .suspend
= azx_suspend
,
2664 .resume
= azx_resume
,
2668 static int __init
alsa_card_azx_init(void)
2670 return pci_register_driver(&driver
);
2673 static void __exit
alsa_card_azx_exit(void)
2675 pci_unregister_driver(&driver
);
2678 module_init(alsa_card_azx_init
)
2679 module_exit(alsa_card_azx_exit
)