3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/set_memory.h>
57 #include <asm/cpufeature.h>
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
73 /* position fix mode */
83 /* Defines for ATI HD Audio support in SB450 south bridge */
84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
87 /* Defines for Nvidia HDA support */
88 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90 #define NVIDIA_HDA_ISTRM_COH 0x4d
91 #define NVIDIA_HDA_OSTRM_COH 0x4c
92 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
94 /* Defines for Intel SCH HDA snoop control */
95 #define INTEL_HDA_CGCTL 0x48
96 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
97 #define INTEL_SCH_HDA_DEVC 0x78
98 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
100 /* Define IN stream 0 FIFO size offset in VIA controller */
101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102 /* Define VIA HD Audio Device ID*/
103 #define VIA_HDAC_DEVICE_ID 0x3288
105 /* max number of SDs */
106 /* ICH, ATI and VIA have 4 playback and 4 capture */
107 #define ICH6_NUM_CAPTURE 4
108 #define ICH6_NUM_PLAYBACK 4
110 /* ULI has 6 playback and 5 capture */
111 #define ULI_NUM_CAPTURE 5
112 #define ULI_NUM_PLAYBACK 6
114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
115 #define ATIHDMI_NUM_CAPTURE 0
116 #define ATIHDMI_NUM_PLAYBACK 8
118 /* TERA has 4 playback and 3 capture */
119 #define TERA_NUM_CAPTURE 3
120 #define TERA_NUM_PLAYBACK 4
123 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
124 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
125 static bool enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
126 static char *model
[SNDRV_CARDS
];
127 static int position_fix
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
128 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
129 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
130 static int probe_only
[SNDRV_CARDS
];
131 static int jackpoll_ms
[SNDRV_CARDS
];
132 static int single_cmd
= -1;
133 static int enable_msi
= -1;
134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
135 static char *patch
[SNDRV_CARDS
];
137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
138 static bool beep_mode
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] =
139 CONFIG_SND_HDA_INPUT_BEEP_MODE
};
142 module_param_array(index
, int, NULL
, 0444);
143 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
144 module_param_array(id
, charp
, NULL
, 0444);
145 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
146 module_param_array(enable
, bool, NULL
, 0444);
147 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
148 module_param_array(model
, charp
, NULL
, 0444);
149 MODULE_PARM_DESC(model
, "Use the given board model.");
150 module_param_array(position_fix
, int, NULL
, 0444);
151 MODULE_PARM_DESC(position_fix
, "DMA pointer read method."
152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
153 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
154 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
155 module_param_array(probe_mask
, int, NULL
, 0444);
156 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
157 module_param_array(probe_only
, int, NULL
, 0444);
158 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
159 module_param_array(jackpoll_ms
, int, NULL
, 0444);
160 MODULE_PARM_DESC(jackpoll_ms
, "Ms between polling for jack events (default = 0, using unsol events only)");
161 module_param(single_cmd
, bint
, 0444);
162 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
163 "(for debugging only).");
164 module_param(enable_msi
, bint
, 0444);
165 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
167 module_param_array(patch
, charp
, NULL
, 0444);
168 MODULE_PARM_DESC(patch
, "Patch file for Intel HD audio interface.");
170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
171 module_param_array(beep_mode
, bool, NULL
, 0444);
172 MODULE_PARM_DESC(beep_mode
, "Select HDA Beep registration mode "
173 "(0=off, 1=on) (default=1).");
177 static int param_set_xint(const char *val
, const struct kernel_param
*kp
);
178 static const struct kernel_param_ops param_ops_xint
= {
179 .set
= param_set_xint
,
180 .get
= param_get_int
,
182 #define param_check_xint param_check_int
184 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
185 module_param(power_save
, xint
, 0644);
186 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
189 /* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
193 static bool power_save_controller
= 1;
194 module_param(power_save_controller
, bool, 0644);
195 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
198 #endif /* CONFIG_PM */
200 static int align_buffer_size
= -1;
201 module_param(align_buffer_size
, bint
, 0644);
202 MODULE_PARM_DESC(align_buffer_size
,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
206 static int hda_snoop
= -1;
207 module_param_named(snoop
, hda_snoop
, bint
, 0444);
208 MODULE_PARM_DESC(snoop
, "Enable/disable snooping");
210 #define hda_snoop true
214 MODULE_LICENSE("GPL");
215 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
249 MODULE_DESCRIPTION("Intel HDA driver");
251 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
252 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
253 #define SUPPORT_VGA_SWITCHEROO
270 AZX_DRIVER_ATIHDMI_NS
,
280 AZX_NUM_DRIVERS
, /* keep this as last entry */
283 #define azx_get_snoop_type(chip) \
284 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
285 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
287 /* quirks for old Intel chipsets */
288 #define AZX_DCAPS_INTEL_ICH \
289 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
291 /* quirks for Intel PCH */
292 #define AZX_DCAPS_INTEL_PCH_BASE \
293 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
294 AZX_DCAPS_SNOOP_TYPE(SCH))
296 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
297 #define AZX_DCAPS_INTEL_PCH_NOPM \
298 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
300 /* PCH for HSW/BDW; with runtime PM */
301 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
302 #define AZX_DCAPS_INTEL_PCH \
303 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
306 #define AZX_DCAPS_INTEL_HASWELL \
307 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
308 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
309 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
311 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
312 #define AZX_DCAPS_INTEL_BROADWELL \
313 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
314 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
315 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))
317 #define AZX_DCAPS_INTEL_BAYTRAIL \
318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\
319 AZX_DCAPS_I915_POWERWELL)
321 #define AZX_DCAPS_INTEL_BRASWELL \
322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
323 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)
325 #define AZX_DCAPS_INTEL_SKYLAKE \
326 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
327 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
328 AZX_DCAPS_I915_POWERWELL)
330 #define AZX_DCAPS_INTEL_BROXTON \
331 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
332 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\
333 AZX_DCAPS_I915_POWERWELL)
335 /* quirks for ATI SB / AMD Hudson */
336 #define AZX_DCAPS_PRESET_ATI_SB \
337 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
338 AZX_DCAPS_SNOOP_TYPE(ATI))
340 /* quirks for ATI/AMD HDMI */
341 #define AZX_DCAPS_PRESET_ATI_HDMI \
342 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
345 /* quirks for ATI HDMI with snoop off */
346 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
347 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
349 /* quirks for Nvidia */
350 #define AZX_DCAPS_PRESET_NVIDIA \
351 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
352 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
354 #define AZX_DCAPS_PRESET_CTHDA \
355 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
356 AZX_DCAPS_NO_64BIT |\
357 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
360 * vga_switcheroo support
362 #ifdef SUPPORT_VGA_SWITCHEROO
363 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
365 #define use_vga_switcheroo(chip) 0
368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
369 ((pci)->device == 0x0c0c) || \
370 ((pci)->device == 0x0d0c) || \
371 ((pci)->device == 0x160c))
373 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
375 static char *driver_short_names
[] = {
376 [AZX_DRIVER_ICH
] = "HDA Intel",
377 [AZX_DRIVER_PCH
] = "HDA Intel PCH",
378 [AZX_DRIVER_SCH
] = "HDA Intel MID",
379 [AZX_DRIVER_SKL
] = "HDA Intel PCH", /* kept old name for compatibility */
380 [AZX_DRIVER_HDMI
] = "HDA Intel HDMI",
381 [AZX_DRIVER_ATI
] = "HDA ATI SB",
382 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
383 [AZX_DRIVER_ATIHDMI_NS
] = "HDA ATI HDMI",
384 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
385 [AZX_DRIVER_SIS
] = "HDA SIS966",
386 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
387 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
388 [AZX_DRIVER_TERA
] = "HDA Teradici",
389 [AZX_DRIVER_CTX
] = "HDA Creative",
390 [AZX_DRIVER_CTHDA
] = "HDA Creative",
391 [AZX_DRIVER_CMEDIA
] = "HDA C-Media",
392 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
396 static void __mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*dmab
, bool on
)
402 if (!dmab
|| !dmab
->area
|| !dmab
->bytes
)
405 #ifdef CONFIG_SND_DMA_SGBUF
406 if (dmab
->dev
.type
== SNDRV_DMA_TYPE_DEV_SG
) {
407 struct snd_sg_buf
*sgbuf
= dmab
->private_data
;
408 if (chip
->driver_type
== AZX_DRIVER_CMEDIA
)
409 return; /* deal with only CORB/RIRB buffers */
411 set_pages_array_wc(sgbuf
->page_table
, sgbuf
->pages
);
413 set_pages_array_wb(sgbuf
->page_table
, sgbuf
->pages
);
418 pages
= (dmab
->bytes
+ PAGE_SIZE
- 1) >> PAGE_SHIFT
;
420 set_memory_wc((unsigned long)dmab
->area
, pages
);
422 set_memory_wb((unsigned long)dmab
->area
, pages
);
425 static inline void mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*buf
,
428 __mark_pages_wc(chip
, buf
, on
);
430 static inline void mark_runtime_wc(struct azx
*chip
, struct azx_dev
*azx_dev
,
431 struct snd_pcm_substream
*substream
, bool on
)
433 if (azx_dev
->wc_marked
!= on
) {
434 __mark_pages_wc(chip
, snd_pcm_get_dma_buf(substream
), on
);
435 azx_dev
->wc_marked
= on
;
439 /* NOP for other archs */
440 static inline void mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*buf
,
444 static inline void mark_runtime_wc(struct azx
*chip
, struct azx_dev
*azx_dev
,
445 struct snd_pcm_substream
*substream
, bool on
)
450 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
453 * initialize the PCI registers
455 /* update bits in a PCI register byte */
456 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
457 unsigned char mask
, unsigned char val
)
461 pci_read_config_byte(pci
, reg
, &data
);
463 data
|= (val
& mask
);
464 pci_write_config_byte(pci
, reg
, data
);
467 static void azx_init_pci(struct azx
*chip
)
469 int snoop_type
= azx_get_snoop_type(chip
);
471 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
472 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
473 * Ensuring these bits are 0 clears playback static on some HD Audio
475 * The PCI register TCSEL is defined in the Intel manuals.
477 if (!(chip
->driver_caps
& AZX_DCAPS_NO_TCSEL
)) {
478 dev_dbg(chip
->card
->dev
, "Clearing TCSEL\n");
479 update_pci_byte(chip
->pci
, AZX_PCIREG_TCSEL
, 0x07, 0);
482 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
483 * we need to enable snoop.
485 if (snoop_type
== AZX_SNOOP_TYPE_ATI
) {
486 dev_dbg(chip
->card
->dev
, "Setting ATI snoop: %d\n",
488 update_pci_byte(chip
->pci
,
489 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
, 0x07,
490 azx_snoop(chip
) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP
: 0);
493 /* For NVIDIA HDA, enable snoop */
494 if (snoop_type
== AZX_SNOOP_TYPE_NVIDIA
) {
495 dev_dbg(chip
->card
->dev
, "Setting Nvidia snoop: %d\n",
497 update_pci_byte(chip
->pci
,
498 NVIDIA_HDA_TRANSREG_ADDR
,
499 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
500 update_pci_byte(chip
->pci
,
501 NVIDIA_HDA_ISTRM_COH
,
502 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
503 update_pci_byte(chip
->pci
,
504 NVIDIA_HDA_OSTRM_COH
,
505 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
508 /* Enable SCH/PCH snoop if needed */
509 if (snoop_type
== AZX_SNOOP_TYPE_SCH
) {
510 unsigned short snoop
;
511 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
512 if ((!azx_snoop(chip
) && !(snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)) ||
513 (azx_snoop(chip
) && (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
))) {
514 snoop
&= ~INTEL_SCH_HDA_DEVC_NOSNOOP
;
515 if (!azx_snoop(chip
))
516 snoop
|= INTEL_SCH_HDA_DEVC_NOSNOOP
;
517 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, snoop
);
518 pci_read_config_word(chip
->pci
,
519 INTEL_SCH_HDA_DEVC
, &snoop
);
521 dev_dbg(chip
->card
->dev
, "SCH snoop: %s\n",
522 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) ?
523 "Disabled" : "Enabled");
528 * In BXT-P A0, HD-Audio DMA requests is later than expected,
529 * and makes an audio stream sensitive to system latencies when
530 * 24/32 bits are playing.
531 * Adjusting threshold of DMA fifo to force the DMA request
532 * sooner to improve latency tolerance at the expense of power.
534 static void bxt_reduce_dma_latency(struct azx
*chip
)
538 val
= azx_readl(chip
, VS_EM4L
);
540 azx_writel(chip
, VS_EM4L
, val
);
545 * bit 0: 6 MHz Supported
546 * bit 1: 12 MHz Supported
547 * bit 2: 24 MHz Supported
548 * bit 3: 48 MHz Supported
549 * bit 4: 96 MHz Supported
550 * bit 5: 192 MHz Supported
552 static int intel_get_lctl_scf(struct azx
*chip
)
554 struct hdac_bus
*bus
= azx_bus(chip
);
555 static int preferred_bits
[] = { 2, 3, 1, 4, 5 };
559 val
= readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCAP
);
561 for (i
= 0; i
< ARRAY_SIZE(preferred_bits
); i
++) {
562 t
= preferred_bits
[i
];
567 dev_warn(chip
->card
->dev
, "set audio clock frequency to 6MHz");
571 static int intel_ml_lctl_set_power(struct azx
*chip
, int state
)
573 struct hdac_bus
*bus
= azx_bus(chip
);
578 * the codecs are sharing the first link setting by default
579 * If other links are enabled for stream, they need similar fix
581 val
= readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
582 val
&= ~AZX_MLCTL_SPA
;
583 val
|= state
<< AZX_MLCTL_SPA_SHIFT
;
584 writel(val
, bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
588 if (((readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
)) &
589 AZX_MLCTL_CPA
) == (state
<< AZX_MLCTL_CPA_SHIFT
))
598 static void intel_init_lctl(struct azx
*chip
)
600 struct hdac_bus
*bus
= azx_bus(chip
);
604 /* 0. check lctl register value is correct or not */
605 val
= readl(bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
606 /* if SCF is already set, let's use it */
607 if ((val
& ML_LCTL_SCF_MASK
) != 0)
611 * Before operating on SPA, CPA must match SPA.
612 * Any deviation may result in undefined behavior.
614 if (((val
& AZX_MLCTL_SPA
) >> AZX_MLCTL_SPA_SHIFT
) !=
615 ((val
& AZX_MLCTL_CPA
) >> AZX_MLCTL_CPA_SHIFT
))
618 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
619 ret
= intel_ml_lctl_set_power(chip
, 0);
624 /* 2. update SCF to select a properly audio clock*/
625 val
&= ~ML_LCTL_SCF_MASK
;
626 val
|= intel_get_lctl_scf(chip
);
627 writel(val
, bus
->mlcap
+ AZX_ML_BASE
+ AZX_REG_ML_LCTL
);
630 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
631 intel_ml_lctl_set_power(chip
, 1);
635 static void hda_intel_init_chip(struct azx
*chip
, bool full_reset
)
637 struct hdac_bus
*bus
= azx_bus(chip
);
638 struct pci_dev
*pci
= chip
->pci
;
641 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
642 snd_hdac_set_codec_wakeup(bus
, true);
643 if (chip
->driver_type
== AZX_DRIVER_SKL
) {
644 pci_read_config_dword(pci
, INTEL_HDA_CGCTL
, &val
);
645 val
= val
& ~INTEL_HDA_CGCTL_MISCBDCGE
;
646 pci_write_config_dword(pci
, INTEL_HDA_CGCTL
, val
);
648 azx_init_chip(chip
, full_reset
);
649 if (chip
->driver_type
== AZX_DRIVER_SKL
) {
650 pci_read_config_dword(pci
, INTEL_HDA_CGCTL
, &val
);
651 val
= val
| INTEL_HDA_CGCTL_MISCBDCGE
;
652 pci_write_config_dword(pci
, INTEL_HDA_CGCTL
, val
);
654 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
655 snd_hdac_set_codec_wakeup(bus
, false);
657 /* reduce dma latency to avoid noise */
659 bxt_reduce_dma_latency(chip
);
661 if (bus
->mlcap
!= NULL
)
662 intel_init_lctl(chip
);
665 /* calculate runtime delay from LPIB */
666 static int azx_get_delay_from_lpib(struct azx
*chip
, struct azx_dev
*azx_dev
,
669 struct snd_pcm_substream
*substream
= azx_dev
->core
.substream
;
670 int stream
= substream
->stream
;
671 unsigned int lpib_pos
= azx_get_pos_lpib(chip
, azx_dev
);
674 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
)
675 delay
= pos
- lpib_pos
;
677 delay
= lpib_pos
- pos
;
679 if (delay
>= azx_dev
->core
.delay_negative_threshold
)
682 delay
+= azx_dev
->core
.bufsize
;
685 if (delay
>= azx_dev
->core
.period_bytes
) {
686 dev_info(chip
->card
->dev
,
687 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
688 delay
, azx_dev
->core
.period_bytes
);
690 chip
->driver_caps
&= ~AZX_DCAPS_COUNT_LPIB_DELAY
;
691 chip
->get_delay
[stream
] = NULL
;
694 return bytes_to_frames(substream
->runtime
, delay
);
697 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
699 /* called from IRQ */
700 static int azx_position_check(struct azx
*chip
, struct azx_dev
*azx_dev
)
702 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
705 ok
= azx_position_ok(chip
, azx_dev
);
707 azx_dev
->irq_pending
= 0;
709 } else if (ok
== 0) {
710 /* bogus IRQ, process it later */
711 azx_dev
->irq_pending
= 1;
712 schedule_work(&hda
->irq_pending_work
);
717 /* Enable/disable i915 display power for the link */
718 static int azx_intel_link_power(struct azx
*chip
, bool enable
)
720 struct hdac_bus
*bus
= azx_bus(chip
);
722 return snd_hdac_display_power(bus
, enable
);
726 * Check whether the current DMA position is acceptable for updating
727 * periods. Returns non-zero if it's OK.
729 * Many HD-audio controllers appear pretty inaccurate about
730 * the update-IRQ timing. The IRQ is issued before actually the
731 * data is processed. So, we need to process it afterwords in a
734 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
736 struct snd_pcm_substream
*substream
= azx_dev
->core
.substream
;
737 int stream
= substream
->stream
;
741 wallclk
= azx_readl(chip
, WALLCLK
) - azx_dev
->core
.start_wallclk
;
742 if (wallclk
< (azx_dev
->core
.period_wallclk
* 2) / 3)
743 return -1; /* bogus (too early) interrupt */
745 if (chip
->get_position
[stream
])
746 pos
= chip
->get_position
[stream
](chip
, azx_dev
);
747 else { /* use the position buffer as default */
748 pos
= azx_get_pos_posbuf(chip
, azx_dev
);
749 if (!pos
|| pos
== (u32
)-1) {
750 dev_info(chip
->card
->dev
,
751 "Invalid position buffer, using LPIB read method instead.\n");
752 chip
->get_position
[stream
] = azx_get_pos_lpib
;
753 if (chip
->get_position
[0] == azx_get_pos_lpib
&&
754 chip
->get_position
[1] == azx_get_pos_lpib
)
755 azx_bus(chip
)->use_posbuf
= false;
756 pos
= azx_get_pos_lpib(chip
, azx_dev
);
757 chip
->get_delay
[stream
] = NULL
;
759 chip
->get_position
[stream
] = azx_get_pos_posbuf
;
760 if (chip
->driver_caps
& AZX_DCAPS_COUNT_LPIB_DELAY
)
761 chip
->get_delay
[stream
] = azx_get_delay_from_lpib
;
765 if (pos
>= azx_dev
->core
.bufsize
)
768 if (WARN_ONCE(!azx_dev
->core
.period_bytes
,
769 "hda-intel: zero azx_dev->period_bytes"))
770 return -1; /* this shouldn't happen! */
771 if (wallclk
< (azx_dev
->core
.period_wallclk
* 5) / 4 &&
772 pos
% azx_dev
->core
.period_bytes
> azx_dev
->core
.period_bytes
/ 2)
773 /* NG - it's below the first next period boundary */
774 return chip
->bdl_pos_adj
? 0 : -1;
775 azx_dev
->core
.start_wallclk
+= wallclk
;
776 return 1; /* OK, it's fine */
780 * The work for pending PCM period updates.
782 static void azx_irq_pending_work(struct work_struct
*work
)
784 struct hda_intel
*hda
= container_of(work
, struct hda_intel
, irq_pending_work
);
785 struct azx
*chip
= &hda
->chip
;
786 struct hdac_bus
*bus
= azx_bus(chip
);
787 struct hdac_stream
*s
;
790 if (!hda
->irq_pending_warned
) {
791 dev_info(chip
->card
->dev
,
792 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
794 hda
->irq_pending_warned
= 1;
799 spin_lock_irq(&bus
->reg_lock
);
800 list_for_each_entry(s
, &bus
->stream_list
, list
) {
801 struct azx_dev
*azx_dev
= stream_to_azx_dev(s
);
802 if (!azx_dev
->irq_pending
||
806 ok
= azx_position_ok(chip
, azx_dev
);
808 azx_dev
->irq_pending
= 0;
809 spin_unlock(&bus
->reg_lock
);
810 snd_pcm_period_elapsed(s
->substream
);
811 spin_lock(&bus
->reg_lock
);
813 pending
= 0; /* too early */
817 spin_unlock_irq(&bus
->reg_lock
);
824 /* clear irq_pending flags and assure no on-going workq */
825 static void azx_clear_irq_pending(struct azx
*chip
)
827 struct hdac_bus
*bus
= azx_bus(chip
);
828 struct hdac_stream
*s
;
830 spin_lock_irq(&bus
->reg_lock
);
831 list_for_each_entry(s
, &bus
->stream_list
, list
) {
832 struct azx_dev
*azx_dev
= stream_to_azx_dev(s
);
833 azx_dev
->irq_pending
= 0;
835 spin_unlock_irq(&bus
->reg_lock
);
838 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
840 struct hdac_bus
*bus
= azx_bus(chip
);
842 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
843 chip
->msi
? 0 : IRQF_SHARED
,
844 chip
->card
->irq_descr
, chip
)) {
845 dev_err(chip
->card
->dev
,
846 "unable to grab IRQ %d, disabling device\n",
849 snd_card_disconnect(chip
->card
);
852 bus
->irq
= chip
->pci
->irq
;
853 pci_intx(chip
->pci
, !chip
->msi
);
857 /* get the current DMA position with correction on VIA chips */
858 static unsigned int azx_via_get_position(struct azx
*chip
,
859 struct azx_dev
*azx_dev
)
861 unsigned int link_pos
, mini_pos
, bound_pos
;
862 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
863 unsigned int fifo_size
;
865 link_pos
= snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev
));
866 if (azx_dev
->core
.substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
867 /* Playback, no problem using link position */
873 * use mod to get the DMA position just like old chipset
875 mod_dma_pos
= le32_to_cpu(*azx_dev
->core
.posbuf
);
876 mod_dma_pos
%= azx_dev
->core
.period_bytes
;
878 /* azx_dev->fifo_size can't get FIFO size of in stream.
879 * Get from base address + offset.
881 fifo_size
= readw(azx_bus(chip
)->remap_addr
+
882 VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
884 if (azx_dev
->insufficient
) {
885 /* Link position never gather than FIFO size */
886 if (link_pos
<= fifo_size
)
889 azx_dev
->insufficient
= 0;
892 if (link_pos
<= fifo_size
)
893 mini_pos
= azx_dev
->core
.bufsize
+ link_pos
- fifo_size
;
895 mini_pos
= link_pos
- fifo_size
;
897 /* Find nearest previous boudary */
898 mod_mini_pos
= mini_pos
% azx_dev
->core
.period_bytes
;
899 mod_link_pos
= link_pos
% azx_dev
->core
.period_bytes
;
900 if (mod_link_pos
>= fifo_size
)
901 bound_pos
= link_pos
- mod_link_pos
;
902 else if (mod_dma_pos
>= mod_mini_pos
)
903 bound_pos
= mini_pos
- mod_mini_pos
;
905 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->core
.period_bytes
;
906 if (bound_pos
>= azx_dev
->core
.bufsize
)
910 /* Calculate real DMA position we want */
911 return bound_pos
+ mod_dma_pos
;
914 static unsigned int azx_skl_get_dpib_pos(struct azx
*chip
,
915 struct azx_dev
*azx_dev
)
917 return _snd_hdac_chip_readl(azx_bus(chip
),
918 AZX_REG_VS_SDXDPIB_XBASE
+
919 (AZX_REG_VS_SDXDPIB_XINTERVAL
*
920 azx_dev
->core
.index
));
923 /* get the current DMA position with correction on SKL+ chips */
924 static unsigned int azx_get_pos_skl(struct azx
*chip
, struct azx_dev
*azx_dev
)
926 /* DPIB register gives a more accurate position for playback */
927 if (azx_dev
->core
.substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
928 return azx_skl_get_dpib_pos(chip
, azx_dev
);
930 /* For capture, we need to read posbuf, but it requires a delay
931 * for the possible boundary overlap; the read of DPIB fetches the
935 azx_skl_get_dpib_pos(chip
, azx_dev
);
936 return azx_get_pos_posbuf(chip
, azx_dev
);
940 static DEFINE_MUTEX(card_list_lock
);
941 static LIST_HEAD(card_list
);
943 static void azx_add_card_list(struct azx
*chip
)
945 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
946 mutex_lock(&card_list_lock
);
947 list_add(&hda
->list
, &card_list
);
948 mutex_unlock(&card_list_lock
);
951 static void azx_del_card_list(struct azx
*chip
)
953 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
954 mutex_lock(&card_list_lock
);
955 list_del_init(&hda
->list
);
956 mutex_unlock(&card_list_lock
);
959 /* trigger power-save check at writing parameter */
960 static int param_set_xint(const char *val
, const struct kernel_param
*kp
)
962 struct hda_intel
*hda
;
964 int prev
= power_save
;
965 int ret
= param_set_int(val
, kp
);
967 if (ret
|| prev
== power_save
)
970 mutex_lock(&card_list_lock
);
971 list_for_each_entry(hda
, &card_list
, list
) {
973 if (!hda
->probe_continued
|| chip
->disabled
)
975 snd_hda_set_power_save(&chip
->bus
, power_save
* 1000);
977 mutex_unlock(&card_list_lock
);
981 #define azx_add_card_list(chip) /* NOP */
982 #define azx_del_card_list(chip) /* NOP */
983 #endif /* CONFIG_PM */
985 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
989 static int azx_suspend(struct device
*dev
)
991 struct snd_card
*card
= dev_get_drvdata(dev
);
993 struct hda_intel
*hda
;
994 struct hdac_bus
*bus
;
999 chip
= card
->private_data
;
1000 hda
= container_of(chip
, struct hda_intel
, chip
);
1001 if (chip
->disabled
|| hda
->init_failed
|| !chip
->running
)
1004 bus
= azx_bus(chip
);
1005 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1006 azx_clear_irq_pending(chip
);
1007 azx_stop_chip(chip
);
1008 azx_enter_link_reset(chip
);
1009 if (bus
->irq
>= 0) {
1010 free_irq(bus
->irq
, chip
);
1015 pci_disable_msi(chip
->pci
);
1016 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
1017 && hda
->need_i915_power
)
1018 snd_hdac_display_power(bus
, false);
1020 trace_azx_suspend(chip
);
1024 static int azx_resume(struct device
*dev
)
1026 struct pci_dev
*pci
= to_pci_dev(dev
);
1027 struct snd_card
*card
= dev_get_drvdata(dev
);
1029 struct hda_intel
*hda
;
1030 struct hdac_bus
*bus
;
1035 chip
= card
->private_data
;
1036 hda
= container_of(chip
, struct hda_intel
, chip
);
1037 bus
= azx_bus(chip
);
1038 if (chip
->disabled
|| hda
->init_failed
|| !chip
->running
)
1041 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
1042 snd_hdac_display_power(bus
, true);
1043 if (hda
->need_i915_power
)
1044 snd_hdac_i915_set_bclk(bus
);
1048 if (pci_enable_msi(pci
) < 0)
1050 if (azx_acquire_irq(chip
, 1) < 0)
1054 hda_intel_init_chip(chip
, true);
1056 /* power down again for link-controlled chips */
1057 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) &&
1058 !hda
->need_i915_power
)
1059 snd_hdac_display_power(bus
, false);
1061 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1063 trace_azx_resume(chip
);
1066 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1068 #ifdef CONFIG_PM_SLEEP
1069 /* put codec down to D3 at hibernation for Intel SKL+;
1070 * otherwise BIOS may still access the codec and screw up the driver
1072 static int azx_freeze_noirq(struct device
*dev
)
1074 struct snd_card
*card
= dev_get_drvdata(dev
);
1075 struct azx
*chip
= card
->private_data
;
1076 struct pci_dev
*pci
= to_pci_dev(dev
);
1078 if (chip
->driver_type
== AZX_DRIVER_SKL
)
1079 pci_set_power_state(pci
, PCI_D3hot
);
1084 static int azx_thaw_noirq(struct device
*dev
)
1086 struct snd_card
*card
= dev_get_drvdata(dev
);
1087 struct azx
*chip
= card
->private_data
;
1088 struct pci_dev
*pci
= to_pci_dev(dev
);
1090 if (chip
->driver_type
== AZX_DRIVER_SKL
)
1091 pci_set_power_state(pci
, PCI_D0
);
1095 #endif /* CONFIG_PM_SLEEP */
1098 static int azx_runtime_suspend(struct device
*dev
)
1100 struct snd_card
*card
= dev_get_drvdata(dev
);
1102 struct hda_intel
*hda
;
1107 chip
= card
->private_data
;
1108 hda
= container_of(chip
, struct hda_intel
, chip
);
1109 if (chip
->disabled
|| hda
->init_failed
)
1112 if (!azx_has_pm_runtime(chip
))
1115 /* enable controller wake up event */
1116 azx_writew(chip
, WAKEEN
, azx_readw(chip
, WAKEEN
) |
1119 azx_stop_chip(chip
);
1120 azx_enter_link_reset(chip
);
1121 azx_clear_irq_pending(chip
);
1122 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
1123 && hda
->need_i915_power
)
1124 snd_hdac_display_power(azx_bus(chip
), false);
1126 trace_azx_runtime_suspend(chip
);
1130 static int azx_runtime_resume(struct device
*dev
)
1132 struct snd_card
*card
= dev_get_drvdata(dev
);
1134 struct hda_intel
*hda
;
1135 struct hdac_bus
*bus
;
1136 struct hda_codec
*codec
;
1142 chip
= card
->private_data
;
1143 hda
= container_of(chip
, struct hda_intel
, chip
);
1144 bus
= azx_bus(chip
);
1145 if (chip
->disabled
|| hda
->init_failed
)
1148 if (!azx_has_pm_runtime(chip
))
1151 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
1152 snd_hdac_display_power(bus
, true);
1153 if (hda
->need_i915_power
)
1154 snd_hdac_i915_set_bclk(bus
);
1157 /* Read STATESTS before controller reset */
1158 status
= azx_readw(chip
, STATESTS
);
1161 hda_intel_init_chip(chip
, true);
1164 list_for_each_codec(codec
, &chip
->bus
)
1165 if (status
& (1 << codec
->addr
))
1166 schedule_delayed_work(&codec
->jackpoll_work
,
1167 codec
->jackpoll_interval
);
1170 /* disable controller Wake Up event*/
1171 azx_writew(chip
, WAKEEN
, azx_readw(chip
, WAKEEN
) &
1172 ~STATESTS_INT_MASK
);
1174 /* power down again for link-controlled chips */
1175 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) &&
1176 !hda
->need_i915_power
)
1177 snd_hdac_display_power(bus
, false);
1179 trace_azx_runtime_resume(chip
);
1183 static int azx_runtime_idle(struct device
*dev
)
1185 struct snd_card
*card
= dev_get_drvdata(dev
);
1187 struct hda_intel
*hda
;
1192 chip
= card
->private_data
;
1193 hda
= container_of(chip
, struct hda_intel
, chip
);
1194 if (chip
->disabled
|| hda
->init_failed
)
1197 if (!power_save_controller
|| !azx_has_pm_runtime(chip
) ||
1198 azx_bus(chip
)->codec_powered
|| !chip
->running
)
1204 static const struct dev_pm_ops azx_pm
= {
1205 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend
, azx_resume
)
1206 #ifdef CONFIG_PM_SLEEP
1207 .freeze_noirq
= azx_freeze_noirq
,
1208 .thaw_noirq
= azx_thaw_noirq
,
1210 SET_RUNTIME_PM_OPS(azx_runtime_suspend
, azx_runtime_resume
, azx_runtime_idle
)
1213 #define AZX_PM_OPS &azx_pm
1215 #define AZX_PM_OPS NULL
1216 #endif /* CONFIG_PM */
1219 static int azx_probe_continue(struct azx
*chip
);
1221 #ifdef SUPPORT_VGA_SWITCHEROO
1222 static struct pci_dev
*get_bound_vga(struct pci_dev
*pci
);
1224 static void azx_vs_set_state(struct pci_dev
*pci
,
1225 enum vga_switcheroo_state state
)
1227 struct snd_card
*card
= pci_get_drvdata(pci
);
1228 struct azx
*chip
= card
->private_data
;
1229 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1232 wait_for_completion(&hda
->probe_wait
);
1233 if (hda
->init_failed
)
1236 disabled
= (state
== VGA_SWITCHEROO_OFF
);
1237 if (chip
->disabled
== disabled
)
1240 if (!hda
->probe_continued
) {
1241 chip
->disabled
= disabled
;
1243 dev_info(chip
->card
->dev
,
1244 "Start delayed initialization\n");
1245 if (azx_probe_continue(chip
) < 0) {
1246 dev_err(chip
->card
->dev
, "initialization error\n");
1247 hda
->init_failed
= true;
1251 dev_info(chip
->card
->dev
, "%s via vga_switcheroo\n",
1252 disabled
? "Disabling" : "Enabling");
1254 pm_runtime_put_sync_suspend(card
->dev
);
1255 azx_suspend(card
->dev
);
1256 /* when we get suspended by vga_switcheroo we end up in D3cold,
1257 * however we have no ACPI handle, so pci/acpi can't put us there,
1258 * put ourselves there */
1259 pci
->current_state
= PCI_D3cold
;
1260 chip
->disabled
= true;
1261 if (snd_hda_lock_devices(&chip
->bus
))
1262 dev_warn(chip
->card
->dev
,
1263 "Cannot lock devices!\n");
1265 snd_hda_unlock_devices(&chip
->bus
);
1266 pm_runtime_get_noresume(card
->dev
);
1267 chip
->disabled
= false;
1268 azx_resume(card
->dev
);
1273 static bool azx_vs_can_switch(struct pci_dev
*pci
)
1275 struct snd_card
*card
= pci_get_drvdata(pci
);
1276 struct azx
*chip
= card
->private_data
;
1277 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1279 wait_for_completion(&hda
->probe_wait
);
1280 if (hda
->init_failed
)
1282 if (chip
->disabled
|| !hda
->probe_continued
)
1284 if (snd_hda_lock_devices(&chip
->bus
))
1286 snd_hda_unlock_devices(&chip
->bus
);
1290 static void init_vga_switcheroo(struct azx
*chip
)
1292 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1293 struct pci_dev
*p
= get_bound_vga(chip
->pci
);
1295 dev_info(chip
->card
->dev
,
1296 "Handle vga_switcheroo audio client\n");
1297 hda
->use_vga_switcheroo
= 1;
1302 static const struct vga_switcheroo_client_ops azx_vs_ops
= {
1303 .set_gpu_state
= azx_vs_set_state
,
1304 .can_switch
= azx_vs_can_switch
,
1307 static int register_vga_switcheroo(struct azx
*chip
)
1309 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1312 if (!hda
->use_vga_switcheroo
)
1314 /* FIXME: currently only handling DIS controller
1315 * is there any machine with two switchable HDMI audio controllers?
1317 err
= vga_switcheroo_register_audio_client(chip
->pci
, &azx_vs_ops
,
1318 VGA_SWITCHEROO_DIS
);
1321 hda
->vga_switcheroo_registered
= 1;
1323 /* register as an optimus hdmi audio power domain */
1324 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip
->card
->dev
,
1325 &hda
->hdmi_pm_domain
);
1329 #define init_vga_switcheroo(chip) /* NOP */
1330 #define register_vga_switcheroo(chip) 0
1331 #define check_hdmi_disabled(pci) false
1332 #endif /* SUPPORT_VGA_SWITCHER */
1337 static int azx_free(struct azx
*chip
)
1339 struct pci_dev
*pci
= chip
->pci
;
1340 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
1341 struct hdac_bus
*bus
= azx_bus(chip
);
1343 if (azx_has_pm_runtime(chip
) && chip
->running
)
1344 pm_runtime_get_noresume(&pci
->dev
);
1346 azx_del_card_list(chip
);
1348 hda
->init_failed
= 1; /* to be sure */
1349 complete_all(&hda
->probe_wait
);
1351 if (use_vga_switcheroo(hda
)) {
1352 if (chip
->disabled
&& hda
->probe_continued
)
1353 snd_hda_unlock_devices(&chip
->bus
);
1354 if (hda
->vga_switcheroo_registered
) {
1355 vga_switcheroo_unregister_client(chip
->pci
);
1356 vga_switcheroo_fini_domain_pm_ops(chip
->card
->dev
);
1360 if (bus
->chip_init
) {
1361 azx_clear_irq_pending(chip
);
1362 azx_stop_all_streams(chip
);
1363 azx_stop_chip(chip
);
1367 free_irq(bus
->irq
, (void*)chip
);
1369 pci_disable_msi(chip
->pci
);
1370 iounmap(bus
->remap_addr
);
1372 azx_free_stream_pages(chip
);
1373 azx_free_streams(chip
);
1374 snd_hdac_bus_exit(bus
);
1376 if (chip
->region_requested
)
1377 pci_release_regions(chip
->pci
);
1379 pci_disable_device(chip
->pci
);
1380 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1381 release_firmware(chip
->fw
);
1384 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
1385 if (hda
->need_i915_power
)
1386 snd_hdac_display_power(bus
, false);
1388 if (chip
->driver_caps
& AZX_DCAPS_I915_COMPONENT
)
1389 snd_hdac_i915_exit(bus
);
1395 static int azx_dev_disconnect(struct snd_device
*device
)
1397 struct azx
*chip
= device
->device_data
;
1399 chip
->bus
.shutdown
= 1;
1403 static int azx_dev_free(struct snd_device
*device
)
1405 return azx_free(device
->device_data
);
1408 #ifdef SUPPORT_VGA_SWITCHEROO
1410 * Check of disabled HDMI controller by vga_switcheroo
1412 static struct pci_dev
*get_bound_vga(struct pci_dev
*pci
)
1416 /* check only discrete GPU */
1417 switch (pci
->vendor
) {
1418 case PCI_VENDOR_ID_ATI
:
1419 case PCI_VENDOR_ID_AMD
:
1420 case PCI_VENDOR_ID_NVIDIA
:
1421 if (pci
->devfn
== 1) {
1422 p
= pci_get_domain_bus_and_slot(pci_domain_nr(pci
->bus
),
1423 pci
->bus
->number
, 0);
1425 if ((p
->class >> 8) == PCI_CLASS_DISPLAY_VGA
)
1435 static bool check_hdmi_disabled(struct pci_dev
*pci
)
1437 bool vga_inactive
= false;
1438 struct pci_dev
*p
= get_bound_vga(pci
);
1441 if (vga_switcheroo_get_client_state(p
) == VGA_SWITCHEROO_OFF
)
1442 vga_inactive
= true;
1445 return vga_inactive
;
1447 #endif /* SUPPORT_VGA_SWITCHEROO */
1450 * white/black-listing for position_fix
1452 static struct snd_pci_quirk position_fix_list
[] = {
1453 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
1454 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
1455 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB
),
1456 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
1457 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB
),
1458 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB
),
1459 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB
),
1460 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB
),
1461 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB
),
1462 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB
),
1463 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB
),
1464 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB
),
1465 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB
),
1466 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB
),
1470 static int check_position_fix(struct azx
*chip
, int fix
)
1472 const struct snd_pci_quirk
*q
;
1477 case POS_FIX_POSBUF
:
1478 case POS_FIX_VIACOMBO
:
1484 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
1486 dev_info(chip
->card
->dev
,
1487 "position_fix set to %d for device %04x:%04x\n",
1488 q
->value
, q
->subvendor
, q
->subdevice
);
1492 /* Check VIA/ATI HD Audio Controller exist */
1493 if (chip
->driver_type
== AZX_DRIVER_VIA
) {
1494 dev_dbg(chip
->card
->dev
, "Using VIACOMBO position fix\n");
1495 return POS_FIX_VIACOMBO
;
1497 if (chip
->driver_caps
& AZX_DCAPS_POSFIX_LPIB
) {
1498 dev_dbg(chip
->card
->dev
, "Using LPIB position fix\n");
1499 return POS_FIX_LPIB
;
1501 if (chip
->driver_type
== AZX_DRIVER_SKL
) {
1502 dev_dbg(chip
->card
->dev
, "Using SKL position fix\n");
1505 return POS_FIX_AUTO
;
1508 static void assign_position_fix(struct azx
*chip
, int fix
)
1510 static azx_get_pos_callback_t callbacks
[] = {
1511 [POS_FIX_AUTO
] = NULL
,
1512 [POS_FIX_LPIB
] = azx_get_pos_lpib
,
1513 [POS_FIX_POSBUF
] = azx_get_pos_posbuf
,
1514 [POS_FIX_VIACOMBO
] = azx_via_get_position
,
1515 [POS_FIX_COMBO
] = azx_get_pos_lpib
,
1516 [POS_FIX_SKL
] = azx_get_pos_skl
,
1519 chip
->get_position
[0] = chip
->get_position
[1] = callbacks
[fix
];
1521 /* combo mode uses LPIB only for playback */
1522 if (fix
== POS_FIX_COMBO
)
1523 chip
->get_position
[1] = NULL
;
1525 if ((fix
== POS_FIX_POSBUF
|| fix
== POS_FIX_SKL
) &&
1526 (chip
->driver_caps
& AZX_DCAPS_COUNT_LPIB_DELAY
)) {
1527 chip
->get_delay
[0] = chip
->get_delay
[1] =
1528 azx_get_delay_from_lpib
;
1534 * black-lists for probe_mask
1536 static struct snd_pci_quirk probe_mask_list
[] = {
1537 /* Thinkpad often breaks the controller communication when accessing
1538 * to the non-working (or non-existing) modem codec slot.
1540 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1541 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1542 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1544 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1545 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1546 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1547 /* forced codec slots */
1548 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1549 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1550 /* WinFast VP200 H (Teradici) user reported broken communication */
1551 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1555 #define AZX_FORCE_CODEC_MASK 0x100
1557 static void check_probe_mask(struct azx
*chip
, int dev
)
1559 const struct snd_pci_quirk
*q
;
1561 chip
->codec_probe_mask
= probe_mask
[dev
];
1562 if (chip
->codec_probe_mask
== -1) {
1563 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
1565 dev_info(chip
->card
->dev
,
1566 "probe_mask set to 0x%x for device %04x:%04x\n",
1567 q
->value
, q
->subvendor
, q
->subdevice
);
1568 chip
->codec_probe_mask
= q
->value
;
1572 /* check forced option */
1573 if (chip
->codec_probe_mask
!= -1 &&
1574 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
1575 azx_bus(chip
)->codec_mask
= chip
->codec_probe_mask
& 0xff;
1576 dev_info(chip
->card
->dev
, "codec_mask forced to 0x%x\n",
1577 (int)azx_bus(chip
)->codec_mask
);
1582 * white/black-list for enable_msi
1584 static struct snd_pci_quirk msi_black_list
[] = {
1585 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1586 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1587 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1588 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1589 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1590 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1591 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1592 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1593 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1594 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1598 static void check_msi(struct azx
*chip
)
1600 const struct snd_pci_quirk
*q
;
1602 if (enable_msi
>= 0) {
1603 chip
->msi
= !!enable_msi
;
1606 chip
->msi
= 1; /* enable MSI as default */
1607 q
= snd_pci_quirk_lookup(chip
->pci
, msi_black_list
);
1609 dev_info(chip
->card
->dev
,
1610 "msi for device %04x:%04x set to %d\n",
1611 q
->subvendor
, q
->subdevice
, q
->value
);
1612 chip
->msi
= q
->value
;
1616 /* NVidia chipsets seem to cause troubles with MSI */
1617 if (chip
->driver_caps
& AZX_DCAPS_NO_MSI
) {
1618 dev_info(chip
->card
->dev
, "Disabling MSI\n");
1623 /* check the snoop mode availability */
1624 static void azx_check_snoop_available(struct azx
*chip
)
1626 int snoop
= hda_snoop
;
1629 dev_info(chip
->card
->dev
, "Force to %s mode by module option\n",
1630 snoop
? "snoop" : "non-snoop");
1631 chip
->snoop
= snoop
;
1636 if (azx_get_snoop_type(chip
) == AZX_SNOOP_TYPE_NONE
&&
1637 chip
->driver_type
== AZX_DRIVER_VIA
) {
1638 /* force to non-snoop mode for a new VIA controller
1642 pci_read_config_byte(chip
->pci
, 0x42, &val
);
1643 if (!(val
& 0x80) && chip
->pci
->revision
== 0x30)
1647 if (chip
->driver_caps
& AZX_DCAPS_SNOOP_OFF
)
1650 chip
->snoop
= snoop
;
1652 dev_info(chip
->card
->dev
, "Force to non-snoop mode\n");
1655 static void azx_probe_work(struct work_struct
*work
)
1657 struct hda_intel
*hda
= container_of(work
, struct hda_intel
, probe_work
);
1658 azx_probe_continue(&hda
->chip
);
1661 static int default_bdl_pos_adj(struct azx
*chip
)
1663 /* some exceptions: Atoms seem problematic with value 1 */
1664 if (chip
->pci
->vendor
== PCI_VENDOR_ID_INTEL
) {
1665 switch (chip
->pci
->device
) {
1666 case 0x0f04: /* Baytrail */
1667 case 0x2284: /* Braswell */
1672 switch (chip
->driver_type
) {
1673 case AZX_DRIVER_ICH
:
1674 case AZX_DRIVER_PCH
:
1684 static const struct hdac_io_ops pci_hda_io_ops
;
1685 static const struct hda_controller_ops pci_hda_ops
;
1687 static int azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1688 int dev
, unsigned int driver_caps
,
1691 static struct snd_device_ops ops
= {
1692 .dev_disconnect
= azx_dev_disconnect
,
1693 .dev_free
= azx_dev_free
,
1695 struct hda_intel
*hda
;
1701 err
= pci_enable_device(pci
);
1705 hda
= kzalloc(sizeof(*hda
), GFP_KERNEL
);
1707 pci_disable_device(pci
);
1712 mutex_init(&chip
->open_mutex
);
1715 chip
->ops
= &pci_hda_ops
;
1716 chip
->driver_caps
= driver_caps
;
1717 chip
->driver_type
= driver_caps
& 0xff;
1719 chip
->dev_index
= dev
;
1720 chip
->jackpoll_ms
= jackpoll_ms
;
1721 INIT_LIST_HEAD(&chip
->pcm_list
);
1722 INIT_WORK(&hda
->irq_pending_work
, azx_irq_pending_work
);
1723 INIT_LIST_HEAD(&hda
->list
);
1724 init_vga_switcheroo(chip
);
1725 init_completion(&hda
->probe_wait
);
1727 assign_position_fix(chip
, check_position_fix(chip
, position_fix
[dev
]));
1729 check_probe_mask(chip
, dev
);
1731 if (single_cmd
< 0) /* allow fallback to single_cmd at errors */
1732 chip
->fallback_to_single_cmd
= 1;
1733 else /* explicitly set to single_cmd or not */
1734 chip
->single_cmd
= single_cmd
;
1736 azx_check_snoop_available(chip
);
1738 if (bdl_pos_adj
[dev
] < 0)
1739 chip
->bdl_pos_adj
= default_bdl_pos_adj(chip
);
1741 chip
->bdl_pos_adj
= bdl_pos_adj
[dev
];
1743 err
= azx_bus_init(chip
, model
[dev
], &pci_hda_io_ops
);
1746 pci_disable_device(pci
);
1750 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
) {
1751 dev_dbg(chip
->card
->dev
, "Enable delay in RIRB handling\n");
1752 chip
->bus
.needs_damn_long_delay
= 1;
1755 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
1757 dev_err(card
->dev
, "Error creating device [card]!\n");
1762 /* continue probing in work context as may trigger request module */
1763 INIT_WORK(&hda
->probe_work
, azx_probe_work
);
1770 static int azx_first_init(struct azx
*chip
)
1772 int dev
= chip
->dev_index
;
1773 struct pci_dev
*pci
= chip
->pci
;
1774 struct snd_card
*card
= chip
->card
;
1775 struct hdac_bus
*bus
= azx_bus(chip
);
1777 unsigned short gcap
;
1778 unsigned int dma_bits
= 64;
1780 #if BITS_PER_LONG != 64
1781 /* Fix up base address on ULI M5461 */
1782 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1784 pci_read_config_word(pci
, 0x40, &tmp3
);
1785 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1786 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1790 err
= pci_request_regions(pci
, "ICH HD audio");
1793 chip
->region_requested
= 1;
1795 bus
->addr
= pci_resource_start(pci
, 0);
1796 bus
->remap_addr
= pci_ioremap_bar(pci
, 0);
1797 if (bus
->remap_addr
== NULL
) {
1798 dev_err(card
->dev
, "ioremap error\n");
1802 if (chip
->driver_type
== AZX_DRIVER_SKL
)
1803 snd_hdac_bus_parse_capabilities(bus
);
1806 * Some Intel CPUs has always running timer (ART) feature and
1807 * controller may have Global time sync reporting capability, so
1808 * check both of these before declaring synchronized time reporting
1809 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1811 chip
->gts_present
= false;
1814 if (bus
->ppcap
&& boot_cpu_has(X86_FEATURE_ART
))
1815 chip
->gts_present
= true;
1819 if (chip
->driver_caps
& AZX_DCAPS_NO_MSI64
) {
1820 dev_dbg(card
->dev
, "Disabling 64bit MSI\n");
1821 pci
->no_64bit_msi
= true;
1823 if (pci_enable_msi(pci
) < 0)
1827 if (azx_acquire_irq(chip
, 0) < 0)
1830 pci_set_master(pci
);
1831 synchronize_irq(bus
->irq
);
1833 gcap
= azx_readw(chip
, GCAP
);
1834 dev_dbg(card
->dev
, "chipset global capabilities = 0x%x\n", gcap
);
1836 /* AMD devices support 40 or 48bit DMA, take the safe one */
1837 if (chip
->pci
->vendor
== PCI_VENDOR_ID_AMD
)
1840 /* disable SB600 64bit support for safety */
1841 if (chip
->pci
->vendor
== PCI_VENDOR_ID_ATI
) {
1842 struct pci_dev
*p_smbus
;
1844 p_smbus
= pci_get_device(PCI_VENDOR_ID_ATI
,
1845 PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
1848 if (p_smbus
->revision
< 0x30)
1849 gcap
&= ~AZX_GCAP_64OK
;
1850 pci_dev_put(p_smbus
);
1854 /* NVidia hardware normally only supports up to 40 bits of DMA */
1855 if (chip
->pci
->vendor
== PCI_VENDOR_ID_NVIDIA
)
1858 /* disable 64bit DMA address on some devices */
1859 if (chip
->driver_caps
& AZX_DCAPS_NO_64BIT
) {
1860 dev_dbg(card
->dev
, "Disabling 64bit DMA\n");
1861 gcap
&= ~AZX_GCAP_64OK
;
1864 /* disable buffer size rounding to 128-byte multiples if supported */
1865 if (align_buffer_size
>= 0)
1866 chip
->align_buffer_size
= !!align_buffer_size
;
1868 if (chip
->driver_caps
& AZX_DCAPS_NO_ALIGN_BUFSIZE
)
1869 chip
->align_buffer_size
= 0;
1871 chip
->align_buffer_size
= 1;
1874 /* allow 64bit DMA address if supported by H/W */
1875 if (!(gcap
& AZX_GCAP_64OK
))
1877 if (!dma_set_mask(&pci
->dev
, DMA_BIT_MASK(dma_bits
))) {
1878 dma_set_coherent_mask(&pci
->dev
, DMA_BIT_MASK(dma_bits
));
1880 dma_set_mask(&pci
->dev
, DMA_BIT_MASK(32));
1881 dma_set_coherent_mask(&pci
->dev
, DMA_BIT_MASK(32));
1884 /* read number of streams from GCAP register instead of using
1887 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
1888 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
1889 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
1890 /* gcap didn't give any info, switching to old method */
1892 switch (chip
->driver_type
) {
1893 case AZX_DRIVER_ULI
:
1894 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1895 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1897 case AZX_DRIVER_ATIHDMI
:
1898 case AZX_DRIVER_ATIHDMI_NS
:
1899 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
1900 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
1902 case AZX_DRIVER_GENERIC
:
1904 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1905 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1909 chip
->capture_index_offset
= 0;
1910 chip
->playback_index_offset
= chip
->capture_streams
;
1911 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1913 /* sanity check for the SDxCTL.STRM field overflow */
1914 if (chip
->num_streams
> 15 &&
1915 (chip
->driver_caps
& AZX_DCAPS_SEPARATE_STREAM_TAG
) == 0) {
1916 dev_warn(chip
->card
->dev
, "number of I/O streams is %d, "
1917 "forcing separate stream tags", chip
->num_streams
);
1918 chip
->driver_caps
|= AZX_DCAPS_SEPARATE_STREAM_TAG
;
1921 /* initialize streams */
1922 err
= azx_init_streams(chip
);
1926 err
= azx_alloc_stream_pages(chip
);
1930 /* initialize chip */
1933 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
1934 snd_hdac_i915_set_bclk(bus
);
1936 hda_intel_init_chip(chip
, (probe_only
[dev
] & 2) == 0);
1938 /* codec detection */
1939 if (!azx_bus(chip
)->codec_mask
) {
1940 dev_err(card
->dev
, "no codecs found!\n");
1944 strcpy(card
->driver
, "HDA-Intel");
1945 strlcpy(card
->shortname
, driver_short_names
[chip
->driver_type
],
1946 sizeof(card
->shortname
));
1947 snprintf(card
->longname
, sizeof(card
->longname
),
1948 "%s at 0x%lx irq %i",
1949 card
->shortname
, bus
->addr
, bus
->irq
);
1954 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1955 /* callback from request_firmware_nowait() */
1956 static void azx_firmware_cb(const struct firmware
*fw
, void *context
)
1958 struct snd_card
*card
= context
;
1959 struct azx
*chip
= card
->private_data
;
1960 struct pci_dev
*pci
= chip
->pci
;
1963 dev_err(card
->dev
, "Cannot load firmware, aborting\n");
1968 if (!chip
->disabled
) {
1969 /* continue probing */
1970 if (azx_probe_continue(chip
))
1976 snd_card_free(card
);
1977 pci_set_drvdata(pci
, NULL
);
1982 * HDA controller ops.
1985 /* PCI register access. */
1986 static void pci_azx_writel(u32 value
, u32 __iomem
*addr
)
1988 writel(value
, addr
);
1991 static u32
pci_azx_readl(u32 __iomem
*addr
)
1996 static void pci_azx_writew(u16 value
, u16 __iomem
*addr
)
1998 writew(value
, addr
);
2001 static u16
pci_azx_readw(u16 __iomem
*addr
)
2006 static void pci_azx_writeb(u8 value
, u8 __iomem
*addr
)
2008 writeb(value
, addr
);
2011 static u8
pci_azx_readb(u8 __iomem
*addr
)
2016 static int disable_msi_reset_irq(struct azx
*chip
)
2018 struct hdac_bus
*bus
= azx_bus(chip
);
2021 free_irq(bus
->irq
, chip
);
2023 pci_disable_msi(chip
->pci
);
2025 err
= azx_acquire_irq(chip
, 1);
2032 /* DMA page allocation helpers. */
2033 static int dma_alloc_pages(struct hdac_bus
*bus
,
2036 struct snd_dma_buffer
*buf
)
2038 struct azx
*chip
= bus_to_azx(bus
);
2041 err
= snd_dma_alloc_pages(type
,
2046 mark_pages_wc(chip
, buf
, true);
2050 static void dma_free_pages(struct hdac_bus
*bus
, struct snd_dma_buffer
*buf
)
2052 struct azx
*chip
= bus_to_azx(bus
);
2054 mark_pages_wc(chip
, buf
, false);
2055 snd_dma_free_pages(buf
);
2058 static int substream_alloc_pages(struct azx
*chip
,
2059 struct snd_pcm_substream
*substream
,
2062 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
2065 mark_runtime_wc(chip
, azx_dev
, substream
, false);
2066 ret
= snd_pcm_lib_malloc_pages(substream
, size
);
2069 mark_runtime_wc(chip
, azx_dev
, substream
, true);
2073 static int substream_free_pages(struct azx
*chip
,
2074 struct snd_pcm_substream
*substream
)
2076 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
2077 mark_runtime_wc(chip
, azx_dev
, substream
, false);
2078 return snd_pcm_lib_free_pages(substream
);
2081 static void pcm_mmap_prepare(struct snd_pcm_substream
*substream
,
2082 struct vm_area_struct
*area
)
2085 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
2086 struct azx
*chip
= apcm
->chip
;
2087 if (!azx_snoop(chip
) && chip
->driver_type
!= AZX_DRIVER_CMEDIA
)
2088 area
->vm_page_prot
= pgprot_writecombine(area
->vm_page_prot
);
2092 static const struct hdac_io_ops pci_hda_io_ops
= {
2093 .reg_writel
= pci_azx_writel
,
2094 .reg_readl
= pci_azx_readl
,
2095 .reg_writew
= pci_azx_writew
,
2096 .reg_readw
= pci_azx_readw
,
2097 .reg_writeb
= pci_azx_writeb
,
2098 .reg_readb
= pci_azx_readb
,
2099 .dma_alloc_pages
= dma_alloc_pages
,
2100 .dma_free_pages
= dma_free_pages
,
2103 static const struct hda_controller_ops pci_hda_ops
= {
2104 .disable_msi_reset_irq
= disable_msi_reset_irq
,
2105 .substream_alloc_pages
= substream_alloc_pages
,
2106 .substream_free_pages
= substream_free_pages
,
2107 .pcm_mmap_prepare
= pcm_mmap_prepare
,
2108 .position_check
= azx_position_check
,
2109 .link_power
= azx_intel_link_power
,
2112 static int azx_probe(struct pci_dev
*pci
,
2113 const struct pci_device_id
*pci_id
)
2116 struct snd_card
*card
;
2117 struct hda_intel
*hda
;
2119 bool schedule_probe
;
2122 if (dev
>= SNDRV_CARDS
)
2129 err
= snd_card_new(&pci
->dev
, index
[dev
], id
[dev
], THIS_MODULE
,
2132 dev_err(&pci
->dev
, "Error creating card!\n");
2136 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2139 card
->private_data
= chip
;
2140 hda
= container_of(chip
, struct hda_intel
, chip
);
2142 pci_set_drvdata(pci
, card
);
2144 err
= register_vga_switcheroo(chip
);
2146 dev_err(card
->dev
, "Error registering vga_switcheroo client\n");
2150 if (check_hdmi_disabled(pci
)) {
2151 dev_info(card
->dev
, "VGA controller is disabled\n");
2152 dev_info(card
->dev
, "Delaying initialization\n");
2153 chip
->disabled
= true;
2156 schedule_probe
= !chip
->disabled
;
2158 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2159 if (patch
[dev
] && *patch
[dev
]) {
2160 dev_info(card
->dev
, "Applying patch firmware '%s'\n",
2162 err
= request_firmware_nowait(THIS_MODULE
, true, patch
[dev
],
2163 &pci
->dev
, GFP_KERNEL
, card
,
2167 schedule_probe
= false; /* continued in azx_firmware_cb() */
2169 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2171 #ifndef CONFIG_SND_HDA_I915
2172 if (CONTROLLER_IN_GPU(pci
))
2173 dev_err(card
->dev
, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2177 schedule_work(&hda
->probe_work
);
2181 complete_all(&hda
->probe_wait
);
2185 snd_card_free(card
);
2189 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2190 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] = {
2191 [AZX_DRIVER_NVIDIA
] = 8,
2192 [AZX_DRIVER_TERA
] = 1,
2195 static int azx_probe_continue(struct azx
*chip
)
2197 struct hda_intel
*hda
= container_of(chip
, struct hda_intel
, chip
);
2198 struct hdac_bus
*bus
= azx_bus(chip
);
2199 struct pci_dev
*pci
= chip
->pci
;
2200 int dev
= chip
->dev_index
;
2203 hda
->probe_continued
= 1;
2205 /* bind with i915 if needed */
2206 if (chip
->driver_caps
& AZX_DCAPS_I915_COMPONENT
) {
2207 err
= snd_hdac_i915_init(bus
);
2209 /* if the controller is bound only with HDMI/DP
2210 * (for HSW and BDW), we need to abort the probe;
2211 * for other chips, still continue probing as other
2212 * codecs can be on the same link.
2214 if (CONTROLLER_IN_GPU(pci
)) {
2215 dev_err(chip
->card
->dev
,
2216 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2219 /* don't bother any longer */
2220 chip
->driver_caps
&=
2221 ~(AZX_DCAPS_I915_COMPONENT
| AZX_DCAPS_I915_POWERWELL
);
2226 /* Request display power well for the HDA controller or codec. For
2227 * Haswell/Broadwell, both the display HDA controller and codec need
2228 * this power. For other platforms, like Baytrail/Braswell, only the
2229 * display codec needs the power and it can be released after probe.
2231 if (chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
) {
2232 /* HSW/BDW controllers need this power */
2233 if (CONTROLLER_IN_GPU(pci
))
2234 hda
->need_i915_power
= 1;
2236 err
= snd_hdac_display_power(bus
, true);
2238 dev_err(chip
->card
->dev
,
2239 "Cannot turn on display power on i915\n");
2240 goto i915_power_fail
;
2244 err
= azx_first_init(chip
);
2248 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2249 chip
->beep_mode
= beep_mode
[dev
];
2252 /* create codec instances */
2253 err
= azx_probe_codecs(chip
, azx_max_codecs
[chip
->driver_type
]);
2257 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2259 err
= snd_hda_load_patch(&chip
->bus
, chip
->fw
->size
,
2264 release_firmware(chip
->fw
); /* no longer needed */
2269 if ((probe_only
[dev
] & 1) == 0) {
2270 err
= azx_codec_configure(chip
);
2275 err
= snd_card_register(chip
->card
);
2280 azx_add_card_list(chip
);
2281 snd_hda_set_power_save(&chip
->bus
, power_save
* 1000);
2282 if (azx_has_pm_runtime(chip
) || hda
->use_vga_switcheroo
)
2283 pm_runtime_put_autosuspend(&pci
->dev
);
2286 if ((chip
->driver_caps
& AZX_DCAPS_I915_POWERWELL
)
2287 && !hda
->need_i915_power
)
2288 snd_hdac_display_power(bus
, false);
2292 hda
->init_failed
= 1;
2293 complete_all(&hda
->probe_wait
);
2297 static void azx_remove(struct pci_dev
*pci
)
2299 struct snd_card
*card
= pci_get_drvdata(pci
);
2301 struct hda_intel
*hda
;
2304 /* cancel the pending probing work */
2305 chip
= card
->private_data
;
2306 hda
= container_of(chip
, struct hda_intel
, chip
);
2307 /* FIXME: below is an ugly workaround.
2308 * Both device_release_driver() and driver_probe_device()
2309 * take *both* the device's and its parent's lock before
2310 * calling the remove() and probe() callbacks. The codec
2311 * probe takes the locks of both the codec itself and its
2312 * parent, i.e. the PCI controller dev. Meanwhile, when
2313 * the PCI controller is unbound, it takes its lock, too
2314 * ==> ouch, a deadlock!
2315 * As a workaround, we unlock temporarily here the controller
2316 * device during cancel_work_sync() call.
2318 device_unlock(&pci
->dev
);
2319 cancel_work_sync(&hda
->probe_work
);
2320 device_lock(&pci
->dev
);
2322 snd_card_free(card
);
2326 static void azx_shutdown(struct pci_dev
*pci
)
2328 struct snd_card
*card
= pci_get_drvdata(pci
);
2333 chip
= card
->private_data
;
2334 if (chip
&& chip
->running
)
2335 azx_stop_chip(chip
);
2339 static const struct pci_device_id azx_ids
[] = {
2341 { PCI_DEVICE(0x8086, 0x1c20),
2342 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2344 { PCI_DEVICE(0x8086, 0x1d20),
2345 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2347 { PCI_DEVICE(0x8086, 0x1e20),
2348 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2350 { PCI_DEVICE(0x8086, 0x8c20),
2351 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2353 { PCI_DEVICE(0x8086, 0x8ca0),
2354 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2356 { PCI_DEVICE(0x8086, 0x8d20),
2357 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2358 { PCI_DEVICE(0x8086, 0x8d21),
2359 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2361 { PCI_DEVICE(0x8086, 0xa1f0),
2362 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_SKYLAKE
},
2363 { PCI_DEVICE(0x8086, 0xa270),
2364 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_SKYLAKE
},
2366 { PCI_DEVICE(0x8086, 0x9c20),
2367 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2369 { PCI_DEVICE(0x8086, 0x9c21),
2370 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2371 /* Wildcat Point-LP */
2372 { PCI_DEVICE(0x8086, 0x9ca0),
2373 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_PCH
},
2375 { PCI_DEVICE(0x8086, 0xa170),
2376 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2377 /* Sunrise Point-LP */
2378 { PCI_DEVICE(0x8086, 0x9d70),
2379 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2381 { PCI_DEVICE(0x8086, 0xa171),
2382 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2384 { PCI_DEVICE(0x8086, 0x9d71),
2385 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2387 { PCI_DEVICE(0x8086, 0xa2f0),
2388 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2390 { PCI_DEVICE(0x8086, 0xa348),
2391 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2393 { PCI_DEVICE(0x8086, 0x9dc8),
2394 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_SKYLAKE
},
2395 /* Broxton-P(Apollolake) */
2396 { PCI_DEVICE(0x8086, 0x5a98),
2397 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_BROXTON
},
2399 { PCI_DEVICE(0x8086, 0x1a98),
2400 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_BROXTON
},
2402 { PCI_DEVICE(0x8086, 0x3198),
2403 .driver_data
= AZX_DRIVER_SKL
| AZX_DCAPS_INTEL_BROXTON
},
2405 { PCI_DEVICE(0x8086, 0x0a0c),
2406 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_HASWELL
},
2407 { PCI_DEVICE(0x8086, 0x0c0c),
2408 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_HASWELL
},
2409 { PCI_DEVICE(0x8086, 0x0d0c),
2410 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_HASWELL
},
2412 { PCI_DEVICE(0x8086, 0x160c),
2413 .driver_data
= AZX_DRIVER_HDMI
| AZX_DCAPS_INTEL_BROADWELL
},
2415 { PCI_DEVICE(0x8086, 0x3b56),
2416 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_INTEL_PCH_NOPM
},
2418 { PCI_DEVICE(0x8086, 0x811b),
2419 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_INTEL_PCH_BASE
},
2421 { PCI_DEVICE(0x8086, 0x080a),
2422 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_INTEL_PCH_BASE
},
2424 { PCI_DEVICE(0x8086, 0x0f04),
2425 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_BAYTRAIL
},
2427 { PCI_DEVICE(0x8086, 0x2284),
2428 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_INTEL_BRASWELL
},
2430 { PCI_DEVICE(0x8086, 0x2668),
2431 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2433 { PCI_DEVICE(0x8086, 0x27d8),
2434 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2436 { PCI_DEVICE(0x8086, 0x269a),
2437 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2439 { PCI_DEVICE(0x8086, 0x284b),
2440 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2442 { PCI_DEVICE(0x8086, 0x293e),
2443 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2445 { PCI_DEVICE(0x8086, 0x293f),
2446 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2448 { PCI_DEVICE(0x8086, 0x3a3e),
2449 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2451 { PCI_DEVICE(0x8086, 0x3a6e),
2452 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_INTEL_ICH
},
2454 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
),
2455 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2456 .class_mask
= 0xffffff,
2457 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_NO_ALIGN_BUFSIZE
},
2458 /* ATI SB 450/600/700/800/900 */
2459 { PCI_DEVICE(0x1002, 0x437b),
2460 .driver_data
= AZX_DRIVER_ATI
| AZX_DCAPS_PRESET_ATI_SB
},
2461 { PCI_DEVICE(0x1002, 0x4383),
2462 .driver_data
= AZX_DRIVER_ATI
| AZX_DCAPS_PRESET_ATI_SB
},
2464 { PCI_DEVICE(0x1022, 0x780d),
2465 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_SB
},
2467 { PCI_DEVICE(0x1002, 0x0002),
2468 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2469 { PCI_DEVICE(0x1002, 0x1308),
2470 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2471 { PCI_DEVICE(0x1002, 0x157a),
2472 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2473 { PCI_DEVICE(0x1002, 0x15b3),
2474 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2475 { PCI_DEVICE(0x1002, 0x793b),
2476 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2477 { PCI_DEVICE(0x1002, 0x7919),
2478 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2479 { PCI_DEVICE(0x1002, 0x960f),
2480 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2481 { PCI_DEVICE(0x1002, 0x970f),
2482 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2483 { PCI_DEVICE(0x1002, 0x9840),
2484 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2485 { PCI_DEVICE(0x1002, 0xaa00),
2486 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2487 { PCI_DEVICE(0x1002, 0xaa08),
2488 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2489 { PCI_DEVICE(0x1002, 0xaa10),
2490 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2491 { PCI_DEVICE(0x1002, 0xaa18),
2492 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2493 { PCI_DEVICE(0x1002, 0xaa20),
2494 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2495 { PCI_DEVICE(0x1002, 0xaa28),
2496 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2497 { PCI_DEVICE(0x1002, 0xaa30),
2498 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2499 { PCI_DEVICE(0x1002, 0xaa38),
2500 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2501 { PCI_DEVICE(0x1002, 0xaa40),
2502 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2503 { PCI_DEVICE(0x1002, 0xaa48),
2504 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2505 { PCI_DEVICE(0x1002, 0xaa50),
2506 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2507 { PCI_DEVICE(0x1002, 0xaa58),
2508 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2509 { PCI_DEVICE(0x1002, 0xaa60),
2510 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2511 { PCI_DEVICE(0x1002, 0xaa68),
2512 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2513 { PCI_DEVICE(0x1002, 0xaa80),
2514 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2515 { PCI_DEVICE(0x1002, 0xaa88),
2516 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2517 { PCI_DEVICE(0x1002, 0xaa90),
2518 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2519 { PCI_DEVICE(0x1002, 0xaa98),
2520 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
2521 { PCI_DEVICE(0x1002, 0x9902),
2522 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2523 { PCI_DEVICE(0x1002, 0xaaa0),
2524 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2525 { PCI_DEVICE(0x1002, 0xaaa8),
2526 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2527 { PCI_DEVICE(0x1002, 0xaab0),
2528 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2529 { PCI_DEVICE(0x1002, 0xaac0),
2530 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2531 { PCI_DEVICE(0x1002, 0xaac8),
2532 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2533 { PCI_DEVICE(0x1002, 0xaad8),
2534 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2535 { PCI_DEVICE(0x1002, 0xaae8),
2536 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2537 { PCI_DEVICE(0x1002, 0xaae0),
2538 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2539 { PCI_DEVICE(0x1002, 0xaaf0),
2540 .driver_data
= AZX_DRIVER_ATIHDMI_NS
| AZX_DCAPS_PRESET_ATI_HDMI_NS
},
2541 /* VIA VT8251/VT8237A */
2542 { PCI_DEVICE(0x1106, 0x3288), .driver_data
= AZX_DRIVER_VIA
},
2543 /* VIA GFX VT7122/VX900 */
2544 { PCI_DEVICE(0x1106, 0x9170), .driver_data
= AZX_DRIVER_GENERIC
},
2545 /* VIA GFX VT6122/VX11 */
2546 { PCI_DEVICE(0x1106, 0x9140), .driver_data
= AZX_DRIVER_GENERIC
},
2548 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
2550 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
2552 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
),
2553 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2554 .class_mask
= 0xffffff,
2555 .driver_data
= AZX_DRIVER_NVIDIA
| AZX_DCAPS_PRESET_NVIDIA
},
2557 { PCI_DEVICE(0x6549, 0x1200),
2558 .driver_data
= AZX_DRIVER_TERA
| AZX_DCAPS_NO_64BIT
},
2559 { PCI_DEVICE(0x6549, 0x2200),
2560 .driver_data
= AZX_DRIVER_TERA
| AZX_DCAPS_NO_64BIT
},
2561 /* Creative X-Fi (CA0110-IBG) */
2563 { PCI_DEVICE(0x1102, 0x0010),
2564 .driver_data
= AZX_DRIVER_CTHDA
| AZX_DCAPS_PRESET_CTHDA
},
2565 { PCI_DEVICE(0x1102, 0x0012),
2566 .driver_data
= AZX_DRIVER_CTHDA
| AZX_DCAPS_PRESET_CTHDA
},
2567 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2568 /* the following entry conflicts with snd-ctxfi driver,
2569 * as ctxfi driver mutates from HD-audio to native mode with
2570 * a special command sequence.
2572 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE
, PCI_ANY_ID
),
2573 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2574 .class_mask
= 0xffffff,
2575 .driver_data
= AZX_DRIVER_CTX
| AZX_DCAPS_CTX_WORKAROUND
|
2576 AZX_DCAPS_NO_64BIT
| AZX_DCAPS_POSFIX_LPIB
},
2578 /* this entry seems still valid -- i.e. without emu20kx chip */
2579 { PCI_DEVICE(0x1102, 0x0009),
2580 .driver_data
= AZX_DRIVER_CTX
| AZX_DCAPS_CTX_WORKAROUND
|
2581 AZX_DCAPS_NO_64BIT
| AZX_DCAPS_POSFIX_LPIB
},
2584 { PCI_DEVICE(0x13f6, 0x5011),
2585 .driver_data
= AZX_DRIVER_CMEDIA
|
2586 AZX_DCAPS_NO_MSI
| AZX_DCAPS_POSFIX_LPIB
| AZX_DCAPS_SNOOP_OFF
},
2588 { PCI_DEVICE(0x17f3, 0x3010), .driver_data
= AZX_DRIVER_GENERIC
},
2589 /* VMware HDAudio */
2590 { PCI_DEVICE(0x15ad, 0x1977), .driver_data
= AZX_DRIVER_GENERIC
},
2591 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2592 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
2593 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2594 .class_mask
= 0xffffff,
2595 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_HDMI
},
2596 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
),
2597 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2598 .class_mask
= 0xffffff,
2599 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_HDMI
},
2602 MODULE_DEVICE_TABLE(pci
, azx_ids
);
2604 /* pci_driver definition */
2605 static struct pci_driver azx_driver
= {
2606 .name
= KBUILD_MODNAME
,
2607 .id_table
= azx_ids
,
2609 .remove
= azx_remove
,
2610 .shutdown
= azx_shutdown
,
2616 module_pci_driver(azx_driver
);