3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
53 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
54 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
55 static char *model
[SNDRV_CARDS
];
56 static int position_fix
[SNDRV_CARDS
];
57 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
58 static int single_cmd
;
59 static int enable_msi
;
61 module_param_array(index
, int, NULL
, 0444);
62 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
63 module_param_array(id
, charp
, NULL
, 0444);
64 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
65 module_param_array(enable
, bool, NULL
, 0444);
66 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
67 module_param_array(model
, charp
, NULL
, 0444);
68 MODULE_PARM_DESC(model
, "Use the given board model.");
69 module_param_array(position_fix
, int, NULL
, 0444);
70 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask
, int, NULL
, 0444);
73 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd
, bool, 0444);
75 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi
, int, 0444);
78 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
87 static int power_save_controller
= 1;
88 module_param(power_save_controller
, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
115 MODULE_DESCRIPTION("Intel HDA driver");
117 #define SFX "hda-intel: "
123 #define ICH6_REG_GCAP 0x00
124 #define ICH6_REG_VMIN 0x02
125 #define ICH6_REG_VMAJ 0x03
126 #define ICH6_REG_OUTPAY 0x04
127 #define ICH6_REG_INPAY 0x06
128 #define ICH6_REG_GCTL 0x08
129 #define ICH6_REG_WAKEEN 0x0c
130 #define ICH6_REG_STATESTS 0x0e
131 #define ICH6_REG_GSTS 0x10
132 #define ICH6_REG_INTCTL 0x20
133 #define ICH6_REG_INTSTS 0x24
134 #define ICH6_REG_WALCLK 0x30
135 #define ICH6_REG_SYNC 0x34
136 #define ICH6_REG_CORBLBASE 0x40
137 #define ICH6_REG_CORBUBASE 0x44
138 #define ICH6_REG_CORBWP 0x48
139 #define ICH6_REG_CORBRP 0x4A
140 #define ICH6_REG_CORBCTL 0x4c
141 #define ICH6_REG_CORBSTS 0x4d
142 #define ICH6_REG_CORBSIZE 0x4e
144 #define ICH6_REG_RIRBLBASE 0x50
145 #define ICH6_REG_RIRBUBASE 0x54
146 #define ICH6_REG_RIRBWP 0x58
147 #define ICH6_REG_RINTCNT 0x5a
148 #define ICH6_REG_RIRBCTL 0x5c
149 #define ICH6_REG_RIRBSTS 0x5d
150 #define ICH6_REG_RIRBSIZE 0x5e
152 #define ICH6_REG_IC 0x60
153 #define ICH6_REG_IR 0x64
154 #define ICH6_REG_IRS 0x68
155 #define ICH6_IRS_VALID (1<<1)
156 #define ICH6_IRS_BUSY (1<<0)
158 #define ICH6_REG_DPLBASE 0x70
159 #define ICH6_REG_DPUBASE 0x74
160 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
162 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
163 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
165 /* stream register offsets from stream base */
166 #define ICH6_REG_SD_CTL 0x00
167 #define ICH6_REG_SD_STS 0x03
168 #define ICH6_REG_SD_LPIB 0x04
169 #define ICH6_REG_SD_CBL 0x08
170 #define ICH6_REG_SD_LVI 0x0c
171 #define ICH6_REG_SD_FIFOW 0x0e
172 #define ICH6_REG_SD_FIFOSIZE 0x10
173 #define ICH6_REG_SD_FORMAT 0x12
174 #define ICH6_REG_SD_BDLPL 0x18
175 #define ICH6_REG_SD_BDLPU 0x1c
178 #define ICH6_PCIREG_TCSEL 0x44
184 /* max number of SDs */
185 /* ICH, ATI and VIA have 4 playback and 4 capture */
186 #define ICH6_CAPTURE_INDEX 0
187 #define ICH6_NUM_CAPTURE 4
188 #define ICH6_PLAYBACK_INDEX 4
189 #define ICH6_NUM_PLAYBACK 4
191 /* ULI has 6 playback and 5 capture */
192 #define ULI_CAPTURE_INDEX 0
193 #define ULI_NUM_CAPTURE 5
194 #define ULI_PLAYBACK_INDEX 5
195 #define ULI_NUM_PLAYBACK 6
197 /* ATI HDMI has 1 playback and 0 capture */
198 #define ATIHDMI_CAPTURE_INDEX 0
199 #define ATIHDMI_NUM_CAPTURE 0
200 #define ATIHDMI_PLAYBACK_INDEX 0
201 #define ATIHDMI_NUM_PLAYBACK 1
203 /* this number is statically defined for simplicity */
204 #define MAX_AZX_DEV 16
206 /* max number of fragments - we may use more if allocating more pages for BDL */
207 #define BDL_SIZE PAGE_ALIGN(8192)
208 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
209 /* max buffer size - no h/w limit, you can increase as you like */
210 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
211 /* max number of PCM devics per card */
212 #define AZX_MAX_AUDIO_PCMS 6
213 #define AZX_MAX_MODEM_PCMS 2
214 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
216 /* RIRB int mask: overrun[2], response[0] */
217 #define RIRB_INT_RESPONSE 0x01
218 #define RIRB_INT_OVERRUN 0x04
219 #define RIRB_INT_MASK 0x05
221 /* STATESTS int mask: SD2,SD1,SD0 */
222 #define AZX_MAX_CODECS 3
223 #define STATESTS_INT_MASK 0x07
226 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
227 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
228 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
229 #define SD_CTL_STREAM_TAG_SHIFT 20
231 /* SD_CTL and SD_STS */
232 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
233 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
234 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
235 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
239 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
241 /* INTCTL and INTSTS */
242 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
243 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
244 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
246 /* GCTL unsolicited response enable bit */
247 #define ICH6_GCTL_UREN (1<<8)
250 #define ICH6_GCTL_RESET (1<<0)
252 /* CORB/RIRB control, read/write pointer */
253 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
254 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
255 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
256 /* below are so far hardcoded - should read registers in future */
257 #define ICH6_MAX_CORB_ENTRIES 256
258 #define ICH6_MAX_RIRB_ENTRIES 256
260 /* position fix mode */
268 /* Defines for ATI HD Audio support in SB450 south bridge */
269 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
270 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
272 /* Defines for Nvidia HDA support */
273 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
274 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
280 u32
*bdl
; /* virtual address of the BDL */
281 dma_addr_t bdl_addr
; /* physical address of the BDL */
282 u32
*posbuf
; /* position buffer pointer */
284 unsigned int bufsize
; /* size of the play buffer in bytes */
285 unsigned int fragsize
; /* size of each period in bytes */
286 unsigned int frags
; /* number for period in the play buffer */
287 unsigned int fifo_size
; /* FIFO size */
289 void __iomem
*sd_addr
; /* stream descriptor pointer */
291 u32 sd_int_sta_mask
; /* stream int status mask */
294 struct snd_pcm_substream
*substream
; /* assigned substream,
297 unsigned int format_val
; /* format value to be set in the
298 * controller and the codec
300 unsigned char stream_tag
; /* assigned stream */
301 unsigned char index
; /* stream index */
302 /* for sanity check of position buffer */
303 unsigned int period_intr
;
305 unsigned int opened
:1;
306 unsigned int running
:1;
311 u32
*buf
; /* CORB/RIRB buffer
312 * Each CORB entry is 4byte, RIRB is 8byte
314 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
316 unsigned short rp
, wp
; /* read/write pointers */
317 int cmds
; /* number of pending requests */
318 u32 res
; /* last read value */
322 struct snd_card
*card
;
325 /* chip type specific */
327 int playback_streams
;
328 int playback_index_offset
;
330 int capture_index_offset
;
335 void __iomem
*remap_addr
;
340 struct mutex open_mutex
;
342 /* streams (x num_streams) */
343 struct azx_dev
*azx_dev
;
346 unsigned int pcm_devs
;
347 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
350 unsigned short codec_mask
;
357 /* BDL, CORB/RIRB and position buffers */
358 struct snd_dma_buffer bdl
;
359 struct snd_dma_buffer rb
;
360 struct snd_dma_buffer posbuf
;
364 unsigned int running
:1;
365 unsigned int initialized
:1;
366 unsigned int single_cmd
:1;
367 unsigned int polling_mode
:1;
371 unsigned int last_cmd
; /* last issued command (to sync) */
385 static char *driver_short_names
[] __devinitdata
= {
386 [AZX_DRIVER_ICH
] = "HDA Intel",
387 [AZX_DRIVER_ATI
] = "HDA ATI SB",
388 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
389 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
390 [AZX_DRIVER_SIS
] = "HDA SIS966",
391 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
392 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
396 * macros for easy use
398 #define azx_writel(chip,reg,value) \
399 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
400 #define azx_readl(chip,reg) \
401 readl((chip)->remap_addr + ICH6_REG_##reg)
402 #define azx_writew(chip,reg,value) \
403 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_readw(chip,reg) \
405 readw((chip)->remap_addr + ICH6_REG_##reg)
406 #define azx_writeb(chip,reg,value) \
407 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
408 #define azx_readb(chip,reg) \
409 readb((chip)->remap_addr + ICH6_REG_##reg)
411 #define azx_sd_writel(dev,reg,value) \
412 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
413 #define azx_sd_readl(dev,reg) \
414 readl((dev)->sd_addr + ICH6_REG_##reg)
415 #define azx_sd_writew(dev,reg,value) \
416 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_readw(dev,reg) \
418 readw((dev)->sd_addr + ICH6_REG_##reg)
419 #define azx_sd_writeb(dev,reg,value) \
420 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
421 #define azx_sd_readb(dev,reg) \
422 readb((dev)->sd_addr + ICH6_REG_##reg)
424 /* for pcm support */
425 #define get_azx_dev(substream) (substream->runtime->private_data)
427 /* Get the upper 32bit of the given dma_addr_t
428 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
430 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
432 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
435 * Interface for HD codec
439 * CORB / RIRB interface
441 static int azx_alloc_cmd_io(struct azx
*chip
)
445 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
446 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
447 snd_dma_pci_data(chip
->pci
),
448 PAGE_SIZE
, &chip
->rb
);
450 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
456 static void azx_init_cmd_io(struct azx
*chip
)
459 chip
->corb
.addr
= chip
->rb
.addr
;
460 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
461 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
462 azx_writel(chip
, CORBUBASE
, upper_32bit(chip
->corb
.addr
));
464 /* set the corb size to 256 entries (ULI requires explicitly) */
465 azx_writeb(chip
, CORBSIZE
, 0x02);
466 /* set the corb write pointer to 0 */
467 azx_writew(chip
, CORBWP
, 0);
468 /* reset the corb hw read pointer */
469 azx_writew(chip
, CORBRP
, ICH6_RBRWP_CLR
);
470 /* enable corb dma */
471 azx_writeb(chip
, CORBCTL
, ICH6_RBCTL_DMA_EN
);
474 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
475 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
476 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
477 azx_writel(chip
, RIRBUBASE
, upper_32bit(chip
->rirb
.addr
));
479 /* set the rirb size to 256 entries (ULI requires explicitly) */
480 azx_writeb(chip
, RIRBSIZE
, 0x02);
481 /* reset the rirb hw write pointer */
482 azx_writew(chip
, RIRBWP
, ICH6_RBRWP_CLR
);
483 /* set N=1, get RIRB response interrupt for new entry */
484 azx_writew(chip
, RINTCNT
, 1);
485 /* enable rirb dma and response irq */
486 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
487 chip
->rirb
.rp
= chip
->rirb
.cmds
= 0;
490 static void azx_free_cmd_io(struct azx
*chip
)
492 /* disable ringbuffer DMAs */
493 azx_writeb(chip
, RIRBCTL
, 0);
494 azx_writeb(chip
, CORBCTL
, 0);
498 static int azx_corb_send_cmd(struct hda_codec
*codec
, u32 val
)
500 struct azx
*chip
= codec
->bus
->private_data
;
503 /* add command to corb */
504 wp
= azx_readb(chip
, CORBWP
);
506 wp
%= ICH6_MAX_CORB_ENTRIES
;
508 spin_lock_irq(&chip
->reg_lock
);
510 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
511 azx_writel(chip
, CORBWP
, wp
);
512 spin_unlock_irq(&chip
->reg_lock
);
517 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
519 /* retrieve RIRB entry - called from interrupt handler */
520 static void azx_update_rirb(struct azx
*chip
)
525 wp
= azx_readb(chip
, RIRBWP
);
526 if (wp
== chip
->rirb
.wp
)
530 while (chip
->rirb
.rp
!= wp
) {
532 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
534 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
535 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
536 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
537 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
538 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
539 else if (chip
->rirb
.cmds
) {
541 chip
->rirb
.res
= res
;
546 /* receive a response */
547 static unsigned int azx_rirb_get_response(struct hda_codec
*codec
)
549 struct azx
*chip
= codec
->bus
->private_data
;
550 unsigned long timeout
;
553 timeout
= jiffies
+ msecs_to_jiffies(1000);
555 if (chip
->polling_mode
) {
556 spin_lock_irq(&chip
->reg_lock
);
557 azx_update_rirb(chip
);
558 spin_unlock_irq(&chip
->reg_lock
);
560 if (!chip
->rirb
.cmds
)
561 return chip
->rirb
.res
; /* the last value */
564 } while (time_after_eq(timeout
, jiffies
));
567 snd_printk(KERN_WARNING
"hda_intel: No response from codec, "
568 "disabling MSI: last cmd=0x%08x\n", chip
->last_cmd
);
569 free_irq(chip
->irq
, chip
);
571 pci_disable_msi(chip
->pci
);
573 if (azx_acquire_irq(chip
, 1) < 0)
578 if (!chip
->polling_mode
) {
579 snd_printk(KERN_WARNING
"hda_intel: azx_get_response timeout, "
580 "switching to polling mode: last cmd=0x%08x\n",
582 chip
->polling_mode
= 1;
586 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
587 "switching to single_cmd mode: last cmd=0x%08x\n",
589 chip
->rirb
.rp
= azx_readb(chip
, RIRBWP
);
591 /* switch to single_cmd mode */
592 chip
->single_cmd
= 1;
593 azx_free_cmd_io(chip
);
598 * Use the single immediate command instead of CORB/RIRB for simplicity
600 * Note: according to Intel, this is not preferred use. The command was
601 * intended for the BIOS only, and may get confused with unsolicited
602 * responses. So, we shouldn't use it for normal operation from the
604 * I left the codes, however, for debugging/testing purposes.
608 static int azx_single_send_cmd(struct hda_codec
*codec
, u32 val
)
610 struct azx
*chip
= codec
->bus
->private_data
;
614 /* check ICB busy bit */
615 if (!((azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
))) {
616 /* Clear IRV valid bit */
617 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
619 azx_writel(chip
, IC
, val
);
620 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
626 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
627 azx_readw(chip
, IRS
), val
);
631 /* receive a response */
632 static unsigned int azx_single_get_response(struct hda_codec
*codec
)
634 struct azx
*chip
= codec
->bus
->private_data
;
638 /* check IRV busy bit */
639 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
)
640 return azx_readl(chip
, IR
);
643 snd_printd(SFX
"get_response timeout: IRS=0x%x\n",
644 azx_readw(chip
, IRS
));
645 return (unsigned int)-1;
649 * The below are the main callbacks from hda_codec.
651 * They are just the skeleton to call sub-callbacks according to the
652 * current setting of chip->single_cmd.
656 static int azx_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
657 int direct
, unsigned int verb
,
660 struct azx
*chip
= codec
->bus
->private_data
;
663 val
= (u32
)(codec
->addr
& 0x0f) << 28;
664 val
|= (u32
)direct
<< 27;
665 val
|= (u32
)nid
<< 20;
668 chip
->last_cmd
= val
;
670 if (chip
->single_cmd
)
671 return azx_single_send_cmd(codec
, val
);
673 return azx_corb_send_cmd(codec
, val
);
677 static unsigned int azx_get_response(struct hda_codec
*codec
)
679 struct azx
*chip
= codec
->bus
->private_data
;
680 if (chip
->single_cmd
)
681 return azx_single_get_response(codec
);
683 return azx_rirb_get_response(codec
);
686 #ifdef CONFIG_SND_HDA_POWER_SAVE
687 static void azx_power_notify(struct hda_codec
*codec
);
690 /* reset codec link */
691 static int azx_reset(struct azx
*chip
)
696 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
698 /* reset controller */
699 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
702 while (azx_readb(chip
, GCTL
) && --count
)
705 /* delay for >= 100us for codec PLL to settle per spec
706 * Rev 0.9 section 5.5.1
710 /* Bring controller out of reset */
711 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
714 while (!azx_readb(chip
, GCTL
) && --count
)
717 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
720 /* check to see if controller is ready */
721 if (!azx_readb(chip
, GCTL
)) {
722 snd_printd("azx_reset: controller not ready!\n");
726 /* Accept unsolicited responses */
727 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UREN
);
730 if (!chip
->codec_mask
) {
731 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
732 snd_printdd("codec_mask = 0x%x\n", chip
->codec_mask
);
743 /* enable interrupts */
744 static void azx_int_enable(struct azx
*chip
)
746 /* enable controller CIE and GIE */
747 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
748 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
751 /* disable interrupts */
752 static void azx_int_disable(struct azx
*chip
)
756 /* disable interrupts in stream descriptor */
757 for (i
= 0; i
< chip
->num_streams
; i
++) {
758 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
759 azx_sd_writeb(azx_dev
, SD_CTL
,
760 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
763 /* disable SIE for all streams */
764 azx_writeb(chip
, INTCTL
, 0);
766 /* disable controller CIE and GIE */
767 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
768 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
771 /* clear interrupts */
772 static void azx_int_clear(struct azx
*chip
)
776 /* clear stream status */
777 for (i
= 0; i
< chip
->num_streams
; i
++) {
778 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
779 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
783 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
785 /* clear rirb status */
786 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
788 /* clear int status */
789 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
793 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
796 azx_writeb(chip
, INTCTL
,
797 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
798 /* set DMA start and interrupt mask */
799 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
800 SD_CTL_DMA_START
| SD_INT_MASK
);
804 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
807 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
808 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
809 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
811 azx_writeb(chip
, INTCTL
,
812 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
817 * reset and start the controller registers
819 static void azx_init_chip(struct azx
*chip
)
821 if (chip
->initialized
)
824 /* reset controller */
827 /* initialize interrupts */
829 azx_int_enable(chip
);
831 /* initialize the codec command I/O */
832 if (!chip
->single_cmd
)
833 azx_init_cmd_io(chip
);
835 /* program the position buffer */
836 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
837 azx_writel(chip
, DPUBASE
, upper_32bit(chip
->posbuf
.addr
));
839 chip
->initialized
= 1;
843 * initialize the PCI registers
845 /* update bits in a PCI register byte */
846 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
847 unsigned char mask
, unsigned char val
)
851 pci_read_config_byte(pci
, reg
, &data
);
853 data
|= (val
& mask
);
854 pci_write_config_byte(pci
, reg
, data
);
857 static void azx_init_pci(struct azx
*chip
)
859 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
860 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
861 * Ensuring these bits are 0 clears playback static on some HD Audio
864 update_pci_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, 0x07, 0);
866 switch (chip
->driver_type
) {
868 /* For ATI SB450 azalia HD audio, we need to enable snoop */
869 update_pci_byte(chip
->pci
,
870 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
871 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
873 case AZX_DRIVER_NVIDIA
:
874 /* For NVIDIA HDA, enable snoop */
875 update_pci_byte(chip
->pci
,
876 NVIDIA_HDA_TRANSREG_ADDR
,
877 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
886 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
888 struct azx
*chip
= dev_id
;
889 struct azx_dev
*azx_dev
;
893 spin_lock(&chip
->reg_lock
);
895 status
= azx_readl(chip
, INTSTS
);
897 spin_unlock(&chip
->reg_lock
);
901 for (i
= 0; i
< chip
->num_streams
; i
++) {
902 azx_dev
= &chip
->azx_dev
[i
];
903 if (status
& azx_dev
->sd_int_sta_mask
) {
904 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
905 if (azx_dev
->substream
&& azx_dev
->running
) {
906 azx_dev
->period_intr
++;
907 spin_unlock(&chip
->reg_lock
);
908 snd_pcm_period_elapsed(azx_dev
->substream
);
909 spin_lock(&chip
->reg_lock
);
915 status
= azx_readb(chip
, RIRBSTS
);
916 if (status
& RIRB_INT_MASK
) {
917 if (!chip
->single_cmd
&& (status
& RIRB_INT_RESPONSE
))
918 azx_update_rirb(chip
);
919 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
923 /* clear state status int */
924 if (azx_readb(chip
, STATESTS
) & 0x04)
925 azx_writeb(chip
, STATESTS
, 0x04);
927 spin_unlock(&chip
->reg_lock
);
936 static void azx_setup_periods(struct azx_dev
*azx_dev
)
938 u32
*bdl
= azx_dev
->bdl
;
939 dma_addr_t dma_addr
= azx_dev
->substream
->runtime
->dma_addr
;
942 /* reset BDL address */
943 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
944 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
946 /* program the initial BDL entries */
947 for (idx
= 0; idx
< azx_dev
->frags
; idx
++) {
948 unsigned int off
= idx
<< 2; /* 4 dword step */
949 dma_addr_t addr
= dma_addr
+ idx
* azx_dev
->fragsize
;
950 /* program the address field of the BDL entry */
951 bdl
[off
] = cpu_to_le32((u32
)addr
);
952 bdl
[off
+1] = cpu_to_le32(upper_32bit(addr
));
954 /* program the size field of the BDL entry */
955 bdl
[off
+2] = cpu_to_le32(azx_dev
->fragsize
);
957 /* program the IOC to enable interrupt when buffer completes */
958 bdl
[off
+3] = cpu_to_le32(0x01);
963 * set up the SD for streaming
965 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
970 /* make sure the run bit is zero for SD */
971 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
974 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
975 SD_CTL_STREAM_RESET
);
978 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
981 val
&= ~SD_CTL_STREAM_RESET
;
982 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
986 /* waiting for hardware to report that the stream is out of reset */
987 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
991 /* program the stream_tag */
992 azx_sd_writel(azx_dev
, SD_CTL
,
993 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
)|
994 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
996 /* program the length of samples in cyclic buffer */
997 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
999 /* program the stream format */
1000 /* this value needs to be the same as the one programmed */
1001 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
1003 /* program the stream LVI (last valid index) of the BDL */
1004 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
1006 /* program the BDL address */
1007 /* lower BDL address */
1008 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl_addr
);
1009 /* upper BDL address */
1010 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32bit(azx_dev
->bdl_addr
));
1012 /* enable the position buffer */
1013 if (!(azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
1014 azx_writel(chip
, DPLBASE
,
1015 (u32
)chip
->posbuf
.addr
|ICH6_DPLBASE_ENABLE
);
1017 /* set the interrupt enable bits in the descriptor control register */
1018 azx_sd_writel(azx_dev
, SD_CTL
,
1019 azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
1026 * Codec initialization
1029 static unsigned int azx_max_codecs
[] __devinitdata
= {
1030 [AZX_DRIVER_ICH
] = 3,
1031 [AZX_DRIVER_ATI
] = 4,
1032 [AZX_DRIVER_ATIHDMI
] = 4,
1033 [AZX_DRIVER_VIA
] = 3, /* FIXME: correct? */
1034 [AZX_DRIVER_SIS
] = 3, /* FIXME: correct? */
1035 [AZX_DRIVER_ULI
] = 3, /* FIXME: correct? */
1036 [AZX_DRIVER_NVIDIA
] = 3, /* FIXME: correct? */
1039 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
,
1040 unsigned int codec_probe_mask
)
1042 struct hda_bus_template bus_temp
;
1043 int c
, codecs
, audio_codecs
, err
;
1045 memset(&bus_temp
, 0, sizeof(bus_temp
));
1046 bus_temp
.private_data
= chip
;
1047 bus_temp
.modelname
= model
;
1048 bus_temp
.pci
= chip
->pci
;
1049 bus_temp
.ops
.command
= azx_send_cmd
;
1050 bus_temp
.ops
.get_response
= azx_get_response
;
1051 #ifdef CONFIG_SND_HDA_POWER_SAVE
1052 bus_temp
.ops
.pm_notify
= azx_power_notify
;
1055 err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
);
1059 codecs
= audio_codecs
= 0;
1060 for (c
= 0; c
< AZX_MAX_CODECS
; c
++) {
1061 if ((chip
->codec_mask
& (1 << c
)) & codec_probe_mask
) {
1062 struct hda_codec
*codec
;
1063 err
= snd_hda_codec_new(chip
->bus
, c
, &codec
);
1071 if (!audio_codecs
) {
1072 /* probe additional slots if no codec is found */
1073 for (; c
< azx_max_codecs
[chip
->driver_type
]; c
++) {
1074 if ((chip
->codec_mask
& (1 << c
)) & codec_probe_mask
) {
1075 err
= snd_hda_codec_new(chip
->bus
, c
, NULL
);
1083 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1095 /* assign a stream for the PCM */
1096 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
1099 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1100 dev
= chip
->playback_index_offset
;
1101 nums
= chip
->playback_streams
;
1103 dev
= chip
->capture_index_offset
;
1104 nums
= chip
->capture_streams
;
1106 for (i
= 0; i
< nums
; i
++, dev
++)
1107 if (!chip
->azx_dev
[dev
].opened
) {
1108 chip
->azx_dev
[dev
].opened
= 1;
1109 return &chip
->azx_dev
[dev
];
1114 /* release the assigned stream */
1115 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1117 azx_dev
->opened
= 0;
1120 static struct snd_pcm_hardware azx_pcm_hw
= {
1121 .info
= (SNDRV_PCM_INFO_MMAP
|
1122 SNDRV_PCM_INFO_INTERLEAVED
|
1123 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1124 SNDRV_PCM_INFO_MMAP_VALID
|
1125 /* No full-resume yet implemented */
1126 /* SNDRV_PCM_INFO_RESUME |*/
1127 SNDRV_PCM_INFO_PAUSE
),
1128 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1129 .rates
= SNDRV_PCM_RATE_48000
,
1134 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1135 .period_bytes_min
= 128,
1136 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1138 .periods_max
= AZX_MAX_FRAG
,
1144 struct hda_codec
*codec
;
1145 struct hda_pcm_stream
*hinfo
[2];
1148 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1150 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1151 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1152 struct azx
*chip
= apcm
->chip
;
1153 struct azx_dev
*azx_dev
;
1154 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1155 unsigned long flags
;
1158 mutex_lock(&chip
->open_mutex
);
1159 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1160 if (azx_dev
== NULL
) {
1161 mutex_unlock(&chip
->open_mutex
);
1164 runtime
->hw
= azx_pcm_hw
;
1165 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1166 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1167 runtime
->hw
.formats
= hinfo
->formats
;
1168 runtime
->hw
.rates
= hinfo
->rates
;
1169 snd_pcm_limit_hw_rates(runtime
);
1170 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1171 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1173 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1175 snd_hda_power_up(apcm
->codec
);
1176 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
1178 azx_release_device(azx_dev
);
1179 snd_hda_power_down(apcm
->codec
);
1180 mutex_unlock(&chip
->open_mutex
);
1183 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1184 azx_dev
->substream
= substream
;
1185 azx_dev
->running
= 0;
1186 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1188 runtime
->private_data
= azx_dev
;
1189 mutex_unlock(&chip
->open_mutex
);
1193 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1195 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1196 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1197 struct azx
*chip
= apcm
->chip
;
1198 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1199 unsigned long flags
;
1201 mutex_lock(&chip
->open_mutex
);
1202 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1203 azx_dev
->substream
= NULL
;
1204 azx_dev
->running
= 0;
1205 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1206 azx_release_device(azx_dev
);
1207 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1208 snd_hda_power_down(apcm
->codec
);
1209 mutex_unlock(&chip
->open_mutex
);
1213 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
1214 struct snd_pcm_hw_params
*hw_params
)
1216 return snd_pcm_lib_malloc_pages(substream
,
1217 params_buffer_bytes(hw_params
));
1220 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1222 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1223 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1224 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1226 /* reset BDL address */
1227 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1228 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1229 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1231 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1233 return snd_pcm_lib_free_pages(substream
);
1236 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1238 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1239 struct azx
*chip
= apcm
->chip
;
1240 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1241 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1242 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1244 azx_dev
->bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1245 azx_dev
->fragsize
= snd_pcm_lib_period_bytes(substream
);
1246 azx_dev
->frags
= azx_dev
->bufsize
/ azx_dev
->fragsize
;
1247 azx_dev
->format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1251 if (!azx_dev
->format_val
) {
1252 snd_printk(KERN_ERR SFX
1253 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1254 runtime
->rate
, runtime
->channels
, runtime
->format
);
1258 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1260 azx_dev
->bufsize
, azx_dev
->fragsize
, azx_dev
->format_val
);
1261 azx_setup_periods(azx_dev
);
1262 azx_setup_controller(chip
, azx_dev
);
1263 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1264 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1266 azx_dev
->fifo_size
= 0;
1268 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1269 azx_dev
->format_val
, substream
);
1272 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1274 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1275 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1276 struct azx
*chip
= apcm
->chip
;
1279 spin_lock(&chip
->reg_lock
);
1281 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1282 case SNDRV_PCM_TRIGGER_RESUME
:
1283 case SNDRV_PCM_TRIGGER_START
:
1284 azx_stream_start(chip
, azx_dev
);
1285 azx_dev
->running
= 1;
1287 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1288 case SNDRV_PCM_TRIGGER_SUSPEND
:
1289 case SNDRV_PCM_TRIGGER_STOP
:
1290 azx_stream_stop(chip
, azx_dev
);
1291 azx_dev
->running
= 0;
1296 spin_unlock(&chip
->reg_lock
);
1297 if (cmd
== SNDRV_PCM_TRIGGER_PAUSE_PUSH
||
1298 cmd
== SNDRV_PCM_TRIGGER_SUSPEND
||
1299 cmd
== SNDRV_PCM_TRIGGER_STOP
) {
1301 while ((azx_sd_readb(azx_dev
, SD_CTL
) & SD_CTL_DMA_START
) &&
1308 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1310 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1311 struct azx
*chip
= apcm
->chip
;
1312 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1315 if (chip
->position_fix
== POS_FIX_POSBUF
||
1316 chip
->position_fix
== POS_FIX_AUTO
) {
1317 /* use the position buffer */
1318 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1319 if (chip
->position_fix
== POS_FIX_AUTO
&&
1320 azx_dev
->period_intr
== 1 && !pos
) {
1322 "hda-intel: Invalid position buffer, "
1323 "using LPIB read method instead.\n");
1324 chip
->position_fix
= POS_FIX_NONE
;
1330 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1331 if (chip
->position_fix
== POS_FIX_FIFO
)
1332 pos
+= azx_dev
->fifo_size
;
1334 if (pos
>= azx_dev
->bufsize
)
1336 return bytes_to_frames(substream
->runtime
, pos
);
1339 static struct snd_pcm_ops azx_pcm_ops
= {
1340 .open
= azx_pcm_open
,
1341 .close
= azx_pcm_close
,
1342 .ioctl
= snd_pcm_lib_ioctl
,
1343 .hw_params
= azx_pcm_hw_params
,
1344 .hw_free
= azx_pcm_hw_free
,
1345 .prepare
= azx_pcm_prepare
,
1346 .trigger
= azx_pcm_trigger
,
1347 .pointer
= azx_pcm_pointer
,
1350 static void azx_pcm_free(struct snd_pcm
*pcm
)
1352 kfree(pcm
->private_data
);
1355 static int __devinit
create_codec_pcm(struct azx
*chip
, struct hda_codec
*codec
,
1356 struct hda_pcm
*cpcm
, int pcm_dev
)
1359 struct snd_pcm
*pcm
;
1360 struct azx_pcm
*apcm
;
1362 /* if no substreams are defined for both playback and capture,
1363 * it's just a placeholder. ignore it.
1365 if (!cpcm
->stream
[0].substreams
&& !cpcm
->stream
[1].substreams
)
1368 snd_assert(cpcm
->name
, return -EINVAL
);
1370 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1371 cpcm
->stream
[0].substreams
,
1372 cpcm
->stream
[1].substreams
,
1376 strcpy(pcm
->name
, cpcm
->name
);
1377 apcm
= kmalloc(sizeof(*apcm
), GFP_KERNEL
);
1381 apcm
->codec
= codec
;
1382 apcm
->hinfo
[0] = &cpcm
->stream
[0];
1383 apcm
->hinfo
[1] = &cpcm
->stream
[1];
1384 pcm
->private_data
= apcm
;
1385 pcm
->private_free
= azx_pcm_free
;
1386 if (cpcm
->stream
[0].substreams
)
1387 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &azx_pcm_ops
);
1388 if (cpcm
->stream
[1].substreams
)
1389 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &azx_pcm_ops
);
1390 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1391 snd_dma_pci_data(chip
->pci
),
1392 1024 * 64, 1024 * 1024);
1393 chip
->pcm
[pcm_dev
] = pcm
;
1394 if (chip
->pcm_devs
< pcm_dev
+ 1)
1395 chip
->pcm_devs
= pcm_dev
+ 1;
1400 static int __devinit
azx_pcm_create(struct azx
*chip
)
1402 struct hda_codec
*codec
;
1406 err
= snd_hda_build_pcms(chip
->bus
);
1410 /* create audio PCMs */
1412 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
1413 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1414 if (codec
->pcm_info
[c
].is_modem
)
1415 continue; /* create later */
1416 if (pcm_dev
>= AZX_MAX_AUDIO_PCMS
) {
1417 snd_printk(KERN_ERR SFX
1418 "Too many audio PCMs\n");
1421 err
= create_codec_pcm(chip
, codec
,
1422 &codec
->pcm_info
[c
], pcm_dev
);
1429 /* create modem PCMs */
1430 pcm_dev
= AZX_MAX_AUDIO_PCMS
;
1431 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
1432 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1433 if (!codec
->pcm_info
[c
].is_modem
)
1434 continue; /* already created */
1435 if (pcm_dev
>= AZX_MAX_PCMS
) {
1436 snd_printk(KERN_ERR SFX
1437 "Too many modem PCMs\n");
1440 err
= create_codec_pcm(chip
, codec
,
1441 &codec
->pcm_info
[c
], pcm_dev
);
1444 chip
->pcm
[pcm_dev
]->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1452 * mixer creation - all stuff is implemented in hda module
1454 static int __devinit
azx_mixer_create(struct azx
*chip
)
1456 return snd_hda_build_controls(chip
->bus
);
1461 * initialize SD streams
1463 static int __devinit
azx_init_stream(struct azx
*chip
)
1467 /* initialize each stream (aka device)
1468 * assign the starting bdl address to each stream (device)
1471 for (i
= 0; i
< chip
->num_streams
; i
++) {
1472 unsigned int off
= sizeof(u32
) * (i
* AZX_MAX_FRAG
* 4);
1473 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1474 azx_dev
->bdl
= (u32
*)(chip
->bdl
.area
+ off
);
1475 azx_dev
->bdl_addr
= chip
->bdl
.addr
+ off
;
1476 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
1477 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1478 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1479 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1480 azx_dev
->sd_int_sta_mask
= 1 << i
;
1481 /* stream tag: must be non-zero and unique */
1483 azx_dev
->stream_tag
= i
+ 1;
1489 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
1491 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
1492 chip
->msi
? 0 : IRQF_SHARED
,
1493 "HDA Intel", chip
)) {
1494 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
1495 "disabling device\n", chip
->pci
->irq
);
1497 snd_card_disconnect(chip
->card
);
1500 chip
->irq
= chip
->pci
->irq
;
1501 pci_intx(chip
->pci
, !chip
->msi
);
1506 static void azx_stop_chip(struct azx
*chip
)
1508 if (!chip
->initialized
)
1511 /* disable interrupts */
1512 azx_int_disable(chip
);
1513 azx_int_clear(chip
);
1515 /* disable CORB/RIRB */
1516 azx_free_cmd_io(chip
);
1518 /* disable position buffer */
1519 azx_writel(chip
, DPLBASE
, 0);
1520 azx_writel(chip
, DPUBASE
, 0);
1522 chip
->initialized
= 0;
1525 #ifdef CONFIG_SND_HDA_POWER_SAVE
1526 /* power-up/down the controller */
1527 static void azx_power_notify(struct hda_codec
*codec
)
1529 struct azx
*chip
= codec
->bus
->private_data
;
1530 struct hda_codec
*c
;
1533 list_for_each_entry(c
, &codec
->bus
->codec_list
, list
) {
1540 azx_init_chip(chip
);
1541 else if (chip
->running
&& power_save_controller
)
1542 azx_stop_chip(chip
);
1544 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1550 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
1552 struct snd_card
*card
= pci_get_drvdata(pci
);
1553 struct azx
*chip
= card
->private_data
;
1556 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1557 for (i
= 0; i
< chip
->pcm_devs
; i
++)
1558 snd_pcm_suspend_all(chip
->pcm
[i
]);
1559 if (chip
->initialized
)
1560 snd_hda_suspend(chip
->bus
, state
);
1561 azx_stop_chip(chip
);
1562 if (chip
->irq
>= 0) {
1563 synchronize_irq(chip
->irq
);
1564 free_irq(chip
->irq
, chip
);
1568 pci_disable_msi(chip
->pci
);
1569 pci_disable_device(pci
);
1570 pci_save_state(pci
);
1571 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
1575 static int azx_resume(struct pci_dev
*pci
)
1577 struct snd_card
*card
= pci_get_drvdata(pci
);
1578 struct azx
*chip
= card
->private_data
;
1580 pci_set_power_state(pci
, PCI_D0
);
1581 pci_restore_state(pci
);
1582 if (pci_enable_device(pci
) < 0) {
1583 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
1584 "disabling device\n");
1585 snd_card_disconnect(card
);
1588 pci_set_master(pci
);
1590 if (pci_enable_msi(pci
) < 0)
1592 if (azx_acquire_irq(chip
, 1) < 0)
1596 if (snd_hda_codecs_inuse(chip
->bus
))
1597 azx_init_chip(chip
);
1599 snd_hda_resume(chip
->bus
);
1600 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1603 #endif /* CONFIG_PM */
1609 static int azx_free(struct azx
*chip
)
1611 if (chip
->initialized
) {
1613 for (i
= 0; i
< chip
->num_streams
; i
++)
1614 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
1615 azx_stop_chip(chip
);
1618 if (chip
->irq
>= 0) {
1619 synchronize_irq(chip
->irq
);
1620 free_irq(chip
->irq
, (void*)chip
);
1623 pci_disable_msi(chip
->pci
);
1624 if (chip
->remap_addr
)
1625 iounmap(chip
->remap_addr
);
1628 snd_dma_free_pages(&chip
->bdl
);
1630 snd_dma_free_pages(&chip
->rb
);
1631 if (chip
->posbuf
.area
)
1632 snd_dma_free_pages(&chip
->posbuf
);
1633 pci_release_regions(chip
->pci
);
1634 pci_disable_device(chip
->pci
);
1635 kfree(chip
->azx_dev
);
1641 static int azx_dev_free(struct snd_device
*device
)
1643 return azx_free(device
->device_data
);
1647 * white/black-listing for position_fix
1649 static struct snd_pci_quirk position_fix_list
[] __devinitdata
= {
1650 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE
),
1651 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE
),
1655 static int __devinit
check_position_fix(struct azx
*chip
, int fix
)
1657 const struct snd_pci_quirk
*q
;
1659 if (fix
== POS_FIX_AUTO
) {
1660 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
1663 "hda_intel: position_fix set to %d "
1664 "for device %04x:%04x\n",
1665 q
->value
, q
->subvendor
, q
->subdevice
);
1673 * black-lists for probe_mask
1675 static struct snd_pci_quirk probe_mask_list
[] __devinitdata
= {
1676 /* Thinkpad often breaks the controller communication when accessing
1677 * to the non-working (or non-existing) modem codec slot.
1679 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1680 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1681 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1685 static void __devinit
check_probe_mask(struct azx
*chip
, int dev
)
1687 const struct snd_pci_quirk
*q
;
1689 if (probe_mask
[dev
] == -1) {
1690 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
1693 "hda_intel: probe_mask set to 0x%x "
1694 "for device %04x:%04x\n",
1695 q
->value
, q
->subvendor
, q
->subdevice
);
1696 probe_mask
[dev
] = q
->value
;
1705 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1706 int dev
, int driver_type
,
1711 static struct snd_device_ops ops
= {
1712 .dev_free
= azx_dev_free
,
1717 err
= pci_enable_device(pci
);
1721 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1723 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
1724 pci_disable_device(pci
);
1728 spin_lock_init(&chip
->reg_lock
);
1729 mutex_init(&chip
->open_mutex
);
1733 chip
->driver_type
= driver_type
;
1734 chip
->msi
= enable_msi
;
1736 chip
->position_fix
= check_position_fix(chip
, position_fix
[dev
]);
1737 check_probe_mask(chip
, dev
);
1739 chip
->single_cmd
= single_cmd
;
1741 #if BITS_PER_LONG != 64
1742 /* Fix up base address on ULI M5461 */
1743 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1745 pci_read_config_word(pci
, 0x40, &tmp3
);
1746 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1747 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1751 err
= pci_request_regions(pci
, "ICH HD audio");
1754 pci_disable_device(pci
);
1758 chip
->addr
= pci_resource_start(pci
, 0);
1759 chip
->remap_addr
= ioremap_nocache(chip
->addr
, pci_resource_len(pci
,0));
1760 if (chip
->remap_addr
== NULL
) {
1761 snd_printk(KERN_ERR SFX
"ioremap error\n");
1767 if (pci_enable_msi(pci
) < 0)
1770 if (azx_acquire_irq(chip
, 0) < 0) {
1775 pci_set_master(pci
);
1776 synchronize_irq(chip
->irq
);
1778 switch (chip
->driver_type
) {
1779 case AZX_DRIVER_ULI
:
1780 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1781 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1782 chip
->playback_index_offset
= ULI_PLAYBACK_INDEX
;
1783 chip
->capture_index_offset
= ULI_CAPTURE_INDEX
;
1785 case AZX_DRIVER_ATIHDMI
:
1786 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
1787 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
1788 chip
->playback_index_offset
= ATIHDMI_PLAYBACK_INDEX
;
1789 chip
->capture_index_offset
= ATIHDMI_CAPTURE_INDEX
;
1792 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1793 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1794 chip
->playback_index_offset
= ICH6_PLAYBACK_INDEX
;
1795 chip
->capture_index_offset
= ICH6_CAPTURE_INDEX
;
1798 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1799 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
),
1801 if (!chip
->azx_dev
) {
1802 snd_printk(KERN_ERR
"cannot malloc azx_dev\n");
1806 /* allocate memory for the BDL for each stream */
1807 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
1808 snd_dma_pci_data(chip
->pci
),
1809 BDL_SIZE
, &chip
->bdl
);
1811 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
1814 /* allocate memory for the position buffer */
1815 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
1816 snd_dma_pci_data(chip
->pci
),
1817 chip
->num_streams
* 8, &chip
->posbuf
);
1819 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
1822 /* allocate CORB/RIRB */
1823 if (!chip
->single_cmd
) {
1824 err
= azx_alloc_cmd_io(chip
);
1829 /* initialize streams */
1830 azx_init_stream(chip
);
1832 /* initialize chip */
1834 azx_init_chip(chip
);
1836 /* codec detection */
1837 if (!chip
->codec_mask
) {
1838 snd_printk(KERN_ERR SFX
"no codecs found!\n");
1843 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
1845 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
1849 strcpy(card
->driver
, "HDA-Intel");
1850 strcpy(card
->shortname
, driver_short_names
[chip
->driver_type
]);
1851 sprintf(card
->longname
, "%s at 0x%lx irq %i",
1852 card
->shortname
, chip
->addr
, chip
->irq
);
1862 static void power_down_all_codecs(struct azx
*chip
)
1864 #ifdef CONFIG_SND_HDA_POWER_SAVE
1865 /* The codecs were powered up in snd_hda_codec_new().
1866 * Now all initialization done, so turn them down if possible
1868 struct hda_codec
*codec
;
1869 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
1870 snd_hda_power_down(codec
);
1875 static int __devinit
azx_probe(struct pci_dev
*pci
,
1876 const struct pci_device_id
*pci_id
)
1879 struct snd_card
*card
;
1883 if (dev
>= SNDRV_CARDS
)
1890 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
1892 snd_printk(KERN_ERR SFX
"Error creating card!\n");
1896 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
1898 snd_card_free(card
);
1901 card
->private_data
= chip
;
1903 /* create codec instances */
1904 err
= azx_codec_create(chip
, model
[dev
], probe_mask
[dev
]);
1906 snd_card_free(card
);
1910 /* create PCM streams */
1911 err
= azx_pcm_create(chip
);
1913 snd_card_free(card
);
1917 /* create mixer controls */
1918 err
= azx_mixer_create(chip
);
1920 snd_card_free(card
);
1924 snd_card_set_dev(card
, &pci
->dev
);
1926 err
= snd_card_register(card
);
1928 snd_card_free(card
);
1932 pci_set_drvdata(pci
, card
);
1934 power_down_all_codecs(chip
);
1939 static void __devexit
azx_remove(struct pci_dev
*pci
)
1941 snd_card_free(pci_get_drvdata(pci
));
1942 pci_set_drvdata(pci
, NULL
);
1946 static struct pci_device_id azx_ids
[] = {
1947 { 0x8086, 0x2668, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH6 */
1948 { 0x8086, 0x27d8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH7 */
1949 { 0x8086, 0x269a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ESB2 */
1950 { 0x8086, 0x284b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH8 */
1951 { 0x8086, 0x293e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH9 */
1952 { 0x8086, 0x293f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH9 */
1953 { 0x1002, 0x437b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB450 */
1954 { 0x1002, 0x4383, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB600 */
1955 { 0x1002, 0x793b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS600 HDMI */
1956 { 0x1002, 0x7919, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS690 HDMI */
1957 { 0x1002, 0x960f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS780 HDMI */
1958 { 0x1002, 0xaa00, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI R600 HDMI */
1959 { 0x1002, 0xaa08, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RV630 HDMI */
1960 { 0x1002, 0xaa10, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RV610 HDMI */
1961 { 0x1002, 0xaa18, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RV670 HDMI */
1962 { 0x1002, 0xaa20, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RV635 HDMI */
1963 { 0x1002, 0xaa28, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RV620 HDMI */
1964 { 0x1002, 0xaa30, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RV770 HDMI */
1965 { 0x1106, 0x3288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_VIA
}, /* VIA VT8251/VT8237A */
1966 { 0x1039, 0x7502, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_SIS
}, /* SIS966 */
1967 { 0x10b9, 0x5461, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ULI
}, /* ULI M5461 */
1968 { 0x10de, 0x026c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP51 */
1969 { 0x10de, 0x0371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP55 */
1970 { 0x10de, 0x03e4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP61 */
1971 { 0x10de, 0x03f0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP61 */
1972 { 0x10de, 0x044a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP65 */
1973 { 0x10de, 0x044b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP65 */
1974 { 0x10de, 0x055c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP67 */
1975 { 0x10de, 0x055d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP67 */
1976 { 0x10de, 0x07fc, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP73 */
1977 { 0x10de, 0x07fd, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP73 */
1978 { 0x10de, 0x0774, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP77 */
1979 { 0x10de, 0x0775, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP77 */
1980 { 0x10de, 0x0776, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP77 */
1981 { 0x10de, 0x0777, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP77 */
1982 { 0x10de, 0x0ac0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP79 */
1983 { 0x10de, 0x0ac1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP79 */
1984 { 0x10de, 0x0ac2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP79 */
1985 { 0x10de, 0x0ac3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA MCP79 */
1988 MODULE_DEVICE_TABLE(pci
, azx_ids
);
1990 /* pci_driver definition */
1991 static struct pci_driver driver
= {
1992 .name
= "HDA Intel",
1993 .id_table
= azx_ids
,
1995 .remove
= __devexit_p(azx_remove
),
1997 .suspend
= azx_suspend
,
1998 .resume
= azx_resume
,
2002 static int __init
alsa_card_azx_init(void)
2004 return pci_register_driver(&driver
);
2007 static void __exit
alsa_card_azx_exit(void)
2009 pci_unregister_driver(&driver
);
2012 module_init(alsa_card_azx_init
)
2013 module_exit(alsa_card_azx_exit
)