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Merge branch 'for-linus-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[mirror_ubuntu-artful-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_SCH_HDA_DEVC 0x78
94 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
95
96 /* Define IN stream 0 FIFO size offset in VIA controller */
97 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
98 /* Define VIA HD Audio Device ID*/
99 #define VIA_HDAC_DEVICE_ID 0x3288
100
101 /* max number of SDs */
102 /* ICH, ATI and VIA have 4 playback and 4 capture */
103 #define ICH6_NUM_CAPTURE 4
104 #define ICH6_NUM_PLAYBACK 4
105
106 /* ULI has 6 playback and 5 capture */
107 #define ULI_NUM_CAPTURE 5
108 #define ULI_NUM_PLAYBACK 6
109
110 /* ATI HDMI may have up to 8 playbacks and 0 capture */
111 #define ATIHDMI_NUM_CAPTURE 0
112 #define ATIHDMI_NUM_PLAYBACK 8
113
114 /* TERA has 4 playback and 3 capture */
115 #define TERA_NUM_CAPTURE 3
116 #define TERA_NUM_PLAYBACK 4
117
118
119 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
120 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
121 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
122 static char *model[SNDRV_CARDS];
123 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
124 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
125 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int probe_only[SNDRV_CARDS];
127 static int jackpoll_ms[SNDRV_CARDS];
128 static bool single_cmd;
129 static int enable_msi = -1;
130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
131 static char *patch[SNDRV_CARDS];
132 #endif
133 #ifdef CONFIG_SND_HDA_INPUT_BEEP
134 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
135 CONFIG_SND_HDA_INPUT_BEEP_MODE};
136 #endif
137
138 module_param_array(index, int, NULL, 0444);
139 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
140 module_param_array(id, charp, NULL, 0444);
141 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
142 module_param_array(enable, bool, NULL, 0444);
143 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
144 module_param_array(model, charp, NULL, 0444);
145 MODULE_PARM_DESC(model, "Use the given board model.");
146 module_param_array(position_fix, int, NULL, 0444);
147 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
148 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
149 module_param_array(bdl_pos_adj, int, NULL, 0644);
150 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
151 module_param_array(probe_mask, int, NULL, 0444);
152 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
153 module_param_array(probe_only, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
155 module_param_array(jackpoll_ms, int, NULL, 0444);
156 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
157 module_param(single_cmd, bool, 0444);
158 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
159 "(for debugging only).");
160 module_param(enable_msi, bint, 0444);
161 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
162 #ifdef CONFIG_SND_HDA_PATCH_LOADER
163 module_param_array(patch, charp, NULL, 0444);
164 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
165 #endif
166 #ifdef CONFIG_SND_HDA_INPUT_BEEP
167 module_param_array(beep_mode, bool, NULL, 0444);
168 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
169 "(0=off, 1=on) (default=1).");
170 #endif
171
172 #ifdef CONFIG_PM
173 static int param_set_xint(const char *val, const struct kernel_param *kp);
174 static const struct kernel_param_ops param_ops_xint = {
175 .set = param_set_xint,
176 .get = param_get_int,
177 };
178 #define param_check_xint param_check_int
179
180 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
181 module_param(power_save, xint, 0644);
182 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
183 "(in second, 0 = disable).");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
212 "{Intel, ICH6M},"
213 "{Intel, ICH7},"
214 "{Intel, ESB2},"
215 "{Intel, ICH8},"
216 "{Intel, ICH9},"
217 "{Intel, ICH10},"
218 "{Intel, PCH},"
219 "{Intel, CPT},"
220 "{Intel, PPT},"
221 "{Intel, LPT},"
222 "{Intel, LPT_LP},"
223 "{Intel, WPT_LP},"
224 "{Intel, SPT},"
225 "{Intel, SPT_LP},"
226 "{Intel, HPT},"
227 "{Intel, PBG},"
228 "{Intel, SCH},"
229 "{ATI, SB450},"
230 "{ATI, SB600},"
231 "{ATI, RS600},"
232 "{ATI, RS690},"
233 "{ATI, RS780},"
234 "{ATI, R600},"
235 "{ATI, RV630},"
236 "{ATI, RV610},"
237 "{ATI, RV670},"
238 "{ATI, RV635},"
239 "{ATI, RV620},"
240 "{ATI, RV770},"
241 "{VIA, VT8251},"
242 "{VIA, VT8237A},"
243 "{SiS, SIS966},"
244 "{ULI, M5461}}");
245 MODULE_DESCRIPTION("Intel HDA driver");
246
247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
249 #define SUPPORT_VGA_SWITCHEROO
250 #endif
251 #endif
252
253
254 /*
255 */
256
257 /* driver types */
258 enum {
259 AZX_DRIVER_ICH,
260 AZX_DRIVER_PCH,
261 AZX_DRIVER_SCH,
262 AZX_DRIVER_HDMI,
263 AZX_DRIVER_ATI,
264 AZX_DRIVER_ATIHDMI,
265 AZX_DRIVER_ATIHDMI_NS,
266 AZX_DRIVER_VIA,
267 AZX_DRIVER_SIS,
268 AZX_DRIVER_ULI,
269 AZX_DRIVER_NVIDIA,
270 AZX_DRIVER_TERA,
271 AZX_DRIVER_CTX,
272 AZX_DRIVER_CTHDA,
273 AZX_DRIVER_CMEDIA,
274 AZX_DRIVER_GENERIC,
275 AZX_NUM_DRIVERS, /* keep this as last entry */
276 };
277
278 #define azx_get_snoop_type(chip) \
279 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
280 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
281
282 /* quirks for old Intel chipsets */
283 #define AZX_DCAPS_INTEL_ICH \
284 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
285
286 /* quirks for Intel PCH */
287 #define AZX_DCAPS_INTEL_PCH_NOPM \
288 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
290
291 #define AZX_DCAPS_INTEL_PCH \
292 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
293
294 #define AZX_DCAPS_INTEL_HASWELL \
295 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
296 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
297 AZX_DCAPS_SNOOP_TYPE(SCH))
298
299 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
300 #define AZX_DCAPS_INTEL_BROADWELL \
301 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
302 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
303 AZX_DCAPS_SNOOP_TYPE(SCH))
304
305 #define AZX_DCAPS_INTEL_BAYTRAIL \
306 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
307
308 #define AZX_DCAPS_INTEL_BRASWELL \
309 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
310
311 #define AZX_DCAPS_INTEL_SKYLAKE \
312 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
313 AZX_DCAPS_I915_POWERWELL)
314
315 #define AZX_DCAPS_INTEL_BROXTON \
316 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
317 AZX_DCAPS_I915_POWERWELL)
318
319 /* quirks for ATI SB / AMD Hudson */
320 #define AZX_DCAPS_PRESET_ATI_SB \
321 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
322 AZX_DCAPS_SNOOP_TYPE(ATI))
323
324 /* quirks for ATI/AMD HDMI */
325 #define AZX_DCAPS_PRESET_ATI_HDMI \
326 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
327 AZX_DCAPS_NO_MSI64)
328
329 /* quirks for ATI HDMI with snoop off */
330 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
331 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
332
333 /* quirks for Nvidia */
334 #define AZX_DCAPS_PRESET_NVIDIA \
335 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
336 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
337 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
338
339 #define AZX_DCAPS_PRESET_CTHDA \
340 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
341 AZX_DCAPS_NO_64BIT |\
342 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
343
344 /*
345 * vga_switcheroo support
346 */
347 #ifdef SUPPORT_VGA_SWITCHEROO
348 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
349 #else
350 #define use_vga_switcheroo(chip) 0
351 #endif
352
353 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
354 ((pci)->device == 0x0c0c) || \
355 ((pci)->device == 0x0d0c) || \
356 ((pci)->device == 0x160c))
357
358 static char *driver_short_names[] = {
359 [AZX_DRIVER_ICH] = "HDA Intel",
360 [AZX_DRIVER_PCH] = "HDA Intel PCH",
361 [AZX_DRIVER_SCH] = "HDA Intel MID",
362 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
363 [AZX_DRIVER_ATI] = "HDA ATI SB",
364 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
365 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
366 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
367 [AZX_DRIVER_SIS] = "HDA SIS966",
368 [AZX_DRIVER_ULI] = "HDA ULI M5461",
369 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
370 [AZX_DRIVER_TERA] = "HDA Teradici",
371 [AZX_DRIVER_CTX] = "HDA Creative",
372 [AZX_DRIVER_CTHDA] = "HDA Creative",
373 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
374 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
375 };
376
377 #ifdef CONFIG_X86
378 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
379 {
380 int pages;
381
382 if (azx_snoop(chip))
383 return;
384 if (!dmab || !dmab->area || !dmab->bytes)
385 return;
386
387 #ifdef CONFIG_SND_DMA_SGBUF
388 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
389 struct snd_sg_buf *sgbuf = dmab->private_data;
390 if (chip->driver_type == AZX_DRIVER_CMEDIA)
391 return; /* deal with only CORB/RIRB buffers */
392 if (on)
393 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
394 else
395 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
396 return;
397 }
398 #endif
399
400 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
401 if (on)
402 set_memory_wc((unsigned long)dmab->area, pages);
403 else
404 set_memory_wb((unsigned long)dmab->area, pages);
405 }
406
407 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
408 bool on)
409 {
410 __mark_pages_wc(chip, buf, on);
411 }
412 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
413 struct snd_pcm_substream *substream, bool on)
414 {
415 if (azx_dev->wc_marked != on) {
416 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
417 azx_dev->wc_marked = on;
418 }
419 }
420 #else
421 /* NOP for other archs */
422 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
423 bool on)
424 {
425 }
426 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
427 struct snd_pcm_substream *substream, bool on)
428 {
429 }
430 #endif
431
432 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
433
434 /*
435 * initialize the PCI registers
436 */
437 /* update bits in a PCI register byte */
438 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
439 unsigned char mask, unsigned char val)
440 {
441 unsigned char data;
442
443 pci_read_config_byte(pci, reg, &data);
444 data &= ~mask;
445 data |= (val & mask);
446 pci_write_config_byte(pci, reg, data);
447 }
448
449 static void azx_init_pci(struct azx *chip)
450 {
451 int snoop_type = azx_get_snoop_type(chip);
452
453 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
454 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
455 * Ensuring these bits are 0 clears playback static on some HD Audio
456 * codecs.
457 * The PCI register TCSEL is defined in the Intel manuals.
458 */
459 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
460 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
461 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
462 }
463
464 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
465 * we need to enable snoop.
466 */
467 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
468 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
469 azx_snoop(chip));
470 update_pci_byte(chip->pci,
471 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
472 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
473 }
474
475 /* For NVIDIA HDA, enable snoop */
476 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
477 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
478 azx_snoop(chip));
479 update_pci_byte(chip->pci,
480 NVIDIA_HDA_TRANSREG_ADDR,
481 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
482 update_pci_byte(chip->pci,
483 NVIDIA_HDA_ISTRM_COH,
484 0x01, NVIDIA_HDA_ENABLE_COHBIT);
485 update_pci_byte(chip->pci,
486 NVIDIA_HDA_OSTRM_COH,
487 0x01, NVIDIA_HDA_ENABLE_COHBIT);
488 }
489
490 /* Enable SCH/PCH snoop if needed */
491 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
492 unsigned short snoop;
493 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
494 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
495 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
496 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
497 if (!azx_snoop(chip))
498 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
499 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
500 pci_read_config_word(chip->pci,
501 INTEL_SCH_HDA_DEVC, &snoop);
502 }
503 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
504 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
505 "Disabled" : "Enabled");
506 }
507 }
508
509 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
510 {
511 struct hdac_bus *bus = azx_bus(chip);
512
513 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
514 snd_hdac_set_codec_wakeup(bus, true);
515 azx_init_chip(chip, full_reset);
516 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
517 snd_hdac_set_codec_wakeup(bus, false);
518 }
519
520 /* calculate runtime delay from LPIB */
521 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
522 unsigned int pos)
523 {
524 struct snd_pcm_substream *substream = azx_dev->core.substream;
525 int stream = substream->stream;
526 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
527 int delay;
528
529 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
530 delay = pos - lpib_pos;
531 else
532 delay = lpib_pos - pos;
533 if (delay < 0) {
534 if (delay >= azx_dev->core.delay_negative_threshold)
535 delay = 0;
536 else
537 delay += azx_dev->core.bufsize;
538 }
539
540 if (delay >= azx_dev->core.period_bytes) {
541 dev_info(chip->card->dev,
542 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
543 delay, azx_dev->core.period_bytes);
544 delay = 0;
545 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
546 chip->get_delay[stream] = NULL;
547 }
548
549 return bytes_to_frames(substream->runtime, delay);
550 }
551
552 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
553
554 /* called from IRQ */
555 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
556 {
557 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
558 int ok;
559
560 ok = azx_position_ok(chip, azx_dev);
561 if (ok == 1) {
562 azx_dev->irq_pending = 0;
563 return ok;
564 } else if (ok == 0) {
565 /* bogus IRQ, process it later */
566 azx_dev->irq_pending = 1;
567 schedule_work(&hda->irq_pending_work);
568 }
569 return 0;
570 }
571
572 /* Enable/disable i915 display power for the link */
573 static int azx_intel_link_power(struct azx *chip, bool enable)
574 {
575 struct hdac_bus *bus = azx_bus(chip);
576
577 return snd_hdac_display_power(bus, enable);
578 }
579
580 /*
581 * Check whether the current DMA position is acceptable for updating
582 * periods. Returns non-zero if it's OK.
583 *
584 * Many HD-audio controllers appear pretty inaccurate about
585 * the update-IRQ timing. The IRQ is issued before actually the
586 * data is processed. So, we need to process it afterwords in a
587 * workqueue.
588 */
589 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
590 {
591 struct snd_pcm_substream *substream = azx_dev->core.substream;
592 int stream = substream->stream;
593 u32 wallclk;
594 unsigned int pos;
595
596 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
597 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
598 return -1; /* bogus (too early) interrupt */
599
600 if (chip->get_position[stream])
601 pos = chip->get_position[stream](chip, azx_dev);
602 else { /* use the position buffer as default */
603 pos = azx_get_pos_posbuf(chip, azx_dev);
604 if (!pos || pos == (u32)-1) {
605 dev_info(chip->card->dev,
606 "Invalid position buffer, using LPIB read method instead.\n");
607 chip->get_position[stream] = azx_get_pos_lpib;
608 if (chip->get_position[0] == azx_get_pos_lpib &&
609 chip->get_position[1] == azx_get_pos_lpib)
610 azx_bus(chip)->use_posbuf = false;
611 pos = azx_get_pos_lpib(chip, azx_dev);
612 chip->get_delay[stream] = NULL;
613 } else {
614 chip->get_position[stream] = azx_get_pos_posbuf;
615 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
616 chip->get_delay[stream] = azx_get_delay_from_lpib;
617 }
618 }
619
620 if (pos >= azx_dev->core.bufsize)
621 pos = 0;
622
623 if (WARN_ONCE(!azx_dev->core.period_bytes,
624 "hda-intel: zero azx_dev->period_bytes"))
625 return -1; /* this shouldn't happen! */
626 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
627 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
628 /* NG - it's below the first next period boundary */
629 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
630 azx_dev->core.start_wallclk += wallclk;
631 return 1; /* OK, it's fine */
632 }
633
634 /*
635 * The work for pending PCM period updates.
636 */
637 static void azx_irq_pending_work(struct work_struct *work)
638 {
639 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
640 struct azx *chip = &hda->chip;
641 struct hdac_bus *bus = azx_bus(chip);
642 struct hdac_stream *s;
643 int pending, ok;
644
645 if (!hda->irq_pending_warned) {
646 dev_info(chip->card->dev,
647 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
648 chip->card->number);
649 hda->irq_pending_warned = 1;
650 }
651
652 for (;;) {
653 pending = 0;
654 spin_lock_irq(&bus->reg_lock);
655 list_for_each_entry(s, &bus->stream_list, list) {
656 struct azx_dev *azx_dev = stream_to_azx_dev(s);
657 if (!azx_dev->irq_pending ||
658 !s->substream ||
659 !s->running)
660 continue;
661 ok = azx_position_ok(chip, azx_dev);
662 if (ok > 0) {
663 azx_dev->irq_pending = 0;
664 spin_unlock(&bus->reg_lock);
665 snd_pcm_period_elapsed(s->substream);
666 spin_lock(&bus->reg_lock);
667 } else if (ok < 0) {
668 pending = 0; /* too early */
669 } else
670 pending++;
671 }
672 spin_unlock_irq(&bus->reg_lock);
673 if (!pending)
674 return;
675 msleep(1);
676 }
677 }
678
679 /* clear irq_pending flags and assure no on-going workq */
680 static void azx_clear_irq_pending(struct azx *chip)
681 {
682 struct hdac_bus *bus = azx_bus(chip);
683 struct hdac_stream *s;
684
685 spin_lock_irq(&bus->reg_lock);
686 list_for_each_entry(s, &bus->stream_list, list) {
687 struct azx_dev *azx_dev = stream_to_azx_dev(s);
688 azx_dev->irq_pending = 0;
689 }
690 spin_unlock_irq(&bus->reg_lock);
691 }
692
693 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
694 {
695 struct hdac_bus *bus = azx_bus(chip);
696
697 if (request_irq(chip->pci->irq, azx_interrupt,
698 chip->msi ? 0 : IRQF_SHARED,
699 KBUILD_MODNAME, chip)) {
700 dev_err(chip->card->dev,
701 "unable to grab IRQ %d, disabling device\n",
702 chip->pci->irq);
703 if (do_disconnect)
704 snd_card_disconnect(chip->card);
705 return -1;
706 }
707 bus->irq = chip->pci->irq;
708 pci_intx(chip->pci, !chip->msi);
709 return 0;
710 }
711
712 /* get the current DMA position with correction on VIA chips */
713 static unsigned int azx_via_get_position(struct azx *chip,
714 struct azx_dev *azx_dev)
715 {
716 unsigned int link_pos, mini_pos, bound_pos;
717 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
718 unsigned int fifo_size;
719
720 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
721 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
722 /* Playback, no problem using link position */
723 return link_pos;
724 }
725
726 /* Capture */
727 /* For new chipset,
728 * use mod to get the DMA position just like old chipset
729 */
730 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
731 mod_dma_pos %= azx_dev->core.period_bytes;
732
733 /* azx_dev->fifo_size can't get FIFO size of in stream.
734 * Get from base address + offset.
735 */
736 fifo_size = readw(azx_bus(chip)->remap_addr +
737 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
738
739 if (azx_dev->insufficient) {
740 /* Link position never gather than FIFO size */
741 if (link_pos <= fifo_size)
742 return 0;
743
744 azx_dev->insufficient = 0;
745 }
746
747 if (link_pos <= fifo_size)
748 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
749 else
750 mini_pos = link_pos - fifo_size;
751
752 /* Find nearest previous boudary */
753 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
754 mod_link_pos = link_pos % azx_dev->core.period_bytes;
755 if (mod_link_pos >= fifo_size)
756 bound_pos = link_pos - mod_link_pos;
757 else if (mod_dma_pos >= mod_mini_pos)
758 bound_pos = mini_pos - mod_mini_pos;
759 else {
760 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
761 if (bound_pos >= azx_dev->core.bufsize)
762 bound_pos = 0;
763 }
764
765 /* Calculate real DMA position we want */
766 return bound_pos + mod_dma_pos;
767 }
768
769 #ifdef CONFIG_PM
770 static DEFINE_MUTEX(card_list_lock);
771 static LIST_HEAD(card_list);
772
773 static void azx_add_card_list(struct azx *chip)
774 {
775 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
776 mutex_lock(&card_list_lock);
777 list_add(&hda->list, &card_list);
778 mutex_unlock(&card_list_lock);
779 }
780
781 static void azx_del_card_list(struct azx *chip)
782 {
783 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
784 mutex_lock(&card_list_lock);
785 list_del_init(&hda->list);
786 mutex_unlock(&card_list_lock);
787 }
788
789 /* trigger power-save check at writing parameter */
790 static int param_set_xint(const char *val, const struct kernel_param *kp)
791 {
792 struct hda_intel *hda;
793 struct azx *chip;
794 int prev = power_save;
795 int ret = param_set_int(val, kp);
796
797 if (ret || prev == power_save)
798 return ret;
799
800 mutex_lock(&card_list_lock);
801 list_for_each_entry(hda, &card_list, list) {
802 chip = &hda->chip;
803 if (!hda->probe_continued || chip->disabled)
804 continue;
805 snd_hda_set_power_save(&chip->bus, power_save * 1000);
806 }
807 mutex_unlock(&card_list_lock);
808 return 0;
809 }
810 #else
811 #define azx_add_card_list(chip) /* NOP */
812 #define azx_del_card_list(chip) /* NOP */
813 #endif /* CONFIG_PM */
814
815 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
816 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
817 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
818 * BCLK = CDCLK * M / N
819 * The values will be lost when the display power well is disabled and need to
820 * be restored to avoid abnormal playback speed.
821 */
822 static void haswell_set_bclk(struct hda_intel *hda)
823 {
824 struct azx *chip = &hda->chip;
825 int cdclk_freq;
826 unsigned int bclk_m, bclk_n;
827
828 if (!hda->need_i915_power)
829 return;
830
831 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
832 switch (cdclk_freq) {
833 case 337500:
834 bclk_m = 16;
835 bclk_n = 225;
836 break;
837
838 case 450000:
839 default: /* default CDCLK 450MHz */
840 bclk_m = 4;
841 bclk_n = 75;
842 break;
843
844 case 540000:
845 bclk_m = 4;
846 bclk_n = 90;
847 break;
848
849 case 675000:
850 bclk_m = 8;
851 bclk_n = 225;
852 break;
853 }
854
855 azx_writew(chip, HSW_EM4, bclk_m);
856 azx_writew(chip, HSW_EM5, bclk_n);
857 }
858
859 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
860 /*
861 * power management
862 */
863 static int azx_suspend(struct device *dev)
864 {
865 struct snd_card *card = dev_get_drvdata(dev);
866 struct azx *chip;
867 struct hda_intel *hda;
868 struct hdac_bus *bus;
869
870 if (!card)
871 return 0;
872
873 chip = card->private_data;
874 hda = container_of(chip, struct hda_intel, chip);
875 if (chip->disabled || hda->init_failed || !chip->running)
876 return 0;
877
878 bus = azx_bus(chip);
879 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
880 azx_clear_irq_pending(chip);
881 azx_stop_chip(chip);
882 azx_enter_link_reset(chip);
883 if (bus->irq >= 0) {
884 free_irq(bus->irq, chip);
885 bus->irq = -1;
886 }
887
888 if (chip->msi)
889 pci_disable_msi(chip->pci);
890 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
891 && hda->need_i915_power)
892 snd_hdac_display_power(bus, false);
893
894 trace_azx_suspend(chip);
895 return 0;
896 }
897
898 static int azx_resume(struct device *dev)
899 {
900 struct pci_dev *pci = to_pci_dev(dev);
901 struct snd_card *card = dev_get_drvdata(dev);
902 struct azx *chip;
903 struct hda_intel *hda;
904
905 if (!card)
906 return 0;
907
908 chip = card->private_data;
909 hda = container_of(chip, struct hda_intel, chip);
910 if (chip->disabled || hda->init_failed || !chip->running)
911 return 0;
912
913 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
914 && hda->need_i915_power) {
915 snd_hdac_display_power(azx_bus(chip), true);
916 haswell_set_bclk(hda);
917 }
918 if (chip->msi)
919 if (pci_enable_msi(pci) < 0)
920 chip->msi = 0;
921 if (azx_acquire_irq(chip, 1) < 0)
922 return -EIO;
923 azx_init_pci(chip);
924
925 hda_intel_init_chip(chip, true);
926
927 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
928
929 trace_azx_resume(chip);
930 return 0;
931 }
932 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
933
934 #ifdef CONFIG_PM
935 static int azx_runtime_suspend(struct device *dev)
936 {
937 struct snd_card *card = dev_get_drvdata(dev);
938 struct azx *chip;
939 struct hda_intel *hda;
940
941 if (!card)
942 return 0;
943
944 chip = card->private_data;
945 hda = container_of(chip, struct hda_intel, chip);
946 if (chip->disabled || hda->init_failed)
947 return 0;
948
949 if (!azx_has_pm_runtime(chip))
950 return 0;
951
952 /* enable controller wake up event */
953 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
954 STATESTS_INT_MASK);
955
956 azx_stop_chip(chip);
957 azx_enter_link_reset(chip);
958 azx_clear_irq_pending(chip);
959 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
960 && hda->need_i915_power)
961 snd_hdac_display_power(azx_bus(chip), false);
962
963 trace_azx_runtime_suspend(chip);
964 return 0;
965 }
966
967 static int azx_runtime_resume(struct device *dev)
968 {
969 struct snd_card *card = dev_get_drvdata(dev);
970 struct azx *chip;
971 struct hda_intel *hda;
972 struct hdac_bus *bus;
973 struct hda_codec *codec;
974 int status;
975
976 if (!card)
977 return 0;
978
979 chip = card->private_data;
980 hda = container_of(chip, struct hda_intel, chip);
981 if (chip->disabled || hda->init_failed)
982 return 0;
983
984 if (!azx_has_pm_runtime(chip))
985 return 0;
986
987 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
988 bus = azx_bus(chip);
989 if (hda->need_i915_power) {
990 snd_hdac_display_power(bus, true);
991 haswell_set_bclk(hda);
992 } else {
993 /* toggle codec wakeup bit for STATESTS read */
994 snd_hdac_set_codec_wakeup(bus, true);
995 snd_hdac_set_codec_wakeup(bus, false);
996 }
997 }
998
999 /* Read STATESTS before controller reset */
1000 status = azx_readw(chip, STATESTS);
1001
1002 azx_init_pci(chip);
1003 hda_intel_init_chip(chip, true);
1004
1005 if (status) {
1006 list_for_each_codec(codec, &chip->bus)
1007 if (status & (1 << codec->addr))
1008 schedule_delayed_work(&codec->jackpoll_work,
1009 codec->jackpoll_interval);
1010 }
1011
1012 /* disable controller Wake Up event*/
1013 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1014 ~STATESTS_INT_MASK);
1015
1016 trace_azx_runtime_resume(chip);
1017 return 0;
1018 }
1019
1020 static int azx_runtime_idle(struct device *dev)
1021 {
1022 struct snd_card *card = dev_get_drvdata(dev);
1023 struct azx *chip;
1024 struct hda_intel *hda;
1025
1026 if (!card)
1027 return 0;
1028
1029 chip = card->private_data;
1030 hda = container_of(chip, struct hda_intel, chip);
1031 if (chip->disabled || hda->init_failed)
1032 return 0;
1033
1034 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1035 azx_bus(chip)->codec_powered || !chip->running)
1036 return -EBUSY;
1037
1038 return 0;
1039 }
1040
1041 static const struct dev_pm_ops azx_pm = {
1042 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1043 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1044 };
1045
1046 #define AZX_PM_OPS &azx_pm
1047 #else
1048 #define AZX_PM_OPS NULL
1049 #endif /* CONFIG_PM */
1050
1051
1052 static int azx_probe_continue(struct azx *chip);
1053
1054 #ifdef SUPPORT_VGA_SWITCHEROO
1055 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1056
1057 static void azx_vs_set_state(struct pci_dev *pci,
1058 enum vga_switcheroo_state state)
1059 {
1060 struct snd_card *card = pci_get_drvdata(pci);
1061 struct azx *chip = card->private_data;
1062 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1063 bool disabled;
1064
1065 wait_for_completion(&hda->probe_wait);
1066 if (hda->init_failed)
1067 return;
1068
1069 disabled = (state == VGA_SWITCHEROO_OFF);
1070 if (chip->disabled == disabled)
1071 return;
1072
1073 if (!hda->probe_continued) {
1074 chip->disabled = disabled;
1075 if (!disabled) {
1076 dev_info(chip->card->dev,
1077 "Start delayed initialization\n");
1078 if (azx_probe_continue(chip) < 0) {
1079 dev_err(chip->card->dev, "initialization error\n");
1080 hda->init_failed = true;
1081 }
1082 }
1083 } else {
1084 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1085 disabled ? "Disabling" : "Enabling");
1086 if (disabled) {
1087 pm_runtime_put_sync_suspend(card->dev);
1088 azx_suspend(card->dev);
1089 /* when we get suspended by vga_switcheroo we end up in D3cold,
1090 * however we have no ACPI handle, so pci/acpi can't put us there,
1091 * put ourselves there */
1092 pci->current_state = PCI_D3cold;
1093 chip->disabled = true;
1094 if (snd_hda_lock_devices(&chip->bus))
1095 dev_warn(chip->card->dev,
1096 "Cannot lock devices!\n");
1097 } else {
1098 snd_hda_unlock_devices(&chip->bus);
1099 pm_runtime_get_noresume(card->dev);
1100 chip->disabled = false;
1101 azx_resume(card->dev);
1102 }
1103 }
1104 }
1105
1106 static bool azx_vs_can_switch(struct pci_dev *pci)
1107 {
1108 struct snd_card *card = pci_get_drvdata(pci);
1109 struct azx *chip = card->private_data;
1110 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1111
1112 wait_for_completion(&hda->probe_wait);
1113 if (hda->init_failed)
1114 return false;
1115 if (chip->disabled || !hda->probe_continued)
1116 return true;
1117 if (snd_hda_lock_devices(&chip->bus))
1118 return false;
1119 snd_hda_unlock_devices(&chip->bus);
1120 return true;
1121 }
1122
1123 static void init_vga_switcheroo(struct azx *chip)
1124 {
1125 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1126 struct pci_dev *p = get_bound_vga(chip->pci);
1127 if (p) {
1128 dev_info(chip->card->dev,
1129 "Handle vga_switcheroo audio client\n");
1130 hda->use_vga_switcheroo = 1;
1131 pci_dev_put(p);
1132 }
1133 }
1134
1135 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1136 .set_gpu_state = azx_vs_set_state,
1137 .can_switch = azx_vs_can_switch,
1138 };
1139
1140 static int register_vga_switcheroo(struct azx *chip)
1141 {
1142 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1143 int err;
1144
1145 if (!hda->use_vga_switcheroo)
1146 return 0;
1147 /* FIXME: currently only handling DIS controller
1148 * is there any machine with two switchable HDMI audio controllers?
1149 */
1150 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1151 VGA_SWITCHEROO_DIS);
1152 if (err < 0)
1153 return err;
1154 hda->vga_switcheroo_registered = 1;
1155
1156 /* register as an optimus hdmi audio power domain */
1157 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1158 &hda->hdmi_pm_domain);
1159 return 0;
1160 }
1161 #else
1162 #define init_vga_switcheroo(chip) /* NOP */
1163 #define register_vga_switcheroo(chip) 0
1164 #define check_hdmi_disabled(pci) false
1165 #endif /* SUPPORT_VGA_SWITCHER */
1166
1167 /*
1168 * destructor
1169 */
1170 static int azx_free(struct azx *chip)
1171 {
1172 struct pci_dev *pci = chip->pci;
1173 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1174 struct hdac_bus *bus = azx_bus(chip);
1175
1176 if (azx_has_pm_runtime(chip) && chip->running)
1177 pm_runtime_get_noresume(&pci->dev);
1178
1179 azx_del_card_list(chip);
1180
1181 hda->init_failed = 1; /* to be sure */
1182 complete_all(&hda->probe_wait);
1183
1184 if (use_vga_switcheroo(hda)) {
1185 if (chip->disabled && hda->probe_continued)
1186 snd_hda_unlock_devices(&chip->bus);
1187 if (hda->vga_switcheroo_registered)
1188 vga_switcheroo_unregister_client(chip->pci);
1189 }
1190
1191 if (bus->chip_init) {
1192 azx_clear_irq_pending(chip);
1193 azx_stop_all_streams(chip);
1194 azx_stop_chip(chip);
1195 }
1196
1197 if (bus->irq >= 0)
1198 free_irq(bus->irq, (void*)chip);
1199 if (chip->msi)
1200 pci_disable_msi(chip->pci);
1201 iounmap(bus->remap_addr);
1202
1203 azx_free_stream_pages(chip);
1204 azx_free_streams(chip);
1205 snd_hdac_bus_exit(bus);
1206
1207 if (chip->region_requested)
1208 pci_release_regions(chip->pci);
1209
1210 pci_disable_device(chip->pci);
1211 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1212 release_firmware(chip->fw);
1213 #endif
1214
1215 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1216 if (hda->need_i915_power)
1217 snd_hdac_display_power(bus, false);
1218 snd_hdac_i915_exit(bus);
1219 }
1220 kfree(hda);
1221
1222 return 0;
1223 }
1224
1225 static int azx_dev_disconnect(struct snd_device *device)
1226 {
1227 struct azx *chip = device->device_data;
1228
1229 chip->bus.shutdown = 1;
1230 return 0;
1231 }
1232
1233 static int azx_dev_free(struct snd_device *device)
1234 {
1235 return azx_free(device->device_data);
1236 }
1237
1238 #ifdef SUPPORT_VGA_SWITCHEROO
1239 /*
1240 * Check of disabled HDMI controller by vga_switcheroo
1241 */
1242 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1243 {
1244 struct pci_dev *p;
1245
1246 /* check only discrete GPU */
1247 switch (pci->vendor) {
1248 case PCI_VENDOR_ID_ATI:
1249 case PCI_VENDOR_ID_AMD:
1250 case PCI_VENDOR_ID_NVIDIA:
1251 if (pci->devfn == 1) {
1252 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1253 pci->bus->number, 0);
1254 if (p) {
1255 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1256 return p;
1257 pci_dev_put(p);
1258 }
1259 }
1260 break;
1261 }
1262 return NULL;
1263 }
1264
1265 static bool check_hdmi_disabled(struct pci_dev *pci)
1266 {
1267 bool vga_inactive = false;
1268 struct pci_dev *p = get_bound_vga(pci);
1269
1270 if (p) {
1271 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1272 vga_inactive = true;
1273 pci_dev_put(p);
1274 }
1275 return vga_inactive;
1276 }
1277 #endif /* SUPPORT_VGA_SWITCHEROO */
1278
1279 /*
1280 * white/black-listing for position_fix
1281 */
1282 static struct snd_pci_quirk position_fix_list[] = {
1283 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1284 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1285 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1286 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1287 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1288 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1289 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1290 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1291 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1292 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1293 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1294 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1295 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1296 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1297 {}
1298 };
1299
1300 static int check_position_fix(struct azx *chip, int fix)
1301 {
1302 const struct snd_pci_quirk *q;
1303
1304 switch (fix) {
1305 case POS_FIX_AUTO:
1306 case POS_FIX_LPIB:
1307 case POS_FIX_POSBUF:
1308 case POS_FIX_VIACOMBO:
1309 case POS_FIX_COMBO:
1310 return fix;
1311 }
1312
1313 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1314 if (q) {
1315 dev_info(chip->card->dev,
1316 "position_fix set to %d for device %04x:%04x\n",
1317 q->value, q->subvendor, q->subdevice);
1318 return q->value;
1319 }
1320
1321 /* Check VIA/ATI HD Audio Controller exist */
1322 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1323 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1324 return POS_FIX_VIACOMBO;
1325 }
1326 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1327 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1328 return POS_FIX_LPIB;
1329 }
1330 return POS_FIX_AUTO;
1331 }
1332
1333 static void assign_position_fix(struct azx *chip, int fix)
1334 {
1335 static azx_get_pos_callback_t callbacks[] = {
1336 [POS_FIX_AUTO] = NULL,
1337 [POS_FIX_LPIB] = azx_get_pos_lpib,
1338 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1339 [POS_FIX_VIACOMBO] = azx_via_get_position,
1340 [POS_FIX_COMBO] = azx_get_pos_lpib,
1341 };
1342
1343 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1344
1345 /* combo mode uses LPIB only for playback */
1346 if (fix == POS_FIX_COMBO)
1347 chip->get_position[1] = NULL;
1348
1349 if (fix == POS_FIX_POSBUF &&
1350 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1351 chip->get_delay[0] = chip->get_delay[1] =
1352 azx_get_delay_from_lpib;
1353 }
1354
1355 }
1356
1357 /*
1358 * black-lists for probe_mask
1359 */
1360 static struct snd_pci_quirk probe_mask_list[] = {
1361 /* Thinkpad often breaks the controller communication when accessing
1362 * to the non-working (or non-existing) modem codec slot.
1363 */
1364 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1365 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1366 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1367 /* broken BIOS */
1368 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1369 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1370 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1371 /* forced codec slots */
1372 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1373 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1374 /* WinFast VP200 H (Teradici) user reported broken communication */
1375 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1376 {}
1377 };
1378
1379 #define AZX_FORCE_CODEC_MASK 0x100
1380
1381 static void check_probe_mask(struct azx *chip, int dev)
1382 {
1383 const struct snd_pci_quirk *q;
1384
1385 chip->codec_probe_mask = probe_mask[dev];
1386 if (chip->codec_probe_mask == -1) {
1387 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1388 if (q) {
1389 dev_info(chip->card->dev,
1390 "probe_mask set to 0x%x for device %04x:%04x\n",
1391 q->value, q->subvendor, q->subdevice);
1392 chip->codec_probe_mask = q->value;
1393 }
1394 }
1395
1396 /* check forced option */
1397 if (chip->codec_probe_mask != -1 &&
1398 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1399 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1400 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1401 (int)azx_bus(chip)->codec_mask);
1402 }
1403 }
1404
1405 /*
1406 * white/black-list for enable_msi
1407 */
1408 static struct snd_pci_quirk msi_black_list[] = {
1409 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1410 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1411 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1412 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1413 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1414 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1415 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1416 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1417 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1418 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1419 {}
1420 };
1421
1422 static void check_msi(struct azx *chip)
1423 {
1424 const struct snd_pci_quirk *q;
1425
1426 if (enable_msi >= 0) {
1427 chip->msi = !!enable_msi;
1428 return;
1429 }
1430 chip->msi = 1; /* enable MSI as default */
1431 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1432 if (q) {
1433 dev_info(chip->card->dev,
1434 "msi for device %04x:%04x set to %d\n",
1435 q->subvendor, q->subdevice, q->value);
1436 chip->msi = q->value;
1437 return;
1438 }
1439
1440 /* NVidia chipsets seem to cause troubles with MSI */
1441 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1442 dev_info(chip->card->dev, "Disabling MSI\n");
1443 chip->msi = 0;
1444 }
1445 }
1446
1447 /* check the snoop mode availability */
1448 static void azx_check_snoop_available(struct azx *chip)
1449 {
1450 int snoop = hda_snoop;
1451
1452 if (snoop >= 0) {
1453 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1454 snoop ? "snoop" : "non-snoop");
1455 chip->snoop = snoop;
1456 return;
1457 }
1458
1459 snoop = true;
1460 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1461 chip->driver_type == AZX_DRIVER_VIA) {
1462 /* force to non-snoop mode for a new VIA controller
1463 * when BIOS is set
1464 */
1465 u8 val;
1466 pci_read_config_byte(chip->pci, 0x42, &val);
1467 if (!(val & 0x80) && chip->pci->revision == 0x30)
1468 snoop = false;
1469 }
1470
1471 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1472 snoop = false;
1473
1474 chip->snoop = snoop;
1475 if (!snoop)
1476 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1477 }
1478
1479 static void azx_probe_work(struct work_struct *work)
1480 {
1481 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1482 azx_probe_continue(&hda->chip);
1483 }
1484
1485 /*
1486 * constructor
1487 */
1488 static const struct hdac_io_ops pci_hda_io_ops;
1489 static const struct hda_controller_ops pci_hda_ops;
1490
1491 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1492 int dev, unsigned int driver_caps,
1493 struct azx **rchip)
1494 {
1495 static struct snd_device_ops ops = {
1496 .dev_disconnect = azx_dev_disconnect,
1497 .dev_free = azx_dev_free,
1498 };
1499 struct hda_intel *hda;
1500 struct azx *chip;
1501 int err;
1502
1503 *rchip = NULL;
1504
1505 err = pci_enable_device(pci);
1506 if (err < 0)
1507 return err;
1508
1509 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1510 if (!hda) {
1511 pci_disable_device(pci);
1512 return -ENOMEM;
1513 }
1514
1515 chip = &hda->chip;
1516 mutex_init(&chip->open_mutex);
1517 chip->card = card;
1518 chip->pci = pci;
1519 chip->ops = &pci_hda_ops;
1520 chip->driver_caps = driver_caps;
1521 chip->driver_type = driver_caps & 0xff;
1522 check_msi(chip);
1523 chip->dev_index = dev;
1524 chip->jackpoll_ms = jackpoll_ms;
1525 INIT_LIST_HEAD(&chip->pcm_list);
1526 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1527 INIT_LIST_HEAD(&hda->list);
1528 init_vga_switcheroo(chip);
1529 init_completion(&hda->probe_wait);
1530
1531 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1532
1533 check_probe_mask(chip, dev);
1534
1535 chip->single_cmd = single_cmd;
1536 azx_check_snoop_available(chip);
1537
1538 if (bdl_pos_adj[dev] < 0) {
1539 switch (chip->driver_type) {
1540 case AZX_DRIVER_ICH:
1541 case AZX_DRIVER_PCH:
1542 bdl_pos_adj[dev] = 1;
1543 break;
1544 default:
1545 bdl_pos_adj[dev] = 32;
1546 break;
1547 }
1548 }
1549 chip->bdl_pos_adj = bdl_pos_adj;
1550
1551 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1552 if (err < 0) {
1553 kfree(hda);
1554 pci_disable_device(pci);
1555 return err;
1556 }
1557
1558 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1559 if (err < 0) {
1560 dev_err(card->dev, "Error creating device [card]!\n");
1561 azx_free(chip);
1562 return err;
1563 }
1564
1565 /* continue probing in work context as may trigger request module */
1566 INIT_WORK(&hda->probe_work, azx_probe_work);
1567
1568 *rchip = chip;
1569
1570 return 0;
1571 }
1572
1573 static int azx_first_init(struct azx *chip)
1574 {
1575 int dev = chip->dev_index;
1576 struct pci_dev *pci = chip->pci;
1577 struct snd_card *card = chip->card;
1578 struct hdac_bus *bus = azx_bus(chip);
1579 int err;
1580 unsigned short gcap;
1581 unsigned int dma_bits = 64;
1582
1583 #if BITS_PER_LONG != 64
1584 /* Fix up base address on ULI M5461 */
1585 if (chip->driver_type == AZX_DRIVER_ULI) {
1586 u16 tmp3;
1587 pci_read_config_word(pci, 0x40, &tmp3);
1588 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1589 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1590 }
1591 #endif
1592
1593 err = pci_request_regions(pci, "ICH HD audio");
1594 if (err < 0)
1595 return err;
1596 chip->region_requested = 1;
1597
1598 bus->addr = pci_resource_start(pci, 0);
1599 bus->remap_addr = pci_ioremap_bar(pci, 0);
1600 if (bus->remap_addr == NULL) {
1601 dev_err(card->dev, "ioremap error\n");
1602 return -ENXIO;
1603 }
1604
1605 if (chip->msi) {
1606 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1607 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1608 pci->no_64bit_msi = true;
1609 }
1610 if (pci_enable_msi(pci) < 0)
1611 chip->msi = 0;
1612 }
1613
1614 if (azx_acquire_irq(chip, 0) < 0)
1615 return -EBUSY;
1616
1617 pci_set_master(pci);
1618 synchronize_irq(bus->irq);
1619
1620 gcap = azx_readw(chip, GCAP);
1621 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1622
1623 /* AMD devices support 40 or 48bit DMA, take the safe one */
1624 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1625 dma_bits = 40;
1626
1627 /* disable SB600 64bit support for safety */
1628 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1629 struct pci_dev *p_smbus;
1630 dma_bits = 40;
1631 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1632 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1633 NULL);
1634 if (p_smbus) {
1635 if (p_smbus->revision < 0x30)
1636 gcap &= ~AZX_GCAP_64OK;
1637 pci_dev_put(p_smbus);
1638 }
1639 }
1640
1641 /* disable 64bit DMA address on some devices */
1642 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1643 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1644 gcap &= ~AZX_GCAP_64OK;
1645 }
1646
1647 /* disable buffer size rounding to 128-byte multiples if supported */
1648 if (align_buffer_size >= 0)
1649 chip->align_buffer_size = !!align_buffer_size;
1650 else {
1651 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1652 chip->align_buffer_size = 0;
1653 else
1654 chip->align_buffer_size = 1;
1655 }
1656
1657 /* allow 64bit DMA address if supported by H/W */
1658 if (!(gcap & AZX_GCAP_64OK))
1659 dma_bits = 32;
1660 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1661 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1662 } else {
1663 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1664 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1665 }
1666
1667 /* read number of streams from GCAP register instead of using
1668 * hardcoded value
1669 */
1670 chip->capture_streams = (gcap >> 8) & 0x0f;
1671 chip->playback_streams = (gcap >> 12) & 0x0f;
1672 if (!chip->playback_streams && !chip->capture_streams) {
1673 /* gcap didn't give any info, switching to old method */
1674
1675 switch (chip->driver_type) {
1676 case AZX_DRIVER_ULI:
1677 chip->playback_streams = ULI_NUM_PLAYBACK;
1678 chip->capture_streams = ULI_NUM_CAPTURE;
1679 break;
1680 case AZX_DRIVER_ATIHDMI:
1681 case AZX_DRIVER_ATIHDMI_NS:
1682 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1683 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1684 break;
1685 case AZX_DRIVER_GENERIC:
1686 default:
1687 chip->playback_streams = ICH6_NUM_PLAYBACK;
1688 chip->capture_streams = ICH6_NUM_CAPTURE;
1689 break;
1690 }
1691 }
1692 chip->capture_index_offset = 0;
1693 chip->playback_index_offset = chip->capture_streams;
1694 chip->num_streams = chip->playback_streams + chip->capture_streams;
1695
1696 /* initialize streams */
1697 err = azx_init_streams(chip);
1698 if (err < 0)
1699 return err;
1700
1701 err = azx_alloc_stream_pages(chip);
1702 if (err < 0)
1703 return err;
1704
1705 /* initialize chip */
1706 azx_init_pci(chip);
1707
1708 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1709 struct hda_intel *hda;
1710
1711 hda = container_of(chip, struct hda_intel, chip);
1712 haswell_set_bclk(hda);
1713 }
1714
1715 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1716
1717 /* codec detection */
1718 if (!azx_bus(chip)->codec_mask) {
1719 dev_err(card->dev, "no codecs found!\n");
1720 return -ENODEV;
1721 }
1722
1723 strcpy(card->driver, "HDA-Intel");
1724 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1725 sizeof(card->shortname));
1726 snprintf(card->longname, sizeof(card->longname),
1727 "%s at 0x%lx irq %i",
1728 card->shortname, bus->addr, bus->irq);
1729
1730 return 0;
1731 }
1732
1733 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1734 /* callback from request_firmware_nowait() */
1735 static void azx_firmware_cb(const struct firmware *fw, void *context)
1736 {
1737 struct snd_card *card = context;
1738 struct azx *chip = card->private_data;
1739 struct pci_dev *pci = chip->pci;
1740
1741 if (!fw) {
1742 dev_err(card->dev, "Cannot load firmware, aborting\n");
1743 goto error;
1744 }
1745
1746 chip->fw = fw;
1747 if (!chip->disabled) {
1748 /* continue probing */
1749 if (azx_probe_continue(chip))
1750 goto error;
1751 }
1752 return; /* OK */
1753
1754 error:
1755 snd_card_free(card);
1756 pci_set_drvdata(pci, NULL);
1757 }
1758 #endif
1759
1760 /*
1761 * HDA controller ops.
1762 */
1763
1764 /* PCI register access. */
1765 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1766 {
1767 writel(value, addr);
1768 }
1769
1770 static u32 pci_azx_readl(u32 __iomem *addr)
1771 {
1772 return readl(addr);
1773 }
1774
1775 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1776 {
1777 writew(value, addr);
1778 }
1779
1780 static u16 pci_azx_readw(u16 __iomem *addr)
1781 {
1782 return readw(addr);
1783 }
1784
1785 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1786 {
1787 writeb(value, addr);
1788 }
1789
1790 static u8 pci_azx_readb(u8 __iomem *addr)
1791 {
1792 return readb(addr);
1793 }
1794
1795 static int disable_msi_reset_irq(struct azx *chip)
1796 {
1797 struct hdac_bus *bus = azx_bus(chip);
1798 int err;
1799
1800 free_irq(bus->irq, chip);
1801 bus->irq = -1;
1802 pci_disable_msi(chip->pci);
1803 chip->msi = 0;
1804 err = azx_acquire_irq(chip, 1);
1805 if (err < 0)
1806 return err;
1807
1808 return 0;
1809 }
1810
1811 /* DMA page allocation helpers. */
1812 static int dma_alloc_pages(struct hdac_bus *bus,
1813 int type,
1814 size_t size,
1815 struct snd_dma_buffer *buf)
1816 {
1817 struct azx *chip = bus_to_azx(bus);
1818 int err;
1819
1820 err = snd_dma_alloc_pages(type,
1821 bus->dev,
1822 size, buf);
1823 if (err < 0)
1824 return err;
1825 mark_pages_wc(chip, buf, true);
1826 return 0;
1827 }
1828
1829 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1830 {
1831 struct azx *chip = bus_to_azx(bus);
1832
1833 mark_pages_wc(chip, buf, false);
1834 snd_dma_free_pages(buf);
1835 }
1836
1837 static int substream_alloc_pages(struct azx *chip,
1838 struct snd_pcm_substream *substream,
1839 size_t size)
1840 {
1841 struct azx_dev *azx_dev = get_azx_dev(substream);
1842 int ret;
1843
1844 mark_runtime_wc(chip, azx_dev, substream, false);
1845 ret = snd_pcm_lib_malloc_pages(substream, size);
1846 if (ret < 0)
1847 return ret;
1848 mark_runtime_wc(chip, azx_dev, substream, true);
1849 return 0;
1850 }
1851
1852 static int substream_free_pages(struct azx *chip,
1853 struct snd_pcm_substream *substream)
1854 {
1855 struct azx_dev *azx_dev = get_azx_dev(substream);
1856 mark_runtime_wc(chip, azx_dev, substream, false);
1857 return snd_pcm_lib_free_pages(substream);
1858 }
1859
1860 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1861 struct vm_area_struct *area)
1862 {
1863 #ifdef CONFIG_X86
1864 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1865 struct azx *chip = apcm->chip;
1866 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1867 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1868 #endif
1869 }
1870
1871 static const struct hdac_io_ops pci_hda_io_ops = {
1872 .reg_writel = pci_azx_writel,
1873 .reg_readl = pci_azx_readl,
1874 .reg_writew = pci_azx_writew,
1875 .reg_readw = pci_azx_readw,
1876 .reg_writeb = pci_azx_writeb,
1877 .reg_readb = pci_azx_readb,
1878 .dma_alloc_pages = dma_alloc_pages,
1879 .dma_free_pages = dma_free_pages,
1880 };
1881
1882 static const struct hda_controller_ops pci_hda_ops = {
1883 .disable_msi_reset_irq = disable_msi_reset_irq,
1884 .substream_alloc_pages = substream_alloc_pages,
1885 .substream_free_pages = substream_free_pages,
1886 .pcm_mmap_prepare = pcm_mmap_prepare,
1887 .position_check = azx_position_check,
1888 .link_power = azx_intel_link_power,
1889 };
1890
1891 static int azx_probe(struct pci_dev *pci,
1892 const struct pci_device_id *pci_id)
1893 {
1894 static int dev;
1895 struct snd_card *card;
1896 struct hda_intel *hda;
1897 struct azx *chip;
1898 bool schedule_probe;
1899 int err;
1900
1901 if (dev >= SNDRV_CARDS)
1902 return -ENODEV;
1903 if (!enable[dev]) {
1904 dev++;
1905 return -ENOENT;
1906 }
1907
1908 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1909 0, &card);
1910 if (err < 0) {
1911 dev_err(&pci->dev, "Error creating card!\n");
1912 return err;
1913 }
1914
1915 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1916 if (err < 0)
1917 goto out_free;
1918 card->private_data = chip;
1919 hda = container_of(chip, struct hda_intel, chip);
1920
1921 pci_set_drvdata(pci, card);
1922
1923 err = register_vga_switcheroo(chip);
1924 if (err < 0) {
1925 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1926 goto out_free;
1927 }
1928
1929 if (check_hdmi_disabled(pci)) {
1930 dev_info(card->dev, "VGA controller is disabled\n");
1931 dev_info(card->dev, "Delaying initialization\n");
1932 chip->disabled = true;
1933 }
1934
1935 schedule_probe = !chip->disabled;
1936
1937 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1938 if (patch[dev] && *patch[dev]) {
1939 dev_info(card->dev, "Applying patch firmware '%s'\n",
1940 patch[dev]);
1941 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1942 &pci->dev, GFP_KERNEL, card,
1943 azx_firmware_cb);
1944 if (err < 0)
1945 goto out_free;
1946 schedule_probe = false; /* continued in azx_firmware_cb() */
1947 }
1948 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1949
1950 #ifndef CONFIG_SND_HDA_I915
1951 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1952 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1953 #endif
1954
1955 if (schedule_probe)
1956 schedule_work(&hda->probe_work);
1957
1958 dev++;
1959 if (chip->disabled)
1960 complete_all(&hda->probe_wait);
1961 return 0;
1962
1963 out_free:
1964 snd_card_free(card);
1965 return err;
1966 }
1967
1968 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1969 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1970 [AZX_DRIVER_NVIDIA] = 8,
1971 [AZX_DRIVER_TERA] = 1,
1972 };
1973
1974 static int azx_probe_continue(struct azx *chip)
1975 {
1976 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1977 struct hdac_bus *bus = azx_bus(chip);
1978 struct pci_dev *pci = chip->pci;
1979 int dev = chip->dev_index;
1980 int err;
1981
1982 hda->probe_continued = 1;
1983
1984 /* Request display power well for the HDA controller or codec. For
1985 * Haswell/Broadwell, both the display HDA controller and codec need
1986 * this power. For other platforms, like Baytrail/Braswell, only the
1987 * display codec needs the power and it can be released after probe.
1988 */
1989 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1990 /* HSW/BDW controllers need this power */
1991 if (CONTROLLER_IN_GPU(pci))
1992 hda->need_i915_power = 1;
1993
1994 err = snd_hdac_i915_init(bus);
1995 if (err < 0) {
1996 /* if the controller is bound only with HDMI/DP
1997 * (for HSW and BDW), we need to abort the probe;
1998 * for other chips, still continue probing as other
1999 * codecs can be on the same link.
2000 */
2001 if (CONTROLLER_IN_GPU(pci))
2002 goto out_free;
2003 else
2004 goto skip_i915;
2005 }
2006
2007 err = snd_hdac_display_power(bus, true);
2008 if (err < 0) {
2009 dev_err(chip->card->dev,
2010 "Cannot turn on display power on i915\n");
2011 goto i915_power_fail;
2012 }
2013 }
2014
2015 skip_i915:
2016 err = azx_first_init(chip);
2017 if (err < 0)
2018 goto out_free;
2019
2020 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2021 chip->beep_mode = beep_mode[dev];
2022 #endif
2023
2024 /* create codec instances */
2025 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2026 if (err < 0)
2027 goto out_free;
2028
2029 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2030 if (chip->fw) {
2031 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2032 chip->fw->data);
2033 if (err < 0)
2034 goto out_free;
2035 #ifndef CONFIG_PM
2036 release_firmware(chip->fw); /* no longer needed */
2037 chip->fw = NULL;
2038 #endif
2039 }
2040 #endif
2041 if ((probe_only[dev] & 1) == 0) {
2042 err = azx_codec_configure(chip);
2043 if (err < 0)
2044 goto out_free;
2045 }
2046
2047 err = snd_card_register(chip->card);
2048 if (err < 0)
2049 goto out_free;
2050
2051 chip->running = 1;
2052 azx_add_card_list(chip);
2053 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2054 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2055 pm_runtime_put_noidle(&pci->dev);
2056
2057 out_free:
2058 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2059 && !hda->need_i915_power)
2060 snd_hdac_display_power(bus, false);
2061
2062 i915_power_fail:
2063 if (err < 0)
2064 hda->init_failed = 1;
2065 complete_all(&hda->probe_wait);
2066 return err;
2067 }
2068
2069 static void azx_remove(struct pci_dev *pci)
2070 {
2071 struct snd_card *card = pci_get_drvdata(pci);
2072
2073 if (card)
2074 snd_card_free(card);
2075 }
2076
2077 static void azx_shutdown(struct pci_dev *pci)
2078 {
2079 struct snd_card *card = pci_get_drvdata(pci);
2080 struct azx *chip;
2081
2082 if (!card)
2083 return;
2084 chip = card->private_data;
2085 if (chip && chip->running)
2086 azx_stop_chip(chip);
2087 }
2088
2089 /* PCI IDs */
2090 static const struct pci_device_id azx_ids[] = {
2091 /* CPT */
2092 { PCI_DEVICE(0x8086, 0x1c20),
2093 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2094 /* PBG */
2095 { PCI_DEVICE(0x8086, 0x1d20),
2096 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2097 /* Panther Point */
2098 { PCI_DEVICE(0x8086, 0x1e20),
2099 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2100 /* Lynx Point */
2101 { PCI_DEVICE(0x8086, 0x8c20),
2102 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2103 /* 9 Series */
2104 { PCI_DEVICE(0x8086, 0x8ca0),
2105 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2106 /* Wellsburg */
2107 { PCI_DEVICE(0x8086, 0x8d20),
2108 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2109 { PCI_DEVICE(0x8086, 0x8d21),
2110 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2111 /* Lewisburg */
2112 { PCI_DEVICE(0x8086, 0xa1f0),
2113 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2114 { PCI_DEVICE(0x8086, 0xa270),
2115 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2116 /* Lynx Point-LP */
2117 { PCI_DEVICE(0x8086, 0x9c20),
2118 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2119 /* Lynx Point-LP */
2120 { PCI_DEVICE(0x8086, 0x9c21),
2121 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2122 /* Wildcat Point-LP */
2123 { PCI_DEVICE(0x8086, 0x9ca0),
2124 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2125 /* Sunrise Point */
2126 { PCI_DEVICE(0x8086, 0xa170),
2127 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2128 /* Sunrise Point-LP */
2129 { PCI_DEVICE(0x8086, 0x9d70),
2130 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2131 /* Broxton-P(Apollolake) */
2132 { PCI_DEVICE(0x8086, 0x5a98),
2133 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2134 /* Haswell */
2135 { PCI_DEVICE(0x8086, 0x0a0c),
2136 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2137 { PCI_DEVICE(0x8086, 0x0c0c),
2138 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2139 { PCI_DEVICE(0x8086, 0x0d0c),
2140 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2141 /* Broadwell */
2142 { PCI_DEVICE(0x8086, 0x160c),
2143 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2144 /* 5 Series/3400 */
2145 { PCI_DEVICE(0x8086, 0x3b56),
2146 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2147 /* Poulsbo */
2148 { PCI_DEVICE(0x8086, 0x811b),
2149 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2150 /* Oaktrail */
2151 { PCI_DEVICE(0x8086, 0x080a),
2152 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2153 /* BayTrail */
2154 { PCI_DEVICE(0x8086, 0x0f04),
2155 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2156 /* Braswell */
2157 { PCI_DEVICE(0x8086, 0x2284),
2158 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2159 /* ICH6 */
2160 { PCI_DEVICE(0x8086, 0x2668),
2161 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2162 /* ICH7 */
2163 { PCI_DEVICE(0x8086, 0x27d8),
2164 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2165 /* ESB2 */
2166 { PCI_DEVICE(0x8086, 0x269a),
2167 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2168 /* ICH8 */
2169 { PCI_DEVICE(0x8086, 0x284b),
2170 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2171 /* ICH9 */
2172 { PCI_DEVICE(0x8086, 0x293e),
2173 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2174 /* ICH9 */
2175 { PCI_DEVICE(0x8086, 0x293f),
2176 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2177 /* ICH10 */
2178 { PCI_DEVICE(0x8086, 0x3a3e),
2179 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2180 /* ICH10 */
2181 { PCI_DEVICE(0x8086, 0x3a6e),
2182 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2183 /* Generic Intel */
2184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2185 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2186 .class_mask = 0xffffff,
2187 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2188 /* ATI SB 450/600/700/800/900 */
2189 { PCI_DEVICE(0x1002, 0x437b),
2190 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2191 { PCI_DEVICE(0x1002, 0x4383),
2192 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2193 /* AMD Hudson */
2194 { PCI_DEVICE(0x1022, 0x780d),
2195 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2196 /* ATI HDMI */
2197 { PCI_DEVICE(0x1002, 0x1308),
2198 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2199 { PCI_DEVICE(0x1002, 0x157a),
2200 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2201 { PCI_DEVICE(0x1002, 0x793b),
2202 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2203 { PCI_DEVICE(0x1002, 0x7919),
2204 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2205 { PCI_DEVICE(0x1002, 0x960f),
2206 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2207 { PCI_DEVICE(0x1002, 0x970f),
2208 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2209 { PCI_DEVICE(0x1002, 0x9840),
2210 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2211 { PCI_DEVICE(0x1002, 0xaa00),
2212 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2213 { PCI_DEVICE(0x1002, 0xaa08),
2214 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2215 { PCI_DEVICE(0x1002, 0xaa10),
2216 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2217 { PCI_DEVICE(0x1002, 0xaa18),
2218 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2219 { PCI_DEVICE(0x1002, 0xaa20),
2220 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2221 { PCI_DEVICE(0x1002, 0xaa28),
2222 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2223 { PCI_DEVICE(0x1002, 0xaa30),
2224 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2225 { PCI_DEVICE(0x1002, 0xaa38),
2226 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2227 { PCI_DEVICE(0x1002, 0xaa40),
2228 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2229 { PCI_DEVICE(0x1002, 0xaa48),
2230 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2231 { PCI_DEVICE(0x1002, 0xaa50),
2232 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2233 { PCI_DEVICE(0x1002, 0xaa58),
2234 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2235 { PCI_DEVICE(0x1002, 0xaa60),
2236 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2237 { PCI_DEVICE(0x1002, 0xaa68),
2238 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2239 { PCI_DEVICE(0x1002, 0xaa80),
2240 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2241 { PCI_DEVICE(0x1002, 0xaa88),
2242 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2243 { PCI_DEVICE(0x1002, 0xaa90),
2244 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2245 { PCI_DEVICE(0x1002, 0xaa98),
2246 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2247 { PCI_DEVICE(0x1002, 0x9902),
2248 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2249 { PCI_DEVICE(0x1002, 0xaaa0),
2250 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2251 { PCI_DEVICE(0x1002, 0xaaa8),
2252 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2253 { PCI_DEVICE(0x1002, 0xaab0),
2254 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2255 { PCI_DEVICE(0x1002, 0xaac0),
2256 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2257 { PCI_DEVICE(0x1002, 0xaac8),
2258 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2259 { PCI_DEVICE(0x1002, 0xaad8),
2260 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2261 { PCI_DEVICE(0x1002, 0xaae8),
2262 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2263 /* VIA VT8251/VT8237A */
2264 { PCI_DEVICE(0x1106, 0x3288),
2265 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2266 /* VIA GFX VT7122/VX900 */
2267 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2268 /* VIA GFX VT6122/VX11 */
2269 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2270 /* SIS966 */
2271 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2272 /* ULI M5461 */
2273 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2274 /* NVIDIA MCP */
2275 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2276 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2277 .class_mask = 0xffffff,
2278 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2279 /* Teradici */
2280 { PCI_DEVICE(0x6549, 0x1200),
2281 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2282 { PCI_DEVICE(0x6549, 0x2200),
2283 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2284 /* Creative X-Fi (CA0110-IBG) */
2285 /* CTHDA chips */
2286 { PCI_DEVICE(0x1102, 0x0010),
2287 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2288 { PCI_DEVICE(0x1102, 0x0012),
2289 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2290 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2291 /* the following entry conflicts with snd-ctxfi driver,
2292 * as ctxfi driver mutates from HD-audio to native mode with
2293 * a special command sequence.
2294 */
2295 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2296 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2297 .class_mask = 0xffffff,
2298 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2299 AZX_DCAPS_NO_64BIT |
2300 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2301 #else
2302 /* this entry seems still valid -- i.e. without emu20kx chip */
2303 { PCI_DEVICE(0x1102, 0x0009),
2304 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2305 AZX_DCAPS_NO_64BIT |
2306 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2307 #endif
2308 /* CM8888 */
2309 { PCI_DEVICE(0x13f6, 0x5011),
2310 .driver_data = AZX_DRIVER_CMEDIA |
2311 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2312 /* Vortex86MX */
2313 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2314 /* VMware HDAudio */
2315 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2316 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2317 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2318 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2319 .class_mask = 0xffffff,
2320 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2321 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2322 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2323 .class_mask = 0xffffff,
2324 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2325 { 0, }
2326 };
2327 MODULE_DEVICE_TABLE(pci, azx_ids);
2328
2329 /* pci_driver definition */
2330 static struct pci_driver azx_driver = {
2331 .name = KBUILD_MODNAME,
2332 .id_table = azx_ids,
2333 .probe = azx_probe,
2334 .remove = azx_remove,
2335 .shutdown = azx_shutdown,
2336 .driver = {
2337 .pm = AZX_PM_OPS,
2338 },
2339 };
2340
2341 module_pci_driver(azx_driver);
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