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[ALSA] hdsp - Fix section mismatch
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55 static char *model[SNDRV_CARDS];
56 static int position_fix[SNDRV_CARDS];
57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
58 static int single_cmd;
59 static int enable_msi;
60
61 module_param_array(index, int, NULL, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param_array(enable, bool, NULL, 0444);
66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
67 module_param_array(model, charp, NULL, 0444);
68 MODULE_PARM_DESC(model, "Use the given board model.");
69 module_param_array(position_fix, int, NULL, 0444);
70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask, int, NULL, 0444);
73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd, bool, 0444);
75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi, int, 0444);
78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
79
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
82
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
85 * wake up.
86 */
87 static int power_save_controller = 1;
88 module_param(power_save_controller, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
90 #endif
91
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
94 "{Intel, ICH6M},"
95 "{Intel, ICH7},"
96 "{Intel, ESB2},"
97 "{Intel, ICH8},"
98 "{Intel, ICH9},"
99 "{Intel, ICH10},"
100 "{Intel, SCH},"
101 "{ATI, SB450},"
102 "{ATI, SB600},"
103 "{ATI, RS600},"
104 "{ATI, RS690},"
105 "{ATI, RS780},"
106 "{ATI, R600},"
107 "{ATI, RV630},"
108 "{ATI, RV610},"
109 "{ATI, RV670},"
110 "{ATI, RV635},"
111 "{ATI, RV620},"
112 "{ATI, RV770},"
113 "{VIA, VT8251},"
114 "{VIA, VT8237A},"
115 "{SiS, SIS966},"
116 "{ULI, M5461}}");
117 MODULE_DESCRIPTION("Intel HDA driver");
118
119 #define SFX "hda-intel: "
120
121
122 /*
123 * registers
124 */
125 #define ICH6_REG_GCAP 0x00
126 #define ICH6_REG_VMIN 0x02
127 #define ICH6_REG_VMAJ 0x03
128 #define ICH6_REG_OUTPAY 0x04
129 #define ICH6_REG_INPAY 0x06
130 #define ICH6_REG_GCTL 0x08
131 #define ICH6_REG_WAKEEN 0x0c
132 #define ICH6_REG_STATESTS 0x0e
133 #define ICH6_REG_GSTS 0x10
134 #define ICH6_REG_INTCTL 0x20
135 #define ICH6_REG_INTSTS 0x24
136 #define ICH6_REG_WALCLK 0x30
137 #define ICH6_REG_SYNC 0x34
138 #define ICH6_REG_CORBLBASE 0x40
139 #define ICH6_REG_CORBUBASE 0x44
140 #define ICH6_REG_CORBWP 0x48
141 #define ICH6_REG_CORBRP 0x4A
142 #define ICH6_REG_CORBCTL 0x4c
143 #define ICH6_REG_CORBSTS 0x4d
144 #define ICH6_REG_CORBSIZE 0x4e
145
146 #define ICH6_REG_RIRBLBASE 0x50
147 #define ICH6_REG_RIRBUBASE 0x54
148 #define ICH6_REG_RIRBWP 0x58
149 #define ICH6_REG_RINTCNT 0x5a
150 #define ICH6_REG_RIRBCTL 0x5c
151 #define ICH6_REG_RIRBSTS 0x5d
152 #define ICH6_REG_RIRBSIZE 0x5e
153
154 #define ICH6_REG_IC 0x60
155 #define ICH6_REG_IR 0x64
156 #define ICH6_REG_IRS 0x68
157 #define ICH6_IRS_VALID (1<<1)
158 #define ICH6_IRS_BUSY (1<<0)
159
160 #define ICH6_REG_DPLBASE 0x70
161 #define ICH6_REG_DPUBASE 0x74
162 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
163
164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
166
167 /* stream register offsets from stream base */
168 #define ICH6_REG_SD_CTL 0x00
169 #define ICH6_REG_SD_STS 0x03
170 #define ICH6_REG_SD_LPIB 0x04
171 #define ICH6_REG_SD_CBL 0x08
172 #define ICH6_REG_SD_LVI 0x0c
173 #define ICH6_REG_SD_FIFOW 0x0e
174 #define ICH6_REG_SD_FIFOSIZE 0x10
175 #define ICH6_REG_SD_FORMAT 0x12
176 #define ICH6_REG_SD_BDLPL 0x18
177 #define ICH6_REG_SD_BDLPU 0x1c
178
179 /* PCI space */
180 #define ICH6_PCIREG_TCSEL 0x44
181
182 /*
183 * other constants
184 */
185
186 /* max number of SDs */
187 /* ICH, ATI and VIA have 4 playback and 4 capture */
188 #define ICH6_CAPTURE_INDEX 0
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_PLAYBACK_INDEX 4
191 #define ICH6_NUM_PLAYBACK 4
192
193 /* ULI has 6 playback and 5 capture */
194 #define ULI_CAPTURE_INDEX 0
195 #define ULI_NUM_CAPTURE 5
196 #define ULI_PLAYBACK_INDEX 5
197 #define ULI_NUM_PLAYBACK 6
198
199 /* ATI HDMI has 1 playback and 0 capture */
200 #define ATIHDMI_CAPTURE_INDEX 0
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_PLAYBACK_INDEX 0
203 #define ATIHDMI_NUM_PLAYBACK 1
204
205 /* this number is statically defined for simplicity */
206 #define MAX_AZX_DEV 16
207
208 /* max number of fragments - we may use more if allocating more pages for BDL */
209 #define BDL_SIZE PAGE_ALIGN(8192)
210 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
211 /* max buffer size - no h/w limit, you can increase as you like */
212 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
213 /* max number of PCM devics per card */
214 #define AZX_MAX_AUDIO_PCMS 6
215 #define AZX_MAX_MODEM_PCMS 2
216 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
217
218 /* RIRB int mask: overrun[2], response[0] */
219 #define RIRB_INT_RESPONSE 0x01
220 #define RIRB_INT_OVERRUN 0x04
221 #define RIRB_INT_MASK 0x05
222
223 /* STATESTS int mask: SD2,SD1,SD0 */
224 #define AZX_MAX_CODECS 3
225 #define STATESTS_INT_MASK 0x07
226
227 /* SD_CTL bits */
228 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
229 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
230 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
231 #define SD_CTL_STREAM_TAG_SHIFT 20
232
233 /* SD_CTL and SD_STS */
234 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
235 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
236 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
237 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
238 SD_INT_COMPLETE)
239
240 /* SD_STS */
241 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
242
243 /* INTCTL and INTSTS */
244 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
245 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
246 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
247
248 /* GCTL unsolicited response enable bit */
249 #define ICH6_GCTL_UREN (1<<8)
250
251 /* GCTL reset bit */
252 #define ICH6_GCTL_RESET (1<<0)
253
254 /* CORB/RIRB control, read/write pointer */
255 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
256 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
257 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
258 /* below are so far hardcoded - should read registers in future */
259 #define ICH6_MAX_CORB_ENTRIES 256
260 #define ICH6_MAX_RIRB_ENTRIES 256
261
262 /* position fix mode */
263 enum {
264 POS_FIX_AUTO,
265 POS_FIX_NONE,
266 POS_FIX_POSBUF,
267 POS_FIX_FIFO,
268 };
269
270 /* Defines for ATI HD Audio support in SB450 south bridge */
271 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
272 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
273
274 /* Defines for Nvidia HDA support */
275 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
276 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
277
278 /*
279 */
280
281 struct azx_dev {
282 u32 *bdl; /* virtual address of the BDL */
283 dma_addr_t bdl_addr; /* physical address of the BDL */
284 u32 *posbuf; /* position buffer pointer */
285
286 unsigned int bufsize; /* size of the play buffer in bytes */
287 unsigned int fragsize; /* size of each period in bytes */
288 unsigned int frags; /* number for period in the play buffer */
289 unsigned int fifo_size; /* FIFO size */
290
291 void __iomem *sd_addr; /* stream descriptor pointer */
292
293 u32 sd_int_sta_mask; /* stream int status mask */
294
295 /* pcm support */
296 struct snd_pcm_substream *substream; /* assigned substream,
297 * set in PCM open
298 */
299 unsigned int format_val; /* format value to be set in the
300 * controller and the codec
301 */
302 unsigned char stream_tag; /* assigned stream */
303 unsigned char index; /* stream index */
304 /* for sanity check of position buffer */
305 unsigned int period_intr;
306
307 unsigned int opened :1;
308 unsigned int running :1;
309 };
310
311 /* CORB/RIRB */
312 struct azx_rb {
313 u32 *buf; /* CORB/RIRB buffer
314 * Each CORB entry is 4byte, RIRB is 8byte
315 */
316 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
317 /* for RIRB */
318 unsigned short rp, wp; /* read/write pointers */
319 int cmds; /* number of pending requests */
320 u32 res; /* last read value */
321 };
322
323 struct azx {
324 struct snd_card *card;
325 struct pci_dev *pci;
326
327 /* chip type specific */
328 int driver_type;
329 int playback_streams;
330 int playback_index_offset;
331 int capture_streams;
332 int capture_index_offset;
333 int num_streams;
334
335 /* pci resources */
336 unsigned long addr;
337 void __iomem *remap_addr;
338 int irq;
339
340 /* locks */
341 spinlock_t reg_lock;
342 struct mutex open_mutex;
343
344 /* streams (x num_streams) */
345 struct azx_dev *azx_dev;
346
347 /* PCM */
348 unsigned int pcm_devs;
349 struct snd_pcm *pcm[AZX_MAX_PCMS];
350
351 /* HD codec */
352 unsigned short codec_mask;
353 struct hda_bus *bus;
354
355 /* CORB/RIRB */
356 struct azx_rb corb;
357 struct azx_rb rirb;
358
359 /* BDL, CORB/RIRB and position buffers */
360 struct snd_dma_buffer bdl;
361 struct snd_dma_buffer rb;
362 struct snd_dma_buffer posbuf;
363
364 /* flags */
365 int position_fix;
366 unsigned int running :1;
367 unsigned int initialized :1;
368 unsigned int single_cmd :1;
369 unsigned int polling_mode :1;
370 unsigned int msi :1;
371
372 /* for debugging */
373 unsigned int last_cmd; /* last issued command (to sync) */
374 };
375
376 /* driver types */
377 enum {
378 AZX_DRIVER_ICH,
379 AZX_DRIVER_SCH,
380 AZX_DRIVER_ATI,
381 AZX_DRIVER_ATIHDMI,
382 AZX_DRIVER_VIA,
383 AZX_DRIVER_SIS,
384 AZX_DRIVER_ULI,
385 AZX_DRIVER_NVIDIA,
386 };
387
388 static char *driver_short_names[] __devinitdata = {
389 [AZX_DRIVER_ICH] = "HDA Intel",
390 [AZX_DRIVER_SCH] = "HDA Intel MID",
391 [AZX_DRIVER_ATI] = "HDA ATI SB",
392 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
393 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
394 [AZX_DRIVER_SIS] = "HDA SIS966",
395 [AZX_DRIVER_ULI] = "HDA ULI M5461",
396 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
397 };
398
399 /*
400 * macros for easy use
401 */
402 #define azx_writel(chip,reg,value) \
403 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_readl(chip,reg) \
405 readl((chip)->remap_addr + ICH6_REG_##reg)
406 #define azx_writew(chip,reg,value) \
407 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
408 #define azx_readw(chip,reg) \
409 readw((chip)->remap_addr + ICH6_REG_##reg)
410 #define azx_writeb(chip,reg,value) \
411 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
412 #define azx_readb(chip,reg) \
413 readb((chip)->remap_addr + ICH6_REG_##reg)
414
415 #define azx_sd_writel(dev,reg,value) \
416 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_readl(dev,reg) \
418 readl((dev)->sd_addr + ICH6_REG_##reg)
419 #define azx_sd_writew(dev,reg,value) \
420 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
421 #define azx_sd_readw(dev,reg) \
422 readw((dev)->sd_addr + ICH6_REG_##reg)
423 #define azx_sd_writeb(dev,reg,value) \
424 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
425 #define azx_sd_readb(dev,reg) \
426 readb((dev)->sd_addr + ICH6_REG_##reg)
427
428 /* for pcm support */
429 #define get_azx_dev(substream) (substream->runtime->private_data)
430
431 /* Get the upper 32bit of the given dma_addr_t
432 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
433 */
434 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
435
436 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
437
438 /*
439 * Interface for HD codec
440 */
441
442 /*
443 * CORB / RIRB interface
444 */
445 static int azx_alloc_cmd_io(struct azx *chip)
446 {
447 int err;
448
449 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
450 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
451 snd_dma_pci_data(chip->pci),
452 PAGE_SIZE, &chip->rb);
453 if (err < 0) {
454 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
455 return err;
456 }
457 return 0;
458 }
459
460 static void azx_init_cmd_io(struct azx *chip)
461 {
462 /* CORB set up */
463 chip->corb.addr = chip->rb.addr;
464 chip->corb.buf = (u32 *)chip->rb.area;
465 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
466 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
467
468 /* set the corb size to 256 entries (ULI requires explicitly) */
469 azx_writeb(chip, CORBSIZE, 0x02);
470 /* set the corb write pointer to 0 */
471 azx_writew(chip, CORBWP, 0);
472 /* reset the corb hw read pointer */
473 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
474 /* enable corb dma */
475 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
476
477 /* RIRB set up */
478 chip->rirb.addr = chip->rb.addr + 2048;
479 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
480 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
481 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
482
483 /* set the rirb size to 256 entries (ULI requires explicitly) */
484 azx_writeb(chip, RIRBSIZE, 0x02);
485 /* reset the rirb hw write pointer */
486 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
487 /* set N=1, get RIRB response interrupt for new entry */
488 azx_writew(chip, RINTCNT, 1);
489 /* enable rirb dma and response irq */
490 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
491 chip->rirb.rp = chip->rirb.cmds = 0;
492 }
493
494 static void azx_free_cmd_io(struct azx *chip)
495 {
496 /* disable ringbuffer DMAs */
497 azx_writeb(chip, RIRBCTL, 0);
498 azx_writeb(chip, CORBCTL, 0);
499 }
500
501 /* send a command */
502 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
503 {
504 struct azx *chip = codec->bus->private_data;
505 unsigned int wp;
506
507 /* add command to corb */
508 wp = azx_readb(chip, CORBWP);
509 wp++;
510 wp %= ICH6_MAX_CORB_ENTRIES;
511
512 spin_lock_irq(&chip->reg_lock);
513 chip->rirb.cmds++;
514 chip->corb.buf[wp] = cpu_to_le32(val);
515 azx_writel(chip, CORBWP, wp);
516 spin_unlock_irq(&chip->reg_lock);
517
518 return 0;
519 }
520
521 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
522
523 /* retrieve RIRB entry - called from interrupt handler */
524 static void azx_update_rirb(struct azx *chip)
525 {
526 unsigned int rp, wp;
527 u32 res, res_ex;
528
529 wp = azx_readb(chip, RIRBWP);
530 if (wp == chip->rirb.wp)
531 return;
532 chip->rirb.wp = wp;
533
534 while (chip->rirb.rp != wp) {
535 chip->rirb.rp++;
536 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
537
538 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
539 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
540 res = le32_to_cpu(chip->rirb.buf[rp]);
541 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
542 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
543 else if (chip->rirb.cmds) {
544 chip->rirb.cmds--;
545 chip->rirb.res = res;
546 }
547 }
548 }
549
550 /* receive a response */
551 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
552 {
553 struct azx *chip = codec->bus->private_data;
554 unsigned long timeout;
555
556 again:
557 timeout = jiffies + msecs_to_jiffies(1000);
558 for (;;) {
559 if (chip->polling_mode) {
560 spin_lock_irq(&chip->reg_lock);
561 azx_update_rirb(chip);
562 spin_unlock_irq(&chip->reg_lock);
563 }
564 if (!chip->rirb.cmds)
565 return chip->rirb.res; /* the last value */
566 if (time_after(jiffies, timeout))
567 break;
568 if (codec->bus->needs_damn_long_delay)
569 msleep(2); /* temporary workaround */
570 else {
571 udelay(10);
572 cond_resched();
573 }
574 }
575
576 if (chip->msi) {
577 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
578 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
579 free_irq(chip->irq, chip);
580 chip->irq = -1;
581 pci_disable_msi(chip->pci);
582 chip->msi = 0;
583 if (azx_acquire_irq(chip, 1) < 0)
584 return -1;
585 goto again;
586 }
587
588 if (!chip->polling_mode) {
589 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
590 "switching to polling mode: last cmd=0x%08x\n",
591 chip->last_cmd);
592 chip->polling_mode = 1;
593 goto again;
594 }
595
596 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
597 "switching to single_cmd mode: last cmd=0x%08x\n",
598 chip->last_cmd);
599 chip->rirb.rp = azx_readb(chip, RIRBWP);
600 chip->rirb.cmds = 0;
601 /* switch to single_cmd mode */
602 chip->single_cmd = 1;
603 azx_free_cmd_io(chip);
604 return -1;
605 }
606
607 /*
608 * Use the single immediate command instead of CORB/RIRB for simplicity
609 *
610 * Note: according to Intel, this is not preferred use. The command was
611 * intended for the BIOS only, and may get confused with unsolicited
612 * responses. So, we shouldn't use it for normal operation from the
613 * driver.
614 * I left the codes, however, for debugging/testing purposes.
615 */
616
617 /* send a command */
618 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
619 {
620 struct azx *chip = codec->bus->private_data;
621 int timeout = 50;
622
623 while (timeout--) {
624 /* check ICB busy bit */
625 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
626 /* Clear IRV valid bit */
627 azx_writew(chip, IRS, azx_readw(chip, IRS) |
628 ICH6_IRS_VALID);
629 azx_writel(chip, IC, val);
630 azx_writew(chip, IRS, azx_readw(chip, IRS) |
631 ICH6_IRS_BUSY);
632 return 0;
633 }
634 udelay(1);
635 }
636 if (printk_ratelimit())
637 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
638 azx_readw(chip, IRS), val);
639 return -EIO;
640 }
641
642 /* receive a response */
643 static unsigned int azx_single_get_response(struct hda_codec *codec)
644 {
645 struct azx *chip = codec->bus->private_data;
646 int timeout = 50;
647
648 while (timeout--) {
649 /* check IRV busy bit */
650 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
651 return azx_readl(chip, IR);
652 udelay(1);
653 }
654 if (printk_ratelimit())
655 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
656 azx_readw(chip, IRS));
657 return (unsigned int)-1;
658 }
659
660 /*
661 * The below are the main callbacks from hda_codec.
662 *
663 * They are just the skeleton to call sub-callbacks according to the
664 * current setting of chip->single_cmd.
665 */
666
667 /* send a command */
668 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
669 int direct, unsigned int verb,
670 unsigned int para)
671 {
672 struct azx *chip = codec->bus->private_data;
673 u32 val;
674
675 val = (u32)(codec->addr & 0x0f) << 28;
676 val |= (u32)direct << 27;
677 val |= (u32)nid << 20;
678 val |= verb << 8;
679 val |= para;
680 chip->last_cmd = val;
681
682 if (chip->single_cmd)
683 return azx_single_send_cmd(codec, val);
684 else
685 return azx_corb_send_cmd(codec, val);
686 }
687
688 /* get a response */
689 static unsigned int azx_get_response(struct hda_codec *codec)
690 {
691 struct azx *chip = codec->bus->private_data;
692 if (chip->single_cmd)
693 return azx_single_get_response(codec);
694 else
695 return azx_rirb_get_response(codec);
696 }
697
698 #ifdef CONFIG_SND_HDA_POWER_SAVE
699 static void azx_power_notify(struct hda_codec *codec);
700 #endif
701
702 /* reset codec link */
703 static int azx_reset(struct azx *chip)
704 {
705 int count;
706
707 /* clear STATESTS */
708 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
709
710 /* reset controller */
711 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
712
713 count = 50;
714 while (azx_readb(chip, GCTL) && --count)
715 msleep(1);
716
717 /* delay for >= 100us for codec PLL to settle per spec
718 * Rev 0.9 section 5.5.1
719 */
720 msleep(1);
721
722 /* Bring controller out of reset */
723 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
724
725 count = 50;
726 while (!azx_readb(chip, GCTL) && --count)
727 msleep(1);
728
729 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
730 msleep(1);
731
732 /* check to see if controller is ready */
733 if (!azx_readb(chip, GCTL)) {
734 snd_printd("azx_reset: controller not ready!\n");
735 return -EBUSY;
736 }
737
738 /* Accept unsolicited responses */
739 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
740
741 /* detect codecs */
742 if (!chip->codec_mask) {
743 chip->codec_mask = azx_readw(chip, STATESTS);
744 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
745 }
746
747 return 0;
748 }
749
750
751 /*
752 * Lowlevel interface
753 */
754
755 /* enable interrupts */
756 static void azx_int_enable(struct azx *chip)
757 {
758 /* enable controller CIE and GIE */
759 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
760 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
761 }
762
763 /* disable interrupts */
764 static void azx_int_disable(struct azx *chip)
765 {
766 int i;
767
768 /* disable interrupts in stream descriptor */
769 for (i = 0; i < chip->num_streams; i++) {
770 struct azx_dev *azx_dev = &chip->azx_dev[i];
771 azx_sd_writeb(azx_dev, SD_CTL,
772 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
773 }
774
775 /* disable SIE for all streams */
776 azx_writeb(chip, INTCTL, 0);
777
778 /* disable controller CIE and GIE */
779 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
780 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
781 }
782
783 /* clear interrupts */
784 static void azx_int_clear(struct azx *chip)
785 {
786 int i;
787
788 /* clear stream status */
789 for (i = 0; i < chip->num_streams; i++) {
790 struct azx_dev *azx_dev = &chip->azx_dev[i];
791 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
792 }
793
794 /* clear STATESTS */
795 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
796
797 /* clear rirb status */
798 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
799
800 /* clear int status */
801 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
802 }
803
804 /* start a stream */
805 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
806 {
807 /* enable SIE */
808 azx_writeb(chip, INTCTL,
809 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
810 /* set DMA start and interrupt mask */
811 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
812 SD_CTL_DMA_START | SD_INT_MASK);
813 }
814
815 /* stop a stream */
816 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
817 {
818 /* stop DMA */
819 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
820 ~(SD_CTL_DMA_START | SD_INT_MASK));
821 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
822 /* disable SIE */
823 azx_writeb(chip, INTCTL,
824 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
825 }
826
827
828 /*
829 * reset and start the controller registers
830 */
831 static void azx_init_chip(struct azx *chip)
832 {
833 if (chip->initialized)
834 return;
835
836 /* reset controller */
837 azx_reset(chip);
838
839 /* initialize interrupts */
840 azx_int_clear(chip);
841 azx_int_enable(chip);
842
843 /* initialize the codec command I/O */
844 if (!chip->single_cmd)
845 azx_init_cmd_io(chip);
846
847 /* program the position buffer */
848 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
849 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
850
851 chip->initialized = 1;
852 }
853
854 /*
855 * initialize the PCI registers
856 */
857 /* update bits in a PCI register byte */
858 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
859 unsigned char mask, unsigned char val)
860 {
861 unsigned char data;
862
863 pci_read_config_byte(pci, reg, &data);
864 data &= ~mask;
865 data |= (val & mask);
866 pci_write_config_byte(pci, reg, data);
867 }
868
869 static void azx_init_pci(struct azx *chip)
870 {
871 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
872 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
873 * Ensuring these bits are 0 clears playback static on some HD Audio
874 * codecs
875 */
876 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
877
878 switch (chip->driver_type) {
879 case AZX_DRIVER_ATI:
880 /* For ATI SB450 azalia HD audio, we need to enable snoop */
881 update_pci_byte(chip->pci,
882 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
883 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
884 break;
885 case AZX_DRIVER_NVIDIA:
886 /* For NVIDIA HDA, enable snoop */
887 update_pci_byte(chip->pci,
888 NVIDIA_HDA_TRANSREG_ADDR,
889 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
890 break;
891 }
892 }
893
894
895 /*
896 * interrupt handler
897 */
898 static irqreturn_t azx_interrupt(int irq, void *dev_id)
899 {
900 struct azx *chip = dev_id;
901 struct azx_dev *azx_dev;
902 u32 status;
903 int i;
904
905 spin_lock(&chip->reg_lock);
906
907 status = azx_readl(chip, INTSTS);
908 if (status == 0) {
909 spin_unlock(&chip->reg_lock);
910 return IRQ_NONE;
911 }
912
913 for (i = 0; i < chip->num_streams; i++) {
914 azx_dev = &chip->azx_dev[i];
915 if (status & azx_dev->sd_int_sta_mask) {
916 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
917 if (azx_dev->substream && azx_dev->running) {
918 azx_dev->period_intr++;
919 spin_unlock(&chip->reg_lock);
920 snd_pcm_period_elapsed(azx_dev->substream);
921 spin_lock(&chip->reg_lock);
922 }
923 }
924 }
925
926 /* clear rirb int */
927 status = azx_readb(chip, RIRBSTS);
928 if (status & RIRB_INT_MASK) {
929 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
930 azx_update_rirb(chip);
931 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
932 }
933
934 #if 0
935 /* clear state status int */
936 if (azx_readb(chip, STATESTS) & 0x04)
937 azx_writeb(chip, STATESTS, 0x04);
938 #endif
939 spin_unlock(&chip->reg_lock);
940
941 return IRQ_HANDLED;
942 }
943
944
945 /*
946 * set up BDL entries
947 */
948 static void azx_setup_periods(struct azx_dev *azx_dev)
949 {
950 u32 *bdl = azx_dev->bdl;
951 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
952 int idx;
953
954 /* reset BDL address */
955 azx_sd_writel(azx_dev, SD_BDLPL, 0);
956 azx_sd_writel(azx_dev, SD_BDLPU, 0);
957
958 /* program the initial BDL entries */
959 for (idx = 0; idx < azx_dev->frags; idx++) {
960 unsigned int off = idx << 2; /* 4 dword step */
961 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
962 /* program the address field of the BDL entry */
963 bdl[off] = cpu_to_le32((u32)addr);
964 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
965
966 /* program the size field of the BDL entry */
967 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
968
969 /* program the IOC to enable interrupt when buffer completes */
970 bdl[off+3] = cpu_to_le32(0x01);
971 }
972 }
973
974 /*
975 * set up the SD for streaming
976 */
977 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
978 {
979 unsigned char val;
980 int timeout;
981
982 /* make sure the run bit is zero for SD */
983 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
984 ~SD_CTL_DMA_START);
985 /* reset stream */
986 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
987 SD_CTL_STREAM_RESET);
988 udelay(3);
989 timeout = 300;
990 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
991 --timeout)
992 ;
993 val &= ~SD_CTL_STREAM_RESET;
994 azx_sd_writeb(azx_dev, SD_CTL, val);
995 udelay(3);
996
997 timeout = 300;
998 /* waiting for hardware to report that the stream is out of reset */
999 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1000 --timeout)
1001 ;
1002
1003 /* program the stream_tag */
1004 azx_sd_writel(azx_dev, SD_CTL,
1005 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1006 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1007
1008 /* program the length of samples in cyclic buffer */
1009 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1010
1011 /* program the stream format */
1012 /* this value needs to be the same as the one programmed */
1013 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1014
1015 /* program the stream LVI (last valid index) of the BDL */
1016 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1017
1018 /* program the BDL address */
1019 /* lower BDL address */
1020 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1021 /* upper BDL address */
1022 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1023
1024 /* enable the position buffer */
1025 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1026 azx_writel(chip, DPLBASE,
1027 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1028
1029 /* set the interrupt enable bits in the descriptor control register */
1030 azx_sd_writel(azx_dev, SD_CTL,
1031 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1032
1033 return 0;
1034 }
1035
1036
1037 /*
1038 * Codec initialization
1039 */
1040
1041 static unsigned int azx_max_codecs[] __devinitdata = {
1042 [AZX_DRIVER_ICH] = 3,
1043 [AZX_DRIVER_ATI] = 4,
1044 [AZX_DRIVER_ATIHDMI] = 4,
1045 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1046 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1047 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1048 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1049 };
1050
1051 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1052 unsigned int codec_probe_mask)
1053 {
1054 struct hda_bus_template bus_temp;
1055 int c, codecs, audio_codecs, err;
1056
1057 memset(&bus_temp, 0, sizeof(bus_temp));
1058 bus_temp.private_data = chip;
1059 bus_temp.modelname = model;
1060 bus_temp.pci = chip->pci;
1061 bus_temp.ops.command = azx_send_cmd;
1062 bus_temp.ops.get_response = azx_get_response;
1063 #ifdef CONFIG_SND_HDA_POWER_SAVE
1064 bus_temp.ops.pm_notify = azx_power_notify;
1065 #endif
1066
1067 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1068 if (err < 0)
1069 return err;
1070
1071 codecs = audio_codecs = 0;
1072 for (c = 0; c < AZX_MAX_CODECS; c++) {
1073 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1074 struct hda_codec *codec;
1075 err = snd_hda_codec_new(chip->bus, c, &codec);
1076 if (err < 0)
1077 continue;
1078 codecs++;
1079 if (codec->afg)
1080 audio_codecs++;
1081 }
1082 }
1083 if (!audio_codecs) {
1084 /* probe additional slots if no codec is found */
1085 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1086 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1087 err = snd_hda_codec_new(chip->bus, c, NULL);
1088 if (err < 0)
1089 continue;
1090 codecs++;
1091 }
1092 }
1093 }
1094 if (!codecs) {
1095 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1096 return -ENXIO;
1097 }
1098
1099 return 0;
1100 }
1101
1102
1103 /*
1104 * PCM support
1105 */
1106
1107 /* assign a stream for the PCM */
1108 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1109 {
1110 int dev, i, nums;
1111 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1112 dev = chip->playback_index_offset;
1113 nums = chip->playback_streams;
1114 } else {
1115 dev = chip->capture_index_offset;
1116 nums = chip->capture_streams;
1117 }
1118 for (i = 0; i < nums; i++, dev++)
1119 if (!chip->azx_dev[dev].opened) {
1120 chip->azx_dev[dev].opened = 1;
1121 return &chip->azx_dev[dev];
1122 }
1123 return NULL;
1124 }
1125
1126 /* release the assigned stream */
1127 static inline void azx_release_device(struct azx_dev *azx_dev)
1128 {
1129 azx_dev->opened = 0;
1130 }
1131
1132 static struct snd_pcm_hardware azx_pcm_hw = {
1133 .info = (SNDRV_PCM_INFO_MMAP |
1134 SNDRV_PCM_INFO_INTERLEAVED |
1135 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1136 SNDRV_PCM_INFO_MMAP_VALID |
1137 /* No full-resume yet implemented */
1138 /* SNDRV_PCM_INFO_RESUME |*/
1139 SNDRV_PCM_INFO_PAUSE),
1140 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1141 .rates = SNDRV_PCM_RATE_48000,
1142 .rate_min = 48000,
1143 .rate_max = 48000,
1144 .channels_min = 2,
1145 .channels_max = 2,
1146 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1147 .period_bytes_min = 128,
1148 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1149 .periods_min = 2,
1150 .periods_max = AZX_MAX_FRAG,
1151 .fifo_size = 0,
1152 };
1153
1154 struct azx_pcm {
1155 struct azx *chip;
1156 struct hda_codec *codec;
1157 struct hda_pcm_stream *hinfo[2];
1158 };
1159
1160 static int azx_pcm_open(struct snd_pcm_substream *substream)
1161 {
1162 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1163 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1164 struct azx *chip = apcm->chip;
1165 struct azx_dev *azx_dev;
1166 struct snd_pcm_runtime *runtime = substream->runtime;
1167 unsigned long flags;
1168 int err;
1169
1170 mutex_lock(&chip->open_mutex);
1171 azx_dev = azx_assign_device(chip, substream->stream);
1172 if (azx_dev == NULL) {
1173 mutex_unlock(&chip->open_mutex);
1174 return -EBUSY;
1175 }
1176 runtime->hw = azx_pcm_hw;
1177 runtime->hw.channels_min = hinfo->channels_min;
1178 runtime->hw.channels_max = hinfo->channels_max;
1179 runtime->hw.formats = hinfo->formats;
1180 runtime->hw.rates = hinfo->rates;
1181 snd_pcm_limit_hw_rates(runtime);
1182 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1183 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1184 128);
1185 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1186 128);
1187 snd_hda_power_up(apcm->codec);
1188 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1189 if (err < 0) {
1190 azx_release_device(azx_dev);
1191 snd_hda_power_down(apcm->codec);
1192 mutex_unlock(&chip->open_mutex);
1193 return err;
1194 }
1195 spin_lock_irqsave(&chip->reg_lock, flags);
1196 azx_dev->substream = substream;
1197 azx_dev->running = 0;
1198 spin_unlock_irqrestore(&chip->reg_lock, flags);
1199
1200 runtime->private_data = azx_dev;
1201 mutex_unlock(&chip->open_mutex);
1202 return 0;
1203 }
1204
1205 static int azx_pcm_close(struct snd_pcm_substream *substream)
1206 {
1207 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1208 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1209 struct azx *chip = apcm->chip;
1210 struct azx_dev *azx_dev = get_azx_dev(substream);
1211 unsigned long flags;
1212
1213 mutex_lock(&chip->open_mutex);
1214 spin_lock_irqsave(&chip->reg_lock, flags);
1215 azx_dev->substream = NULL;
1216 azx_dev->running = 0;
1217 spin_unlock_irqrestore(&chip->reg_lock, flags);
1218 azx_release_device(azx_dev);
1219 hinfo->ops.close(hinfo, apcm->codec, substream);
1220 snd_hda_power_down(apcm->codec);
1221 mutex_unlock(&chip->open_mutex);
1222 return 0;
1223 }
1224
1225 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1226 struct snd_pcm_hw_params *hw_params)
1227 {
1228 return snd_pcm_lib_malloc_pages(substream,
1229 params_buffer_bytes(hw_params));
1230 }
1231
1232 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1233 {
1234 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1235 struct azx_dev *azx_dev = get_azx_dev(substream);
1236 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1237
1238 /* reset BDL address */
1239 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1240 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1241 azx_sd_writel(azx_dev, SD_CTL, 0);
1242
1243 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1244
1245 return snd_pcm_lib_free_pages(substream);
1246 }
1247
1248 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1249 {
1250 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1251 struct azx *chip = apcm->chip;
1252 struct azx_dev *azx_dev = get_azx_dev(substream);
1253 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1254 struct snd_pcm_runtime *runtime = substream->runtime;
1255
1256 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1257 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1258 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1259 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1260 runtime->channels,
1261 runtime->format,
1262 hinfo->maxbps);
1263 if (!azx_dev->format_val) {
1264 snd_printk(KERN_ERR SFX
1265 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1266 runtime->rate, runtime->channels, runtime->format);
1267 return -EINVAL;
1268 }
1269
1270 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1271 "format=0x%x\n",
1272 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1273 azx_setup_periods(azx_dev);
1274 azx_setup_controller(chip, azx_dev);
1275 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1276 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1277 else
1278 azx_dev->fifo_size = 0;
1279
1280 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1281 azx_dev->format_val, substream);
1282 }
1283
1284 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1285 {
1286 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1287 struct azx_dev *azx_dev = get_azx_dev(substream);
1288 struct azx *chip = apcm->chip;
1289 int err = 0;
1290
1291 spin_lock(&chip->reg_lock);
1292 switch (cmd) {
1293 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1294 case SNDRV_PCM_TRIGGER_RESUME:
1295 case SNDRV_PCM_TRIGGER_START:
1296 azx_stream_start(chip, azx_dev);
1297 azx_dev->running = 1;
1298 break;
1299 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1300 case SNDRV_PCM_TRIGGER_SUSPEND:
1301 case SNDRV_PCM_TRIGGER_STOP:
1302 azx_stream_stop(chip, azx_dev);
1303 azx_dev->running = 0;
1304 break;
1305 default:
1306 err = -EINVAL;
1307 }
1308 spin_unlock(&chip->reg_lock);
1309 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1310 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1311 cmd == SNDRV_PCM_TRIGGER_STOP) {
1312 int timeout = 5000;
1313 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1314 --timeout)
1315 ;
1316 }
1317 return err;
1318 }
1319
1320 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1321 {
1322 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1323 struct azx *chip = apcm->chip;
1324 struct azx_dev *azx_dev = get_azx_dev(substream);
1325 unsigned int pos;
1326
1327 if (chip->position_fix == POS_FIX_POSBUF ||
1328 chip->position_fix == POS_FIX_AUTO) {
1329 /* use the position buffer */
1330 pos = le32_to_cpu(*azx_dev->posbuf);
1331 if (chip->position_fix == POS_FIX_AUTO &&
1332 azx_dev->period_intr == 1 && !pos) {
1333 printk(KERN_WARNING
1334 "hda-intel: Invalid position buffer, "
1335 "using LPIB read method instead.\n");
1336 chip->position_fix = POS_FIX_NONE;
1337 goto read_lpib;
1338 }
1339 } else {
1340 read_lpib:
1341 /* read LPIB */
1342 pos = azx_sd_readl(azx_dev, SD_LPIB);
1343 if (chip->position_fix == POS_FIX_FIFO)
1344 pos += azx_dev->fifo_size;
1345 }
1346 if (pos >= azx_dev->bufsize)
1347 pos = 0;
1348 return bytes_to_frames(substream->runtime, pos);
1349 }
1350
1351 static struct snd_pcm_ops azx_pcm_ops = {
1352 .open = azx_pcm_open,
1353 .close = azx_pcm_close,
1354 .ioctl = snd_pcm_lib_ioctl,
1355 .hw_params = azx_pcm_hw_params,
1356 .hw_free = azx_pcm_hw_free,
1357 .prepare = azx_pcm_prepare,
1358 .trigger = azx_pcm_trigger,
1359 .pointer = azx_pcm_pointer,
1360 };
1361
1362 static void azx_pcm_free(struct snd_pcm *pcm)
1363 {
1364 kfree(pcm->private_data);
1365 }
1366
1367 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1368 struct hda_pcm *cpcm, int pcm_dev)
1369 {
1370 int err;
1371 struct snd_pcm *pcm;
1372 struct azx_pcm *apcm;
1373
1374 /* if no substreams are defined for both playback and capture,
1375 * it's just a placeholder. ignore it.
1376 */
1377 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1378 return 0;
1379
1380 snd_assert(cpcm->name, return -EINVAL);
1381
1382 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1383 cpcm->stream[0].substreams,
1384 cpcm->stream[1].substreams,
1385 &pcm);
1386 if (err < 0)
1387 return err;
1388 strcpy(pcm->name, cpcm->name);
1389 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1390 if (apcm == NULL)
1391 return -ENOMEM;
1392 apcm->chip = chip;
1393 apcm->codec = codec;
1394 apcm->hinfo[0] = &cpcm->stream[0];
1395 apcm->hinfo[1] = &cpcm->stream[1];
1396 pcm->private_data = apcm;
1397 pcm->private_free = azx_pcm_free;
1398 if (cpcm->stream[0].substreams)
1399 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1400 if (cpcm->stream[1].substreams)
1401 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1402 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1403 snd_dma_pci_data(chip->pci),
1404 1024 * 64, 1024 * 1024);
1405 chip->pcm[pcm_dev] = pcm;
1406 if (chip->pcm_devs < pcm_dev + 1)
1407 chip->pcm_devs = pcm_dev + 1;
1408
1409 return 0;
1410 }
1411
1412 static int __devinit azx_pcm_create(struct azx *chip)
1413 {
1414 struct hda_codec *codec;
1415 int c, err;
1416 int pcm_dev;
1417
1418 err = snd_hda_build_pcms(chip->bus);
1419 if (err < 0)
1420 return err;
1421
1422 /* create audio PCMs */
1423 pcm_dev = 0;
1424 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1425 for (c = 0; c < codec->num_pcms; c++) {
1426 if (codec->pcm_info[c].is_modem)
1427 continue; /* create later */
1428 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1429 snd_printk(KERN_ERR SFX
1430 "Too many audio PCMs\n");
1431 return -EINVAL;
1432 }
1433 err = create_codec_pcm(chip, codec,
1434 &codec->pcm_info[c], pcm_dev);
1435 if (err < 0)
1436 return err;
1437 pcm_dev++;
1438 }
1439 }
1440
1441 /* create modem PCMs */
1442 pcm_dev = AZX_MAX_AUDIO_PCMS;
1443 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1444 for (c = 0; c < codec->num_pcms; c++) {
1445 if (!codec->pcm_info[c].is_modem)
1446 continue; /* already created */
1447 if (pcm_dev >= AZX_MAX_PCMS) {
1448 snd_printk(KERN_ERR SFX
1449 "Too many modem PCMs\n");
1450 return -EINVAL;
1451 }
1452 err = create_codec_pcm(chip, codec,
1453 &codec->pcm_info[c], pcm_dev);
1454 if (err < 0)
1455 return err;
1456 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1457 pcm_dev++;
1458 }
1459 }
1460 return 0;
1461 }
1462
1463 /*
1464 * mixer creation - all stuff is implemented in hda module
1465 */
1466 static int __devinit azx_mixer_create(struct azx *chip)
1467 {
1468 return snd_hda_build_controls(chip->bus);
1469 }
1470
1471
1472 /*
1473 * initialize SD streams
1474 */
1475 static int __devinit azx_init_stream(struct azx *chip)
1476 {
1477 int i;
1478
1479 /* initialize each stream (aka device)
1480 * assign the starting bdl address to each stream (device)
1481 * and initialize
1482 */
1483 for (i = 0; i < chip->num_streams; i++) {
1484 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1485 struct azx_dev *azx_dev = &chip->azx_dev[i];
1486 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1487 azx_dev->bdl_addr = chip->bdl.addr + off;
1488 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1489 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1490 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1491 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1492 azx_dev->sd_int_sta_mask = 1 << i;
1493 /* stream tag: must be non-zero and unique */
1494 azx_dev->index = i;
1495 azx_dev->stream_tag = i + 1;
1496 }
1497
1498 return 0;
1499 }
1500
1501 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1502 {
1503 if (request_irq(chip->pci->irq, azx_interrupt,
1504 chip->msi ? 0 : IRQF_SHARED,
1505 "HDA Intel", chip)) {
1506 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1507 "disabling device\n", chip->pci->irq);
1508 if (do_disconnect)
1509 snd_card_disconnect(chip->card);
1510 return -1;
1511 }
1512 chip->irq = chip->pci->irq;
1513 pci_intx(chip->pci, !chip->msi);
1514 return 0;
1515 }
1516
1517
1518 static void azx_stop_chip(struct azx *chip)
1519 {
1520 if (!chip->initialized)
1521 return;
1522
1523 /* disable interrupts */
1524 azx_int_disable(chip);
1525 azx_int_clear(chip);
1526
1527 /* disable CORB/RIRB */
1528 azx_free_cmd_io(chip);
1529
1530 /* disable position buffer */
1531 azx_writel(chip, DPLBASE, 0);
1532 azx_writel(chip, DPUBASE, 0);
1533
1534 chip->initialized = 0;
1535 }
1536
1537 #ifdef CONFIG_SND_HDA_POWER_SAVE
1538 /* power-up/down the controller */
1539 static void azx_power_notify(struct hda_codec *codec)
1540 {
1541 struct azx *chip = codec->bus->private_data;
1542 struct hda_codec *c;
1543 int power_on = 0;
1544
1545 list_for_each_entry(c, &codec->bus->codec_list, list) {
1546 if (c->power_on) {
1547 power_on = 1;
1548 break;
1549 }
1550 }
1551 if (power_on)
1552 azx_init_chip(chip);
1553 else if (chip->running && power_save_controller)
1554 azx_stop_chip(chip);
1555 }
1556 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1557
1558 #ifdef CONFIG_PM
1559 /*
1560 * power management
1561 */
1562 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1563 {
1564 struct snd_card *card = pci_get_drvdata(pci);
1565 struct azx *chip = card->private_data;
1566 int i;
1567
1568 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1569 for (i = 0; i < chip->pcm_devs; i++)
1570 snd_pcm_suspend_all(chip->pcm[i]);
1571 if (chip->initialized)
1572 snd_hda_suspend(chip->bus, state);
1573 azx_stop_chip(chip);
1574 if (chip->irq >= 0) {
1575 synchronize_irq(chip->irq);
1576 free_irq(chip->irq, chip);
1577 chip->irq = -1;
1578 }
1579 if (chip->msi)
1580 pci_disable_msi(chip->pci);
1581 pci_disable_device(pci);
1582 pci_save_state(pci);
1583 pci_set_power_state(pci, pci_choose_state(pci, state));
1584 return 0;
1585 }
1586
1587 static int azx_resume(struct pci_dev *pci)
1588 {
1589 struct snd_card *card = pci_get_drvdata(pci);
1590 struct azx *chip = card->private_data;
1591
1592 pci_set_power_state(pci, PCI_D0);
1593 pci_restore_state(pci);
1594 if (pci_enable_device(pci) < 0) {
1595 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1596 "disabling device\n");
1597 snd_card_disconnect(card);
1598 return -EIO;
1599 }
1600 pci_set_master(pci);
1601 if (chip->msi)
1602 if (pci_enable_msi(pci) < 0)
1603 chip->msi = 0;
1604 if (azx_acquire_irq(chip, 1) < 0)
1605 return -EIO;
1606 azx_init_pci(chip);
1607
1608 if (snd_hda_codecs_inuse(chip->bus))
1609 azx_init_chip(chip);
1610
1611 snd_hda_resume(chip->bus);
1612 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1613 return 0;
1614 }
1615 #endif /* CONFIG_PM */
1616
1617
1618 /*
1619 * destructor
1620 */
1621 static int azx_free(struct azx *chip)
1622 {
1623 if (chip->initialized) {
1624 int i;
1625 for (i = 0; i < chip->num_streams; i++)
1626 azx_stream_stop(chip, &chip->azx_dev[i]);
1627 azx_stop_chip(chip);
1628 }
1629
1630 if (chip->irq >= 0) {
1631 synchronize_irq(chip->irq);
1632 free_irq(chip->irq, (void*)chip);
1633 }
1634 if (chip->msi)
1635 pci_disable_msi(chip->pci);
1636 if (chip->remap_addr)
1637 iounmap(chip->remap_addr);
1638
1639 if (chip->bdl.area)
1640 snd_dma_free_pages(&chip->bdl);
1641 if (chip->rb.area)
1642 snd_dma_free_pages(&chip->rb);
1643 if (chip->posbuf.area)
1644 snd_dma_free_pages(&chip->posbuf);
1645 pci_release_regions(chip->pci);
1646 pci_disable_device(chip->pci);
1647 kfree(chip->azx_dev);
1648 kfree(chip);
1649
1650 return 0;
1651 }
1652
1653 static int azx_dev_free(struct snd_device *device)
1654 {
1655 return azx_free(device->device_data);
1656 }
1657
1658 /*
1659 * white/black-listing for position_fix
1660 */
1661 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1662 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1663 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1664 {}
1665 };
1666
1667 static int __devinit check_position_fix(struct azx *chip, int fix)
1668 {
1669 const struct snd_pci_quirk *q;
1670
1671 if (fix == POS_FIX_AUTO) {
1672 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1673 if (q) {
1674 printk(KERN_INFO
1675 "hda_intel: position_fix set to %d "
1676 "for device %04x:%04x\n",
1677 q->value, q->subvendor, q->subdevice);
1678 return q->value;
1679 }
1680 }
1681 return fix;
1682 }
1683
1684 /*
1685 * black-lists for probe_mask
1686 */
1687 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1688 /* Thinkpad often breaks the controller communication when accessing
1689 * to the non-working (or non-existing) modem codec slot.
1690 */
1691 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1692 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1693 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1694 {}
1695 };
1696
1697 static void __devinit check_probe_mask(struct azx *chip, int dev)
1698 {
1699 const struct snd_pci_quirk *q;
1700
1701 if (probe_mask[dev] == -1) {
1702 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1703 if (q) {
1704 printk(KERN_INFO
1705 "hda_intel: probe_mask set to 0x%x "
1706 "for device %04x:%04x\n",
1707 q->value, q->subvendor, q->subdevice);
1708 probe_mask[dev] = q->value;
1709 }
1710 }
1711 }
1712
1713
1714 /*
1715 * constructor
1716 */
1717 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1718 int dev, int driver_type,
1719 struct azx **rchip)
1720 {
1721 struct azx *chip;
1722 int err;
1723 unsigned short gcap;
1724 static struct snd_device_ops ops = {
1725 .dev_free = azx_dev_free,
1726 };
1727
1728 *rchip = NULL;
1729
1730 err = pci_enable_device(pci);
1731 if (err < 0)
1732 return err;
1733
1734 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1735 if (!chip) {
1736 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1737 pci_disable_device(pci);
1738 return -ENOMEM;
1739 }
1740
1741 spin_lock_init(&chip->reg_lock);
1742 mutex_init(&chip->open_mutex);
1743 chip->card = card;
1744 chip->pci = pci;
1745 chip->irq = -1;
1746 chip->driver_type = driver_type;
1747 chip->msi = enable_msi;
1748
1749 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1750 check_probe_mask(chip, dev);
1751
1752 chip->single_cmd = single_cmd;
1753
1754 #if BITS_PER_LONG != 64
1755 /* Fix up base address on ULI M5461 */
1756 if (chip->driver_type == AZX_DRIVER_ULI) {
1757 u16 tmp3;
1758 pci_read_config_word(pci, 0x40, &tmp3);
1759 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1760 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1761 }
1762 #endif
1763
1764 err = pci_request_regions(pci, "ICH HD audio");
1765 if (err < 0) {
1766 kfree(chip);
1767 pci_disable_device(pci);
1768 return err;
1769 }
1770
1771 chip->addr = pci_resource_start(pci, 0);
1772 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1773 if (chip->remap_addr == NULL) {
1774 snd_printk(KERN_ERR SFX "ioremap error\n");
1775 err = -ENXIO;
1776 goto errout;
1777 }
1778
1779 if (chip->msi)
1780 if (pci_enable_msi(pci) < 0)
1781 chip->msi = 0;
1782
1783 if (azx_acquire_irq(chip, 0) < 0) {
1784 err = -EBUSY;
1785 goto errout;
1786 }
1787
1788 pci_set_master(pci);
1789 synchronize_irq(chip->irq);
1790
1791 gcap = azx_readw(chip, GCAP);
1792 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1793
1794 if (gcap) {
1795 /* read number of streams from GCAP register instead of using
1796 * hardcoded value
1797 */
1798 chip->playback_streams = (gcap & (0xF << 12)) >> 12;
1799 chip->capture_streams = (gcap & (0xF << 8)) >> 8;
1800 chip->playback_index_offset = (gcap & (0xF << 12)) >> 12;
1801 chip->capture_index_offset = 0;
1802 } else {
1803 /* gcap didn't give any info, switching to old method */
1804
1805 switch (chip->driver_type) {
1806 case AZX_DRIVER_ULI:
1807 chip->playback_streams = ULI_NUM_PLAYBACK;
1808 chip->capture_streams = ULI_NUM_CAPTURE;
1809 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1810 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1811 break;
1812 case AZX_DRIVER_ATIHDMI:
1813 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1814 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1815 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1816 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1817 break;
1818 default:
1819 chip->playback_streams = ICH6_NUM_PLAYBACK;
1820 chip->capture_streams = ICH6_NUM_CAPTURE;
1821 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1822 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1823 break;
1824 }
1825 }
1826 chip->num_streams = chip->playback_streams + chip->capture_streams;
1827 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1828 GFP_KERNEL);
1829 if (!chip->azx_dev) {
1830 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1831 goto errout;
1832 }
1833
1834 /* allocate memory for the BDL for each stream */
1835 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1836 snd_dma_pci_data(chip->pci),
1837 BDL_SIZE, &chip->bdl);
1838 if (err < 0) {
1839 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1840 goto errout;
1841 }
1842 /* allocate memory for the position buffer */
1843 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1844 snd_dma_pci_data(chip->pci),
1845 chip->num_streams * 8, &chip->posbuf);
1846 if (err < 0) {
1847 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1848 goto errout;
1849 }
1850 /* allocate CORB/RIRB */
1851 if (!chip->single_cmd) {
1852 err = azx_alloc_cmd_io(chip);
1853 if (err < 0)
1854 goto errout;
1855 }
1856
1857 /* initialize streams */
1858 azx_init_stream(chip);
1859
1860 /* initialize chip */
1861 azx_init_pci(chip);
1862 azx_init_chip(chip);
1863
1864 /* codec detection */
1865 if (!chip->codec_mask) {
1866 snd_printk(KERN_ERR SFX "no codecs found!\n");
1867 err = -ENODEV;
1868 goto errout;
1869 }
1870
1871 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1872 if (err <0) {
1873 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1874 goto errout;
1875 }
1876
1877 strcpy(card->driver, "HDA-Intel");
1878 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1879 sprintf(card->longname, "%s at 0x%lx irq %i",
1880 card->shortname, chip->addr, chip->irq);
1881
1882 *rchip = chip;
1883 return 0;
1884
1885 errout:
1886 azx_free(chip);
1887 return err;
1888 }
1889
1890 static void power_down_all_codecs(struct azx *chip)
1891 {
1892 #ifdef CONFIG_SND_HDA_POWER_SAVE
1893 /* The codecs were powered up in snd_hda_codec_new().
1894 * Now all initialization done, so turn them down if possible
1895 */
1896 struct hda_codec *codec;
1897 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1898 snd_hda_power_down(codec);
1899 }
1900 #endif
1901 }
1902
1903 static int __devinit azx_probe(struct pci_dev *pci,
1904 const struct pci_device_id *pci_id)
1905 {
1906 static int dev;
1907 struct snd_card *card;
1908 struct azx *chip;
1909 int err;
1910
1911 if (dev >= SNDRV_CARDS)
1912 return -ENODEV;
1913 if (!enable[dev]) {
1914 dev++;
1915 return -ENOENT;
1916 }
1917
1918 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1919 if (!card) {
1920 snd_printk(KERN_ERR SFX "Error creating card!\n");
1921 return -ENOMEM;
1922 }
1923
1924 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1925 if (err < 0) {
1926 snd_card_free(card);
1927 return err;
1928 }
1929 card->private_data = chip;
1930
1931 /* create codec instances */
1932 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1933 if (err < 0) {
1934 snd_card_free(card);
1935 return err;
1936 }
1937
1938 /* create PCM streams */
1939 err = azx_pcm_create(chip);
1940 if (err < 0) {
1941 snd_card_free(card);
1942 return err;
1943 }
1944
1945 /* create mixer controls */
1946 err = azx_mixer_create(chip);
1947 if (err < 0) {
1948 snd_card_free(card);
1949 return err;
1950 }
1951
1952 snd_card_set_dev(card, &pci->dev);
1953
1954 err = snd_card_register(card);
1955 if (err < 0) {
1956 snd_card_free(card);
1957 return err;
1958 }
1959
1960 pci_set_drvdata(pci, card);
1961 chip->running = 1;
1962 power_down_all_codecs(chip);
1963
1964 dev++;
1965 return err;
1966 }
1967
1968 static void __devexit azx_remove(struct pci_dev *pci)
1969 {
1970 snd_card_free(pci_get_drvdata(pci));
1971 pci_set_drvdata(pci, NULL);
1972 }
1973
1974 /* PCI IDs */
1975 static struct pci_device_id azx_ids[] = {
1976 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1977 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1978 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1979 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1980 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1981 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1982 { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
1983 { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
1984 { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
1985 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1986 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1987 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1988 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1989 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1990 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1991 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
1992 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
1993 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
1994 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
1995 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
1996 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
1997 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1998 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1999 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2000 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2001 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2002 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2003 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2004 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2005 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2006 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2007 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2008 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2009 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2010 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2011 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2012 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2013 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2014 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2015 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2016 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2017 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2018 { 0, }
2019 };
2020 MODULE_DEVICE_TABLE(pci, azx_ids);
2021
2022 /* pci_driver definition */
2023 static struct pci_driver driver = {
2024 .name = "HDA Intel",
2025 .id_table = azx_ids,
2026 .probe = azx_probe,
2027 .remove = __devexit_p(azx_remove),
2028 #ifdef CONFIG_PM
2029 .suspend = azx_suspend,
2030 .resume = azx_resume,
2031 #endif
2032 };
2033
2034 static int __init alsa_card_azx_init(void)
2035 {
2036 return pci_register_driver(&driver);
2037 }
2038
2039 static void __exit alsa_card_azx_exit(void)
2040 {
2041 pci_unregister_driver(&driver);
2042 }
2043
2044 module_init(alsa_card_azx_init)
2045 module_exit(alsa_card_azx_exit)
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