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ALSA: hda/ca0132 - Clean up ca0132_alt_out_select
[mirror_ubuntu-jammy-kernel.git] / sound / pci / hda / patch_ca0132.c
1 /*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/io.h>
33 #include <linux/pci.h>
34 #include <sound/core.h>
35 #include <sound/hda_codec.h>
36 #include "hda_local.h"
37 #include "hda_auto_parser.h"
38 #include "hda_jack.h"
39
40 #include "ca0132_regs.h"
41
42 /* Enable this to see controls for tuning purpose. */
43 /*#define ENABLE_TUNING_CONTROLS*/
44
45 #ifdef ENABLE_TUNING_CONTROLS
46 #include <sound/tlv.h>
47 #endif
48
49 #define FLOAT_ZERO 0x00000000
50 #define FLOAT_ONE 0x3f800000
51 #define FLOAT_TWO 0x40000000
52 #define FLOAT_THREE 0x40400000
53 #define FLOAT_EIGHT 0x41000000
54 #define FLOAT_MINUS_5 0xc0a00000
55
56 #define UNSOL_TAG_DSP 0x16
57
58 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65 #define MASTERCONTROL 0x80
66 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
67 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
68
69 #define WIDGET_CHIP_CTRL 0x15
70 #define WIDGET_DSP_CTRL 0x16
71
72 #define MEM_CONNID_MICIN1 3
73 #define MEM_CONNID_MICIN2 5
74 #define MEM_CONNID_MICOUT1 12
75 #define MEM_CONNID_MICOUT2 14
76 #define MEM_CONNID_WUH 10
77 #define MEM_CONNID_DSP 16
78 #define MEM_CONNID_DMIC 100
79
80 #define SCP_SET 0
81 #define SCP_GET 1
82
83 #define EFX_FILE "ctefx.bin"
84 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
85 #define R3DI_EFX_FILE "ctefx-r3di.bin"
86
87 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
88 MODULE_FIRMWARE(EFX_FILE);
89 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
90 MODULE_FIRMWARE(R3DI_EFX_FILE);
91 #endif
92
93 static const char *const dirstr[2] = { "Playback", "Capture" };
94
95 #define NUM_OF_OUTPUTS 3
96 enum {
97 SPEAKER_OUT,
98 HEADPHONE_OUT,
99 SURROUND_OUT
100 };
101
102 enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105 };
106
107 /* Strings for Input Source Enum Control */
108 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
109 #define IN_SRC_NUM_OF_INPUTS 3
110 enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114 };
115
116 enum {
117 #define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127 #define EFFECT_START_NID 0x90
128 #define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
156 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157 };
158
159 /* Effects values size*/
160 #define EFFECT_VALS_MAX_COUNT 12
161
162 /*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168 /* Amount of effect level sliders for ca0132_alt controls. */
169 #define EFFECT_LEVEL_SLIDERS 5
170
171 /* Latency introduced by DSP blocks in milliseconds. */
172 #define DSP_CAPTURE_INIT_LATENCY 0
173 #define DSP_CRYSTAL_VOICE_LATENCY 124
174 #define DSP_PLAYBACK_INIT_LATENCY 13
175 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
176 #define DSP_SPEAKER_OUT_LATENCY 7
177
178 struct ct_effect {
179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187 };
188
189 #define EFX_DIR_OUT 0
190 #define EFX_DIR_IN 1
191
192 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286 };
287
288 /* Tuning controls */
289 #ifdef ENABLE_TUNING_CONTROLS
290
291 enum {
292 #define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307 };
308
309 struct ct_tuning_ctl {
310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317 };
318
319 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416 };
417 #endif
418
419 /* Voice FX Presets */
420 #define VOICEFX_MAX_PARAM_COUNT 9
421
422 struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427 };
428
429 struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432 };
433
434 static const struct ct_voicefx ca0132_voicefx = {
435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439 };
440
441 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512 };
513
514 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516 #define EQ_PRESET_MAX_PARAM_COUNT 11
517
518 struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523 };
524
525 struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528 };
529
530 static const struct ct_eq ca0132_alt_eq_enum = {
531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535 };
536
537
538 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599 };
600
601 /* DSP command sequences for ca0132_alt_select_out */
602 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603 struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609 };
610
611 static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642 };
643
644 /*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649 #define DSP_VOL_OUT 0
650 #define DSP_VOL_IN 1
651
652 struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656 };
657
658 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667 };
668
669 enum hda_cmd_vendor_io {
670 /* for DspIO node */
671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
673
674 VENDOR_DSPIO_STATUS = 0xF01,
675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
677 VENDOR_DSPIO_DSP_INIT = 0x703,
678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
680
681 /* for ChipIO node */
682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
685 VENDOR_CHIPIO_DATA_LOW = 0x300,
686 VENDOR_CHIPIO_DATA_HIGH = 0x400,
687
688 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
689 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
690
691 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
692 VENDOR_CHIPIO_STATUS = 0xF01,
693 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
694 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
695
696 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
697 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
698 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
699 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
700 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
701
702 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
703 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
704
705 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
706 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
707 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
708 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
709 VENDOR_CHIPIO_FLAG_SET = 0x70F,
710 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
711 VENDOR_CHIPIO_PARAM_SET = 0x710,
712 VENDOR_CHIPIO_PARAM_GET = 0xF10,
713
714 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
715 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
716 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
717 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
718
719 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
720 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
721 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
722 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
723
724 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
725 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
726 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
727 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
728 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
729 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
730
731 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
732 };
733
734 /*
735 * Control flag IDs
736 */
737 enum control_flag_id {
738 /* Connection manager stream setup is bypassed/enabled */
739 CONTROL_FLAG_C_MGR = 0,
740 /* DSP DMA is bypassed/enabled */
741 CONTROL_FLAG_DMA = 1,
742 /* 8051 'idle' mode is disabled/enabled */
743 CONTROL_FLAG_IDLE_ENABLE = 2,
744 /* Tracker for the SPDIF-in path is bypassed/enabled */
745 CONTROL_FLAG_TRACKER = 3,
746 /* DigitalOut to Spdif2Out connection is disabled/enabled */
747 CONTROL_FLAG_SPDIF2OUT = 4,
748 /* Digital Microphone is disabled/enabled */
749 CONTROL_FLAG_DMIC = 5,
750 /* ADC_B rate is 48 kHz/96 kHz */
751 CONTROL_FLAG_ADC_B_96KHZ = 6,
752 /* ADC_C rate is 48 kHz/96 kHz */
753 CONTROL_FLAG_ADC_C_96KHZ = 7,
754 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
755 CONTROL_FLAG_DAC_96KHZ = 8,
756 /* DSP rate is 48 kHz/96 kHz */
757 CONTROL_FLAG_DSP_96KHZ = 9,
758 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
759 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
760 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
761 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
762 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
763 CONTROL_FLAG_DECODE_LOOP = 12,
764 /* De-emphasis filter on DAC-1 disabled/enabled */
765 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
766 /* De-emphasis filter on DAC-2 disabled/enabled */
767 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
768 /* De-emphasis filter on DAC-3 disabled/enabled */
769 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
770 /* High-pass filter on ADC_B disabled/enabled */
771 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
772 /* High-pass filter on ADC_C disabled/enabled */
773 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
774 /* Common mode on Port_A disabled/enabled */
775 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
776 /* Common mode on Port_D disabled/enabled */
777 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
778 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
779 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
780 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
781 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
782 /* ASI rate is 48kHz/96kHz */
783 CONTROL_FLAG_ASI_96KHZ = 22,
784 /* DAC power settings able to control attached ports no/yes */
785 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
786 /* Clock Stop OK reporting is disabled/enabled */
787 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
788 /* Number of control flags */
789 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
790 };
791
792 /*
793 * Control parameter IDs
794 */
795 enum control_param_id {
796 /* 0: None, 1: Mic1In*/
797 CONTROL_PARAM_VIP_SOURCE = 1,
798 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
799 CONTROL_PARAM_SPDIF1_SOURCE = 2,
800 /* Port A output stage gain setting to use when 16 Ohm output
801 * impedance is selected*/
802 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
803 /* Port D output stage gain setting to use when 16 Ohm output
804 * impedance is selected*/
805 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
806
807 /*
808 * This control param name was found in the 8051 memory, and makes
809 * sense given the fact the AE-5 uses it and has the ASI flag set.
810 */
811 CONTROL_PARAM_ASI = 23,
812
813 /* Stream Control */
814
815 /* Select stream with the given ID */
816 CONTROL_PARAM_STREAM_ID = 24,
817 /* Source connection point for the selected stream */
818 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
819 /* Destination connection point for the selected stream */
820 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
821 /* Number of audio channels in the selected stream */
822 CONTROL_PARAM_STREAMS_CHANNELS = 27,
823 /*Enable control for the selected stream */
824 CONTROL_PARAM_STREAM_CONTROL = 28,
825
826 /* Connection Point Control */
827
828 /* Select connection point with the given ID */
829 CONTROL_PARAM_CONN_POINT_ID = 29,
830 /* Connection point sample rate */
831 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
832
833 /* Node Control */
834
835 /* Select HDA node with the given ID */
836 CONTROL_PARAM_NODE_ID = 31
837 };
838
839 /*
840 * Dsp Io Status codes
841 */
842 enum hda_vendor_status_dspio {
843 /* Success */
844 VENDOR_STATUS_DSPIO_OK = 0x00,
845 /* Busy, unable to accept new command, the host must retry */
846 VENDOR_STATUS_DSPIO_BUSY = 0x01,
847 /* SCP command queue is full */
848 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
849 /* SCP response queue is empty */
850 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
851 };
852
853 /*
854 * Chip Io Status codes
855 */
856 enum hda_vendor_status_chipio {
857 /* Success */
858 VENDOR_STATUS_CHIPIO_OK = 0x00,
859 /* Busy, unable to accept new command, the host must retry */
860 VENDOR_STATUS_CHIPIO_BUSY = 0x01
861 };
862
863 /*
864 * CA0132 sample rate
865 */
866 enum ca0132_sample_rate {
867 SR_6_000 = 0x00,
868 SR_8_000 = 0x01,
869 SR_9_600 = 0x02,
870 SR_11_025 = 0x03,
871 SR_16_000 = 0x04,
872 SR_22_050 = 0x05,
873 SR_24_000 = 0x06,
874 SR_32_000 = 0x07,
875 SR_44_100 = 0x08,
876 SR_48_000 = 0x09,
877 SR_88_200 = 0x0A,
878 SR_96_000 = 0x0B,
879 SR_144_000 = 0x0C,
880 SR_176_400 = 0x0D,
881 SR_192_000 = 0x0E,
882 SR_384_000 = 0x0F,
883
884 SR_COUNT = 0x10,
885
886 SR_RATE_UNKNOWN = 0x1F
887 };
888
889 enum dsp_download_state {
890 DSP_DOWNLOAD_FAILED = -1,
891 DSP_DOWNLOAD_INIT = 0,
892 DSP_DOWNLOADING = 1,
893 DSP_DOWNLOADED = 2
894 };
895
896 /* retrieve parameters from hda format */
897 #define get_hdafmt_chs(fmt) (fmt & 0xf)
898 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
899 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
900 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
901
902 /*
903 * CA0132 specific
904 */
905
906 struct ca0132_spec {
907 const struct snd_kcontrol_new *mixers[5];
908 unsigned int num_mixers;
909 const struct hda_verb *base_init_verbs;
910 const struct hda_verb *base_exit_verbs;
911 const struct hda_verb *chip_init_verbs;
912 const struct hda_verb *desktop_init_verbs;
913 struct hda_verb *spec_init_verbs;
914 struct auto_pin_cfg autocfg;
915
916 /* Nodes configurations */
917 struct hda_multi_out multiout;
918 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
919 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
920 unsigned int num_outputs;
921 hda_nid_t input_pins[AUTO_PIN_LAST];
922 hda_nid_t adcs[AUTO_PIN_LAST];
923 hda_nid_t dig_out;
924 hda_nid_t dig_in;
925 unsigned int num_inputs;
926 hda_nid_t shared_mic_nid;
927 hda_nid_t shared_out_nid;
928 hda_nid_t unsol_tag_hp;
929 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
930 hda_nid_t unsol_tag_amic1;
931
932 /* chip access */
933 struct mutex chipio_mutex; /* chip access mutex */
934 u32 curr_chip_addx;
935
936 /* DSP download related */
937 enum dsp_download_state dsp_state;
938 unsigned int dsp_stream_id;
939 unsigned int wait_scp;
940 unsigned int wait_scp_header;
941 unsigned int wait_num_data;
942 unsigned int scp_resp_header;
943 unsigned int scp_resp_data[4];
944 unsigned int scp_resp_count;
945 bool alt_firmware_present;
946 bool startup_check_entered;
947 bool dsp_reload;
948
949 /* mixer and effects related */
950 unsigned char dmic_ctl;
951 int cur_out_type;
952 int cur_mic_type;
953 long vnode_lvol[VNODES_COUNT];
954 long vnode_rvol[VNODES_COUNT];
955 long vnode_lswitch[VNODES_COUNT];
956 long vnode_rswitch[VNODES_COUNT];
957 long effects_switch[EFFECTS_COUNT];
958 long voicefx_val;
959 long cur_mic_boost;
960 /* ca0132_alt control related values */
961 unsigned char in_enum_val;
962 unsigned char out_enum_val;
963 unsigned char mic_boost_enum_val;
964 unsigned char smart_volume_setting;
965 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
966 long xbass_xover_freq;
967 long eq_preset_val;
968 unsigned int tlv[4];
969 struct hda_vmaster_mute_hook vmaster_mute;
970
971
972 struct hda_codec *codec;
973 struct delayed_work unsol_hp_work;
974 int quirk;
975
976 #ifdef ENABLE_TUNING_CONTROLS
977 long cur_ctl_vals[TUNING_CTLS_COUNT];
978 #endif
979 /*
980 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
981 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
982 * things.
983 */
984 bool use_pci_mmio;
985 void __iomem *mem_base;
986
987 /*
988 * Whether or not to use the alt functions like alt_select_out,
989 * alt_select_in, etc. Only used on desktop codecs for now, because of
990 * surround sound support.
991 */
992 bool use_alt_functions;
993
994 /*
995 * Whether or not to use alt controls: volume effect sliders, EQ
996 * presets, smart volume presets, and new control names with FX prefix.
997 * Renames PlayEnhancement and CrystalVoice too.
998 */
999 bool use_alt_controls;
1000 };
1001
1002 /*
1003 * CA0132 quirks table
1004 */
1005 enum {
1006 QUIRK_NONE,
1007 QUIRK_ALIENWARE,
1008 QUIRK_ALIENWARE_M17XR4,
1009 QUIRK_SBZ,
1010 QUIRK_R3DI,
1011 QUIRK_R3D,
1012 QUIRK_AE5,
1013 };
1014
1015 static const struct hda_pintbl alienware_pincfgs[] = {
1016 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1017 { 0x0c, 0x411111f0 }, /* N/A */
1018 { 0x0d, 0x411111f0 }, /* N/A */
1019 { 0x0e, 0x411111f0 }, /* N/A */
1020 { 0x0f, 0x0321101f }, /* HP */
1021 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1022 { 0x11, 0x03a11021 }, /* Mic */
1023 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1024 { 0x13, 0x411111f0 }, /* N/A */
1025 { 0x18, 0x411111f0 }, /* N/A */
1026 {}
1027 };
1028
1029 /* Sound Blaster Z pin configs taken from Windows Driver */
1030 static const struct hda_pintbl sbz_pincfgs[] = {
1031 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1032 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1033 { 0x0d, 0x014510f0 }, /* Digital Out */
1034 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1035 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1036 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1037 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1038 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1039 { 0x13, 0x908700f0 }, /* What U Hear In*/
1040 { 0x18, 0x50d000f0 }, /* N/A */
1041 {}
1042 };
1043
1044 /* Recon3D pin configs taken from Windows Driver */
1045 static const struct hda_pintbl r3d_pincfgs[] = {
1046 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1047 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1048 { 0x0d, 0x014510f0 }, /* Digital Out */
1049 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1050 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1051 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1052 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1053 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1054 { 0x13, 0x908700f0 }, /* What U Hear In*/
1055 { 0x18, 0x50d000f0 }, /* N/A */
1056 {}
1057 };
1058
1059 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1060 static const struct hda_pintbl ae5_pincfgs[] = {
1061 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1062 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1063 { 0x0d, 0x014510f0 }, /* Digital Out */
1064 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1065 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1066 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1067 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1068 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1069 { 0x13, 0x908700f0 }, /* What U Hear In*/
1070 { 0x18, 0x50d000f0 }, /* N/A */
1071 {}
1072 };
1073
1074 /* Recon3D integrated pin configs taken from Windows Driver */
1075 static const struct hda_pintbl r3di_pincfgs[] = {
1076 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1077 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1078 { 0x0d, 0x014510f0 }, /* Digital Out */
1079 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1080 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1081 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1082 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1083 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1084 { 0x13, 0x908700f0 }, /* What U Hear In*/
1085 { 0x18, 0x500000f0 }, /* N/A */
1086 {}
1087 };
1088
1089 static const struct snd_pci_quirk ca0132_quirks[] = {
1090 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1091 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1092 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1093 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1094 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1095 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1096 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1097 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1098 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1099 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1100 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1101 {}
1102 };
1103
1104 /*
1105 * CA0132 codec access
1106 */
1107 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1108 unsigned int verb, unsigned int parm, unsigned int *res)
1109 {
1110 unsigned int response;
1111 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1112 *res = response;
1113
1114 return ((response == -1) ? -1 : 0);
1115 }
1116
1117 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1118 unsigned short converter_format, unsigned int *res)
1119 {
1120 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1121 converter_format & 0xffff, res);
1122 }
1123
1124 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1125 hda_nid_t nid, unsigned char stream,
1126 unsigned char channel, unsigned int *res)
1127 {
1128 unsigned char converter_stream_channel = 0;
1129
1130 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1131 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1132 converter_stream_channel, res);
1133 }
1134
1135 /* Chip access helper function */
1136 static int chipio_send(struct hda_codec *codec,
1137 unsigned int reg,
1138 unsigned int data)
1139 {
1140 unsigned int res;
1141 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1142
1143 /* send bits of data specified by reg */
1144 do {
1145 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1146 reg, data);
1147 if (res == VENDOR_STATUS_CHIPIO_OK)
1148 return 0;
1149 msleep(20);
1150 } while (time_before(jiffies, timeout));
1151
1152 return -EIO;
1153 }
1154
1155 /*
1156 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1157 */
1158 static int chipio_write_address(struct hda_codec *codec,
1159 unsigned int chip_addx)
1160 {
1161 struct ca0132_spec *spec = codec->spec;
1162 int res;
1163
1164 if (spec->curr_chip_addx == chip_addx)
1165 return 0;
1166
1167 /* send low 16 bits of the address */
1168 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1169 chip_addx & 0xffff);
1170
1171 if (res != -EIO) {
1172 /* send high 16 bits of the address */
1173 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1174 chip_addx >> 16);
1175 }
1176
1177 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1178
1179 return res;
1180 }
1181
1182 /*
1183 * Write data through the vendor widget -- NOT protected by the Mutex!
1184 */
1185 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1186 {
1187 struct ca0132_spec *spec = codec->spec;
1188 int res;
1189
1190 /* send low 16 bits of the data */
1191 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1192
1193 if (res != -EIO) {
1194 /* send high 16 bits of the data */
1195 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1196 data >> 16);
1197 }
1198
1199 /*If no error encountered, automatically increment the address
1200 as per chip behaviour*/
1201 spec->curr_chip_addx = (res != -EIO) ?
1202 (spec->curr_chip_addx + 4) : ~0U;
1203 return res;
1204 }
1205
1206 /*
1207 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1208 */
1209 static int chipio_write_data_multiple(struct hda_codec *codec,
1210 const u32 *data,
1211 unsigned int count)
1212 {
1213 int status = 0;
1214
1215 if (data == NULL) {
1216 codec_dbg(codec, "chipio_write_data null ptr\n");
1217 return -EINVAL;
1218 }
1219
1220 while ((count-- != 0) && (status == 0))
1221 status = chipio_write_data(codec, *data++);
1222
1223 return status;
1224 }
1225
1226
1227 /*
1228 * Read data through the vendor widget -- NOT protected by the Mutex!
1229 */
1230 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1231 {
1232 struct ca0132_spec *spec = codec->spec;
1233 int res;
1234
1235 /* post read */
1236 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1237
1238 if (res != -EIO) {
1239 /* read status */
1240 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1241 }
1242
1243 if (res != -EIO) {
1244 /* read data */
1245 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1246 VENDOR_CHIPIO_HIC_READ_DATA,
1247 0);
1248 }
1249
1250 /*If no error encountered, automatically increment the address
1251 as per chip behaviour*/
1252 spec->curr_chip_addx = (res != -EIO) ?
1253 (spec->curr_chip_addx + 4) : ~0U;
1254 return res;
1255 }
1256
1257 /*
1258 * Write given value to the given address through the chip I/O widget.
1259 * protected by the Mutex
1260 */
1261 static int chipio_write(struct hda_codec *codec,
1262 unsigned int chip_addx, const unsigned int data)
1263 {
1264 struct ca0132_spec *spec = codec->spec;
1265 int err;
1266
1267 mutex_lock(&spec->chipio_mutex);
1268
1269 /* write the address, and if successful proceed to write data */
1270 err = chipio_write_address(codec, chip_addx);
1271 if (err < 0)
1272 goto exit;
1273
1274 err = chipio_write_data(codec, data);
1275 if (err < 0)
1276 goto exit;
1277
1278 exit:
1279 mutex_unlock(&spec->chipio_mutex);
1280 return err;
1281 }
1282
1283 /*
1284 * Write given value to the given address through the chip I/O widget.
1285 * not protected by the Mutex
1286 */
1287 static int chipio_write_no_mutex(struct hda_codec *codec,
1288 unsigned int chip_addx, const unsigned int data)
1289 {
1290 int err;
1291
1292
1293 /* write the address, and if successful proceed to write data */
1294 err = chipio_write_address(codec, chip_addx);
1295 if (err < 0)
1296 goto exit;
1297
1298 err = chipio_write_data(codec, data);
1299 if (err < 0)
1300 goto exit;
1301
1302 exit:
1303 return err;
1304 }
1305
1306 /*
1307 * Write multiple values to the given address through the chip I/O widget.
1308 * protected by the Mutex
1309 */
1310 static int chipio_write_multiple(struct hda_codec *codec,
1311 u32 chip_addx,
1312 const u32 *data,
1313 unsigned int count)
1314 {
1315 struct ca0132_spec *spec = codec->spec;
1316 int status;
1317
1318 mutex_lock(&spec->chipio_mutex);
1319 status = chipio_write_address(codec, chip_addx);
1320 if (status < 0)
1321 goto error;
1322
1323 status = chipio_write_data_multiple(codec, data, count);
1324 error:
1325 mutex_unlock(&spec->chipio_mutex);
1326
1327 return status;
1328 }
1329
1330 /*
1331 * Read the given address through the chip I/O widget
1332 * protected by the Mutex
1333 */
1334 static int chipio_read(struct hda_codec *codec,
1335 unsigned int chip_addx, unsigned int *data)
1336 {
1337 struct ca0132_spec *spec = codec->spec;
1338 int err;
1339
1340 mutex_lock(&spec->chipio_mutex);
1341
1342 /* write the address, and if successful proceed to write data */
1343 err = chipio_write_address(codec, chip_addx);
1344 if (err < 0)
1345 goto exit;
1346
1347 err = chipio_read_data(codec, data);
1348 if (err < 0)
1349 goto exit;
1350
1351 exit:
1352 mutex_unlock(&spec->chipio_mutex);
1353 return err;
1354 }
1355
1356 /*
1357 * Set chip control flags through the chip I/O widget.
1358 */
1359 static void chipio_set_control_flag(struct hda_codec *codec,
1360 enum control_flag_id flag_id,
1361 bool flag_state)
1362 {
1363 unsigned int val;
1364 unsigned int flag_bit;
1365
1366 flag_bit = (flag_state ? 1 : 0);
1367 val = (flag_bit << 7) | (flag_id);
1368 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1369 VENDOR_CHIPIO_FLAG_SET, val);
1370 }
1371
1372 /*
1373 * Set chip parameters through the chip I/O widget.
1374 */
1375 static void chipio_set_control_param(struct hda_codec *codec,
1376 enum control_param_id param_id, int param_val)
1377 {
1378 struct ca0132_spec *spec = codec->spec;
1379 int val;
1380
1381 if ((param_id < 32) && (param_val < 8)) {
1382 val = (param_val << 5) | (param_id);
1383 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1384 VENDOR_CHIPIO_PARAM_SET, val);
1385 } else {
1386 mutex_lock(&spec->chipio_mutex);
1387 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1388 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1389 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1390 param_id);
1391 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1392 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1393 param_val);
1394 }
1395 mutex_unlock(&spec->chipio_mutex);
1396 }
1397 }
1398
1399 /*
1400 * Set chip parameters through the chip I/O widget. NO MUTEX.
1401 */
1402 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1403 enum control_param_id param_id, int param_val)
1404 {
1405 int val;
1406
1407 if ((param_id < 32) && (param_val < 8)) {
1408 val = (param_val << 5) | (param_id);
1409 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1410 VENDOR_CHIPIO_PARAM_SET, val);
1411 } else {
1412 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1413 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1414 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1415 param_id);
1416 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1417 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1418 param_val);
1419 }
1420 }
1421 }
1422 /*
1423 * Connect stream to a source point, and then connect
1424 * that source point to a destination point.
1425 */
1426 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1427 int streamid, int source_point, int dest_point)
1428 {
1429 chipio_set_control_param_no_mutex(codec,
1430 CONTROL_PARAM_STREAM_ID, streamid);
1431 chipio_set_control_param_no_mutex(codec,
1432 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1433 chipio_set_control_param_no_mutex(codec,
1434 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1435 }
1436
1437 /*
1438 * Set number of channels in the selected stream.
1439 */
1440 static void chipio_set_stream_channels(struct hda_codec *codec,
1441 int streamid, unsigned int channels)
1442 {
1443 chipio_set_control_param_no_mutex(codec,
1444 CONTROL_PARAM_STREAM_ID, streamid);
1445 chipio_set_control_param_no_mutex(codec,
1446 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1447 }
1448
1449 /*
1450 * Enable/Disable audio stream.
1451 */
1452 static void chipio_set_stream_control(struct hda_codec *codec,
1453 int streamid, int enable)
1454 {
1455 chipio_set_control_param_no_mutex(codec,
1456 CONTROL_PARAM_STREAM_ID, streamid);
1457 chipio_set_control_param_no_mutex(codec,
1458 CONTROL_PARAM_STREAM_CONTROL, enable);
1459 }
1460
1461
1462 /*
1463 * Set sampling rate of the connection point. NO MUTEX.
1464 */
1465 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1466 int connid, enum ca0132_sample_rate rate)
1467 {
1468 chipio_set_control_param_no_mutex(codec,
1469 CONTROL_PARAM_CONN_POINT_ID, connid);
1470 chipio_set_control_param_no_mutex(codec,
1471 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1472 }
1473
1474 /*
1475 * Set sampling rate of the connection point.
1476 */
1477 static void chipio_set_conn_rate(struct hda_codec *codec,
1478 int connid, enum ca0132_sample_rate rate)
1479 {
1480 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1481 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1482 rate);
1483 }
1484
1485 /*
1486 * Writes to the 8051's internal address space directly instead of indirectly,
1487 * giving access to the special function registers located at addresses
1488 * 0x80-0xFF.
1489 */
1490 static void chipio_8051_write_direct(struct hda_codec *codec,
1491 unsigned int addr, unsigned int data)
1492 {
1493 unsigned int verb;
1494
1495 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1496 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1497 }
1498
1499 /*
1500 * Enable clocks.
1501 */
1502 static void chipio_enable_clocks(struct hda_codec *codec)
1503 {
1504 struct ca0132_spec *spec = codec->spec;
1505
1506 mutex_lock(&spec->chipio_mutex);
1507 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1508 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1509 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1510 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1511 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1512 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1513 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1514 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1515 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1516 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1517 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1518 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1519 mutex_unlock(&spec->chipio_mutex);
1520 }
1521
1522 /*
1523 * CA0132 DSP IO stuffs
1524 */
1525 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1526 unsigned int data)
1527 {
1528 int res;
1529 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1530
1531 /* send bits of data specified by reg to dsp */
1532 do {
1533 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1534 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1535 return res;
1536 msleep(20);
1537 } while (time_before(jiffies, timeout));
1538
1539 return -EIO;
1540 }
1541
1542 /*
1543 * Wait for DSP to be ready for commands
1544 */
1545 static void dspio_write_wait(struct hda_codec *codec)
1546 {
1547 int status;
1548 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1549
1550 do {
1551 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1552 VENDOR_DSPIO_STATUS, 0);
1553 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1554 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1555 break;
1556 msleep(1);
1557 } while (time_before(jiffies, timeout));
1558 }
1559
1560 /*
1561 * Write SCP data to DSP
1562 */
1563 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1564 {
1565 struct ca0132_spec *spec = codec->spec;
1566 int status;
1567
1568 dspio_write_wait(codec);
1569
1570 mutex_lock(&spec->chipio_mutex);
1571 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1572 scp_data & 0xffff);
1573 if (status < 0)
1574 goto error;
1575
1576 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1577 scp_data >> 16);
1578 if (status < 0)
1579 goto error;
1580
1581 /* OK, now check if the write itself has executed*/
1582 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1583 VENDOR_DSPIO_STATUS, 0);
1584 error:
1585 mutex_unlock(&spec->chipio_mutex);
1586
1587 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1588 -EIO : 0;
1589 }
1590
1591 /*
1592 * Write multiple SCP data to DSP
1593 */
1594 static int dspio_write_multiple(struct hda_codec *codec,
1595 unsigned int *buffer, unsigned int size)
1596 {
1597 int status = 0;
1598 unsigned int count;
1599
1600 if (buffer == NULL)
1601 return -EINVAL;
1602
1603 count = 0;
1604 while (count < size) {
1605 status = dspio_write(codec, *buffer++);
1606 if (status != 0)
1607 break;
1608 count++;
1609 }
1610
1611 return status;
1612 }
1613
1614 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1615 {
1616 int status;
1617
1618 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1619 if (status == -EIO)
1620 return status;
1621
1622 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1623 if (status == -EIO ||
1624 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1625 return -EIO;
1626
1627 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1628 VENDOR_DSPIO_SCP_READ_DATA, 0);
1629
1630 return 0;
1631 }
1632
1633 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1634 unsigned int *buf_size, unsigned int size_count)
1635 {
1636 int status = 0;
1637 unsigned int size = *buf_size;
1638 unsigned int count;
1639 unsigned int skip_count;
1640 unsigned int dummy;
1641
1642 if (buffer == NULL)
1643 return -1;
1644
1645 count = 0;
1646 while (count < size && count < size_count) {
1647 status = dspio_read(codec, buffer++);
1648 if (status != 0)
1649 break;
1650 count++;
1651 }
1652
1653 skip_count = count;
1654 if (status == 0) {
1655 while (skip_count < size) {
1656 status = dspio_read(codec, &dummy);
1657 if (status != 0)
1658 break;
1659 skip_count++;
1660 }
1661 }
1662 *buf_size = count;
1663
1664 return status;
1665 }
1666
1667 /*
1668 * Construct the SCP header using corresponding fields
1669 */
1670 static inline unsigned int
1671 make_scp_header(unsigned int target_id, unsigned int source_id,
1672 unsigned int get_flag, unsigned int req,
1673 unsigned int device_flag, unsigned int resp_flag,
1674 unsigned int error_flag, unsigned int data_size)
1675 {
1676 unsigned int header = 0;
1677
1678 header = (data_size & 0x1f) << 27;
1679 header |= (error_flag & 0x01) << 26;
1680 header |= (resp_flag & 0x01) << 25;
1681 header |= (device_flag & 0x01) << 24;
1682 header |= (req & 0x7f) << 17;
1683 header |= (get_flag & 0x01) << 16;
1684 header |= (source_id & 0xff) << 8;
1685 header |= target_id & 0xff;
1686
1687 return header;
1688 }
1689
1690 /*
1691 * Extract corresponding fields from SCP header
1692 */
1693 static inline void
1694 extract_scp_header(unsigned int header,
1695 unsigned int *target_id, unsigned int *source_id,
1696 unsigned int *get_flag, unsigned int *req,
1697 unsigned int *device_flag, unsigned int *resp_flag,
1698 unsigned int *error_flag, unsigned int *data_size)
1699 {
1700 if (data_size)
1701 *data_size = (header >> 27) & 0x1f;
1702 if (error_flag)
1703 *error_flag = (header >> 26) & 0x01;
1704 if (resp_flag)
1705 *resp_flag = (header >> 25) & 0x01;
1706 if (device_flag)
1707 *device_flag = (header >> 24) & 0x01;
1708 if (req)
1709 *req = (header >> 17) & 0x7f;
1710 if (get_flag)
1711 *get_flag = (header >> 16) & 0x01;
1712 if (source_id)
1713 *source_id = (header >> 8) & 0xff;
1714 if (target_id)
1715 *target_id = header & 0xff;
1716 }
1717
1718 #define SCP_MAX_DATA_WORDS (16)
1719
1720 /* Structure to contain any SCP message */
1721 struct scp_msg {
1722 unsigned int hdr;
1723 unsigned int data[SCP_MAX_DATA_WORDS];
1724 };
1725
1726 static void dspio_clear_response_queue(struct hda_codec *codec)
1727 {
1728 unsigned int dummy = 0;
1729 int status = -1;
1730
1731 /* clear all from the response queue */
1732 do {
1733 status = dspio_read(codec, &dummy);
1734 } while (status == 0);
1735 }
1736
1737 static int dspio_get_response_data(struct hda_codec *codec)
1738 {
1739 struct ca0132_spec *spec = codec->spec;
1740 unsigned int data = 0;
1741 unsigned int count;
1742
1743 if (dspio_read(codec, &data) < 0)
1744 return -EIO;
1745
1746 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1747 spec->scp_resp_header = data;
1748 spec->scp_resp_count = data >> 27;
1749 count = spec->wait_num_data;
1750 dspio_read_multiple(codec, spec->scp_resp_data,
1751 &spec->scp_resp_count, count);
1752 return 0;
1753 }
1754
1755 return -EIO;
1756 }
1757
1758 /*
1759 * Send SCP message to DSP
1760 */
1761 static int dspio_send_scp_message(struct hda_codec *codec,
1762 unsigned char *send_buf,
1763 unsigned int send_buf_size,
1764 unsigned char *return_buf,
1765 unsigned int return_buf_size,
1766 unsigned int *bytes_returned)
1767 {
1768 struct ca0132_spec *spec = codec->spec;
1769 int status = -1;
1770 unsigned int scp_send_size = 0;
1771 unsigned int total_size;
1772 bool waiting_for_resp = false;
1773 unsigned int header;
1774 struct scp_msg *ret_msg;
1775 unsigned int resp_src_id, resp_target_id;
1776 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1777
1778 if (bytes_returned)
1779 *bytes_returned = 0;
1780
1781 /* get scp header from buffer */
1782 header = *((unsigned int *)send_buf);
1783 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1784 &device_flag, NULL, NULL, &data_size);
1785 scp_send_size = data_size + 1;
1786 total_size = (scp_send_size * 4);
1787
1788 if (send_buf_size < total_size)
1789 return -EINVAL;
1790
1791 if (get_flag || device_flag) {
1792 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1793 return -EINVAL;
1794
1795 spec->wait_scp_header = *((unsigned int *)send_buf);
1796
1797 /* swap source id with target id */
1798 resp_target_id = src_id;
1799 resp_src_id = target_id;
1800 spec->wait_scp_header &= 0xffff0000;
1801 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1802 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1803 spec->wait_scp = 1;
1804 waiting_for_resp = true;
1805 }
1806
1807 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1808 scp_send_size);
1809 if (status < 0) {
1810 spec->wait_scp = 0;
1811 return status;
1812 }
1813
1814 if (waiting_for_resp) {
1815 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1816 memset(return_buf, 0, return_buf_size);
1817 do {
1818 msleep(20);
1819 } while (spec->wait_scp && time_before(jiffies, timeout));
1820 waiting_for_resp = false;
1821 if (!spec->wait_scp) {
1822 ret_msg = (struct scp_msg *)return_buf;
1823 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1824 memcpy(&ret_msg->data, spec->scp_resp_data,
1825 spec->wait_num_data);
1826 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1827 status = 0;
1828 } else {
1829 status = -EIO;
1830 }
1831 spec->wait_scp = 0;
1832 }
1833
1834 return status;
1835 }
1836
1837 /**
1838 * Prepare and send the SCP message to DSP
1839 * @codec: the HDA codec
1840 * @mod_id: ID of the DSP module to send the command
1841 * @req: ID of request to send to the DSP module
1842 * @dir: SET or GET
1843 * @data: pointer to the data to send with the request, request specific
1844 * @len: length of the data, in bytes
1845 * @reply: point to the buffer to hold data returned for a reply
1846 * @reply_len: length of the reply buffer returned from GET
1847 *
1848 * Returns zero or a negative error code.
1849 */
1850 static int dspio_scp(struct hda_codec *codec,
1851 int mod_id, int src_id, int req, int dir, const void *data,
1852 unsigned int len, void *reply, unsigned int *reply_len)
1853 {
1854 int status = 0;
1855 struct scp_msg scp_send, scp_reply;
1856 unsigned int ret_bytes, send_size, ret_size;
1857 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1858 unsigned int reply_data_size;
1859
1860 memset(&scp_send, 0, sizeof(scp_send));
1861 memset(&scp_reply, 0, sizeof(scp_reply));
1862
1863 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1864 return -EINVAL;
1865
1866 if (dir == SCP_GET && reply == NULL) {
1867 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1868 return -EINVAL;
1869 }
1870
1871 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1872 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1873 return -EINVAL;
1874 }
1875
1876 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1877 0, 0, 0, len/sizeof(unsigned int));
1878 if (data != NULL && len > 0) {
1879 len = min((unsigned int)(sizeof(scp_send.data)), len);
1880 memcpy(scp_send.data, data, len);
1881 }
1882
1883 ret_bytes = 0;
1884 send_size = sizeof(unsigned int) + len;
1885 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1886 send_size, (unsigned char *)&scp_reply,
1887 sizeof(scp_reply), &ret_bytes);
1888
1889 if (status < 0) {
1890 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1891 return status;
1892 }
1893
1894 /* extract send and reply headers members */
1895 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1896 NULL, NULL, NULL, NULL, NULL);
1897 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1898 &reply_resp_flag, &reply_error_flag,
1899 &reply_data_size);
1900
1901 if (!send_get_flag)
1902 return 0;
1903
1904 if (reply_resp_flag && !reply_error_flag) {
1905 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1906 / sizeof(unsigned int);
1907
1908 if (*reply_len < ret_size*sizeof(unsigned int)) {
1909 codec_dbg(codec, "reply too long for buf\n");
1910 return -EINVAL;
1911 } else if (ret_size != reply_data_size) {
1912 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1913 return -EINVAL;
1914 } else if (!reply) {
1915 codec_dbg(codec, "NULL reply\n");
1916 return -EINVAL;
1917 } else {
1918 *reply_len = ret_size*sizeof(unsigned int);
1919 memcpy(reply, scp_reply.data, *reply_len);
1920 }
1921 } else {
1922 codec_dbg(codec, "reply ill-formed or errflag set\n");
1923 return -EIO;
1924 }
1925
1926 return status;
1927 }
1928
1929 /*
1930 * Set DSP parameters
1931 */
1932 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1933 int src_id, int req, const void *data, unsigned int len)
1934 {
1935 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1936 NULL);
1937 }
1938
1939 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1940 int req, const unsigned int data)
1941 {
1942 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1943 sizeof(unsigned int));
1944 }
1945
1946 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1947 int req, const unsigned int data)
1948 {
1949 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1950 sizeof(unsigned int));
1951 }
1952
1953 /*
1954 * Allocate a DSP DMA channel via an SCP message
1955 */
1956 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1957 {
1958 int status = 0;
1959 unsigned int size = sizeof(dma_chan);
1960
1961 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1962 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1963 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1964 dma_chan, &size);
1965
1966 if (status < 0) {
1967 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1968 return status;
1969 }
1970
1971 if ((*dma_chan + 1) == 0) {
1972 codec_dbg(codec, "no free dma channels to allocate\n");
1973 return -EBUSY;
1974 }
1975
1976 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1977 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1978
1979 return status;
1980 }
1981
1982 /*
1983 * Free a DSP DMA via an SCP message
1984 */
1985 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1986 {
1987 int status = 0;
1988 unsigned int dummy = 0;
1989
1990 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1991 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1992
1993 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1994 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1995 sizeof(dma_chan), NULL, &dummy);
1996
1997 if (status < 0) {
1998 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1999 return status;
2000 }
2001
2002 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2003
2004 return status;
2005 }
2006
2007 /*
2008 * (Re)start the DSP
2009 */
2010 static int dsp_set_run_state(struct hda_codec *codec)
2011 {
2012 unsigned int dbg_ctrl_reg;
2013 unsigned int halt_state;
2014 int err;
2015
2016 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2017 if (err < 0)
2018 return err;
2019
2020 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2021 DSP_DBGCNTL_STATE_LOBIT;
2022
2023 if (halt_state != 0) {
2024 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2025 DSP_DBGCNTL_SS_MASK);
2026 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2027 dbg_ctrl_reg);
2028 if (err < 0)
2029 return err;
2030
2031 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2032 DSP_DBGCNTL_EXEC_MASK;
2033 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2034 dbg_ctrl_reg);
2035 if (err < 0)
2036 return err;
2037 }
2038
2039 return 0;
2040 }
2041
2042 /*
2043 * Reset the DSP
2044 */
2045 static int dsp_reset(struct hda_codec *codec)
2046 {
2047 unsigned int res;
2048 int retry = 20;
2049
2050 codec_dbg(codec, "dsp_reset\n");
2051 do {
2052 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2053 retry--;
2054 } while (res == -EIO && retry);
2055
2056 if (!retry) {
2057 codec_dbg(codec, "dsp_reset timeout\n");
2058 return -EIO;
2059 }
2060
2061 return 0;
2062 }
2063
2064 /*
2065 * Convert chip address to DSP address
2066 */
2067 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2068 bool *code, bool *yram)
2069 {
2070 *code = *yram = false;
2071
2072 if (UC_RANGE(chip_addx, 1)) {
2073 *code = true;
2074 return UC_OFF(chip_addx);
2075 } else if (X_RANGE_ALL(chip_addx, 1)) {
2076 return X_OFF(chip_addx);
2077 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2078 *yram = true;
2079 return Y_OFF(chip_addx);
2080 }
2081
2082 return INVALID_CHIP_ADDRESS;
2083 }
2084
2085 /*
2086 * Check if the DSP DMA is active
2087 */
2088 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2089 {
2090 unsigned int dma_chnlstart_reg;
2091
2092 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2093
2094 return ((dma_chnlstart_reg & (1 <<
2095 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2096 }
2097
2098 static int dsp_dma_setup_common(struct hda_codec *codec,
2099 unsigned int chip_addx,
2100 unsigned int dma_chan,
2101 unsigned int port_map_mask,
2102 bool ovly)
2103 {
2104 int status = 0;
2105 unsigned int chnl_prop;
2106 unsigned int dsp_addx;
2107 unsigned int active;
2108 bool code, yram;
2109
2110 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2111
2112 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2113 codec_dbg(codec, "dma chan num invalid\n");
2114 return -EINVAL;
2115 }
2116
2117 if (dsp_is_dma_active(codec, dma_chan)) {
2118 codec_dbg(codec, "dma already active\n");
2119 return -EBUSY;
2120 }
2121
2122 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2123
2124 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2125 codec_dbg(codec, "invalid chip addr\n");
2126 return -ENXIO;
2127 }
2128
2129 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2130 active = 0;
2131
2132 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2133
2134 if (ovly) {
2135 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2136 &chnl_prop);
2137
2138 if (status < 0) {
2139 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2140 return status;
2141 }
2142 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2143 }
2144
2145 if (!code)
2146 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2147 else
2148 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2149
2150 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2151
2152 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2153 if (status < 0) {
2154 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2155 return status;
2156 }
2157 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2158
2159 if (ovly) {
2160 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2161 &active);
2162
2163 if (status < 0) {
2164 codec_dbg(codec, "read ACTIVE Reg fail\n");
2165 return status;
2166 }
2167 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2168 }
2169
2170 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2171 DSPDMAC_ACTIVE_AAR_MASK;
2172
2173 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2174 if (status < 0) {
2175 codec_dbg(codec, "write ACTIVE Reg fail\n");
2176 return status;
2177 }
2178
2179 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2180
2181 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2182 port_map_mask);
2183 if (status < 0) {
2184 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2185 return status;
2186 }
2187 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2188
2189 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2190 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2191 if (status < 0) {
2192 codec_dbg(codec, "write IRQCNT Reg fail\n");
2193 return status;
2194 }
2195 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2196
2197 codec_dbg(codec,
2198 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2199 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2200 chip_addx, dsp_addx, dma_chan,
2201 port_map_mask, chnl_prop, active);
2202
2203 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2204
2205 return 0;
2206 }
2207
2208 /*
2209 * Setup the DSP DMA per-transfer-specific registers
2210 */
2211 static int dsp_dma_setup(struct hda_codec *codec,
2212 unsigned int chip_addx,
2213 unsigned int count,
2214 unsigned int dma_chan)
2215 {
2216 int status = 0;
2217 bool code, yram;
2218 unsigned int dsp_addx;
2219 unsigned int addr_field;
2220 unsigned int incr_field;
2221 unsigned int base_cnt;
2222 unsigned int cur_cnt;
2223 unsigned int dma_cfg = 0;
2224 unsigned int adr_ofs = 0;
2225 unsigned int xfr_cnt = 0;
2226 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2227 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2228
2229 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2230
2231 if (count > max_dma_count) {
2232 codec_dbg(codec, "count too big\n");
2233 return -EINVAL;
2234 }
2235
2236 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2237 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2238 codec_dbg(codec, "invalid chip addr\n");
2239 return -ENXIO;
2240 }
2241
2242 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2243
2244 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2245 incr_field = 0;
2246
2247 if (!code) {
2248 addr_field <<= 1;
2249 if (yram)
2250 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2251
2252 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2253 }
2254
2255 dma_cfg = addr_field + incr_field;
2256 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2257 dma_cfg);
2258 if (status < 0) {
2259 codec_dbg(codec, "write DMACFG Reg fail\n");
2260 return status;
2261 }
2262 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2263
2264 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2265 (code ? 0 : 1));
2266
2267 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2268 adr_ofs);
2269 if (status < 0) {
2270 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2271 return status;
2272 }
2273 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2274
2275 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2276
2277 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2278
2279 xfr_cnt = base_cnt | cur_cnt;
2280
2281 status = chipio_write(codec,
2282 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2283 if (status < 0) {
2284 codec_dbg(codec, "write XFRCNT Reg fail\n");
2285 return status;
2286 }
2287 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2288
2289 codec_dbg(codec,
2290 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2291 "ADROFS=0x%x, XFRCNT=0x%x\n",
2292 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2293
2294 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2295
2296 return 0;
2297 }
2298
2299 /*
2300 * Start the DSP DMA
2301 */
2302 static int dsp_dma_start(struct hda_codec *codec,
2303 unsigned int dma_chan, bool ovly)
2304 {
2305 unsigned int reg = 0;
2306 int status = 0;
2307
2308 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2309
2310 if (ovly) {
2311 status = chipio_read(codec,
2312 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2313
2314 if (status < 0) {
2315 codec_dbg(codec, "read CHNLSTART reg fail\n");
2316 return status;
2317 }
2318 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2319
2320 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2321 DSPDMAC_CHNLSTART_DIS_MASK);
2322 }
2323
2324 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2325 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2326 if (status < 0) {
2327 codec_dbg(codec, "write CHNLSTART reg fail\n");
2328 return status;
2329 }
2330 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2331
2332 return status;
2333 }
2334
2335 /*
2336 * Stop the DSP DMA
2337 */
2338 static int dsp_dma_stop(struct hda_codec *codec,
2339 unsigned int dma_chan, bool ovly)
2340 {
2341 unsigned int reg = 0;
2342 int status = 0;
2343
2344 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2345
2346 if (ovly) {
2347 status = chipio_read(codec,
2348 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2349
2350 if (status < 0) {
2351 codec_dbg(codec, "read CHNLSTART reg fail\n");
2352 return status;
2353 }
2354 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2355 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2356 DSPDMAC_CHNLSTART_DIS_MASK);
2357 }
2358
2359 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2360 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2361 if (status < 0) {
2362 codec_dbg(codec, "write CHNLSTART reg fail\n");
2363 return status;
2364 }
2365 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2366
2367 return status;
2368 }
2369
2370 /**
2371 * Allocate router ports
2372 *
2373 * @codec: the HDA codec
2374 * @num_chans: number of channels in the stream
2375 * @ports_per_channel: number of ports per channel
2376 * @start_device: start device
2377 * @port_map: pointer to the port list to hold the allocated ports
2378 *
2379 * Returns zero or a negative error code.
2380 */
2381 static int dsp_allocate_router_ports(struct hda_codec *codec,
2382 unsigned int num_chans,
2383 unsigned int ports_per_channel,
2384 unsigned int start_device,
2385 unsigned int *port_map)
2386 {
2387 int status = 0;
2388 int res;
2389 u8 val;
2390
2391 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2392 if (status < 0)
2393 return status;
2394
2395 val = start_device << 6;
2396 val |= (ports_per_channel - 1) << 4;
2397 val |= num_chans - 1;
2398
2399 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2400 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2401 val);
2402
2403 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2404 VENDOR_CHIPIO_PORT_ALLOC_SET,
2405 MEM_CONNID_DSP);
2406
2407 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2408 if (status < 0)
2409 return status;
2410
2411 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2412 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2413
2414 *port_map = res;
2415
2416 return (res < 0) ? res : 0;
2417 }
2418
2419 /*
2420 * Free router ports
2421 */
2422 static int dsp_free_router_ports(struct hda_codec *codec)
2423 {
2424 int status = 0;
2425
2426 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2427 if (status < 0)
2428 return status;
2429
2430 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2431 VENDOR_CHIPIO_PORT_FREE_SET,
2432 MEM_CONNID_DSP);
2433
2434 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2435
2436 return status;
2437 }
2438
2439 /*
2440 * Allocate DSP ports for the download stream
2441 */
2442 static int dsp_allocate_ports(struct hda_codec *codec,
2443 unsigned int num_chans,
2444 unsigned int rate_multi, unsigned int *port_map)
2445 {
2446 int status;
2447
2448 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2449
2450 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2451 codec_dbg(codec, "bad rate multiple\n");
2452 return -EINVAL;
2453 }
2454
2455 status = dsp_allocate_router_ports(codec, num_chans,
2456 rate_multi, 0, port_map);
2457
2458 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2459
2460 return status;
2461 }
2462
2463 static int dsp_allocate_ports_format(struct hda_codec *codec,
2464 const unsigned short fmt,
2465 unsigned int *port_map)
2466 {
2467 int status;
2468 unsigned int num_chans;
2469
2470 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2471 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2472 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2473
2474 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2475 codec_dbg(codec, "bad rate multiple\n");
2476 return -EINVAL;
2477 }
2478
2479 num_chans = get_hdafmt_chs(fmt) + 1;
2480
2481 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2482
2483 return status;
2484 }
2485
2486 /*
2487 * free DSP ports
2488 */
2489 static int dsp_free_ports(struct hda_codec *codec)
2490 {
2491 int status;
2492
2493 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2494
2495 status = dsp_free_router_ports(codec);
2496 if (status < 0) {
2497 codec_dbg(codec, "free router ports fail\n");
2498 return status;
2499 }
2500 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2501
2502 return status;
2503 }
2504
2505 /*
2506 * HDA DMA engine stuffs for DSP code download
2507 */
2508 struct dma_engine {
2509 struct hda_codec *codec;
2510 unsigned short m_converter_format;
2511 struct snd_dma_buffer *dmab;
2512 unsigned int buf_size;
2513 };
2514
2515
2516 enum dma_state {
2517 DMA_STATE_STOP = 0,
2518 DMA_STATE_RUN = 1
2519 };
2520
2521 static int dma_convert_to_hda_format(struct hda_codec *codec,
2522 unsigned int sample_rate,
2523 unsigned short channels,
2524 unsigned short *hda_format)
2525 {
2526 unsigned int format_val;
2527
2528 format_val = snd_hdac_calc_stream_format(sample_rate,
2529 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2530
2531 if (hda_format)
2532 *hda_format = (unsigned short)format_val;
2533
2534 return 0;
2535 }
2536
2537 /*
2538 * Reset DMA for DSP download
2539 */
2540 static int dma_reset(struct dma_engine *dma)
2541 {
2542 struct hda_codec *codec = dma->codec;
2543 struct ca0132_spec *spec = codec->spec;
2544 int status;
2545
2546 if (dma->dmab->area)
2547 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2548
2549 status = snd_hda_codec_load_dsp_prepare(codec,
2550 dma->m_converter_format,
2551 dma->buf_size,
2552 dma->dmab);
2553 if (status < 0)
2554 return status;
2555 spec->dsp_stream_id = status;
2556 return 0;
2557 }
2558
2559 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2560 {
2561 bool cmd;
2562
2563 switch (state) {
2564 case DMA_STATE_STOP:
2565 cmd = false;
2566 break;
2567 case DMA_STATE_RUN:
2568 cmd = true;
2569 break;
2570 default:
2571 return 0;
2572 }
2573
2574 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2575 return 0;
2576 }
2577
2578 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2579 {
2580 return dma->dmab->bytes;
2581 }
2582
2583 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2584 {
2585 return dma->dmab->area;
2586 }
2587
2588 static int dma_xfer(struct dma_engine *dma,
2589 const unsigned int *data,
2590 unsigned int count)
2591 {
2592 memcpy(dma->dmab->area, data, count);
2593 return 0;
2594 }
2595
2596 static void dma_get_converter_format(
2597 struct dma_engine *dma,
2598 unsigned short *format)
2599 {
2600 if (format)
2601 *format = dma->m_converter_format;
2602 }
2603
2604 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2605 {
2606 struct ca0132_spec *spec = dma->codec->spec;
2607
2608 return spec->dsp_stream_id;
2609 }
2610
2611 struct dsp_image_seg {
2612 u32 magic;
2613 u32 chip_addr;
2614 u32 count;
2615 u32 data[0];
2616 };
2617
2618 static const u32 g_magic_value = 0x4c46584d;
2619 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2620
2621 static bool is_valid(const struct dsp_image_seg *p)
2622 {
2623 return p->magic == g_magic_value;
2624 }
2625
2626 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2627 {
2628 return g_chip_addr_magic_value == p->chip_addr;
2629 }
2630
2631 static bool is_last(const struct dsp_image_seg *p)
2632 {
2633 return p->count == 0;
2634 }
2635
2636 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2637 {
2638 return sizeof(*p) + p->count*sizeof(u32);
2639 }
2640
2641 static const struct dsp_image_seg *get_next_seg_ptr(
2642 const struct dsp_image_seg *p)
2643 {
2644 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2645 }
2646
2647 /*
2648 * CA0132 chip DSP transfer stuffs. For DSP download.
2649 */
2650 #define INVALID_DMA_CHANNEL (~0U)
2651
2652 /*
2653 * Program a list of address/data pairs via the ChipIO widget.
2654 * The segment data is in the format of successive pairs of words.
2655 * These are repeated as indicated by the segment's count field.
2656 */
2657 static int dspxfr_hci_write(struct hda_codec *codec,
2658 const struct dsp_image_seg *fls)
2659 {
2660 int status;
2661 const u32 *data;
2662 unsigned int count;
2663
2664 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2665 codec_dbg(codec, "hci_write invalid params\n");
2666 return -EINVAL;
2667 }
2668
2669 count = fls->count;
2670 data = (u32 *)(fls->data);
2671 while (count >= 2) {
2672 status = chipio_write(codec, data[0], data[1]);
2673 if (status < 0) {
2674 codec_dbg(codec, "hci_write chipio failed\n");
2675 return status;
2676 }
2677 count -= 2;
2678 data += 2;
2679 }
2680 return 0;
2681 }
2682
2683 /**
2684 * Write a block of data into DSP code or data RAM using pre-allocated
2685 * DMA engine.
2686 *
2687 * @codec: the HDA codec
2688 * @fls: pointer to a fast load image
2689 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2690 * no relocation
2691 * @dma_engine: pointer to DMA engine to be used for DSP download
2692 * @dma_chan: The number of DMA channels used for DSP download
2693 * @port_map_mask: port mapping
2694 * @ovly: TRUE if overlay format is required
2695 *
2696 * Returns zero or a negative error code.
2697 */
2698 static int dspxfr_one_seg(struct hda_codec *codec,
2699 const struct dsp_image_seg *fls,
2700 unsigned int reloc,
2701 struct dma_engine *dma_engine,
2702 unsigned int dma_chan,
2703 unsigned int port_map_mask,
2704 bool ovly)
2705 {
2706 int status = 0;
2707 bool comm_dma_setup_done = false;
2708 const unsigned int *data;
2709 unsigned int chip_addx;
2710 unsigned int words_to_write;
2711 unsigned int buffer_size_words;
2712 unsigned char *buffer_addx;
2713 unsigned short hda_format;
2714 unsigned int sample_rate_div;
2715 unsigned int sample_rate_mul;
2716 unsigned int num_chans;
2717 unsigned int hda_frame_size_words;
2718 unsigned int remainder_words;
2719 const u32 *data_remainder;
2720 u32 chip_addx_remainder;
2721 unsigned int run_size_words;
2722 const struct dsp_image_seg *hci_write = NULL;
2723 unsigned long timeout;
2724 bool dma_active;
2725
2726 if (fls == NULL)
2727 return -EINVAL;
2728 if (is_hci_prog_list_seg(fls)) {
2729 hci_write = fls;
2730 fls = get_next_seg_ptr(fls);
2731 }
2732
2733 if (hci_write && (!fls || is_last(fls))) {
2734 codec_dbg(codec, "hci_write\n");
2735 return dspxfr_hci_write(codec, hci_write);
2736 }
2737
2738 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2739 codec_dbg(codec, "Invalid Params\n");
2740 return -EINVAL;
2741 }
2742
2743 data = fls->data;
2744 chip_addx = fls->chip_addr,
2745 words_to_write = fls->count;
2746
2747 if (!words_to_write)
2748 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2749 if (reloc)
2750 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2751
2752 if (!UC_RANGE(chip_addx, words_to_write) &&
2753 !X_RANGE_ALL(chip_addx, words_to_write) &&
2754 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2755 codec_dbg(codec, "Invalid chip_addx Params\n");
2756 return -EINVAL;
2757 }
2758
2759 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2760 sizeof(u32);
2761
2762 buffer_addx = dma_get_buffer_addr(dma_engine);
2763
2764 if (buffer_addx == NULL) {
2765 codec_dbg(codec, "dma_engine buffer NULL\n");
2766 return -EINVAL;
2767 }
2768
2769 dma_get_converter_format(dma_engine, &hda_format);
2770 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2771 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2772 num_chans = get_hdafmt_chs(hda_format) + 1;
2773
2774 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2775 (num_chans * sample_rate_mul / sample_rate_div));
2776
2777 if (hda_frame_size_words == 0) {
2778 codec_dbg(codec, "frmsz zero\n");
2779 return -EINVAL;
2780 }
2781
2782 buffer_size_words = min(buffer_size_words,
2783 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2784 65536 : 32768));
2785 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2786 codec_dbg(codec,
2787 "chpadr=0x%08x frmsz=%u nchan=%u "
2788 "rate_mul=%u div=%u bufsz=%u\n",
2789 chip_addx, hda_frame_size_words, num_chans,
2790 sample_rate_mul, sample_rate_div, buffer_size_words);
2791
2792 if (buffer_size_words < hda_frame_size_words) {
2793 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2794 return -EINVAL;
2795 }
2796
2797 remainder_words = words_to_write % hda_frame_size_words;
2798 data_remainder = data;
2799 chip_addx_remainder = chip_addx;
2800
2801 data += remainder_words;
2802 chip_addx += remainder_words*sizeof(u32);
2803 words_to_write -= remainder_words;
2804
2805 while (words_to_write != 0) {
2806 run_size_words = min(buffer_size_words, words_to_write);
2807 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2808 words_to_write, run_size_words, remainder_words);
2809 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2810 if (!comm_dma_setup_done) {
2811 status = dsp_dma_stop(codec, dma_chan, ovly);
2812 if (status < 0)
2813 return status;
2814 status = dsp_dma_setup_common(codec, chip_addx,
2815 dma_chan, port_map_mask, ovly);
2816 if (status < 0)
2817 return status;
2818 comm_dma_setup_done = true;
2819 }
2820
2821 status = dsp_dma_setup(codec, chip_addx,
2822 run_size_words, dma_chan);
2823 if (status < 0)
2824 return status;
2825 status = dsp_dma_start(codec, dma_chan, ovly);
2826 if (status < 0)
2827 return status;
2828 if (!dsp_is_dma_active(codec, dma_chan)) {
2829 codec_dbg(codec, "dspxfr:DMA did not start\n");
2830 return -EIO;
2831 }
2832 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2833 if (status < 0)
2834 return status;
2835 if (remainder_words != 0) {
2836 status = chipio_write_multiple(codec,
2837 chip_addx_remainder,
2838 data_remainder,
2839 remainder_words);
2840 if (status < 0)
2841 return status;
2842 remainder_words = 0;
2843 }
2844 if (hci_write) {
2845 status = dspxfr_hci_write(codec, hci_write);
2846 if (status < 0)
2847 return status;
2848 hci_write = NULL;
2849 }
2850
2851 timeout = jiffies + msecs_to_jiffies(2000);
2852 do {
2853 dma_active = dsp_is_dma_active(codec, dma_chan);
2854 if (!dma_active)
2855 break;
2856 msleep(20);
2857 } while (time_before(jiffies, timeout));
2858 if (dma_active)
2859 break;
2860
2861 codec_dbg(codec, "+++++ DMA complete\n");
2862 dma_set_state(dma_engine, DMA_STATE_STOP);
2863 status = dma_reset(dma_engine);
2864
2865 if (status < 0)
2866 return status;
2867
2868 data += run_size_words;
2869 chip_addx += run_size_words*sizeof(u32);
2870 words_to_write -= run_size_words;
2871 }
2872
2873 if (remainder_words != 0) {
2874 status = chipio_write_multiple(codec, chip_addx_remainder,
2875 data_remainder, remainder_words);
2876 }
2877
2878 return status;
2879 }
2880
2881 /**
2882 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2883 *
2884 * @codec: the HDA codec
2885 * @fls_data: pointer to a fast load image
2886 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2887 * no relocation
2888 * @sample_rate: sampling rate of the stream used for DSP download
2889 * @channels: channels of the stream used for DSP download
2890 * @ovly: TRUE if overlay format is required
2891 *
2892 * Returns zero or a negative error code.
2893 */
2894 static int dspxfr_image(struct hda_codec *codec,
2895 const struct dsp_image_seg *fls_data,
2896 unsigned int reloc,
2897 unsigned int sample_rate,
2898 unsigned short channels,
2899 bool ovly)
2900 {
2901 struct ca0132_spec *spec = codec->spec;
2902 int status;
2903 unsigned short hda_format = 0;
2904 unsigned int response;
2905 unsigned char stream_id = 0;
2906 struct dma_engine *dma_engine;
2907 unsigned int dma_chan;
2908 unsigned int port_map_mask;
2909
2910 if (fls_data == NULL)
2911 return -EINVAL;
2912
2913 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2914 if (!dma_engine)
2915 return -ENOMEM;
2916
2917 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2918 if (!dma_engine->dmab) {
2919 kfree(dma_engine);
2920 return -ENOMEM;
2921 }
2922
2923 dma_engine->codec = codec;
2924 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2925 dma_engine->m_converter_format = hda_format;
2926 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2927 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2928
2929 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2930
2931 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2932 hda_format, &response);
2933
2934 if (status < 0) {
2935 codec_dbg(codec, "set converter format fail\n");
2936 goto exit;
2937 }
2938
2939 status = snd_hda_codec_load_dsp_prepare(codec,
2940 dma_engine->m_converter_format,
2941 dma_engine->buf_size,
2942 dma_engine->dmab);
2943 if (status < 0)
2944 goto exit;
2945 spec->dsp_stream_id = status;
2946
2947 if (ovly) {
2948 status = dspio_alloc_dma_chan(codec, &dma_chan);
2949 if (status < 0) {
2950 codec_dbg(codec, "alloc dmachan fail\n");
2951 dma_chan = INVALID_DMA_CHANNEL;
2952 goto exit;
2953 }
2954 }
2955
2956 port_map_mask = 0;
2957 status = dsp_allocate_ports_format(codec, hda_format,
2958 &port_map_mask);
2959 if (status < 0) {
2960 codec_dbg(codec, "alloc ports fail\n");
2961 goto exit;
2962 }
2963
2964 stream_id = dma_get_stream_id(dma_engine);
2965 status = codec_set_converter_stream_channel(codec,
2966 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2967 if (status < 0) {
2968 codec_dbg(codec, "set stream chan fail\n");
2969 goto exit;
2970 }
2971
2972 while ((fls_data != NULL) && !is_last(fls_data)) {
2973 if (!is_valid(fls_data)) {
2974 codec_dbg(codec, "FLS check fail\n");
2975 status = -EINVAL;
2976 goto exit;
2977 }
2978 status = dspxfr_one_seg(codec, fls_data, reloc,
2979 dma_engine, dma_chan,
2980 port_map_mask, ovly);
2981 if (status < 0)
2982 break;
2983
2984 if (is_hci_prog_list_seg(fls_data))
2985 fls_data = get_next_seg_ptr(fls_data);
2986
2987 if ((fls_data != NULL) && !is_last(fls_data))
2988 fls_data = get_next_seg_ptr(fls_data);
2989 }
2990
2991 if (port_map_mask != 0)
2992 status = dsp_free_ports(codec);
2993
2994 if (status < 0)
2995 goto exit;
2996
2997 status = codec_set_converter_stream_channel(codec,
2998 WIDGET_CHIP_CTRL, 0, 0, &response);
2999
3000 exit:
3001 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3002 dspio_free_dma_chan(codec, dma_chan);
3003
3004 if (dma_engine->dmab->area)
3005 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3006 kfree(dma_engine->dmab);
3007 kfree(dma_engine);
3008
3009 return status;
3010 }
3011
3012 /*
3013 * CA0132 DSP download stuffs.
3014 */
3015 static void dspload_post_setup(struct hda_codec *codec)
3016 {
3017 struct ca0132_spec *spec = codec->spec;
3018 codec_dbg(codec, "---- dspload_post_setup ------\n");
3019 if (!spec->use_alt_functions) {
3020 /*set DSP speaker to 2.0 configuration*/
3021 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3022 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3023
3024 /*update write pointer*/
3025 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3026 }
3027 }
3028
3029 /**
3030 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3031 *
3032 * @codec: the HDA codec
3033 * @fls: pointer to a fast load image
3034 * @ovly: TRUE if overlay format is required
3035 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3036 * no relocation
3037 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3038 * @router_chans: number of audio router channels to be allocated (0 means use
3039 * internal defaults; max is 32)
3040 *
3041 * Download DSP from a DSP Image Fast Load structure. This structure is a
3042 * linear, non-constant sized element array of structures, each of which
3043 * contain the count of the data to be loaded, the data itself, and the
3044 * corresponding starting chip address of the starting data location.
3045 * Returns zero or a negative error code.
3046 */
3047 static int dspload_image(struct hda_codec *codec,
3048 const struct dsp_image_seg *fls,
3049 bool ovly,
3050 unsigned int reloc,
3051 bool autostart,
3052 int router_chans)
3053 {
3054 int status = 0;
3055 unsigned int sample_rate;
3056 unsigned short channels;
3057
3058 codec_dbg(codec, "---- dspload_image begin ------\n");
3059 if (router_chans == 0) {
3060 if (!ovly)
3061 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3062 else
3063 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3064 }
3065
3066 sample_rate = 48000;
3067 channels = (unsigned short)router_chans;
3068
3069 while (channels > 16) {
3070 sample_rate *= 2;
3071 channels /= 2;
3072 }
3073
3074 do {
3075 codec_dbg(codec, "Ready to program DMA\n");
3076 if (!ovly)
3077 status = dsp_reset(codec);
3078
3079 if (status < 0)
3080 break;
3081
3082 codec_dbg(codec, "dsp_reset() complete\n");
3083 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3084 ovly);
3085
3086 if (status < 0)
3087 break;
3088
3089 codec_dbg(codec, "dspxfr_image() complete\n");
3090 if (autostart && !ovly) {
3091 dspload_post_setup(codec);
3092 status = dsp_set_run_state(codec);
3093 }
3094
3095 codec_dbg(codec, "LOAD FINISHED\n");
3096 } while (0);
3097
3098 return status;
3099 }
3100
3101 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3102 static bool dspload_is_loaded(struct hda_codec *codec)
3103 {
3104 unsigned int data = 0;
3105 int status = 0;
3106
3107 status = chipio_read(codec, 0x40004, &data);
3108 if ((status < 0) || (data != 1))
3109 return false;
3110
3111 return true;
3112 }
3113 #else
3114 #define dspload_is_loaded(codec) false
3115 #endif
3116
3117 static bool dspload_wait_loaded(struct hda_codec *codec)
3118 {
3119 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3120
3121 do {
3122 if (dspload_is_loaded(codec)) {
3123 codec_info(codec, "ca0132 DSP downloaded and running\n");
3124 return true;
3125 }
3126 msleep(20);
3127 } while (time_before(jiffies, timeout));
3128
3129 codec_err(codec, "ca0132 failed to download DSP\n");
3130 return false;
3131 }
3132
3133 /*
3134 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3135 * based cards, and has a second mmio region, region2, that's used for special
3136 * commands.
3137 */
3138
3139 /*
3140 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3141 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3142 * The first eight bits are just the number of the pin. So far, I've only seen
3143 * this number go to 7.
3144 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3145 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3146 * then off to send that bit.
3147 */
3148 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3149 bool enable)
3150 {
3151 struct ca0132_spec *spec = codec->spec;
3152 unsigned short gpio_data;
3153
3154 gpio_data = gpio_pin & 0xF;
3155 gpio_data |= ((enable << 8) & 0x100);
3156
3157 writew(gpio_data, spec->mem_base + 0x320);
3158 }
3159
3160 /*
3161 * Special pci region2 commands that are only used by the AE-5. They follow
3162 * a set format, and require reads at certain points to seemingly 'clear'
3163 * the response data. My first tests didn't do these reads, and would cause
3164 * the card to get locked up until the memory was read. These commands
3165 * seem to work with three distinct values that I've taken to calling group,
3166 * target-id, and value.
3167 */
3168 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3169 unsigned int target, unsigned int value)
3170 {
3171 struct ca0132_spec *spec = codec->spec;
3172 unsigned int write_val;
3173
3174 writel(0x0000007e, spec->mem_base + 0x210);
3175 readl(spec->mem_base + 0x210);
3176 writel(0x0000005a, spec->mem_base + 0x210);
3177 readl(spec->mem_base + 0x210);
3178 readl(spec->mem_base + 0x210);
3179
3180 writel(0x00800005, spec->mem_base + 0x20c);
3181 writel(group, spec->mem_base + 0x804);
3182
3183 writel(0x00800005, spec->mem_base + 0x20c);
3184 write_val = (target & 0xff);
3185 write_val |= (value << 8);
3186
3187
3188 writel(write_val, spec->mem_base + 0x204);
3189 /*
3190 * Need delay here or else it goes too fast and works inconsistently.
3191 */
3192 msleep(20);
3193
3194 readl(spec->mem_base + 0x860);
3195 readl(spec->mem_base + 0x854);
3196 readl(spec->mem_base + 0x840);
3197
3198 writel(0x00800004, spec->mem_base + 0x20c);
3199 writel(0x00000000, spec->mem_base + 0x210);
3200 readl(spec->mem_base + 0x210);
3201 readl(spec->mem_base + 0x210);
3202 }
3203
3204 /*
3205 * Setup GPIO for the other variants of Core3D.
3206 */
3207
3208 /*
3209 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3210 * the card shows as having no GPIO pins.
3211 */
3212 static void ca0132_gpio_init(struct hda_codec *codec)
3213 {
3214 struct ca0132_spec *spec = codec->spec;
3215
3216 switch (spec->quirk) {
3217 case QUIRK_SBZ:
3218 case QUIRK_AE5:
3219 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3220 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3221 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3222 break;
3223 case QUIRK_R3DI:
3224 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3225 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3226 break;
3227 }
3228
3229 }
3230
3231 /* Sets the GPIO for audio output. */
3232 static void ca0132_gpio_setup(struct hda_codec *codec)
3233 {
3234 struct ca0132_spec *spec = codec->spec;
3235
3236 switch (spec->quirk) {
3237 case QUIRK_SBZ:
3238 snd_hda_codec_write(codec, 0x01, 0,
3239 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3240 snd_hda_codec_write(codec, 0x01, 0,
3241 AC_VERB_SET_GPIO_MASK, 0x07);
3242 snd_hda_codec_write(codec, 0x01, 0,
3243 AC_VERB_SET_GPIO_DATA, 0x04);
3244 snd_hda_codec_write(codec, 0x01, 0,
3245 AC_VERB_SET_GPIO_DATA, 0x06);
3246 break;
3247 case QUIRK_R3DI:
3248 snd_hda_codec_write(codec, 0x01, 0,
3249 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3250 snd_hda_codec_write(codec, 0x01, 0,
3251 AC_VERB_SET_GPIO_MASK, 0x1F);
3252 snd_hda_codec_write(codec, 0x01, 0,
3253 AC_VERB_SET_GPIO_DATA, 0x0C);
3254 break;
3255 }
3256 }
3257
3258 /*
3259 * GPIO control functions for the Recon3D integrated.
3260 */
3261
3262 enum r3di_gpio_bit {
3263 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3264 R3DI_MIC_SELECT_BIT = 1,
3265 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3266 R3DI_OUT_SELECT_BIT = 2,
3267 /*
3268 * I dunno what this actually does, but it stays on until the dsp
3269 * is downloaded.
3270 */
3271 R3DI_GPIO_DSP_DOWNLOADING = 3,
3272 /*
3273 * Same as above, no clue what it does, but it comes on after the dsp
3274 * is downloaded.
3275 */
3276 R3DI_GPIO_DSP_DOWNLOADED = 4
3277 };
3278
3279 enum r3di_mic_select {
3280 /* Set GPIO bit 1 to 0 for rear mic */
3281 R3DI_REAR_MIC = 0,
3282 /* Set GPIO bit 1 to 1 for front microphone*/
3283 R3DI_FRONT_MIC = 1
3284 };
3285
3286 enum r3di_out_select {
3287 /* Set GPIO bit 2 to 0 for headphone */
3288 R3DI_HEADPHONE_OUT = 0,
3289 /* Set GPIO bit 2 to 1 for speaker */
3290 R3DI_LINE_OUT = 1
3291 };
3292 enum r3di_dsp_status {
3293 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3294 R3DI_DSP_DOWNLOADING = 0,
3295 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3296 R3DI_DSP_DOWNLOADED = 1
3297 };
3298
3299
3300 static void r3di_gpio_mic_set(struct hda_codec *codec,
3301 enum r3di_mic_select cur_mic)
3302 {
3303 unsigned int cur_gpio;
3304
3305 /* Get the current GPIO Data setup */
3306 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3307
3308 switch (cur_mic) {
3309 case R3DI_REAR_MIC:
3310 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3311 break;
3312 case R3DI_FRONT_MIC:
3313 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3314 break;
3315 }
3316 snd_hda_codec_write(codec, codec->core.afg, 0,
3317 AC_VERB_SET_GPIO_DATA, cur_gpio);
3318 }
3319
3320 static void r3di_gpio_out_set(struct hda_codec *codec,
3321 enum r3di_out_select cur_out)
3322 {
3323 unsigned int cur_gpio;
3324
3325 /* Get the current GPIO Data setup */
3326 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3327
3328 switch (cur_out) {
3329 case R3DI_HEADPHONE_OUT:
3330 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3331 break;
3332 case R3DI_LINE_OUT:
3333 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3334 break;
3335 }
3336 snd_hda_codec_write(codec, codec->core.afg, 0,
3337 AC_VERB_SET_GPIO_DATA, cur_gpio);
3338 }
3339
3340 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3341 enum r3di_dsp_status dsp_status)
3342 {
3343 unsigned int cur_gpio;
3344
3345 /* Get the current GPIO Data setup */
3346 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3347
3348 switch (dsp_status) {
3349 case R3DI_DSP_DOWNLOADING:
3350 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3351 snd_hda_codec_write(codec, codec->core.afg, 0,
3352 AC_VERB_SET_GPIO_DATA, cur_gpio);
3353 break;
3354 case R3DI_DSP_DOWNLOADED:
3355 /* Set DOWNLOADING bit to 0. */
3356 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3357
3358 snd_hda_codec_write(codec, codec->core.afg, 0,
3359 AC_VERB_SET_GPIO_DATA, cur_gpio);
3360
3361 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3362 break;
3363 }
3364
3365 snd_hda_codec_write(codec, codec->core.afg, 0,
3366 AC_VERB_SET_GPIO_DATA, cur_gpio);
3367 }
3368
3369 /*
3370 * PCM callbacks
3371 */
3372 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3373 struct hda_codec *codec,
3374 unsigned int stream_tag,
3375 unsigned int format,
3376 struct snd_pcm_substream *substream)
3377 {
3378 struct ca0132_spec *spec = codec->spec;
3379
3380 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3381
3382 return 0;
3383 }
3384
3385 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3386 struct hda_codec *codec,
3387 struct snd_pcm_substream *substream)
3388 {
3389 struct ca0132_spec *spec = codec->spec;
3390
3391 if (spec->dsp_state == DSP_DOWNLOADING)
3392 return 0;
3393
3394 /*If Playback effects are on, allow stream some time to flush
3395 *effects tail*/
3396 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3397 msleep(50);
3398
3399 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3400
3401 return 0;
3402 }
3403
3404 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3405 struct hda_codec *codec,
3406 struct snd_pcm_substream *substream)
3407 {
3408 struct ca0132_spec *spec = codec->spec;
3409 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3410 struct snd_pcm_runtime *runtime = substream->runtime;
3411
3412 if (spec->dsp_state != DSP_DOWNLOADED)
3413 return 0;
3414
3415 /* Add latency if playback enhancement and either effect is enabled. */
3416 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3417 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3418 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3419 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3420 }
3421
3422 /* Applying Speaker EQ adds latency as well. */
3423 if (spec->cur_out_type == SPEAKER_OUT)
3424 latency += DSP_SPEAKER_OUT_LATENCY;
3425
3426 return (latency * runtime->rate) / 1000;
3427 }
3428
3429 /*
3430 * Digital out
3431 */
3432 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3433 struct hda_codec *codec,
3434 struct snd_pcm_substream *substream)
3435 {
3436 struct ca0132_spec *spec = codec->spec;
3437 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3438 }
3439
3440 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3441 struct hda_codec *codec,
3442 unsigned int stream_tag,
3443 unsigned int format,
3444 struct snd_pcm_substream *substream)
3445 {
3446 struct ca0132_spec *spec = codec->spec;
3447 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3448 stream_tag, format, substream);
3449 }
3450
3451 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3452 struct hda_codec *codec,
3453 struct snd_pcm_substream *substream)
3454 {
3455 struct ca0132_spec *spec = codec->spec;
3456 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3457 }
3458
3459 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3460 struct hda_codec *codec,
3461 struct snd_pcm_substream *substream)
3462 {
3463 struct ca0132_spec *spec = codec->spec;
3464 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3465 }
3466
3467 /*
3468 * Analog capture
3469 */
3470 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3471 struct hda_codec *codec,
3472 unsigned int stream_tag,
3473 unsigned int format,
3474 struct snd_pcm_substream *substream)
3475 {
3476 snd_hda_codec_setup_stream(codec, hinfo->nid,
3477 stream_tag, 0, format);
3478
3479 return 0;
3480 }
3481
3482 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3483 struct hda_codec *codec,
3484 struct snd_pcm_substream *substream)
3485 {
3486 struct ca0132_spec *spec = codec->spec;
3487
3488 if (spec->dsp_state == DSP_DOWNLOADING)
3489 return 0;
3490
3491 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3492 return 0;
3493 }
3494
3495 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3496 struct hda_codec *codec,
3497 struct snd_pcm_substream *substream)
3498 {
3499 struct ca0132_spec *spec = codec->spec;
3500 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3501 struct snd_pcm_runtime *runtime = substream->runtime;
3502
3503 if (spec->dsp_state != DSP_DOWNLOADED)
3504 return 0;
3505
3506 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3507 latency += DSP_CRYSTAL_VOICE_LATENCY;
3508
3509 return (latency * runtime->rate) / 1000;
3510 }
3511
3512 /*
3513 * Controls stuffs.
3514 */
3515
3516 /*
3517 * Mixer controls helpers.
3518 */
3519 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3520 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3521 .name = xname, \
3522 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3523 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3524 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3525 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3526 .info = ca0132_volume_info, \
3527 .get = ca0132_volume_get, \
3528 .put = ca0132_volume_put, \
3529 .tlv = { .c = ca0132_volume_tlv }, \
3530 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3531
3532 /*
3533 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3534 * volume put, which is used for setting the DSP volume. This was done because
3535 * the ca0132 functions were taking too much time and causing lag.
3536 */
3537 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3538 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3539 .name = xname, \
3540 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3541 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3542 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3543 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3544 .info = snd_hda_mixer_amp_volume_info, \
3545 .get = snd_hda_mixer_amp_volume_get, \
3546 .put = ca0132_alt_volume_put, \
3547 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3548 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3549
3550 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3551 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3552 .name = xname, \
3553 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3554 .info = snd_hda_mixer_amp_switch_info, \
3555 .get = ca0132_switch_get, \
3556 .put = ca0132_switch_put, \
3557 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3558
3559 /* stereo */
3560 #define CA0132_CODEC_VOL(xname, nid, dir) \
3561 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3562 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3563 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3564 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3565 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3566
3567 /* lookup tables */
3568 /*
3569 * Lookup table with decibel values for the DSP. When volume is changed in
3570 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3571 * these values have decimal points, probably because the Windows driver
3572 * actually uses floating point. We can't here, so I made a lookup table of
3573 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3574 * DAC's, and 9 is the maximum.
3575 */
3576 static const unsigned int float_vol_db_lookup[] = {
3577 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3578 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3579 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3580 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3581 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3582 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3583 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3584 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3585 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3586 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3587 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3588 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3589 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3590 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3591 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3592 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3593 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3594 };
3595
3596 /*
3597 * This table counts from float 0 to 1 in increments of .01, which is
3598 * useful for a few different sliders.
3599 */
3600 static const unsigned int float_zero_to_one_lookup[] = {
3601 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3602 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3603 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3604 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3605 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3606 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3607 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3608 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3609 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3610 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3611 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3612 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3613 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3614 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3615 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3616 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3617 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3618 };
3619
3620 /*
3621 * This table counts from float 10 to 1000, which is the range of the x-bass
3622 * crossover slider in Windows.
3623 */
3624 static const unsigned int float_xbass_xover_lookup[] = {
3625 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3626 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3627 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3628 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3629 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3630 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3631 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3632 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3633 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3634 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3635 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3636 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3637 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3638 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3639 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3640 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3641 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3642 };
3643
3644 /* The following are for tuning of products */
3645 #ifdef ENABLE_TUNING_CONTROLS
3646
3647 static unsigned int voice_focus_vals_lookup[] = {
3648 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3649 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3650 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3651 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3652 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3653 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3654 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3655 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3656 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3657 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3658 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3659 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3660 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3661 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3662 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3663 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3664 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3665 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3666 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3667 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3668 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3669 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3670 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3671 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3672 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3673 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3674 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3675 };
3676
3677 static unsigned int mic_svm_vals_lookup[] = {
3678 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3679 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3680 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3681 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3682 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3683 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3684 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3685 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3686 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3687 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3688 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3689 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3690 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3691 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3692 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3693 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3694 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3695 };
3696
3697 static unsigned int equalizer_vals_lookup[] = {
3698 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3699 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3700 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3701 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3702 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3703 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3704 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3705 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3706 0x41C00000
3707 };
3708
3709 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3710 unsigned int *lookup, int idx)
3711 {
3712 int i = 0;
3713
3714 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3715 if (nid == ca0132_tuning_ctls[i].nid)
3716 break;
3717
3718 snd_hda_power_up(codec);
3719 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3720 ca0132_tuning_ctls[i].req,
3721 &(lookup[idx]), sizeof(unsigned int));
3722 snd_hda_power_down(codec);
3723
3724 return 1;
3725 }
3726
3727 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3728 struct snd_ctl_elem_value *ucontrol)
3729 {
3730 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3731 struct ca0132_spec *spec = codec->spec;
3732 hda_nid_t nid = get_amp_nid(kcontrol);
3733 long *valp = ucontrol->value.integer.value;
3734 int idx = nid - TUNING_CTL_START_NID;
3735
3736 *valp = spec->cur_ctl_vals[idx];
3737 return 0;
3738 }
3739
3740 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3741 struct snd_ctl_elem_info *uinfo)
3742 {
3743 int chs = get_amp_channels(kcontrol);
3744 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3745 uinfo->count = chs == 3 ? 2 : 1;
3746 uinfo->value.integer.min = 20;
3747 uinfo->value.integer.max = 180;
3748 uinfo->value.integer.step = 1;
3749
3750 return 0;
3751 }
3752
3753 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3754 struct snd_ctl_elem_value *ucontrol)
3755 {
3756 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3757 struct ca0132_spec *spec = codec->spec;
3758 hda_nid_t nid = get_amp_nid(kcontrol);
3759 long *valp = ucontrol->value.integer.value;
3760 int idx;
3761
3762 idx = nid - TUNING_CTL_START_NID;
3763 /* any change? */
3764 if (spec->cur_ctl_vals[idx] == *valp)
3765 return 0;
3766
3767 spec->cur_ctl_vals[idx] = *valp;
3768
3769 idx = *valp - 20;
3770 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3771
3772 return 1;
3773 }
3774
3775 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3776 struct snd_ctl_elem_info *uinfo)
3777 {
3778 int chs = get_amp_channels(kcontrol);
3779 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3780 uinfo->count = chs == 3 ? 2 : 1;
3781 uinfo->value.integer.min = 0;
3782 uinfo->value.integer.max = 100;
3783 uinfo->value.integer.step = 1;
3784
3785 return 0;
3786 }
3787
3788 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3789 struct snd_ctl_elem_value *ucontrol)
3790 {
3791 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3792 struct ca0132_spec *spec = codec->spec;
3793 hda_nid_t nid = get_amp_nid(kcontrol);
3794 long *valp = ucontrol->value.integer.value;
3795 int idx;
3796
3797 idx = nid - TUNING_CTL_START_NID;
3798 /* any change? */
3799 if (spec->cur_ctl_vals[idx] == *valp)
3800 return 0;
3801
3802 spec->cur_ctl_vals[idx] = *valp;
3803
3804 idx = *valp;
3805 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3806
3807 return 0;
3808 }
3809
3810 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3811 struct snd_ctl_elem_info *uinfo)
3812 {
3813 int chs = get_amp_channels(kcontrol);
3814 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3815 uinfo->count = chs == 3 ? 2 : 1;
3816 uinfo->value.integer.min = 0;
3817 uinfo->value.integer.max = 48;
3818 uinfo->value.integer.step = 1;
3819
3820 return 0;
3821 }
3822
3823 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3824 struct snd_ctl_elem_value *ucontrol)
3825 {
3826 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3827 struct ca0132_spec *spec = codec->spec;
3828 hda_nid_t nid = get_amp_nid(kcontrol);
3829 long *valp = ucontrol->value.integer.value;
3830 int idx;
3831
3832 idx = nid - TUNING_CTL_START_NID;
3833 /* any change? */
3834 if (spec->cur_ctl_vals[idx] == *valp)
3835 return 0;
3836
3837 spec->cur_ctl_vals[idx] = *valp;
3838
3839 idx = *valp;
3840 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3841
3842 return 1;
3843 }
3844
3845 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3846 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3847
3848 static int add_tuning_control(struct hda_codec *codec,
3849 hda_nid_t pnid, hda_nid_t nid,
3850 const char *name, int dir)
3851 {
3852 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3853 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3854 struct snd_kcontrol_new knew =
3855 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3856
3857 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3858 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3859 knew.tlv.c = 0;
3860 knew.tlv.p = 0;
3861 switch (pnid) {
3862 case VOICE_FOCUS:
3863 knew.info = voice_focus_ctl_info;
3864 knew.get = tuning_ctl_get;
3865 knew.put = voice_focus_ctl_put;
3866 knew.tlv.p = voice_focus_db_scale;
3867 break;
3868 case MIC_SVM:
3869 knew.info = mic_svm_ctl_info;
3870 knew.get = tuning_ctl_get;
3871 knew.put = mic_svm_ctl_put;
3872 break;
3873 case EQUALIZER:
3874 knew.info = equalizer_ctl_info;
3875 knew.get = tuning_ctl_get;
3876 knew.put = equalizer_ctl_put;
3877 knew.tlv.p = eq_db_scale;
3878 break;
3879 default:
3880 return 0;
3881 }
3882 knew.private_value =
3883 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3884 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3885 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3886 }
3887
3888 static int add_tuning_ctls(struct hda_codec *codec)
3889 {
3890 int i;
3891 int err;
3892
3893 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3894 err = add_tuning_control(codec,
3895 ca0132_tuning_ctls[i].parent_nid,
3896 ca0132_tuning_ctls[i].nid,
3897 ca0132_tuning_ctls[i].name,
3898 ca0132_tuning_ctls[i].direct);
3899 if (err < 0)
3900 return err;
3901 }
3902
3903 return 0;
3904 }
3905
3906 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3907 {
3908 struct ca0132_spec *spec = codec->spec;
3909 int i;
3910
3911 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3912 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3913 /* SVM level defaults to 0.74. */
3914 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3915
3916 /* EQ defaults to 0dB. */
3917 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3918 spec->cur_ctl_vals[i] = 24;
3919 }
3920 #endif /*ENABLE_TUNING_CONTROLS*/
3921
3922 /*
3923 * Select the active output.
3924 * If autodetect is enabled, output will be selected based on jack detection.
3925 * If jack inserted, headphone will be selected, else built-in speakers
3926 * If autodetect is disabled, output will be selected based on selection.
3927 */
3928 static int ca0132_select_out(struct hda_codec *codec)
3929 {
3930 struct ca0132_spec *spec = codec->spec;
3931 unsigned int pin_ctl;
3932 int jack_present;
3933 int auto_jack;
3934 unsigned int tmp;
3935 int err;
3936
3937 codec_dbg(codec, "ca0132_select_out\n");
3938
3939 snd_hda_power_up_pm(codec);
3940
3941 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3942
3943 if (auto_jack)
3944 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3945 else
3946 jack_present =
3947 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3948
3949 if (jack_present)
3950 spec->cur_out_type = HEADPHONE_OUT;
3951 else
3952 spec->cur_out_type = SPEAKER_OUT;
3953
3954 if (spec->cur_out_type == SPEAKER_OUT) {
3955 codec_dbg(codec, "ca0132_select_out speaker\n");
3956 /*speaker out config*/
3957 tmp = FLOAT_ONE;
3958 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3959 if (err < 0)
3960 goto exit;
3961 /*enable speaker EQ*/
3962 tmp = FLOAT_ONE;
3963 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3964 if (err < 0)
3965 goto exit;
3966
3967 /* Setup EAPD */
3968 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3969 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3970 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3971 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3972 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3973 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3974 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3975 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3976
3977 /* disable headphone node */
3978 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3979 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3980 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3981 pin_ctl & ~PIN_HP);
3982 /* enable speaker node */
3983 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3984 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3985 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3986 pin_ctl | PIN_OUT);
3987 } else {
3988 codec_dbg(codec, "ca0132_select_out hp\n");
3989 /*headphone out config*/
3990 tmp = FLOAT_ZERO;
3991 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3992 if (err < 0)
3993 goto exit;
3994 /*disable speaker EQ*/
3995 tmp = FLOAT_ZERO;
3996 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3997 if (err < 0)
3998 goto exit;
3999
4000 /* Setup EAPD */
4001 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4002 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4003 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4004 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4005 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4006 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4007 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4008 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4009
4010 /* disable speaker*/
4011 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4012 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4013 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4014 pin_ctl & ~PIN_HP);
4015 /* enable headphone*/
4016 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4017 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4018 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4019 pin_ctl | PIN_HP);
4020 }
4021
4022 exit:
4023 snd_hda_power_down_pm(codec);
4024
4025 return err < 0 ? err : 0;
4026 }
4027
4028 /*
4029 * These are the commands needed to setup output on each of the different card
4030 * types.
4031 */
4032 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec)
4033 {
4034 struct ca0132_spec *spec = codec->spec;
4035
4036 switch (spec->cur_out_type) {
4037 case SPEAKER_OUT:
4038 switch (spec->quirk) {
4039 case QUIRK_SBZ:
4040 ca0113_mmio_gpio_set(codec, 7, false);
4041 ca0113_mmio_gpio_set(codec, 4, true);
4042 ca0113_mmio_gpio_set(codec, 1, true);
4043 chipio_set_control_param(codec, 0x0D, 0x18);
4044 break;
4045 case QUIRK_R3DI:
4046 chipio_set_control_param(codec, 0x0D, 0x24);
4047 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4048 break;
4049 case QUIRK_R3D:
4050 chipio_set_control_param(codec, 0x0D, 0x24);
4051 ca0113_mmio_gpio_set(codec, 1, true);
4052 break;
4053 }
4054 break;
4055 case HEADPHONE_OUT:
4056 switch (spec->quirk) {
4057 case QUIRK_SBZ:
4058 ca0113_mmio_gpio_set(codec, 7, true);
4059 ca0113_mmio_gpio_set(codec, 4, true);
4060 ca0113_mmio_gpio_set(codec, 1, false);
4061 chipio_set_control_param(codec, 0x0D, 0x12);
4062 break;
4063 case QUIRK_R3DI:
4064 chipio_set_control_param(codec, 0x0D, 0x21);
4065 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4066 break;
4067 case QUIRK_R3D:
4068 chipio_set_control_param(codec, 0x0D, 0x21);
4069 ca0113_mmio_gpio_set(codec, 0x1, false);
4070 break;
4071 }
4072 break;
4073 case SURROUND_OUT:
4074 switch (spec->quirk) {
4075 case QUIRK_SBZ:
4076 ca0113_mmio_gpio_set(codec, 7, false);
4077 ca0113_mmio_gpio_set(codec, 4, true);
4078 ca0113_mmio_gpio_set(codec, 1, true);
4079 chipio_set_control_param(codec, 0x0D, 0x18);
4080 break;
4081 case QUIRK_R3DI:
4082 chipio_set_control_param(codec, 0x0D, 0x24);
4083 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4084 break;
4085 case QUIRK_R3D:
4086 ca0113_mmio_gpio_set(codec, 1, true);
4087 chipio_set_control_param(codec, 0x0D, 0x24);
4088 break;
4089 }
4090 break;
4091 }
4092 }
4093
4094 /*
4095 * This function behaves similarly to the ca0132_select_out funciton above,
4096 * except with a few differences. It adds the ability to select the current
4097 * output with an enumerated control "output source" if the auto detect
4098 * mute switch is set to off. If the auto detect mute switch is enabled, it
4099 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4100 * It also adds the ability to auto-detect the front headphone port. The only
4101 * way to select surround is to disable auto detect, and set Surround with the
4102 * enumerated control.
4103 */
4104 static int ca0132_alt_select_out(struct hda_codec *codec)
4105 {
4106 struct ca0132_spec *spec = codec->spec;
4107 unsigned int pin_ctl;
4108 int jack_present;
4109 int auto_jack;
4110 unsigned int i;
4111 unsigned int tmp;
4112 int err;
4113 /* Default Headphone is rear headphone */
4114 hda_nid_t headphone_nid = spec->out_pins[1];
4115
4116 codec_dbg(codec, "%s\n", __func__);
4117
4118 snd_hda_power_up_pm(codec);
4119
4120 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4121
4122 /*
4123 * If headphone rear or front is plugged in, set to headphone.
4124 * If neither is plugged in, set to rear line out. Only if
4125 * hp/speaker auto detect is enabled.
4126 */
4127 if (auto_jack) {
4128 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4129 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4130
4131 if (jack_present)
4132 spec->cur_out_type = HEADPHONE_OUT;
4133 else
4134 spec->cur_out_type = SPEAKER_OUT;
4135 } else
4136 spec->cur_out_type = spec->out_enum_val;
4137
4138 /* Begin DSP output switch */
4139 tmp = FLOAT_ONE;
4140 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
4141 if (err < 0)
4142 goto exit;
4143
4144 ca0132_alt_select_out_quirk_handler(codec);
4145
4146 switch (spec->cur_out_type) {
4147 case SPEAKER_OUT:
4148 codec_dbg(codec, "%s speaker\n", __func__);
4149
4150 /* disable headphone node */
4151 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4152 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4153 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4154 pin_ctl & ~PIN_HP);
4155 /* enable line-out node */
4156 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4157 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4158 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4159 pin_ctl | PIN_OUT);
4160 /* Enable EAPD */
4161 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4162 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4163
4164 /* If PlayEnhancement is enabled, set different source */
4165 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4166 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4167 else
4168 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4169 break;
4170 case HEADPHONE_OUT:
4171 codec_dbg(codec, "%s hp\n", __func__);
4172
4173 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4174 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4175
4176 /* disable speaker*/
4177 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4178 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4179 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4180 pin_ctl & ~PIN_HP);
4181
4182 /* enable headphone, either front or rear */
4183
4184 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4185 headphone_nid = spec->out_pins[2];
4186 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4187 headphone_nid = spec->out_pins[1];
4188
4189 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4190 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4191 snd_hda_set_pin_ctl(codec, headphone_nid,
4192 pin_ctl | PIN_HP);
4193
4194 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4195 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4196 else
4197 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4198 break;
4199 case SURROUND_OUT:
4200 codec_dbg(codec, "%s surround\n", __func__);
4201
4202 /* enable line out node */
4203 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4204 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4205 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4206 pin_ctl | PIN_OUT);
4207 /* Disable headphone out */
4208 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4209 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4210 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4211 pin_ctl & ~PIN_HP);
4212 /* Enable EAPD on line out */
4213 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4214 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4215 /* enable center/lfe out node */
4216 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4217 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4218 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4219 pin_ctl | PIN_OUT);
4220 /* Now set rear surround node as out. */
4221 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4222 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4223 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4224 pin_ctl | PIN_OUT);
4225
4226 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4227 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4228 else
4229 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4230 break;
4231 }
4232
4233 /* run through the output dsp commands for line-out */
4234 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4235 err = dspio_set_uint_param(codec,
4236 alt_out_presets[spec->cur_out_type].mids[i],
4237 alt_out_presets[spec->cur_out_type].reqs[i],
4238 alt_out_presets[spec->cur_out_type].vals[i]);
4239
4240 if (err < 0)
4241 goto exit;
4242 }
4243
4244 exit:
4245 snd_hda_power_down_pm(codec);
4246
4247 return err < 0 ? err : 0;
4248 }
4249
4250 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4251 {
4252 struct ca0132_spec *spec = container_of(
4253 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4254 struct hda_jack_tbl *jack;
4255
4256 if (spec->use_alt_functions)
4257 ca0132_alt_select_out(spec->codec);
4258 else
4259 ca0132_select_out(spec->codec);
4260
4261 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4262 if (jack) {
4263 jack->block_report = 0;
4264 snd_hda_jack_report_sync(spec->codec);
4265 }
4266 }
4267
4268 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4269 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4270 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4271 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4272 static int stop_mic1(struct hda_codec *codec);
4273 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4274 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4275
4276 /*
4277 * Select the active VIP source
4278 */
4279 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4280 {
4281 struct ca0132_spec *spec = codec->spec;
4282 unsigned int tmp;
4283
4284 if (spec->dsp_state != DSP_DOWNLOADED)
4285 return 0;
4286
4287 /* if CrystalVoice if off, vipsource should be 0 */
4288 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4289 (val == 0)) {
4290 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4291 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4292 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4293 if (spec->cur_mic_type == DIGITAL_MIC)
4294 tmp = FLOAT_TWO;
4295 else
4296 tmp = FLOAT_ONE;
4297 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4298 tmp = FLOAT_ZERO;
4299 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4300 } else {
4301 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4302 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4303 if (spec->cur_mic_type == DIGITAL_MIC)
4304 tmp = FLOAT_TWO;
4305 else
4306 tmp = FLOAT_ONE;
4307 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4308 tmp = FLOAT_ONE;
4309 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4310 msleep(20);
4311 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4312 }
4313
4314 return 1;
4315 }
4316
4317 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4318 {
4319 struct ca0132_spec *spec = codec->spec;
4320 unsigned int tmp;
4321
4322 if (spec->dsp_state != DSP_DOWNLOADED)
4323 return 0;
4324
4325 codec_dbg(codec, "%s\n", __func__);
4326
4327 chipio_set_stream_control(codec, 0x03, 0);
4328 chipio_set_stream_control(codec, 0x04, 0);
4329
4330 /* if CrystalVoice is off, vipsource should be 0 */
4331 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4332 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4333 codec_dbg(codec, "%s: off.", __func__);
4334 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4335
4336 tmp = FLOAT_ZERO;
4337 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4338
4339 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4340 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4341 if (spec->quirk == QUIRK_R3DI)
4342 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4343
4344
4345 if (spec->in_enum_val == REAR_LINE_IN)
4346 tmp = FLOAT_ZERO;
4347 else {
4348 if (spec->quirk == QUIRK_SBZ)
4349 tmp = FLOAT_THREE;
4350 else
4351 tmp = FLOAT_ONE;
4352 }
4353
4354 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4355
4356 } else {
4357 codec_dbg(codec, "%s: on.", __func__);
4358 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4359 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4360 if (spec->quirk == QUIRK_R3DI)
4361 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4362
4363 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4364 tmp = FLOAT_TWO;
4365 else
4366 tmp = FLOAT_ONE;
4367 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4368
4369 tmp = FLOAT_ONE;
4370 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4371
4372 msleep(20);
4373 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4374 }
4375
4376 chipio_set_stream_control(codec, 0x03, 1);
4377 chipio_set_stream_control(codec, 0x04, 1);
4378
4379 return 1;
4380 }
4381
4382 /*
4383 * Select the active microphone.
4384 * If autodetect is enabled, mic will be selected based on jack detection.
4385 * If jack inserted, ext.mic will be selected, else built-in mic
4386 * If autodetect is disabled, mic will be selected based on selection.
4387 */
4388 static int ca0132_select_mic(struct hda_codec *codec)
4389 {
4390 struct ca0132_spec *spec = codec->spec;
4391 int jack_present;
4392 int auto_jack;
4393
4394 codec_dbg(codec, "ca0132_select_mic\n");
4395
4396 snd_hda_power_up_pm(codec);
4397
4398 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4399
4400 if (auto_jack)
4401 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4402 else
4403 jack_present =
4404 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4405
4406 if (jack_present)
4407 spec->cur_mic_type = LINE_MIC_IN;
4408 else
4409 spec->cur_mic_type = DIGITAL_MIC;
4410
4411 if (spec->cur_mic_type == DIGITAL_MIC) {
4412 /* enable digital Mic */
4413 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4414 ca0132_set_dmic(codec, 1);
4415 ca0132_mic_boost_set(codec, 0);
4416 /* set voice focus */
4417 ca0132_effects_set(codec, VOICE_FOCUS,
4418 spec->effects_switch
4419 [VOICE_FOCUS - EFFECT_START_NID]);
4420 } else {
4421 /* disable digital Mic */
4422 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4423 ca0132_set_dmic(codec, 0);
4424 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4425 /* disable voice focus */
4426 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4427 }
4428
4429 snd_hda_power_down_pm(codec);
4430
4431 return 0;
4432 }
4433
4434 /*
4435 * Select the active input.
4436 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4437 * The front mic has no jack-detection, so the only way to switch to it
4438 * is to do it manually in alsamixer.
4439 */
4440 static int ca0132_alt_select_in(struct hda_codec *codec)
4441 {
4442 struct ca0132_spec *spec = codec->spec;
4443 unsigned int tmp;
4444
4445 codec_dbg(codec, "%s\n", __func__);
4446
4447 snd_hda_power_up_pm(codec);
4448
4449 chipio_set_stream_control(codec, 0x03, 0);
4450 chipio_set_stream_control(codec, 0x04, 0);
4451
4452 spec->cur_mic_type = spec->in_enum_val;
4453
4454 switch (spec->cur_mic_type) {
4455 case REAR_MIC:
4456 switch (spec->quirk) {
4457 case QUIRK_SBZ:
4458 case QUIRK_R3D:
4459 ca0113_mmio_gpio_set(codec, 0, false);
4460 tmp = FLOAT_THREE;
4461 break;
4462 case QUIRK_R3DI:
4463 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4464 tmp = FLOAT_ONE;
4465 break;
4466 default:
4467 tmp = FLOAT_ONE;
4468 break;
4469 }
4470
4471 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4472 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4473 if (spec->quirk == QUIRK_R3DI)
4474 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4475
4476 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4477
4478 chipio_set_stream_control(codec, 0x03, 1);
4479 chipio_set_stream_control(codec, 0x04, 1);
4480
4481 if (spec->quirk == QUIRK_SBZ) {
4482 chipio_write(codec, 0x18B098, 0x0000000C);
4483 chipio_write(codec, 0x18B09C, 0x0000000C);
4484 }
4485 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4486 break;
4487 case REAR_LINE_IN:
4488 ca0132_mic_boost_set(codec, 0);
4489 switch (spec->quirk) {
4490 case QUIRK_SBZ:
4491 case QUIRK_R3D:
4492 ca0113_mmio_gpio_set(codec, 0, false);
4493 break;
4494 case QUIRK_R3DI:
4495 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4496 break;
4497 }
4498
4499 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4500 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4501 if (spec->quirk == QUIRK_R3DI)
4502 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4503
4504 tmp = FLOAT_ZERO;
4505 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4506
4507 if (spec->quirk == QUIRK_SBZ) {
4508 chipio_write(codec, 0x18B098, 0x00000000);
4509 chipio_write(codec, 0x18B09C, 0x00000000);
4510 }
4511
4512 chipio_set_stream_control(codec, 0x03, 1);
4513 chipio_set_stream_control(codec, 0x04, 1);
4514 break;
4515 case FRONT_MIC:
4516 switch (spec->quirk) {
4517 case QUIRK_SBZ:
4518 case QUIRK_R3D:
4519 ca0113_mmio_gpio_set(codec, 0, true);
4520 ca0113_mmio_gpio_set(codec, 5, false);
4521 tmp = FLOAT_THREE;
4522 break;
4523 case QUIRK_R3DI:
4524 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4525 tmp = FLOAT_ONE;
4526 break;
4527 default:
4528 tmp = FLOAT_ONE;
4529 break;
4530 }
4531
4532 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4533 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4534 if (spec->quirk == QUIRK_R3DI)
4535 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4536
4537 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4538
4539 chipio_set_stream_control(codec, 0x03, 1);
4540 chipio_set_stream_control(codec, 0x04, 1);
4541
4542 if (spec->quirk == QUIRK_SBZ) {
4543 chipio_write(codec, 0x18B098, 0x0000000C);
4544 chipio_write(codec, 0x18B09C, 0x000000CC);
4545 }
4546 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4547 break;
4548 }
4549 ca0132_cvoice_switch_set(codec);
4550
4551 snd_hda_power_down_pm(codec);
4552 return 0;
4553
4554 }
4555
4556 /*
4557 * Check if VNODE settings take effect immediately.
4558 */
4559 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4560 hda_nid_t vnid,
4561 hda_nid_t *shared_nid)
4562 {
4563 struct ca0132_spec *spec = codec->spec;
4564 hda_nid_t nid;
4565
4566 switch (vnid) {
4567 case VNID_SPK:
4568 nid = spec->shared_out_nid;
4569 break;
4570 case VNID_MIC:
4571 nid = spec->shared_mic_nid;
4572 break;
4573 default:
4574 return false;
4575 }
4576
4577 if (shared_nid)
4578 *shared_nid = nid;
4579
4580 return true;
4581 }
4582
4583 /*
4584 * The following functions are control change helpers.
4585 * They return 0 if no changed. Return 1 if changed.
4586 */
4587 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4588 {
4589 struct ca0132_spec *spec = codec->spec;
4590 unsigned int tmp;
4591
4592 /* based on CrystalVoice state to enable VoiceFX. */
4593 if (enable) {
4594 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4595 FLOAT_ONE : FLOAT_ZERO;
4596 } else {
4597 tmp = FLOAT_ZERO;
4598 }
4599
4600 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4601 ca0132_voicefx.reqs[0], tmp);
4602
4603 return 1;
4604 }
4605
4606 /*
4607 * Set the effects parameters
4608 */
4609 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4610 {
4611 struct ca0132_spec *spec = codec->spec;
4612 unsigned int on, tmp;
4613 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4614 int err = 0;
4615 int idx = nid - EFFECT_START_NID;
4616
4617 if ((idx < 0) || (idx >= num_fx))
4618 return 0; /* no changed */
4619
4620 /* for out effect, qualify with PE */
4621 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4622 /* if PE if off, turn off out effects. */
4623 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4624 val = 0;
4625 }
4626
4627 /* for in effect, qualify with CrystalVoice */
4628 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4629 /* if CrystalVoice if off, turn off in effects. */
4630 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4631 val = 0;
4632
4633 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4634 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4635 val = 0;
4636
4637 /* If Voice Focus on SBZ, set to two channel. */
4638 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4639 && (spec->cur_mic_type != REAR_LINE_IN)) {
4640 if (spec->effects_switch[CRYSTAL_VOICE -
4641 EFFECT_START_NID]) {
4642
4643 if (spec->effects_switch[VOICE_FOCUS -
4644 EFFECT_START_NID]) {
4645 tmp = FLOAT_TWO;
4646 val = 1;
4647 } else
4648 tmp = FLOAT_ONE;
4649
4650 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4651 }
4652 }
4653 /*
4654 * For SBZ noise reduction, there's an extra command
4655 * to module ID 0x47. No clue why.
4656 */
4657 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4658 && (spec->cur_mic_type != REAR_LINE_IN)) {
4659 if (spec->effects_switch[CRYSTAL_VOICE -
4660 EFFECT_START_NID]) {
4661 if (spec->effects_switch[NOISE_REDUCTION -
4662 EFFECT_START_NID])
4663 tmp = FLOAT_ONE;
4664 else
4665 tmp = FLOAT_ZERO;
4666 } else
4667 tmp = FLOAT_ZERO;
4668
4669 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4670 }
4671
4672 /* If rear line in disable effects. */
4673 if (spec->use_alt_functions &&
4674 spec->in_enum_val == REAR_LINE_IN)
4675 val = 0;
4676 }
4677
4678 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4679 nid, val);
4680
4681 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4682 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4683 ca0132_effects[idx].reqs[0], on);
4684
4685 if (err < 0)
4686 return 0; /* no changed */
4687
4688 return 1;
4689 }
4690
4691 /*
4692 * Turn on/off Playback Enhancements
4693 */
4694 static int ca0132_pe_switch_set(struct hda_codec *codec)
4695 {
4696 struct ca0132_spec *spec = codec->spec;
4697 hda_nid_t nid;
4698 int i, ret = 0;
4699
4700 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4701 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4702
4703 if (spec->use_alt_functions)
4704 ca0132_alt_select_out(codec);
4705
4706 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4707 nid = OUT_EFFECT_START_NID;
4708 /* PE affects all out effects */
4709 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4710 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4711
4712 return ret;
4713 }
4714
4715 /* Check if Mic1 is streaming, if so, stop streaming */
4716 static int stop_mic1(struct hda_codec *codec)
4717 {
4718 struct ca0132_spec *spec = codec->spec;
4719 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4720 AC_VERB_GET_CONV, 0);
4721 if (oldval != 0)
4722 snd_hda_codec_write(codec, spec->adcs[0], 0,
4723 AC_VERB_SET_CHANNEL_STREAMID,
4724 0);
4725 return oldval;
4726 }
4727
4728 /* Resume Mic1 streaming if it was stopped. */
4729 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4730 {
4731 struct ca0132_spec *spec = codec->spec;
4732 /* Restore the previous stream and channel */
4733 if (oldval != 0)
4734 snd_hda_codec_write(codec, spec->adcs[0], 0,
4735 AC_VERB_SET_CHANNEL_STREAMID,
4736 oldval);
4737 }
4738
4739 /*
4740 * Turn on/off CrystalVoice
4741 */
4742 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4743 {
4744 struct ca0132_spec *spec = codec->spec;
4745 hda_nid_t nid;
4746 int i, ret = 0;
4747 unsigned int oldval;
4748
4749 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4750 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4751
4752 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4753 nid = IN_EFFECT_START_NID;
4754 /* CrystalVoice affects all in effects */
4755 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4756 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4757
4758 /* including VoiceFX */
4759 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4760
4761 /* set correct vipsource */
4762 oldval = stop_mic1(codec);
4763 if (spec->use_alt_functions)
4764 ret |= ca0132_alt_set_vipsource(codec, 1);
4765 else
4766 ret |= ca0132_set_vipsource(codec, 1);
4767 resume_mic1(codec, oldval);
4768 return ret;
4769 }
4770
4771 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4772 {
4773 struct ca0132_spec *spec = codec->spec;
4774 int ret = 0;
4775
4776 if (val) /* on */
4777 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4778 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4779 else /* off */
4780 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4781 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4782
4783 return ret;
4784 }
4785
4786 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4787 {
4788 struct ca0132_spec *spec = codec->spec;
4789 int ret = 0;
4790
4791 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4792 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4793 return ret;
4794 }
4795
4796 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4797 struct snd_ctl_elem_value *ucontrol)
4798 {
4799 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4800 hda_nid_t nid = get_amp_nid(kcontrol);
4801 hda_nid_t shared_nid = 0;
4802 bool effective;
4803 int ret = 0;
4804 struct ca0132_spec *spec = codec->spec;
4805 int auto_jack;
4806
4807 if (nid == VNID_HP_SEL) {
4808 auto_jack =
4809 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4810 if (!auto_jack) {
4811 if (spec->use_alt_functions)
4812 ca0132_alt_select_out(codec);
4813 else
4814 ca0132_select_out(codec);
4815 }
4816 return 1;
4817 }
4818
4819 if (nid == VNID_AMIC1_SEL) {
4820 auto_jack =
4821 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4822 if (!auto_jack)
4823 ca0132_select_mic(codec);
4824 return 1;
4825 }
4826
4827 if (nid == VNID_HP_ASEL) {
4828 if (spec->use_alt_functions)
4829 ca0132_alt_select_out(codec);
4830 else
4831 ca0132_select_out(codec);
4832 return 1;
4833 }
4834
4835 if (nid == VNID_AMIC1_ASEL) {
4836 ca0132_select_mic(codec);
4837 return 1;
4838 }
4839
4840 /* if effective conditions, then update hw immediately. */
4841 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4842 if (effective) {
4843 int dir = get_amp_direction(kcontrol);
4844 int ch = get_amp_channels(kcontrol);
4845 unsigned long pval;
4846
4847 mutex_lock(&codec->control_mutex);
4848 pval = kcontrol->private_value;
4849 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4850 0, dir);
4851 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4852 kcontrol->private_value = pval;
4853 mutex_unlock(&codec->control_mutex);
4854 }
4855
4856 return ret;
4857 }
4858 /* End of control change helpers. */
4859 /*
4860 * Below I've added controls to mess with the effect levels, I've only enabled
4861 * them on the Sound Blaster Z, but they would probably also work on the
4862 * Chromebook. I figured they were probably tuned specifically for it, and left
4863 * out for a reason.
4864 */
4865
4866 /* Sets DSP effect level from the sliders above the controls */
4867 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4868 const unsigned int *lookup, int idx)
4869 {
4870 int i = 0;
4871 unsigned int y;
4872 /*
4873 * For X_BASS, req 2 is actually crossover freq instead of
4874 * effect level
4875 */
4876 if (nid == X_BASS)
4877 y = 2;
4878 else
4879 y = 1;
4880
4881 snd_hda_power_up(codec);
4882 if (nid == XBASS_XOVER) {
4883 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4884 if (ca0132_effects[i].nid == X_BASS)
4885 break;
4886
4887 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4888 ca0132_effects[i].reqs[1],
4889 &(lookup[idx - 1]), sizeof(unsigned int));
4890 } else {
4891 /* Find the actual effect structure */
4892 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4893 if (nid == ca0132_effects[i].nid)
4894 break;
4895
4896 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4897 ca0132_effects[i].reqs[y],
4898 &(lookup[idx]), sizeof(unsigned int));
4899 }
4900
4901 snd_hda_power_down(codec);
4902
4903 return 0;
4904 }
4905
4906 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4907 struct snd_ctl_elem_value *ucontrol)
4908 {
4909 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4910 struct ca0132_spec *spec = codec->spec;
4911 long *valp = ucontrol->value.integer.value;
4912
4913 *valp = spec->xbass_xover_freq;
4914 return 0;
4915 }
4916
4917 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4918 struct snd_ctl_elem_value *ucontrol)
4919 {
4920 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4921 struct ca0132_spec *spec = codec->spec;
4922 hda_nid_t nid = get_amp_nid(kcontrol);
4923 long *valp = ucontrol->value.integer.value;
4924 int idx = nid - OUT_EFFECT_START_NID;
4925
4926 *valp = spec->fx_ctl_val[idx];
4927 return 0;
4928 }
4929
4930 /*
4931 * The X-bass crossover starts at 10hz, so the min is 1. The
4932 * frequency is set in multiples of 10.
4933 */
4934 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4935 struct snd_ctl_elem_info *uinfo)
4936 {
4937 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4938 uinfo->count = 1;
4939 uinfo->value.integer.min = 1;
4940 uinfo->value.integer.max = 100;
4941 uinfo->value.integer.step = 1;
4942
4943 return 0;
4944 }
4945
4946 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4947 struct snd_ctl_elem_info *uinfo)
4948 {
4949 int chs = get_amp_channels(kcontrol);
4950
4951 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4952 uinfo->count = chs == 3 ? 2 : 1;
4953 uinfo->value.integer.min = 0;
4954 uinfo->value.integer.max = 100;
4955 uinfo->value.integer.step = 1;
4956
4957 return 0;
4958 }
4959
4960 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4961 struct snd_ctl_elem_value *ucontrol)
4962 {
4963 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4964 struct ca0132_spec *spec = codec->spec;
4965 hda_nid_t nid = get_amp_nid(kcontrol);
4966 long *valp = ucontrol->value.integer.value;
4967 int idx;
4968
4969 /* any change? */
4970 if (spec->xbass_xover_freq == *valp)
4971 return 0;
4972
4973 spec->xbass_xover_freq = *valp;
4974
4975 idx = *valp;
4976 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4977
4978 return 0;
4979 }
4980
4981 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4982 struct snd_ctl_elem_value *ucontrol)
4983 {
4984 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4985 struct ca0132_spec *spec = codec->spec;
4986 hda_nid_t nid = get_amp_nid(kcontrol);
4987 long *valp = ucontrol->value.integer.value;
4988 int idx;
4989
4990 idx = nid - EFFECT_START_NID;
4991 /* any change? */
4992 if (spec->fx_ctl_val[idx] == *valp)
4993 return 0;
4994
4995 spec->fx_ctl_val[idx] = *valp;
4996
4997 idx = *valp;
4998 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4999
5000 return 0;
5001 }
5002
5003
5004 /*
5005 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5006 * only has off or full 30 dB, and didn't like making a volume slider that has
5007 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5008 */
5009 #define MIC_BOOST_NUM_OF_STEPS 4
5010 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5011
5012 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5013 struct snd_ctl_elem_info *uinfo)
5014 {
5015 char *sfx = "dB";
5016 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5017
5018 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5019 uinfo->count = 1;
5020 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5021 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5022 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5023 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5024 strcpy(uinfo->value.enumerated.name, namestr);
5025 return 0;
5026 }
5027
5028 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5029 struct snd_ctl_elem_value *ucontrol)
5030 {
5031 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5032 struct ca0132_spec *spec = codec->spec;
5033
5034 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5035 return 0;
5036 }
5037
5038 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5039 struct snd_ctl_elem_value *ucontrol)
5040 {
5041 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5042 struct ca0132_spec *spec = codec->spec;
5043 int sel = ucontrol->value.enumerated.item[0];
5044 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5045
5046 if (sel >= items)
5047 return 0;
5048
5049 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5050 sel);
5051
5052 spec->mic_boost_enum_val = sel;
5053
5054 if (spec->in_enum_val != REAR_LINE_IN)
5055 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5056
5057 return 1;
5058 }
5059
5060
5061 /*
5062 * Input Select Control for alternative ca0132 codecs. This exists because
5063 * front microphone has no auto-detect, and we need a way to set the rear
5064 * as line-in
5065 */
5066 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5067 struct snd_ctl_elem_info *uinfo)
5068 {
5069 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5070 uinfo->count = 1;
5071 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5072 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5073 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5074 strcpy(uinfo->value.enumerated.name,
5075 in_src_str[uinfo->value.enumerated.item]);
5076 return 0;
5077 }
5078
5079 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5080 struct snd_ctl_elem_value *ucontrol)
5081 {
5082 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5083 struct ca0132_spec *spec = codec->spec;
5084
5085 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5086 return 0;
5087 }
5088
5089 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5090 struct snd_ctl_elem_value *ucontrol)
5091 {
5092 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5093 struct ca0132_spec *spec = codec->spec;
5094 int sel = ucontrol->value.enumerated.item[0];
5095 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5096
5097 if (sel >= items)
5098 return 0;
5099
5100 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5101 sel, in_src_str[sel]);
5102
5103 spec->in_enum_val = sel;
5104
5105 ca0132_alt_select_in(codec);
5106
5107 return 1;
5108 }
5109
5110 /* Sound Blaster Z Output Select Control */
5111 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5112 struct snd_ctl_elem_info *uinfo)
5113 {
5114 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5115 uinfo->count = 1;
5116 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5117 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5118 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5119 strcpy(uinfo->value.enumerated.name,
5120 alt_out_presets[uinfo->value.enumerated.item].name);
5121 return 0;
5122 }
5123
5124 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5125 struct snd_ctl_elem_value *ucontrol)
5126 {
5127 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5128 struct ca0132_spec *spec = codec->spec;
5129
5130 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5131 return 0;
5132 }
5133
5134 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5135 struct snd_ctl_elem_value *ucontrol)
5136 {
5137 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5138 struct ca0132_spec *spec = codec->spec;
5139 int sel = ucontrol->value.enumerated.item[0];
5140 unsigned int items = NUM_OF_OUTPUTS;
5141 unsigned int auto_jack;
5142
5143 if (sel >= items)
5144 return 0;
5145
5146 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5147 sel, alt_out_presets[sel].name);
5148
5149 spec->out_enum_val = sel;
5150
5151 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5152
5153 if (!auto_jack)
5154 ca0132_alt_select_out(codec);
5155
5156 return 1;
5157 }
5158
5159 /*
5160 * Smart Volume output setting control. Three different settings, Normal,
5161 * which takes the value from the smart volume slider. The two others, loud
5162 * and night, disregard the slider value and have uneditable values.
5163 */
5164 #define NUM_OF_SVM_SETTINGS 3
5165 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5166
5167 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5168 struct snd_ctl_elem_info *uinfo)
5169 {
5170 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5171 uinfo->count = 1;
5172 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5173 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5174 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5175 strcpy(uinfo->value.enumerated.name,
5176 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5177 return 0;
5178 }
5179
5180 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5181 struct snd_ctl_elem_value *ucontrol)
5182 {
5183 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5184 struct ca0132_spec *spec = codec->spec;
5185
5186 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5187 return 0;
5188 }
5189
5190 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5191 struct snd_ctl_elem_value *ucontrol)
5192 {
5193 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5194 struct ca0132_spec *spec = codec->spec;
5195 int sel = ucontrol->value.enumerated.item[0];
5196 unsigned int items = NUM_OF_SVM_SETTINGS;
5197 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5198 unsigned int tmp;
5199
5200 if (sel >= items)
5201 return 0;
5202
5203 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5204 sel, out_svm_set_enum_str[sel]);
5205
5206 spec->smart_volume_setting = sel;
5207
5208 switch (sel) {
5209 case 0:
5210 tmp = FLOAT_ZERO;
5211 break;
5212 case 1:
5213 tmp = FLOAT_ONE;
5214 break;
5215 case 2:
5216 tmp = FLOAT_TWO;
5217 break;
5218 default:
5219 tmp = FLOAT_ZERO;
5220 break;
5221 }
5222 /* Req 2 is the Smart Volume Setting req. */
5223 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5224 ca0132_effects[idx].reqs[2], tmp);
5225 return 1;
5226 }
5227
5228 /* Sound Blaster Z EQ preset controls */
5229 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5230 struct snd_ctl_elem_info *uinfo)
5231 {
5232 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5233
5234 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5235 uinfo->count = 1;
5236 uinfo->value.enumerated.items = items;
5237 if (uinfo->value.enumerated.item >= items)
5238 uinfo->value.enumerated.item = items - 1;
5239 strcpy(uinfo->value.enumerated.name,
5240 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5241 return 0;
5242 }
5243
5244 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5245 struct snd_ctl_elem_value *ucontrol)
5246 {
5247 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5248 struct ca0132_spec *spec = codec->spec;
5249
5250 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5251 return 0;
5252 }
5253
5254 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5255 struct snd_ctl_elem_value *ucontrol)
5256 {
5257 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5258 struct ca0132_spec *spec = codec->spec;
5259 int i, err = 0;
5260 int sel = ucontrol->value.enumerated.item[0];
5261 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5262
5263 if (sel >= items)
5264 return 0;
5265
5266 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5267 ca0132_alt_eq_presets[sel].name);
5268 /*
5269 * Idx 0 is default.
5270 * Default needs to qualify with CrystalVoice state.
5271 */
5272 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5273 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5274 ca0132_alt_eq_enum.reqs[i],
5275 ca0132_alt_eq_presets[sel].vals[i]);
5276 if (err < 0)
5277 break;
5278 }
5279
5280 if (err >= 0)
5281 spec->eq_preset_val = sel;
5282
5283 return 1;
5284 }
5285
5286 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5287 struct snd_ctl_elem_info *uinfo)
5288 {
5289 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5290
5291 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5292 uinfo->count = 1;
5293 uinfo->value.enumerated.items = items;
5294 if (uinfo->value.enumerated.item >= items)
5295 uinfo->value.enumerated.item = items - 1;
5296 strcpy(uinfo->value.enumerated.name,
5297 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5298 return 0;
5299 }
5300
5301 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5302 struct snd_ctl_elem_value *ucontrol)
5303 {
5304 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5305 struct ca0132_spec *spec = codec->spec;
5306
5307 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5308 return 0;
5309 }
5310
5311 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5312 struct snd_ctl_elem_value *ucontrol)
5313 {
5314 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5315 struct ca0132_spec *spec = codec->spec;
5316 int i, err = 0;
5317 int sel = ucontrol->value.enumerated.item[0];
5318
5319 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5320 return 0;
5321
5322 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5323 sel, ca0132_voicefx_presets[sel].name);
5324
5325 /*
5326 * Idx 0 is default.
5327 * Default needs to qualify with CrystalVoice state.
5328 */
5329 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5330 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5331 ca0132_voicefx.reqs[i],
5332 ca0132_voicefx_presets[sel].vals[i]);
5333 if (err < 0)
5334 break;
5335 }
5336
5337 if (err >= 0) {
5338 spec->voicefx_val = sel;
5339 /* enable voice fx */
5340 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5341 }
5342
5343 return 1;
5344 }
5345
5346 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5347 struct snd_ctl_elem_value *ucontrol)
5348 {
5349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5350 struct ca0132_spec *spec = codec->spec;
5351 hda_nid_t nid = get_amp_nid(kcontrol);
5352 int ch = get_amp_channels(kcontrol);
5353 long *valp = ucontrol->value.integer.value;
5354
5355 /* vnode */
5356 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5357 if (ch & 1) {
5358 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5359 valp++;
5360 }
5361 if (ch & 2) {
5362 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5363 valp++;
5364 }
5365 return 0;
5366 }
5367
5368 /* effects, include PE and CrystalVoice */
5369 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5370 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5371 return 0;
5372 }
5373
5374 /* mic boost */
5375 if (nid == spec->input_pins[0]) {
5376 *valp = spec->cur_mic_boost;
5377 return 0;
5378 }
5379
5380 return 0;
5381 }
5382
5383 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5384 struct snd_ctl_elem_value *ucontrol)
5385 {
5386 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5387 struct ca0132_spec *spec = codec->spec;
5388 hda_nid_t nid = get_amp_nid(kcontrol);
5389 int ch = get_amp_channels(kcontrol);
5390 long *valp = ucontrol->value.integer.value;
5391 int changed = 1;
5392
5393 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5394 nid, *valp);
5395
5396 snd_hda_power_up(codec);
5397 /* vnode */
5398 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5399 if (ch & 1) {
5400 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5401 valp++;
5402 }
5403 if (ch & 2) {
5404 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5405 valp++;
5406 }
5407 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5408 goto exit;
5409 }
5410
5411 /* PE */
5412 if (nid == PLAY_ENHANCEMENT) {
5413 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5414 changed = ca0132_pe_switch_set(codec);
5415 goto exit;
5416 }
5417
5418 /* CrystalVoice */
5419 if (nid == CRYSTAL_VOICE) {
5420 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5421 changed = ca0132_cvoice_switch_set(codec);
5422 goto exit;
5423 }
5424
5425 /* out and in effects */
5426 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5427 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5428 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5429 changed = ca0132_effects_set(codec, nid, *valp);
5430 goto exit;
5431 }
5432
5433 /* mic boost */
5434 if (nid == spec->input_pins[0]) {
5435 spec->cur_mic_boost = *valp;
5436 if (spec->use_alt_functions) {
5437 if (spec->in_enum_val != REAR_LINE_IN)
5438 changed = ca0132_mic_boost_set(codec, *valp);
5439 } else {
5440 /* Mic boost does not apply to Digital Mic */
5441 if (spec->cur_mic_type != DIGITAL_MIC)
5442 changed = ca0132_mic_boost_set(codec, *valp);
5443 }
5444
5445 goto exit;
5446 }
5447
5448 exit:
5449 snd_hda_power_down(codec);
5450 return changed;
5451 }
5452
5453 /*
5454 * Volume related
5455 */
5456 /*
5457 * Sets the internal DSP decibel level to match the DAC for output, and the
5458 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5459 * all alternative codecs set DSP playback volume.
5460 */
5461 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5462 {
5463 struct ca0132_spec *spec = codec->spec;
5464 unsigned int dsp_dir;
5465 unsigned int lookup_val;
5466
5467 if (nid == VNID_SPK)
5468 dsp_dir = DSP_VOL_OUT;
5469 else
5470 dsp_dir = DSP_VOL_IN;
5471
5472 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5473
5474 dspio_set_uint_param(codec,
5475 ca0132_alt_vol_ctls[dsp_dir].mid,
5476 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5477 float_vol_db_lookup[lookup_val]);
5478
5479 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5480
5481 dspio_set_uint_param(codec,
5482 ca0132_alt_vol_ctls[dsp_dir].mid,
5483 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5484 float_vol_db_lookup[lookup_val]);
5485
5486 dspio_set_uint_param(codec,
5487 ca0132_alt_vol_ctls[dsp_dir].mid,
5488 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5489 }
5490
5491 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5492 struct snd_ctl_elem_info *uinfo)
5493 {
5494 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5495 struct ca0132_spec *spec = codec->spec;
5496 hda_nid_t nid = get_amp_nid(kcontrol);
5497 int ch = get_amp_channels(kcontrol);
5498 int dir = get_amp_direction(kcontrol);
5499 unsigned long pval;
5500 int err;
5501
5502 switch (nid) {
5503 case VNID_SPK:
5504 /* follow shared_out info */
5505 nid = spec->shared_out_nid;
5506 mutex_lock(&codec->control_mutex);
5507 pval = kcontrol->private_value;
5508 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5509 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5510 kcontrol->private_value = pval;
5511 mutex_unlock(&codec->control_mutex);
5512 break;
5513 case VNID_MIC:
5514 /* follow shared_mic info */
5515 nid = spec->shared_mic_nid;
5516 mutex_lock(&codec->control_mutex);
5517 pval = kcontrol->private_value;
5518 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5519 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5520 kcontrol->private_value = pval;
5521 mutex_unlock(&codec->control_mutex);
5522 break;
5523 default:
5524 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5525 }
5526 return err;
5527 }
5528
5529 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5530 struct snd_ctl_elem_value *ucontrol)
5531 {
5532 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5533 struct ca0132_spec *spec = codec->spec;
5534 hda_nid_t nid = get_amp_nid(kcontrol);
5535 int ch = get_amp_channels(kcontrol);
5536 long *valp = ucontrol->value.integer.value;
5537
5538 /* store the left and right volume */
5539 if (ch & 1) {
5540 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5541 valp++;
5542 }
5543 if (ch & 2) {
5544 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5545 valp++;
5546 }
5547 return 0;
5548 }
5549
5550 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5551 struct snd_ctl_elem_value *ucontrol)
5552 {
5553 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5554 struct ca0132_spec *spec = codec->spec;
5555 hda_nid_t nid = get_amp_nid(kcontrol);
5556 int ch = get_amp_channels(kcontrol);
5557 long *valp = ucontrol->value.integer.value;
5558 hda_nid_t shared_nid = 0;
5559 bool effective;
5560 int changed = 1;
5561
5562 /* store the left and right volume */
5563 if (ch & 1) {
5564 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5565 valp++;
5566 }
5567 if (ch & 2) {
5568 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5569 valp++;
5570 }
5571
5572 /* if effective conditions, then update hw immediately. */
5573 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5574 if (effective) {
5575 int dir = get_amp_direction(kcontrol);
5576 unsigned long pval;
5577
5578 snd_hda_power_up(codec);
5579 mutex_lock(&codec->control_mutex);
5580 pval = kcontrol->private_value;
5581 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5582 0, dir);
5583 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5584 kcontrol->private_value = pval;
5585 mutex_unlock(&codec->control_mutex);
5586 snd_hda_power_down(codec);
5587 }
5588
5589 return changed;
5590 }
5591
5592 /*
5593 * This function is the same as the one above, because using an if statement
5594 * inside of the above volume control for the DSP volume would cause too much
5595 * lag. This is a lot more smooth.
5596 */
5597 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5598 struct snd_ctl_elem_value *ucontrol)
5599 {
5600 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5601 struct ca0132_spec *spec = codec->spec;
5602 hda_nid_t nid = get_amp_nid(kcontrol);
5603 int ch = get_amp_channels(kcontrol);
5604 long *valp = ucontrol->value.integer.value;
5605 hda_nid_t vnid = 0;
5606 int changed = 1;
5607
5608 switch (nid) {
5609 case 0x02:
5610 vnid = VNID_SPK;
5611 break;
5612 case 0x07:
5613 vnid = VNID_MIC;
5614 break;
5615 }
5616
5617 /* store the left and right volume */
5618 if (ch & 1) {
5619 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5620 valp++;
5621 }
5622 if (ch & 2) {
5623 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5624 valp++;
5625 }
5626
5627 snd_hda_power_up(codec);
5628 ca0132_alt_dsp_volume_put(codec, vnid);
5629 mutex_lock(&codec->control_mutex);
5630 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5631 mutex_unlock(&codec->control_mutex);
5632 snd_hda_power_down(codec);
5633
5634 return changed;
5635 }
5636
5637 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5638 unsigned int size, unsigned int __user *tlv)
5639 {
5640 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5641 struct ca0132_spec *spec = codec->spec;
5642 hda_nid_t nid = get_amp_nid(kcontrol);
5643 int ch = get_amp_channels(kcontrol);
5644 int dir = get_amp_direction(kcontrol);
5645 unsigned long pval;
5646 int err;
5647
5648 switch (nid) {
5649 case VNID_SPK:
5650 /* follow shared_out tlv */
5651 nid = spec->shared_out_nid;
5652 mutex_lock(&codec->control_mutex);
5653 pval = kcontrol->private_value;
5654 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5655 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5656 kcontrol->private_value = pval;
5657 mutex_unlock(&codec->control_mutex);
5658 break;
5659 case VNID_MIC:
5660 /* follow shared_mic tlv */
5661 nid = spec->shared_mic_nid;
5662 mutex_lock(&codec->control_mutex);
5663 pval = kcontrol->private_value;
5664 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5665 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5666 kcontrol->private_value = pval;
5667 mutex_unlock(&codec->control_mutex);
5668 break;
5669 default:
5670 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5671 }
5672 return err;
5673 }
5674
5675 /* Add volume slider control for effect level */
5676 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5677 const char *pfx, int dir)
5678 {
5679 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5680 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5681 struct snd_kcontrol_new knew =
5682 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5683
5684 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5685
5686 knew.tlv.c = NULL;
5687
5688 switch (nid) {
5689 case XBASS_XOVER:
5690 knew.info = ca0132_alt_xbass_xover_slider_info;
5691 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5692 knew.put = ca0132_alt_xbass_xover_slider_put;
5693 break;
5694 default:
5695 knew.info = ca0132_alt_effect_slider_info;
5696 knew.get = ca0132_alt_slider_ctl_get;
5697 knew.put = ca0132_alt_effect_slider_put;
5698 knew.private_value =
5699 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5700 break;
5701 }
5702
5703 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5704 }
5705
5706 /*
5707 * Added FX: prefix for the alternative codecs, because otherwise the surround
5708 * effect would conflict with the Surround sound volume control. Also seems more
5709 * clear as to what the switches do. Left alone for others.
5710 */
5711 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5712 const char *pfx, int dir)
5713 {
5714 struct ca0132_spec *spec = codec->spec;
5715 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5716 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5717 struct snd_kcontrol_new knew =
5718 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5719 /* If using alt_controls, add FX: prefix. But, don't add FX:
5720 * prefix to OutFX or InFX enable controls.
5721 */
5722 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5723 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5724 else
5725 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5726
5727 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5728 }
5729
5730 static int add_voicefx(struct hda_codec *codec)
5731 {
5732 struct snd_kcontrol_new knew =
5733 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5734 VOICEFX, 1, 0, HDA_INPUT);
5735 knew.info = ca0132_voicefx_info;
5736 knew.get = ca0132_voicefx_get;
5737 knew.put = ca0132_voicefx_put;
5738 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5739 }
5740
5741 /* Create the EQ Preset control */
5742 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5743 {
5744 struct snd_kcontrol_new knew =
5745 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5746 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5747 knew.info = ca0132_alt_eq_preset_info;
5748 knew.get = ca0132_alt_eq_preset_get;
5749 knew.put = ca0132_alt_eq_preset_put;
5750 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5751 snd_ctl_new1(&knew, codec));
5752 }
5753
5754 /*
5755 * Add enumerated control for the three different settings of the smart volume
5756 * output effect. Normal just uses the slider value, and loud and night are
5757 * their own things that ignore that value.
5758 */
5759 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5760 {
5761 struct snd_kcontrol_new knew =
5762 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5763 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5764 knew.info = ca0132_alt_svm_setting_info;
5765 knew.get = ca0132_alt_svm_setting_get;
5766 knew.put = ca0132_alt_svm_setting_put;
5767 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5768 snd_ctl_new1(&knew, codec));
5769
5770 }
5771
5772 /*
5773 * Create an Output Select enumerated control for codecs with surround
5774 * out capabilities.
5775 */
5776 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5777 {
5778 struct snd_kcontrol_new knew =
5779 HDA_CODEC_MUTE_MONO("Output Select",
5780 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5781 knew.info = ca0132_alt_output_select_get_info;
5782 knew.get = ca0132_alt_output_select_get;
5783 knew.put = ca0132_alt_output_select_put;
5784 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5785 snd_ctl_new1(&knew, codec));
5786 }
5787
5788 /*
5789 * Create an Input Source enumerated control for the alternate ca0132 codecs
5790 * because the front microphone has no auto-detect, and Line-in has to be set
5791 * somehow.
5792 */
5793 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5794 {
5795 struct snd_kcontrol_new knew =
5796 HDA_CODEC_MUTE_MONO("Input Source",
5797 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5798 knew.info = ca0132_alt_input_source_info;
5799 knew.get = ca0132_alt_input_source_get;
5800 knew.put = ca0132_alt_input_source_put;
5801 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5802 snd_ctl_new1(&knew, codec));
5803 }
5804
5805 /*
5806 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5807 * more control than the original mic boost, which is either full 30dB or off.
5808 */
5809 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5810 {
5811 struct snd_kcontrol_new knew =
5812 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5813 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5814 knew.info = ca0132_alt_mic_boost_info;
5815 knew.get = ca0132_alt_mic_boost_get;
5816 knew.put = ca0132_alt_mic_boost_put;
5817 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5818 snd_ctl_new1(&knew, codec));
5819
5820 }
5821
5822 /*
5823 * Need to create slave controls for the alternate codecs that have surround
5824 * capabilities.
5825 */
5826 static const char * const ca0132_alt_slave_pfxs[] = {
5827 "Front", "Surround", "Center", "LFE", NULL,
5828 };
5829
5830 /*
5831 * Also need special channel map, because the default one is incorrect.
5832 * I think this has to do with the pin for rear surround being 0x11,
5833 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5834 */
5835 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5836 { .channels = 2,
5837 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5838 { .channels = 4,
5839 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5840 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5841 { .channels = 6,
5842 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5843 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5844 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5845 { }
5846 };
5847
5848 /* Add the correct chmap for streams with 6 channels. */
5849 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5850 {
5851 int err = 0;
5852 struct hda_pcm *pcm;
5853
5854 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5855 struct hda_pcm_stream *hinfo =
5856 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5857 struct snd_pcm_chmap *chmap;
5858 const struct snd_pcm_chmap_elem *elem;
5859
5860 elem = ca0132_alt_chmaps;
5861 if (hinfo->channels_max == 6) {
5862 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5863 SNDRV_PCM_STREAM_PLAYBACK,
5864 elem, hinfo->channels_max, 0, &chmap);
5865 if (err < 0)
5866 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5867 }
5868 }
5869 }
5870
5871 /*
5872 * When changing Node IDs for Mixer Controls below, make sure to update
5873 * Node IDs in ca0132_config() as well.
5874 */
5875 static const struct snd_kcontrol_new ca0132_mixer[] = {
5876 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5877 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5878 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5879 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5880 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5881 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5882 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5883 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5884 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5885 0x12, 1, HDA_INPUT),
5886 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5887 VNID_HP_SEL, 1, HDA_OUTPUT),
5888 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5889 VNID_AMIC1_SEL, 1, HDA_INPUT),
5890 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5891 VNID_HP_ASEL, 1, HDA_OUTPUT),
5892 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5893 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5894 { } /* end */
5895 };
5896
5897 /*
5898 * Desktop specific control mixer. Removes auto-detect for mic, and adds
5899 * surround controls. Also sets both the Front Playback and Capture Volume
5900 * controls to alt so they set the DSP's decibel level.
5901 */
5902 static const struct snd_kcontrol_new desktop_mixer[] = {
5903 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5904 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5905 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5906 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5907 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5908 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5909 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5910 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5911 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5912 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5913 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5914 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5915 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5916 VNID_HP_ASEL, 1, HDA_OUTPUT),
5917 { } /* end */
5918 };
5919
5920 /*
5921 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5922 * because it doesn't set decibel levels for the DSP for capture.
5923 */
5924 static const struct snd_kcontrol_new r3di_mixer[] = {
5925 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5926 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5927 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5928 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5929 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5930 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5931 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5932 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5933 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5934 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5935 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5936 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5937 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5938 VNID_HP_ASEL, 1, HDA_OUTPUT),
5939 { } /* end */
5940 };
5941
5942 static int ca0132_build_controls(struct hda_codec *codec)
5943 {
5944 struct ca0132_spec *spec = codec->spec;
5945 int i, num_fx, num_sliders;
5946 int err = 0;
5947
5948 /* Add Mixer controls */
5949 for (i = 0; i < spec->num_mixers; i++) {
5950 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5951 if (err < 0)
5952 return err;
5953 }
5954 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5955 if (spec->use_alt_functions) {
5956 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5957 spec->tlv);
5958 snd_hda_add_vmaster(codec, "Master Playback Volume",
5959 spec->tlv, ca0132_alt_slave_pfxs,
5960 "Playback Volume");
5961 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5962 NULL, ca0132_alt_slave_pfxs,
5963 "Playback Switch",
5964 true, &spec->vmaster_mute.sw_kctl);
5965
5966 }
5967
5968 /* Add in and out effects controls.
5969 * VoiceFX, PE and CrystalVoice are added separately.
5970 */
5971 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5972 for (i = 0; i < num_fx; i++) {
5973 /* SBZ and R3D break if Echo Cancellation is used. */
5974 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D) {
5975 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5976 OUT_EFFECTS_COUNT))
5977 continue;
5978 }
5979
5980 err = add_fx_switch(codec, ca0132_effects[i].nid,
5981 ca0132_effects[i].name,
5982 ca0132_effects[i].direct);
5983 if (err < 0)
5984 return err;
5985 }
5986 /*
5987 * If codec has use_alt_controls set to true, add effect level sliders,
5988 * EQ presets, and Smart Volume presets. Also, change names to add FX
5989 * prefix, and change PlayEnhancement and CrystalVoice to match.
5990 */
5991 if (spec->use_alt_controls) {
5992 ca0132_alt_add_svm_enum(codec);
5993 add_ca0132_alt_eq_presets(codec);
5994 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5995 "Enable OutFX", 0);
5996 if (err < 0)
5997 return err;
5998
5999 err = add_fx_switch(codec, CRYSTAL_VOICE,
6000 "Enable InFX", 1);
6001 if (err < 0)
6002 return err;
6003
6004 num_sliders = OUT_EFFECTS_COUNT - 1;
6005 for (i = 0; i < num_sliders; i++) {
6006 err = ca0132_alt_add_effect_slider(codec,
6007 ca0132_effects[i].nid,
6008 ca0132_effects[i].name,
6009 ca0132_effects[i].direct);
6010 if (err < 0)
6011 return err;
6012 }
6013
6014 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6015 "X-Bass Crossover", EFX_DIR_OUT);
6016
6017 if (err < 0)
6018 return err;
6019 } else {
6020 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6021 "PlayEnhancement", 0);
6022 if (err < 0)
6023 return err;
6024
6025 err = add_fx_switch(codec, CRYSTAL_VOICE,
6026 "CrystalVoice", 1);
6027 if (err < 0)
6028 return err;
6029 }
6030 add_voicefx(codec);
6031
6032 /*
6033 * If the codec uses alt_functions, you need the enumerated controls
6034 * to select the new outputs and inputs, plus add the new mic boost
6035 * setting control.
6036 */
6037 if (spec->use_alt_functions) {
6038 ca0132_alt_add_output_enum(codec);
6039 ca0132_alt_add_input_enum(codec);
6040 ca0132_alt_add_mic_boost_enum(codec);
6041 }
6042 #ifdef ENABLE_TUNING_CONTROLS
6043 add_tuning_ctls(codec);
6044 #endif
6045
6046 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
6047 if (err < 0)
6048 return err;
6049
6050 if (spec->dig_out) {
6051 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
6052 spec->dig_out);
6053 if (err < 0)
6054 return err;
6055 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
6056 if (err < 0)
6057 return err;
6058 /* spec->multiout.share_spdif = 1; */
6059 }
6060
6061 if (spec->dig_in) {
6062 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
6063 if (err < 0)
6064 return err;
6065 }
6066
6067 if (spec->use_alt_functions)
6068 ca0132_alt_add_chmap_ctls(codec);
6069
6070 return 0;
6071 }
6072
6073 /*
6074 * PCM
6075 */
6076 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
6077 .substreams = 1,
6078 .channels_min = 2,
6079 .channels_max = 6,
6080 .ops = {
6081 .prepare = ca0132_playback_pcm_prepare,
6082 .cleanup = ca0132_playback_pcm_cleanup,
6083 .get_delay = ca0132_playback_pcm_delay,
6084 },
6085 };
6086
6087 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
6088 .substreams = 1,
6089 .channels_min = 2,
6090 .channels_max = 2,
6091 .ops = {
6092 .prepare = ca0132_capture_pcm_prepare,
6093 .cleanup = ca0132_capture_pcm_cleanup,
6094 .get_delay = ca0132_capture_pcm_delay,
6095 },
6096 };
6097
6098 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
6099 .substreams = 1,
6100 .channels_min = 2,
6101 .channels_max = 2,
6102 .ops = {
6103 .open = ca0132_dig_playback_pcm_open,
6104 .close = ca0132_dig_playback_pcm_close,
6105 .prepare = ca0132_dig_playback_pcm_prepare,
6106 .cleanup = ca0132_dig_playback_pcm_cleanup
6107 },
6108 };
6109
6110 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
6111 .substreams = 1,
6112 .channels_min = 2,
6113 .channels_max = 2,
6114 };
6115
6116 static int ca0132_build_pcms(struct hda_codec *codec)
6117 {
6118 struct ca0132_spec *spec = codec->spec;
6119 struct hda_pcm *info;
6120
6121 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6122 if (!info)
6123 return -ENOMEM;
6124 if (spec->use_alt_functions) {
6125 info->own_chmap = true;
6126 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6127 = ca0132_alt_chmaps;
6128 }
6129 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6130 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6131 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6132 spec->multiout.max_channels;
6133 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6134 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6135 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6136
6137 /* With the DSP enabled, desktops don't use this ADC. */
6138 if (!spec->use_alt_functions) {
6139 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6140 if (!info)
6141 return -ENOMEM;
6142 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6143 ca0132_pcm_analog_capture;
6144 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6145 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6146 }
6147
6148 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6149 if (!info)
6150 return -ENOMEM;
6151 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6152 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6153 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6154
6155 if (!spec->dig_out && !spec->dig_in)
6156 return 0;
6157
6158 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6159 if (!info)
6160 return -ENOMEM;
6161 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6162 if (spec->dig_out) {
6163 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6164 ca0132_pcm_digital_playback;
6165 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6166 }
6167 if (spec->dig_in) {
6168 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6169 ca0132_pcm_digital_capture;
6170 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6171 }
6172
6173 return 0;
6174 }
6175
6176 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6177 {
6178 if (pin) {
6179 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6180 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6181 snd_hda_codec_write(codec, pin, 0,
6182 AC_VERB_SET_AMP_GAIN_MUTE,
6183 AMP_OUT_UNMUTE);
6184 }
6185 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6186 snd_hda_codec_write(codec, dac, 0,
6187 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6188 }
6189
6190 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6191 {
6192 if (pin) {
6193 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6194 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6195 snd_hda_codec_write(codec, pin, 0,
6196 AC_VERB_SET_AMP_GAIN_MUTE,
6197 AMP_IN_UNMUTE(0));
6198 }
6199 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6200 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6201 AMP_IN_UNMUTE(0));
6202
6203 /* init to 0 dB and unmute. */
6204 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6205 HDA_AMP_VOLMASK, 0x5a);
6206 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6207 HDA_AMP_MUTE, 0);
6208 }
6209 }
6210
6211 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6212 {
6213 unsigned int caps;
6214
6215 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6216 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6217 snd_hda_override_amp_caps(codec, nid, dir, caps);
6218 }
6219
6220 /*
6221 * Switch between Digital built-in mic and analog mic.
6222 */
6223 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6224 {
6225 struct ca0132_spec *spec = codec->spec;
6226 unsigned int tmp;
6227 u8 val;
6228 unsigned int oldval;
6229
6230 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6231
6232 oldval = stop_mic1(codec);
6233 ca0132_set_vipsource(codec, 0);
6234 if (enable) {
6235 /* set DMic input as 2-ch */
6236 tmp = FLOAT_TWO;
6237 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6238
6239 val = spec->dmic_ctl;
6240 val |= 0x80;
6241 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6242 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6243
6244 if (!(spec->dmic_ctl & 0x20))
6245 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6246 } else {
6247 /* set AMic input as mono */
6248 tmp = FLOAT_ONE;
6249 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6250
6251 val = spec->dmic_ctl;
6252 /* clear bit7 and bit5 to disable dmic */
6253 val &= 0x5f;
6254 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6255 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6256
6257 if (!(spec->dmic_ctl & 0x20))
6258 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6259 }
6260 ca0132_set_vipsource(codec, 1);
6261 resume_mic1(codec, oldval);
6262 }
6263
6264 /*
6265 * Initialization for Digital Mic.
6266 */
6267 static void ca0132_init_dmic(struct hda_codec *codec)
6268 {
6269 struct ca0132_spec *spec = codec->spec;
6270 u8 val;
6271
6272 /* Setup Digital Mic here, but don't enable.
6273 * Enable based on jack detect.
6274 */
6275
6276 /* MCLK uses MPIO1, set to enable.
6277 * Bit 2-0: MPIO select
6278 * Bit 3: set to disable
6279 * Bit 7-4: reserved
6280 */
6281 val = 0x01;
6282 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6283 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6284
6285 /* Data1 uses MPIO3. Data2 not use
6286 * Bit 2-0: Data1 MPIO select
6287 * Bit 3: set disable Data1
6288 * Bit 6-4: Data2 MPIO select
6289 * Bit 7: set disable Data2
6290 */
6291 val = 0x83;
6292 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6293 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6294
6295 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6296 * Bit 3-0: Channel mask
6297 * Bit 4: set for 48KHz, clear for 32KHz
6298 * Bit 5: mode
6299 * Bit 6: set to select Data2, clear for Data1
6300 * Bit 7: set to enable DMic, clear for AMic
6301 */
6302 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6303 val = 0x33;
6304 else
6305 val = 0x23;
6306 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6307 spec->dmic_ctl = val;
6308 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6309 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6310 }
6311
6312 /*
6313 * Initialization for Analog Mic 2
6314 */
6315 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6316 {
6317 struct ca0132_spec *spec = codec->spec;
6318
6319 mutex_lock(&spec->chipio_mutex);
6320 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6321 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6322 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6323 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6324 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6325 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6326 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6327 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6328 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6329 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6330 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6331 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6332 mutex_unlock(&spec->chipio_mutex);
6333 }
6334
6335 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6336 {
6337 struct ca0132_spec *spec = codec->spec;
6338 int i;
6339
6340 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6341 snd_hda_codec_update_widgets(codec);
6342
6343 for (i = 0; i < spec->multiout.num_dacs; i++)
6344 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6345
6346 for (i = 0; i < spec->num_outputs; i++)
6347 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6348
6349 for (i = 0; i < spec->num_inputs; i++) {
6350 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6351 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6352 }
6353 }
6354
6355 /*
6356 * Creates a dummy stream to bind the output to. This seems to have to be done
6357 * after changing the main outputs source and destination streams.
6358 */
6359 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
6360 {
6361 struct ca0132_spec *spec = codec->spec;
6362 unsigned int stream_format;
6363
6364 stream_format = snd_hdac_calc_stream_format(48000, 2,
6365 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6366
6367 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6368 0, stream_format);
6369
6370 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6371 }
6372
6373 /*
6374 * Initialize mic for non-chromebook ca0132 implementations.
6375 */
6376 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
6377 {
6378 struct ca0132_spec *spec = codec->spec;
6379 unsigned int tmp;
6380
6381 /* Mic 1 Setup */
6382 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6383 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6384 if (spec->quirk == QUIRK_R3DI) {
6385 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6386 tmp = FLOAT_ONE;
6387 } else
6388 tmp = FLOAT_THREE;
6389 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6390
6391 /* Mic 2 setup (not present on desktop cards) */
6392 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6393 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6394 if (spec->quirk == QUIRK_R3DI)
6395 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6396 tmp = FLOAT_ZERO;
6397 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6398 }
6399
6400 /*
6401 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6402 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6403 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6404 * having an updated DAC, which changes the destination to that DAC.
6405 */
6406 static void sbz_connect_streams(struct hda_codec *codec)
6407 {
6408 struct ca0132_spec *spec = codec->spec;
6409
6410 mutex_lock(&spec->chipio_mutex);
6411
6412 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6413
6414 chipio_set_stream_channels(codec, 0x0C, 6);
6415 chipio_set_stream_control(codec, 0x0C, 1);
6416
6417 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6418 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6419
6420 /* Setup stream 0x14 with it's source and destination points */
6421 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6422 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6423 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6424 chipio_set_stream_channels(codec, 0x14, 2);
6425 chipio_set_stream_control(codec, 0x14, 1);
6426
6427 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6428
6429 mutex_unlock(&spec->chipio_mutex);
6430 }
6431
6432 /*
6433 * Write data through ChipIO to setup proper stream destinations.
6434 * Not sure how it exactly works, but it seems to direct data
6435 * to different destinations. Example is f8 to c0, e0 to c0.
6436 * All I know is, if you don't set these, you get no sound.
6437 */
6438 static void sbz_chipio_startup_data(struct hda_codec *codec)
6439 {
6440 struct ca0132_spec *spec = codec->spec;
6441
6442 mutex_lock(&spec->chipio_mutex);
6443 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6444
6445 /* These control audio output */
6446 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6447 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6448 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6449 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6450 /* Signal to update I think */
6451 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6452
6453 chipio_set_stream_channels(codec, 0x0C, 6);
6454 chipio_set_stream_control(codec, 0x0C, 1);
6455 /* No clue what these control */
6456 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6457 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6458 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6459 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6460 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6461 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6462 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6463 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6464 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6465 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6466 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6467 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6468
6469 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6470
6471 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6472 mutex_unlock(&spec->chipio_mutex);
6473 }
6474
6475 /*
6476 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
6477 * done after the DSP is loaded.
6478 */
6479 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
6480 {
6481 struct ca0132_spec *spec = codec->spec;
6482 unsigned int tmp;
6483
6484 switch (spec->quirk) {
6485 case QUIRK_SBZ:
6486 case QUIRK_AE5:
6487 tmp = 0x00000003;
6488 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6489 tmp = 0x00000000;
6490 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6491 tmp = 0x00000001;
6492 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6493 tmp = 0x00000004;
6494 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6495 tmp = 0x00000005;
6496 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6497 tmp = 0x00000000;
6498 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6499 break;
6500 case QUIRK_R3D:
6501 case QUIRK_R3DI:
6502 tmp = 0x00000000;
6503 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6504 tmp = 0x00000001;
6505 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6506 tmp = 0x00000004;
6507 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6508 tmp = 0x00000005;
6509 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6510 tmp = 0x00000000;
6511 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6512 break;
6513 }
6514 }
6515
6516 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
6517 {
6518 struct ca0132_spec *spec = codec->spec;
6519 unsigned int tmp;
6520
6521 chipio_set_stream_control(codec, 0x03, 0);
6522 chipio_set_stream_control(codec, 0x04, 0);
6523
6524 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6525 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6526
6527 tmp = FLOAT_THREE;
6528 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6529
6530 chipio_set_stream_control(codec, 0x03, 1);
6531 chipio_set_stream_control(codec, 0x04, 1);
6532
6533 switch (spec->quirk) {
6534 case QUIRK_SBZ:
6535 chipio_write(codec, 0x18b098, 0x0000000c);
6536 chipio_write(codec, 0x18b09C, 0x0000000c);
6537 break;
6538 case QUIRK_AE5:
6539 chipio_write(codec, 0x18b098, 0x0000000c);
6540 chipio_write(codec, 0x18b09c, 0x0000004c);
6541 break;
6542 }
6543 }
6544
6545 static void ae5_post_dsp_register_set(struct hda_codec *codec)
6546 {
6547 struct ca0132_spec *spec = codec->spec;
6548
6549 chipio_8051_write_direct(codec, 0x93, 0x10);
6550 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6551 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
6552 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6553 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
6554
6555 writeb(0xff, spec->mem_base + 0x304);
6556 writeb(0xff, spec->mem_base + 0x304);
6557 writeb(0xff, spec->mem_base + 0x304);
6558 writeb(0xff, spec->mem_base + 0x304);
6559 writeb(0x00, spec->mem_base + 0x100);
6560 writeb(0xff, spec->mem_base + 0x304);
6561 writeb(0x00, spec->mem_base + 0x100);
6562 writeb(0xff, spec->mem_base + 0x304);
6563 writeb(0x00, spec->mem_base + 0x100);
6564 writeb(0xff, spec->mem_base + 0x304);
6565 writeb(0x00, spec->mem_base + 0x100);
6566 writeb(0xff, spec->mem_base + 0x304);
6567
6568 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
6569 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
6570 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6571 }
6572
6573 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
6574 {
6575 /*
6576 * Param3 in the 8051's memory is represented by the ascii string 'mch'
6577 * which seems to be 'multichannel'. This is also mentioned in the
6578 * AE-5's registry values in Windows.
6579 */
6580 chipio_set_control_param(codec, 3, 0);
6581 /*
6582 * I believe ASI is 'audio serial interface' and that it's used to
6583 * change colors on the external LED strip connected to the AE-5.
6584 */
6585 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
6586
6587 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
6588 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
6589
6590 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6591 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
6592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6593 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
6594 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6595 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
6596 }
6597
6598 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
6599 {
6600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6601 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
6602 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6603 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
6604
6605 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6606 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
6607 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6608 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
6609
6610 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6611 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
6612 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6613 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
6614
6615 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6616 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
6617 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6618 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
6619
6620 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6621 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
6622 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6623 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
6624 }
6625
6626 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
6627 {
6628 struct ca0132_spec *spec = codec->spec;
6629
6630 mutex_lock(&spec->chipio_mutex);
6631
6632 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
6633
6634 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
6635
6636 chipio_set_stream_channels(codec, 0x0C, 6);
6637 chipio_set_stream_control(codec, 0x0C, 1);
6638
6639 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
6640
6641 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
6642 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
6643 chipio_set_stream_channels(codec, 0x18, 6);
6644 chipio_set_stream_control(codec, 0x18, 1);
6645
6646 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
6647
6648 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6649 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
6650 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6651 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
6652
6653 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
6654
6655 mutex_unlock(&spec->chipio_mutex);
6656 }
6657
6658 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
6659 {
6660 struct ca0132_spec *spec = codec->spec;
6661
6662 mutex_lock(&spec->chipio_mutex);
6663
6664 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
6665 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
6666 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
6667 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
6668
6669 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
6670 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
6671 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
6672 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
6673 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
6674 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
6675 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
6676 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
6677 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
6678 ca0113_mmio_gpio_set(codec, 0, true);
6679 ca0113_mmio_gpio_set(codec, 1, true);
6680 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
6681
6682 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
6683
6684 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
6685 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
6686
6687 mutex_unlock(&spec->chipio_mutex);
6688 }
6689
6690 /*
6691 * Setup default parameters for DSP
6692 */
6693 static void ca0132_setup_defaults(struct hda_codec *codec)
6694 {
6695 struct ca0132_spec *spec = codec->spec;
6696 unsigned int tmp;
6697 int num_fx;
6698 int idx, i;
6699
6700 if (spec->dsp_state != DSP_DOWNLOADED)
6701 return;
6702
6703 /* out, in effects + voicefx */
6704 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6705 for (idx = 0; idx < num_fx; idx++) {
6706 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6707 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6708 ca0132_effects[idx].reqs[i],
6709 ca0132_effects[idx].def_vals[i]);
6710 }
6711 }
6712
6713 /*remove DSP headroom*/
6714 tmp = FLOAT_ZERO;
6715 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6716
6717 /*set speaker EQ bypass attenuation*/
6718 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6719
6720 /* set AMic1 and AMic2 as mono mic */
6721 tmp = FLOAT_ONE;
6722 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6723 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6724
6725 /* set AMic1 as CrystalVoice input */
6726 tmp = FLOAT_ONE;
6727 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6728
6729 /* set WUH source */
6730 tmp = FLOAT_TWO;
6731 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6732 }
6733
6734 /*
6735 * Setup default parameters for Recon3D/Recon3Di DSP.
6736 */
6737
6738 static void r3d_setup_defaults(struct hda_codec *codec)
6739 {
6740 struct ca0132_spec *spec = codec->spec;
6741 unsigned int tmp;
6742 int num_fx;
6743 int idx, i;
6744
6745 if (spec->dsp_state != DSP_DOWNLOADED)
6746 return;
6747
6748 ca0132_alt_dsp_scp_startup(codec);
6749 ca0132_alt_init_analog_mics(codec);
6750
6751 /*remove DSP headroom*/
6752 tmp = FLOAT_ZERO;
6753 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6754
6755 /* set WUH source */
6756 tmp = FLOAT_TWO;
6757 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6758 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6759
6760 /* Set speaker source? */
6761 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6762
6763 if (spec->quirk == QUIRK_R3DI)
6764 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6765
6766 /* Setup effect defaults */
6767 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6768 for (idx = 0; idx < num_fx; idx++) {
6769 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6770 dspio_set_uint_param(codec,
6771 ca0132_effects[idx].mid,
6772 ca0132_effects[idx].reqs[i],
6773 ca0132_effects[idx].def_vals[i]);
6774 }
6775 }
6776 }
6777
6778 /*
6779 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6780 * than the Chromebook setup.
6781 */
6782 static void sbz_setup_defaults(struct hda_codec *codec)
6783 {
6784 struct ca0132_spec *spec = codec->spec;
6785 unsigned int tmp;
6786 int num_fx;
6787 int idx, i;
6788
6789 if (spec->dsp_state != DSP_DOWNLOADED)
6790 return;
6791
6792 ca0132_alt_dsp_scp_startup(codec);
6793 ca0132_alt_init_analog_mics(codec);
6794 sbz_connect_streams(codec);
6795 sbz_chipio_startup_data(codec);
6796
6797 chipio_set_stream_control(codec, 0x03, 1);
6798 chipio_set_stream_control(codec, 0x04, 1);
6799
6800 /*
6801 * Sets internal input loopback to off, used to have a switch to
6802 * enable input loopback, but turned out to be way too buggy.
6803 */
6804 tmp = FLOAT_ONE;
6805 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6806 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6807
6808 /*remove DSP headroom*/
6809 tmp = FLOAT_ZERO;
6810 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6811
6812 /* set WUH source */
6813 tmp = FLOAT_TWO;
6814 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6815 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6816
6817 /* Set speaker source? */
6818 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6819
6820 ca0132_alt_dsp_initial_mic_setup(codec);
6821
6822 /* out, in effects + voicefx */
6823 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6824 for (idx = 0; idx < num_fx; idx++) {
6825 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6826 dspio_set_uint_param(codec,
6827 ca0132_effects[idx].mid,
6828 ca0132_effects[idx].reqs[i],
6829 ca0132_effects[idx].def_vals[i]);
6830 }
6831 }
6832
6833 ca0132_alt_create_dummy_stream(codec);
6834 }
6835
6836 /*
6837 * Setup default parameters for the Sound BlasterX AE-5 DSP.
6838 */
6839 static void ae5_setup_defaults(struct hda_codec *codec)
6840 {
6841 struct ca0132_spec *spec = codec->spec;
6842 unsigned int tmp;
6843 int num_fx;
6844 int idx, i;
6845
6846 if (spec->dsp_state != DSP_DOWNLOADED)
6847 return;
6848
6849 ca0132_alt_dsp_scp_startup(codec);
6850 ca0132_alt_init_analog_mics(codec);
6851 chipio_set_stream_control(codec, 0x03, 1);
6852 chipio_set_stream_control(codec, 0x04, 1);
6853
6854 /* New, unknown SCP req's */
6855 tmp = FLOAT_ZERO;
6856 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
6857 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
6858 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
6859 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
6860
6861 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
6862 ca0113_mmio_gpio_set(codec, 0, false);
6863 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
6864
6865 /* Internal loopback off */
6866 tmp = FLOAT_ONE;
6867 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6868 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6869
6870 /*remove DSP headroom*/
6871 tmp = FLOAT_ZERO;
6872 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6873
6874 /* set WUH source */
6875 tmp = FLOAT_TWO;
6876 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6877 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6878
6879 /* Set speaker source? */
6880 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6881
6882 ca0132_alt_dsp_initial_mic_setup(codec);
6883 ae5_post_dsp_register_set(codec);
6884 ae5_post_dsp_param_setup(codec);
6885 ae5_post_dsp_pll_setup(codec);
6886 ae5_post_dsp_stream_setup(codec);
6887 ae5_post_dsp_startup_data(codec);
6888
6889 /* out, in effects + voicefx */
6890 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6891 for (idx = 0; idx < num_fx; idx++) {
6892 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6893 dspio_set_uint_param(codec,
6894 ca0132_effects[idx].mid,
6895 ca0132_effects[idx].reqs[i],
6896 ca0132_effects[idx].def_vals[i]);
6897 }
6898 }
6899
6900 ca0132_alt_create_dummy_stream(codec);
6901 }
6902
6903 /*
6904 * Initialization of flags in chip
6905 */
6906 static void ca0132_init_flags(struct hda_codec *codec)
6907 {
6908 struct ca0132_spec *spec = codec->spec;
6909
6910 if (spec->use_alt_functions) {
6911 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6912 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6913 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6914 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6915 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6916 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6917 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6918 chipio_set_control_flag(codec,
6919 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6920 chipio_set_control_flag(codec,
6921 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6922 } else {
6923 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6924 chipio_set_control_flag(codec,
6925 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6926 chipio_set_control_flag(codec,
6927 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6928 chipio_set_control_flag(codec,
6929 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6930 chipio_set_control_flag(codec,
6931 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6932 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6933 }
6934 }
6935
6936 /*
6937 * Initialization of parameters in chip
6938 */
6939 static void ca0132_init_params(struct hda_codec *codec)
6940 {
6941 struct ca0132_spec *spec = codec->spec;
6942
6943 if (spec->use_alt_functions) {
6944 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6945 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6946 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6947 chipio_set_control_param(codec, 0, 0);
6948 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6949 }
6950
6951 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6952 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6953 }
6954
6955 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6956 {
6957 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6958 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6959 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6960 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6961 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6962 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6963
6964 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6965 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6966 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6967 }
6968
6969 static bool ca0132_download_dsp_images(struct hda_codec *codec)
6970 {
6971 bool dsp_loaded = false;
6972 struct ca0132_spec *spec = codec->spec;
6973 const struct dsp_image_seg *dsp_os_image;
6974 const struct firmware *fw_entry;
6975 /*
6976 * Alternate firmwares for different variants. The Recon3Di apparently
6977 * can use the default firmware, but I'll leave the option in case
6978 * it needs it again.
6979 */
6980 switch (spec->quirk) {
6981 case QUIRK_SBZ:
6982 case QUIRK_R3D:
6983 case QUIRK_AE5:
6984 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
6985 codec->card->dev) != 0) {
6986 codec_dbg(codec, "Desktop firmware not found.");
6987 spec->alt_firmware_present = false;
6988 } else {
6989 codec_dbg(codec, "Desktop firmware selected.");
6990 spec->alt_firmware_present = true;
6991 }
6992 break;
6993 case QUIRK_R3DI:
6994 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6995 codec->card->dev) != 0) {
6996 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6997 spec->alt_firmware_present = false;
6998 } else {
6999 codec_dbg(codec, "Recon3Di firmware selected.");
7000 spec->alt_firmware_present = true;
7001 }
7002 break;
7003 default:
7004 spec->alt_firmware_present = false;
7005 break;
7006 }
7007 /*
7008 * Use default ctefx.bin if no alt firmware is detected, or if none
7009 * exists for your particular codec.
7010 */
7011 if (!spec->alt_firmware_present) {
7012 codec_dbg(codec, "Default firmware selected.");
7013 if (request_firmware(&fw_entry, EFX_FILE,
7014 codec->card->dev) != 0)
7015 return false;
7016 }
7017
7018 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
7019 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
7020 codec_err(codec, "ca0132 DSP load image failed\n");
7021 goto exit_download;
7022 }
7023
7024 dsp_loaded = dspload_wait_loaded(codec);
7025
7026 exit_download:
7027 release_firmware(fw_entry);
7028
7029 return dsp_loaded;
7030 }
7031
7032 static void ca0132_download_dsp(struct hda_codec *codec)
7033 {
7034 struct ca0132_spec *spec = codec->spec;
7035
7036 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
7037 return; /* NOP */
7038 #endif
7039
7040 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
7041 return; /* don't retry failures */
7042
7043 chipio_enable_clocks(codec);
7044 if (spec->dsp_state != DSP_DOWNLOADED) {
7045 spec->dsp_state = DSP_DOWNLOADING;
7046
7047 if (!ca0132_download_dsp_images(codec))
7048 spec->dsp_state = DSP_DOWNLOAD_FAILED;
7049 else
7050 spec->dsp_state = DSP_DOWNLOADED;
7051 }
7052
7053 /* For codecs using alt functions, this is already done earlier */
7054 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
7055 ca0132_set_dsp_msr(codec, true);
7056 }
7057
7058 static void ca0132_process_dsp_response(struct hda_codec *codec,
7059 struct hda_jack_callback *callback)
7060 {
7061 struct ca0132_spec *spec = codec->spec;
7062
7063 codec_dbg(codec, "ca0132_process_dsp_response\n");
7064 if (spec->wait_scp) {
7065 if (dspio_get_response_data(codec) >= 0)
7066 spec->wait_scp = 0;
7067 }
7068
7069 dspio_clear_response_queue(codec);
7070 }
7071
7072 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7073 {
7074 struct ca0132_spec *spec = codec->spec;
7075 struct hda_jack_tbl *tbl;
7076
7077 /* Delay enabling the HP amp, to let the mic-detection
7078 * state machine run.
7079 */
7080 cancel_delayed_work_sync(&spec->unsol_hp_work);
7081 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
7082 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
7083 if (tbl)
7084 tbl->block_report = 1;
7085 }
7086
7087 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
7088 {
7089 struct ca0132_spec *spec = codec->spec;
7090
7091 if (spec->use_alt_functions)
7092 ca0132_alt_select_in(codec);
7093 else
7094 ca0132_select_mic(codec);
7095 }
7096
7097 static void ca0132_init_unsol(struct hda_codec *codec)
7098 {
7099 struct ca0132_spec *spec = codec->spec;
7100 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
7101 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
7102 amic_callback);
7103 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
7104 ca0132_process_dsp_response);
7105 /* Front headphone jack detection */
7106 if (spec->use_alt_functions)
7107 snd_hda_jack_detect_enable_callback(codec,
7108 spec->unsol_tag_front_hp, hp_callback);
7109 }
7110
7111 /*
7112 * Verbs tables.
7113 */
7114
7115 /* Sends before DSP download. */
7116 static struct hda_verb ca0132_base_init_verbs[] = {
7117 /*enable ct extension*/
7118 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
7119 {}
7120 };
7121
7122 /* Send at exit. */
7123 static struct hda_verb ca0132_base_exit_verbs[] = {
7124 /*set afg to D3*/
7125 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
7126 /*disable ct extension*/
7127 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
7128 {}
7129 };
7130
7131 /* Other verbs tables. Sends after DSP download. */
7132
7133 static struct hda_verb ca0132_init_verbs0[] = {
7134 /* chip init verbs */
7135 {0x15, 0x70D, 0xF0},
7136 {0x15, 0x70E, 0xFE},
7137 {0x15, 0x707, 0x75},
7138 {0x15, 0x707, 0xD3},
7139 {0x15, 0x707, 0x09},
7140 {0x15, 0x707, 0x53},
7141 {0x15, 0x707, 0xD4},
7142 {0x15, 0x707, 0xEF},
7143 {0x15, 0x707, 0x75},
7144 {0x15, 0x707, 0xD3},
7145 {0x15, 0x707, 0x09},
7146 {0x15, 0x707, 0x02},
7147 {0x15, 0x707, 0x37},
7148 {0x15, 0x707, 0x78},
7149 {0x15, 0x53C, 0xCE},
7150 {0x15, 0x575, 0xC9},
7151 {0x15, 0x53D, 0xCE},
7152 {0x15, 0x5B7, 0xC9},
7153 {0x15, 0x70D, 0xE8},
7154 {0x15, 0x70E, 0xFE},
7155 {0x15, 0x707, 0x02},
7156 {0x15, 0x707, 0x68},
7157 {0x15, 0x707, 0x62},
7158 {0x15, 0x53A, 0xCE},
7159 {0x15, 0x546, 0xC9},
7160 {0x15, 0x53B, 0xCE},
7161 {0x15, 0x5E8, 0xC9},
7162 {}
7163 };
7164
7165 /* Extra init verbs for desktop cards. */
7166 static struct hda_verb ca0132_init_verbs1[] = {
7167 {0x15, 0x70D, 0x20},
7168 {0x15, 0x70E, 0x19},
7169 {0x15, 0x707, 0x00},
7170 {0x15, 0x539, 0xCE},
7171 {0x15, 0x546, 0xC9},
7172 {0x15, 0x70D, 0xB7},
7173 {0x15, 0x70E, 0x09},
7174 {0x15, 0x707, 0x10},
7175 {0x15, 0x70D, 0xAF},
7176 {0x15, 0x70E, 0x09},
7177 {0x15, 0x707, 0x01},
7178 {0x15, 0x707, 0x05},
7179 {0x15, 0x70D, 0x73},
7180 {0x15, 0x70E, 0x09},
7181 {0x15, 0x707, 0x14},
7182 {0x15, 0x6FF, 0xC4},
7183 {}
7184 };
7185
7186 static void ca0132_init_chip(struct hda_codec *codec)
7187 {
7188 struct ca0132_spec *spec = codec->spec;
7189 int num_fx;
7190 int i;
7191 unsigned int on;
7192
7193 mutex_init(&spec->chipio_mutex);
7194
7195 spec->cur_out_type = SPEAKER_OUT;
7196 if (!spec->use_alt_functions)
7197 spec->cur_mic_type = DIGITAL_MIC;
7198 else
7199 spec->cur_mic_type = REAR_MIC;
7200
7201 spec->cur_mic_boost = 0;
7202
7203 for (i = 0; i < VNODES_COUNT; i++) {
7204 spec->vnode_lvol[i] = 0x5a;
7205 spec->vnode_rvol[i] = 0x5a;
7206 spec->vnode_lswitch[i] = 0;
7207 spec->vnode_rswitch[i] = 0;
7208 }
7209
7210 /*
7211 * Default states for effects are in ca0132_effects[].
7212 */
7213 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7214 for (i = 0; i < num_fx; i++) {
7215 on = (unsigned int)ca0132_effects[i].reqs[0];
7216 spec->effects_switch[i] = on ? 1 : 0;
7217 }
7218 /*
7219 * Sets defaults for the effect slider controls, only for alternative
7220 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
7221 */
7222 if (spec->use_alt_controls) {
7223 spec->xbass_xover_freq = 8;
7224 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
7225 spec->fx_ctl_val[i] = effect_slider_defaults[i];
7226 }
7227
7228 spec->voicefx_val = 0;
7229 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
7230 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
7231
7232 #ifdef ENABLE_TUNING_CONTROLS
7233 ca0132_init_tuning_defaults(codec);
7234 #endif
7235 }
7236
7237 /*
7238 * Recon3Di exit specific commands.
7239 */
7240 /* prevents popping noise on shutdown */
7241 static void r3di_gpio_shutdown(struct hda_codec *codec)
7242 {
7243 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
7244 }
7245
7246 /*
7247 * Sound Blaster Z exit specific commands.
7248 */
7249 static void sbz_region2_exit(struct hda_codec *codec)
7250 {
7251 struct ca0132_spec *spec = codec->spec;
7252 unsigned int i;
7253
7254 for (i = 0; i < 4; i++)
7255 writeb(0x0, spec->mem_base + 0x100);
7256 for (i = 0; i < 8; i++)
7257 writeb(0xb3, spec->mem_base + 0x304);
7258
7259 ca0113_mmio_gpio_set(codec, 0, false);
7260 ca0113_mmio_gpio_set(codec, 1, false);
7261 ca0113_mmio_gpio_set(codec, 4, true);
7262 ca0113_mmio_gpio_set(codec, 5, false);
7263 ca0113_mmio_gpio_set(codec, 7, false);
7264 }
7265
7266 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
7267 {
7268 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
7269 unsigned int i;
7270
7271 snd_hda_codec_write(codec, 0x11, 0,
7272 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
7273
7274 for (i = 0; i < 5; i++)
7275 snd_hda_codec_write(codec, pins[i], 0,
7276 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
7277 }
7278
7279 static void ca0132_clear_unsolicited(struct hda_codec *codec)
7280 {
7281 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
7282 unsigned int i;
7283
7284 for (i = 0; i < 7; i++) {
7285 snd_hda_codec_write(codec, pins[i], 0,
7286 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
7287 }
7288 }
7289
7290 /* On shutdown, sends commands in sets of three */
7291 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
7292 int mask, int data)
7293 {
7294 if (dir >= 0)
7295 snd_hda_codec_write(codec, 0x01, 0,
7296 AC_VERB_SET_GPIO_DIRECTION, dir);
7297 if (mask >= 0)
7298 snd_hda_codec_write(codec, 0x01, 0,
7299 AC_VERB_SET_GPIO_MASK, mask);
7300
7301 if (data >= 0)
7302 snd_hda_codec_write(codec, 0x01, 0,
7303 AC_VERB_SET_GPIO_DATA, data);
7304 }
7305
7306 static void sbz_exit_chip(struct hda_codec *codec)
7307 {
7308 chipio_set_stream_control(codec, 0x03, 0);
7309 chipio_set_stream_control(codec, 0x04, 0);
7310
7311 /* Mess with GPIO */
7312 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7313 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7314 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7315
7316 chipio_set_stream_control(codec, 0x14, 0);
7317 chipio_set_stream_control(codec, 0x0C, 0);
7318
7319 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7320 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7321
7322 chipio_write(codec, 0x18a020, 0x00000083);
7323
7324 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7325 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7326 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7327
7328 chipio_set_stream_control(codec, 0x0C, 0);
7329
7330 chipio_set_control_param(codec, 0x0D, 0x24);
7331
7332 ca0132_clear_unsolicited(codec);
7333 sbz_set_pin_ctl_default(codec);
7334
7335 snd_hda_codec_write(codec, 0x0B, 0,
7336 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7337
7338 sbz_region2_exit(codec);
7339 }
7340
7341 static void r3d_exit_chip(struct hda_codec *codec)
7342 {
7343 ca0132_clear_unsolicited(codec);
7344 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7345 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7346 }
7347
7348 static void ca0132_exit_chip(struct hda_codec *codec)
7349 {
7350 /* put any chip cleanup stuffs here. */
7351
7352 if (dspload_is_loaded(codec))
7353 dsp_reset(codec);
7354 }
7355
7356 /*
7357 * This fixes a problem that was hard to reproduce. Very rarely, I would
7358 * boot up, and there would be no sound, but the DSP indicated it had loaded
7359 * properly. I did a few memory dumps to see if anything was different, and
7360 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7361 * checks if those areas are uninitialized, and if they are, it'll attempt to
7362 * reload the card 3 times. Usually it fixes by the second.
7363 */
7364 static void sbz_dsp_startup_check(struct hda_codec *codec)
7365 {
7366 struct ca0132_spec *spec = codec->spec;
7367 unsigned int dsp_data_check[4];
7368 unsigned int cur_address = 0x390;
7369 unsigned int i;
7370 unsigned int failure = 0;
7371 unsigned int reload = 3;
7372
7373 if (spec->startup_check_entered)
7374 return;
7375
7376 spec->startup_check_entered = true;
7377
7378 for (i = 0; i < 4; i++) {
7379 chipio_read(codec, cur_address, &dsp_data_check[i]);
7380 cur_address += 0x4;
7381 }
7382 for (i = 0; i < 4; i++) {
7383 if (dsp_data_check[i] == 0xa1a2a3a4)
7384 failure = 1;
7385 }
7386
7387 codec_dbg(codec, "Startup Check: %d ", failure);
7388 if (failure)
7389 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7390 /*
7391 * While the failure condition is true, and we haven't reached our
7392 * three reload limit, continue trying to reload the driver and
7393 * fix the issue.
7394 */
7395 while (failure && (reload != 0)) {
7396 codec_info(codec, "Reloading... Tries left: %d", reload);
7397 sbz_exit_chip(codec);
7398 spec->dsp_state = DSP_DOWNLOAD_INIT;
7399 codec->patch_ops.init(codec);
7400 failure = 0;
7401 for (i = 0; i < 4; i++) {
7402 chipio_read(codec, cur_address, &dsp_data_check[i]);
7403 cur_address += 0x4;
7404 }
7405 for (i = 0; i < 4; i++) {
7406 if (dsp_data_check[i] == 0xa1a2a3a4)
7407 failure = 1;
7408 }
7409 reload--;
7410 }
7411
7412 if (!failure && reload < 3)
7413 codec_info(codec, "DSP fixed.");
7414
7415 if (!failure)
7416 return;
7417
7418 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7419 }
7420
7421 /*
7422 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7423 * extra precision for decibel values. If you had the dB value in floating point
7424 * you would take the value after the decimal point, multiply by 64, and divide
7425 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7426 * implement fixed point or floating point dB volumes. For now, I'll set them
7427 * to 0 just incase a value has lingered from a boot into Windows.
7428 */
7429 static void ca0132_alt_vol_setup(struct hda_codec *codec)
7430 {
7431 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7432 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7433 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7434 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7435 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7436 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7437 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7438 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7439 }
7440
7441 /*
7442 * Extra commands that don't really fit anywhere else.
7443 */
7444 static void sbz_pre_dsp_setup(struct hda_codec *codec)
7445 {
7446 struct ca0132_spec *spec = codec->spec;
7447
7448 writel(0x00820680, spec->mem_base + 0x01C);
7449 writel(0x00820680, spec->mem_base + 0x01C);
7450
7451 chipio_write(codec, 0x18b0a4, 0x000000c2);
7452
7453 snd_hda_codec_write(codec, 0x11, 0,
7454 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7455 }
7456
7457 static void r3d_pre_dsp_setup(struct hda_codec *codec)
7458 {
7459 chipio_write(codec, 0x18b0a4, 0x000000c2);
7460
7461 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7462 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7463 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7464 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7465 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7466 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7467
7468 snd_hda_codec_write(codec, 0x11, 0,
7469 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7470 }
7471
7472 static void r3di_pre_dsp_setup(struct hda_codec *codec)
7473 {
7474 chipio_write(codec, 0x18b0a4, 0x000000c2);
7475
7476 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7477 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7478 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7479 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7480 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7481 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7482
7483 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7484 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7485 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7486 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7487 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7488 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7489 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7490 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7491
7492 snd_hda_codec_write(codec, 0x11, 0,
7493 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7494 }
7495
7496 /*
7497 * These are sent before the DSP is downloaded. Not sure
7498 * what they do, or if they're necessary. Could possibly
7499 * be removed. Figure they're better to leave in.
7500 */
7501 static void ca0132_mmio_init(struct hda_codec *codec)
7502 {
7503 struct ca0132_spec *spec = codec->spec;
7504
7505 if (spec->quirk == QUIRK_AE5)
7506 writel(0x00000001, spec->mem_base + 0x400);
7507 else
7508 writel(0x00000000, spec->mem_base + 0x400);
7509
7510 if (spec->quirk == QUIRK_AE5)
7511 writel(0x00000001, spec->mem_base + 0x408);
7512 else
7513 writel(0x00000000, spec->mem_base + 0x408);
7514
7515 if (spec->quirk == QUIRK_AE5)
7516 writel(0x00000001, spec->mem_base + 0x40c);
7517 else
7518 writel(0x00000000, spec->mem_base + 0x40C);
7519
7520 writel(0x00880680, spec->mem_base + 0x01C);
7521
7522 if (spec->quirk == QUIRK_AE5)
7523 writel(0x00000080, spec->mem_base + 0xC0C);
7524 else
7525 writel(0x00000083, spec->mem_base + 0xC0C);
7526
7527 writel(0x00000030, spec->mem_base + 0xC00);
7528 writel(0x00000000, spec->mem_base + 0xC04);
7529
7530 if (spec->quirk == QUIRK_AE5)
7531 writel(0x00000000, spec->mem_base + 0xC0C);
7532 else
7533 writel(0x00000003, spec->mem_base + 0xC0C);
7534
7535 writel(0x00000003, spec->mem_base + 0xC0C);
7536 writel(0x00000003, spec->mem_base + 0xC0C);
7537 writel(0x00000003, spec->mem_base + 0xC0C);
7538
7539 if (spec->quirk == QUIRK_AE5)
7540 writel(0x00000001, spec->mem_base + 0xC08);
7541 else
7542 writel(0x000000C1, spec->mem_base + 0xC08);
7543
7544 writel(0x000000F1, spec->mem_base + 0xC08);
7545 writel(0x00000001, spec->mem_base + 0xC08);
7546 writel(0x000000C7, spec->mem_base + 0xC08);
7547 writel(0x000000C1, spec->mem_base + 0xC08);
7548 writel(0x00000080, spec->mem_base + 0xC04);
7549
7550 if (spec->quirk == QUIRK_AE5) {
7551 writel(0x00000000, spec->mem_base + 0x42c);
7552 writel(0x00000000, spec->mem_base + 0x46c);
7553 writel(0x00000000, spec->mem_base + 0x4ac);
7554 writel(0x00000000, spec->mem_base + 0x4ec);
7555 writel(0x00000000, spec->mem_base + 0x43c);
7556 writel(0x00000000, spec->mem_base + 0x47c);
7557 writel(0x00000000, spec->mem_base + 0x4bc);
7558 writel(0x00000000, spec->mem_base + 0x4fc);
7559 writel(0x00000600, spec->mem_base + 0x100);
7560 writel(0x00000014, spec->mem_base + 0x410);
7561 writel(0x0000060f, spec->mem_base + 0x100);
7562 writel(0x0000070f, spec->mem_base + 0x100);
7563 writel(0x00000aff, spec->mem_base + 0x830);
7564 writel(0x00000000, spec->mem_base + 0x86c);
7565 writel(0x0000006b, spec->mem_base + 0x800);
7566 writel(0x00000001, spec->mem_base + 0x86c);
7567 writel(0x0000006b, spec->mem_base + 0x800);
7568 writel(0x00000057, spec->mem_base + 0x804);
7569 writel(0x00800000, spec->mem_base + 0x20c);
7570 }
7571 }
7572
7573 /*
7574 * This function writes to some SFR's, does some region2 writes, and then
7575 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
7576 * what it does.
7577 */
7578 static void ae5_register_set(struct hda_codec *codec)
7579 {
7580 struct ca0132_spec *spec = codec->spec;
7581
7582 chipio_8051_write_direct(codec, 0x93, 0x10);
7583 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7584 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7585 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7586 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7587
7588 writeb(0x0f, spec->mem_base + 0x304);
7589 writeb(0x0f, spec->mem_base + 0x304);
7590 writeb(0x0f, spec->mem_base + 0x304);
7591 writeb(0x0f, spec->mem_base + 0x304);
7592 writeb(0x0e, spec->mem_base + 0x100);
7593 writeb(0x1f, spec->mem_base + 0x304);
7594 writeb(0x0c, spec->mem_base + 0x100);
7595 writeb(0x3f, spec->mem_base + 0x304);
7596 writeb(0x08, spec->mem_base + 0x100);
7597 writeb(0x7f, spec->mem_base + 0x304);
7598 writeb(0x00, spec->mem_base + 0x100);
7599 writeb(0xff, spec->mem_base + 0x304);
7600
7601 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7602
7603 chipio_8051_write_direct(codec, 0x90, 0x00);
7604 chipio_8051_write_direct(codec, 0x90, 0x10);
7605
7606 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7607
7608 chipio_write(codec, 0x18b0a4, 0x000000c2);
7609
7610 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7611 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7612 }
7613
7614 /*
7615 * Extra init functions for alternative ca0132 codecs. Done
7616 * here so they don't clutter up the main ca0132_init function
7617 * anymore than they have to.
7618 */
7619 static void ca0132_alt_init(struct hda_codec *codec)
7620 {
7621 struct ca0132_spec *spec = codec->spec;
7622
7623 ca0132_alt_vol_setup(codec);
7624
7625 switch (spec->quirk) {
7626 case QUIRK_SBZ:
7627 codec_dbg(codec, "SBZ alt_init");
7628 ca0132_gpio_init(codec);
7629 sbz_pre_dsp_setup(codec);
7630 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7631 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7632 break;
7633 case QUIRK_R3DI:
7634 codec_dbg(codec, "R3DI alt_init");
7635 ca0132_gpio_init(codec);
7636 ca0132_gpio_setup(codec);
7637 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7638 r3di_pre_dsp_setup(codec);
7639 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7640 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7641 break;
7642 case QUIRK_R3D:
7643 r3d_pre_dsp_setup(codec);
7644 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7645 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7646 break;
7647 case QUIRK_AE5:
7648 ca0132_gpio_init(codec);
7649 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7650 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
7651 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7652 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
7653 chipio_write(codec, 0x18b030, 0x00000020);
7654 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7655 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7656 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
7657 break;
7658 }
7659 }
7660
7661 static int ca0132_init(struct hda_codec *codec)
7662 {
7663 struct ca0132_spec *spec = codec->spec;
7664 struct auto_pin_cfg *cfg = &spec->autocfg;
7665 int i;
7666 bool dsp_loaded;
7667
7668 /*
7669 * If the DSP is already downloaded, and init has been entered again,
7670 * there's only two reasons for it. One, the codec has awaken from a
7671 * suspended state, and in that case dspload_is_loaded will return
7672 * false, and the init will be ran again. The other reason it gets
7673 * re entered is on startup for some reason it triggers a suspend and
7674 * resume state. In this case, it will check if the DSP is downloaded,
7675 * and not run the init function again. For codecs using alt_functions,
7676 * it will check if the DSP is loaded properly.
7677 */
7678 if (spec->dsp_state == DSP_DOWNLOADED) {
7679 dsp_loaded = dspload_is_loaded(codec);
7680 if (!dsp_loaded) {
7681 spec->dsp_reload = true;
7682 spec->dsp_state = DSP_DOWNLOAD_INIT;
7683 } else {
7684 if (spec->quirk == QUIRK_SBZ)
7685 sbz_dsp_startup_check(codec);
7686 return 0;
7687 }
7688 }
7689
7690 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7691 spec->dsp_state = DSP_DOWNLOAD_INIT;
7692 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7693
7694 if (spec->use_pci_mmio)
7695 ca0132_mmio_init(codec);
7696
7697 snd_hda_power_up_pm(codec);
7698
7699 if (spec->quirk == QUIRK_AE5)
7700 ae5_register_set(codec);
7701
7702 ca0132_init_unsol(codec);
7703 ca0132_init_params(codec);
7704 ca0132_init_flags(codec);
7705
7706 snd_hda_sequence_write(codec, spec->base_init_verbs);
7707
7708 if (spec->use_alt_functions)
7709 ca0132_alt_init(codec);
7710
7711 ca0132_download_dsp(codec);
7712
7713 ca0132_refresh_widget_caps(codec);
7714
7715 switch (spec->quirk) {
7716 case QUIRK_R3DI:
7717 case QUIRK_R3D:
7718 r3d_setup_defaults(codec);
7719 break;
7720 case QUIRK_SBZ:
7721 sbz_setup_defaults(codec);
7722 break;
7723 case QUIRK_AE5:
7724 ae5_setup_defaults(codec);
7725 break;
7726 default:
7727 ca0132_setup_defaults(codec);
7728 ca0132_init_analog_mic2(codec);
7729 ca0132_init_dmic(codec);
7730 break;
7731 }
7732
7733 for (i = 0; i < spec->num_outputs; i++)
7734 init_output(codec, spec->out_pins[i], spec->dacs[0]);
7735
7736 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7737
7738 for (i = 0; i < spec->num_inputs; i++)
7739 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7740
7741 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7742
7743 if (!spec->use_alt_functions) {
7744 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7745 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7746 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7747 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7748 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7749 }
7750
7751 if (spec->quirk == QUIRK_SBZ)
7752 ca0132_gpio_setup(codec);
7753
7754 snd_hda_sequence_write(codec, spec->spec_init_verbs);
7755 if (spec->use_alt_functions) {
7756 ca0132_alt_select_out(codec);
7757 ca0132_alt_select_in(codec);
7758 } else {
7759 ca0132_select_out(codec);
7760 ca0132_select_mic(codec);
7761 }
7762
7763 snd_hda_jack_report_sync(codec);
7764
7765 /*
7766 * Re set the PlayEnhancement switch on a resume event, because the
7767 * controls will not be reloaded.
7768 */
7769 if (spec->dsp_reload) {
7770 spec->dsp_reload = false;
7771 ca0132_pe_switch_set(codec);
7772 }
7773
7774 snd_hda_power_down_pm(codec);
7775
7776 return 0;
7777 }
7778
7779 static void ca0132_free(struct hda_codec *codec)
7780 {
7781 struct ca0132_spec *spec = codec->spec;
7782
7783 cancel_delayed_work_sync(&spec->unsol_hp_work);
7784 snd_hda_power_up(codec);
7785 switch (spec->quirk) {
7786 case QUIRK_SBZ:
7787 sbz_exit_chip(codec);
7788 break;
7789 case QUIRK_R3D:
7790 r3d_exit_chip(codec);
7791 break;
7792 case QUIRK_R3DI:
7793 r3di_gpio_shutdown(codec);
7794 break;
7795 }
7796
7797 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7798 ca0132_exit_chip(codec);
7799
7800 snd_hda_power_down(codec);
7801 if (spec->mem_base)
7802 iounmap(spec->mem_base);
7803 kfree(spec->spec_init_verbs);
7804 kfree(codec->spec);
7805 }
7806
7807 static void ca0132_reboot_notify(struct hda_codec *codec)
7808 {
7809 codec->patch_ops.free(codec);
7810 }
7811
7812 static const struct hda_codec_ops ca0132_patch_ops = {
7813 .build_controls = ca0132_build_controls,
7814 .build_pcms = ca0132_build_pcms,
7815 .init = ca0132_init,
7816 .free = ca0132_free,
7817 .unsol_event = snd_hda_jack_unsol_event,
7818 .reboot_notify = ca0132_reboot_notify,
7819 };
7820
7821 static void ca0132_config(struct hda_codec *codec)
7822 {
7823 struct ca0132_spec *spec = codec->spec;
7824
7825 spec->dacs[0] = 0x2;
7826 spec->dacs[1] = 0x3;
7827 spec->dacs[2] = 0x4;
7828
7829 spec->multiout.dac_nids = spec->dacs;
7830 spec->multiout.num_dacs = 3;
7831
7832 if (!spec->use_alt_functions)
7833 spec->multiout.max_channels = 2;
7834 else
7835 spec->multiout.max_channels = 6;
7836
7837 switch (spec->quirk) {
7838 case QUIRK_ALIENWARE:
7839 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
7840 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7841 break;
7842 case QUIRK_SBZ:
7843 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7844 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7845 break;
7846 case QUIRK_R3D:
7847 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7848 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7849 break;
7850 case QUIRK_R3DI:
7851 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7852 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7853 break;
7854 case QUIRK_AE5:
7855 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
7856 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7857 break;
7858 }
7859
7860 switch (spec->quirk) {
7861 case QUIRK_ALIENWARE:
7862 spec->num_outputs = 2;
7863 spec->out_pins[0] = 0x0b; /* speaker out */
7864 spec->out_pins[1] = 0x0f;
7865 spec->shared_out_nid = 0x2;
7866 spec->unsol_tag_hp = 0x0f;
7867
7868 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7869 spec->adcs[1] = 0x8; /* analog mic2 */
7870 spec->adcs[2] = 0xa; /* what u hear */
7871
7872 spec->num_inputs = 3;
7873 spec->input_pins[0] = 0x12;
7874 spec->input_pins[1] = 0x11;
7875 spec->input_pins[2] = 0x13;
7876 spec->shared_mic_nid = 0x7;
7877 spec->unsol_tag_amic1 = 0x11;
7878 break;
7879 case QUIRK_SBZ:
7880 case QUIRK_R3D:
7881 spec->num_outputs = 2;
7882 spec->out_pins[0] = 0x0B; /* Line out */
7883 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7884 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7885 spec->out_pins[3] = 0x11; /* Rear surround */
7886 spec->shared_out_nid = 0x2;
7887 spec->unsol_tag_hp = spec->out_pins[1];
7888 spec->unsol_tag_front_hp = spec->out_pins[2];
7889
7890 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7891 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7892 spec->adcs[2] = 0xa; /* what u hear */
7893
7894 spec->num_inputs = 2;
7895 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7896 spec->input_pins[1] = 0x13; /* What U Hear */
7897 spec->shared_mic_nid = 0x7;
7898 spec->unsol_tag_amic1 = spec->input_pins[0];
7899
7900 /* SPDIF I/O */
7901 spec->dig_out = 0x05;
7902 spec->multiout.dig_out_nid = spec->dig_out;
7903 spec->dig_in = 0x09;
7904 break;
7905 case QUIRK_AE5:
7906 spec->num_outputs = 2;
7907 spec->out_pins[0] = 0x0B; /* Line out */
7908 spec->out_pins[1] = 0x11; /* Rear headphone out */
7909 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7910 spec->out_pins[3] = 0x0F; /* Rear surround */
7911 spec->shared_out_nid = 0x2;
7912 spec->unsol_tag_hp = spec->out_pins[1];
7913 spec->unsol_tag_front_hp = spec->out_pins[2];
7914
7915 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7916 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7917 spec->adcs[2] = 0xa; /* what u hear */
7918
7919 spec->num_inputs = 2;
7920 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7921 spec->input_pins[1] = 0x13; /* What U Hear */
7922 spec->shared_mic_nid = 0x7;
7923 spec->unsol_tag_amic1 = spec->input_pins[0];
7924
7925 /* SPDIF I/O */
7926 spec->dig_out = 0x05;
7927 spec->multiout.dig_out_nid = spec->dig_out;
7928 break;
7929 case QUIRK_R3DI:
7930 spec->num_outputs = 2;
7931 spec->out_pins[0] = 0x0B; /* Line out */
7932 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7933 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7934 spec->out_pins[3] = 0x11; /* Rear surround */
7935 spec->shared_out_nid = 0x2;
7936 spec->unsol_tag_hp = spec->out_pins[1];
7937 spec->unsol_tag_front_hp = spec->out_pins[2];
7938
7939 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7940 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7941 spec->adcs[2] = 0x0a; /* what u hear */
7942
7943 spec->num_inputs = 2;
7944 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7945 spec->input_pins[1] = 0x13; /* What U Hear */
7946 spec->shared_mic_nid = 0x7;
7947 spec->unsol_tag_amic1 = spec->input_pins[0];
7948
7949 /* SPDIF I/O */
7950 spec->dig_out = 0x05;
7951 spec->multiout.dig_out_nid = spec->dig_out;
7952 break;
7953 default:
7954 spec->num_outputs = 2;
7955 spec->out_pins[0] = 0x0b; /* speaker out */
7956 spec->out_pins[1] = 0x10; /* headphone out */
7957 spec->shared_out_nid = 0x2;
7958 spec->unsol_tag_hp = spec->out_pins[1];
7959
7960 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7961 spec->adcs[1] = 0x8; /* analog mic2 */
7962 spec->adcs[2] = 0xa; /* what u hear */
7963
7964 spec->num_inputs = 3;
7965 spec->input_pins[0] = 0x12;
7966 spec->input_pins[1] = 0x11;
7967 spec->input_pins[2] = 0x13;
7968 spec->shared_mic_nid = 0x7;
7969 spec->unsol_tag_amic1 = spec->input_pins[0];
7970
7971 /* SPDIF I/O */
7972 spec->dig_out = 0x05;
7973 spec->multiout.dig_out_nid = spec->dig_out;
7974 spec->dig_in = 0x09;
7975 break;
7976 }
7977 }
7978
7979 static int ca0132_prepare_verbs(struct hda_codec *codec)
7980 {
7981 /* Verbs + terminator (an empty element) */
7982 #define NUM_SPEC_VERBS 2
7983 struct ca0132_spec *spec = codec->spec;
7984
7985 spec->chip_init_verbs = ca0132_init_verbs0;
7986 /*
7987 * Since desktop cards use pci_mmio, this can be used to determine
7988 * whether or not to use these verbs instead of a separate bool.
7989 */
7990 if (spec->use_pci_mmio)
7991 spec->desktop_init_verbs = ca0132_init_verbs1;
7992 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7993 sizeof(struct hda_verb),
7994 GFP_KERNEL);
7995 if (!spec->spec_init_verbs)
7996 return -ENOMEM;
7997
7998 /* config EAPD */
7999 spec->spec_init_verbs[0].nid = 0x0b;
8000 spec->spec_init_verbs[0].param = 0x78D;
8001 spec->spec_init_verbs[0].verb = 0x00;
8002
8003 /* Previously commented configuration */
8004 /*
8005 spec->spec_init_verbs[2].nid = 0x0b;
8006 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
8007 spec->spec_init_verbs[2].verb = 0x02;
8008
8009 spec->spec_init_verbs[3].nid = 0x10;
8010 spec->spec_init_verbs[3].param = 0x78D;
8011 spec->spec_init_verbs[3].verb = 0x02;
8012
8013 spec->spec_init_verbs[4].nid = 0x10;
8014 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
8015 spec->spec_init_verbs[4].verb = 0x02;
8016 */
8017
8018 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
8019 return 0;
8020 }
8021
8022 static int patch_ca0132(struct hda_codec *codec)
8023 {
8024 struct ca0132_spec *spec;
8025 int err;
8026 const struct snd_pci_quirk *quirk;
8027
8028 codec_dbg(codec, "patch_ca0132\n");
8029
8030 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
8031 if (!spec)
8032 return -ENOMEM;
8033 codec->spec = spec;
8034 spec->codec = codec;
8035
8036 codec->patch_ops = ca0132_patch_ops;
8037 codec->pcm_format_first = 1;
8038 codec->no_sticky_stream = 1;
8039
8040 /* Detect codec quirk */
8041 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
8042 if (quirk)
8043 spec->quirk = quirk->value;
8044 else
8045 spec->quirk = QUIRK_NONE;
8046
8047 spec->dsp_state = DSP_DOWNLOAD_INIT;
8048 spec->num_mixers = 1;
8049
8050 /* Set which mixers each quirk uses. */
8051 switch (spec->quirk) {
8052 case QUIRK_SBZ:
8053 spec->mixers[0] = desktop_mixer;
8054 snd_hda_codec_set_name(codec, "Sound Blaster Z");
8055 break;
8056 case QUIRK_R3D:
8057 spec->mixers[0] = desktop_mixer;
8058 snd_hda_codec_set_name(codec, "Recon3D");
8059 break;
8060 case QUIRK_R3DI:
8061 spec->mixers[0] = r3di_mixer;
8062 snd_hda_codec_set_name(codec, "Recon3Di");
8063 break;
8064 case QUIRK_AE5:
8065 spec->mixers[0] = desktop_mixer;
8066 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
8067 break;
8068 default:
8069 spec->mixers[0] = ca0132_mixer;
8070 break;
8071 }
8072
8073 /* Setup whether or not to use alt functions/controls/pci_mmio */
8074 switch (spec->quirk) {
8075 case QUIRK_SBZ:
8076 case QUIRK_R3D:
8077 case QUIRK_AE5:
8078 spec->use_alt_controls = true;
8079 spec->use_alt_functions = true;
8080 spec->use_pci_mmio = true;
8081 break;
8082 case QUIRK_R3DI:
8083 spec->use_alt_controls = true;
8084 spec->use_alt_functions = true;
8085 spec->use_pci_mmio = false;
8086 break;
8087 default:
8088 spec->use_alt_controls = false;
8089 spec->use_alt_functions = false;
8090 spec->use_pci_mmio = false;
8091 break;
8092 }
8093
8094 if (spec->use_pci_mmio) {
8095 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
8096 if (spec->mem_base == NULL) {
8097 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
8098 spec->quirk = QUIRK_NONE;
8099 }
8100 }
8101
8102 spec->base_init_verbs = ca0132_base_init_verbs;
8103 spec->base_exit_verbs = ca0132_base_exit_verbs;
8104
8105 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
8106
8107 ca0132_init_chip(codec);
8108
8109 ca0132_config(codec);
8110
8111 err = ca0132_prepare_verbs(codec);
8112 if (err < 0)
8113 goto error;
8114
8115 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
8116 if (err < 0)
8117 goto error;
8118
8119 return 0;
8120
8121 error:
8122 ca0132_free(codec);
8123 return err;
8124 }
8125
8126 /*
8127 * patch entries
8128 */
8129 static struct hda_device_id snd_hda_id_ca0132[] = {
8130 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
8131 {} /* terminator */
8132 };
8133 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
8134
8135 MODULE_LICENSE("GPL");
8136 MODULE_DESCRIPTION("Creative Sound Core3D codec");
8137
8138 static struct hda_codec_driver ca0132_driver = {
8139 .id = snd_hda_id_ca0132,
8140 };
8141
8142 module_hda_codec_driver(ca0132_driver);
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