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[mirror_ubuntu-eoan-kernel.git] / sound / pci / hda / patch_hdmi.c
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include "hda_codec.h"
41 #include "hda_local.h"
42 #include "hda_jack.h"
43
44 static bool static_hdmi_pcm;
45 module_param(static_hdmi_pcm, bool, 0644);
46 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
48 #define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
49 #define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec))
51
52 #define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
53
54 struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62 };
63
64 /* max. connections to a widget */
65 #define HDA_MAX_CONNECTIONS 32
66
67 struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
71 int mux_idx;
72 hda_nid_t cvt_nid;
73
74 struct hda_codec *codec;
75 struct hdmi_eld sink_eld;
76 struct mutex lock;
77 struct delayed_work work;
78 struct snd_kcontrol *eld_ctl;
79 int repoll_count;
80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
82 bool non_pcm;
83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
85 char pcm_name[8]; /* filled in build_pcm callbacks */
86 #ifdef CONFIG_PROC_FS
87 struct snd_info_entry *proc_entry;
88 #endif
89 };
90
91 struct cea_channel_speaker_allocation;
92
93 /* operations used by generic code that can be overridden by patches */
94 struct hdmi_ops {
95 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
96 unsigned char *buf, int *eld_size);
97
98 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
99 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int asp_slot);
101 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int asp_slot, int channel);
103
104 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
105 int ca, int active_channels, int conn_type);
106
107 /* enable/disable HBR (HD passthrough) */
108 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
109
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, u32 stream_tag, int format);
112
113 /* Helpers for producing the channel map TLVs. These can be overridden
114 * for devices that have non-standard mapping requirements. */
115 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
116 int channels);
117 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
118 unsigned int *chmap, int channels);
119
120 /* check that the user-given chmap is supported */
121 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
122 };
123
124 struct hdmi_spec {
125 int num_cvts;
126 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
127 hda_nid_t cvt_nids[4]; /* only for haswell fix */
128
129 int num_pins;
130 struct snd_array pins; /* struct hdmi_spec_per_pin */
131 struct snd_array pcm_rec; /* struct hda_pcm */
132 unsigned int channels_max; /* max over all cvts */
133
134 struct hdmi_eld temp_eld;
135 struct hdmi_ops ops;
136
137 bool dyn_pin_out;
138
139 /*
140 * Non-generic VIA/NVIDIA specific
141 */
142 struct hda_multi_out multiout;
143 struct hda_pcm_stream pcm_playback;
144 };
145
146
147 struct hdmi_audio_infoframe {
148 u8 type; /* 0x84 */
149 u8 ver; /* 0x01 */
150 u8 len; /* 0x0a */
151
152 u8 checksum;
153
154 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
155 u8 SS01_SF24;
156 u8 CXT04;
157 u8 CA;
158 u8 LFEPBL01_LSV36_DM_INH7;
159 };
160
161 struct dp_audio_infoframe {
162 u8 type; /* 0x84 */
163 u8 len; /* 0x1b */
164 u8 ver; /* 0x11 << 2 */
165
166 u8 CC02_CT47; /* match with HDMI infoframe from this on */
167 u8 SS01_SF24;
168 u8 CXT04;
169 u8 CA;
170 u8 LFEPBL01_LSV36_DM_INH7;
171 };
172
173 union audio_infoframe {
174 struct hdmi_audio_infoframe hdmi;
175 struct dp_audio_infoframe dp;
176 u8 bytes[0];
177 };
178
179 /*
180 * CEA speaker placement:
181 *
182 * FLH FCH FRH
183 * FLW FL FLC FC FRC FR FRW
184 *
185 * LFE
186 * TC
187 *
188 * RL RLC RC RRC RR
189 *
190 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
191 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
192 */
193 enum cea_speaker_placement {
194 FL = (1 << 0), /* Front Left */
195 FC = (1 << 1), /* Front Center */
196 FR = (1 << 2), /* Front Right */
197 FLC = (1 << 3), /* Front Left Center */
198 FRC = (1 << 4), /* Front Right Center */
199 RL = (1 << 5), /* Rear Left */
200 RC = (1 << 6), /* Rear Center */
201 RR = (1 << 7), /* Rear Right */
202 RLC = (1 << 8), /* Rear Left Center */
203 RRC = (1 << 9), /* Rear Right Center */
204 LFE = (1 << 10), /* Low Frequency Effect */
205 FLW = (1 << 11), /* Front Left Wide */
206 FRW = (1 << 12), /* Front Right Wide */
207 FLH = (1 << 13), /* Front Left High */
208 FCH = (1 << 14), /* Front Center High */
209 FRH = (1 << 15), /* Front Right High */
210 TC = (1 << 16), /* Top Center */
211 };
212
213 /*
214 * ELD SA bits in the CEA Speaker Allocation data block
215 */
216 static int eld_speaker_allocation_bits[] = {
217 [0] = FL | FR,
218 [1] = LFE,
219 [2] = FC,
220 [3] = RL | RR,
221 [4] = RC,
222 [5] = FLC | FRC,
223 [6] = RLC | RRC,
224 /* the following are not defined in ELD yet */
225 [7] = FLW | FRW,
226 [8] = FLH | FRH,
227 [9] = TC,
228 [10] = FCH,
229 };
230
231 struct cea_channel_speaker_allocation {
232 int ca_index;
233 int speakers[8];
234
235 /* derived values, just for convenience */
236 int channels;
237 int spk_mask;
238 };
239
240 /*
241 * ALSA sequence is:
242 *
243 * surround40 surround41 surround50 surround51 surround71
244 * ch0 front left = = = =
245 * ch1 front right = = = =
246 * ch2 rear left = = = =
247 * ch3 rear right = = = =
248 * ch4 LFE center center center
249 * ch5 LFE LFE
250 * ch6 side left
251 * ch7 side right
252 *
253 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
254 */
255 static int hdmi_channel_mapping[0x32][8] = {
256 /* stereo */
257 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
258 /* 2.1 */
259 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
260 /* Dolby Surround */
261 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
262 /* surround40 */
263 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
264 /* 4ch */
265 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
266 /* surround41 */
267 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
268 /* surround50 */
269 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
270 /* surround51 */
271 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
272 /* 7.1 */
273 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
274 };
275
276 /*
277 * This is an ordered list!
278 *
279 * The preceding ones have better chances to be selected by
280 * hdmi_channel_allocation().
281 */
282 static struct cea_channel_speaker_allocation channel_allocations[] = {
283 /* channel: 7 6 5 4 3 2 1 0 */
284 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
285 /* 2.1 */
286 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
287 /* Dolby Surround */
288 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
289 /* surround40 */
290 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
291 /* surround41 */
292 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
293 /* surround50 */
294 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
295 /* surround51 */
296 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
297 /* 6.1 */
298 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
299 /* surround71 */
300 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
301
302 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
303 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
304 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
305 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
306 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
307 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
308 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
309 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
310 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
311 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
312 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
313 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
314 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
315 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
316 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
317 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
318 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
319 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
320 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
321 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
322 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
323 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
324 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
325 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
326 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
327 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
328 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
329 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
330 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
331 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
332 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
333 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
334 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
335 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
336 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
337 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
338 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
339 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
340 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
341 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
342 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
343 };
344
345
346 /*
347 * HDMI routines
348 */
349
350 #define get_pin(spec, idx) \
351 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
352 #define get_cvt(spec, idx) \
353 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
354 #define get_pcm_rec(spec, idx) \
355 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
356
357 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
358 {
359 struct hdmi_spec *spec = codec->spec;
360 int pin_idx;
361
362 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
363 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
364 return pin_idx;
365
366 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
367 return -EINVAL;
368 }
369
370 static int hinfo_to_pin_index(struct hda_codec *codec,
371 struct hda_pcm_stream *hinfo)
372 {
373 struct hdmi_spec *spec = codec->spec;
374 int pin_idx;
375
376 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
377 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
378 return pin_idx;
379
380 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
381 return -EINVAL;
382 }
383
384 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
385 {
386 struct hdmi_spec *spec = codec->spec;
387 int cvt_idx;
388
389 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
390 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
391 return cvt_idx;
392
393 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
394 return -EINVAL;
395 }
396
397 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_info *uinfo)
399 {
400 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
401 struct hdmi_spec *spec = codec->spec;
402 struct hdmi_spec_per_pin *per_pin;
403 struct hdmi_eld *eld;
404 int pin_idx;
405
406 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
407
408 pin_idx = kcontrol->private_value;
409 per_pin = get_pin(spec, pin_idx);
410 eld = &per_pin->sink_eld;
411
412 mutex_lock(&per_pin->lock);
413 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
414 mutex_unlock(&per_pin->lock);
415
416 return 0;
417 }
418
419 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol)
421 {
422 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
423 struct hdmi_spec *spec = codec->spec;
424 struct hdmi_spec_per_pin *per_pin;
425 struct hdmi_eld *eld;
426 int pin_idx;
427
428 pin_idx = kcontrol->private_value;
429 per_pin = get_pin(spec, pin_idx);
430 eld = &per_pin->sink_eld;
431
432 mutex_lock(&per_pin->lock);
433 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
434 mutex_unlock(&per_pin->lock);
435 snd_BUG();
436 return -EINVAL;
437 }
438
439 memset(ucontrol->value.bytes.data, 0,
440 ARRAY_SIZE(ucontrol->value.bytes.data));
441 if (eld->eld_valid)
442 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
443 eld->eld_size);
444 mutex_unlock(&per_pin->lock);
445
446 return 0;
447 }
448
449 static struct snd_kcontrol_new eld_bytes_ctl = {
450 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
451 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
452 .name = "ELD",
453 .info = hdmi_eld_ctl_info,
454 .get = hdmi_eld_ctl_get,
455 };
456
457 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
458 int device)
459 {
460 struct snd_kcontrol *kctl;
461 struct hdmi_spec *spec = codec->spec;
462 int err;
463
464 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
465 if (!kctl)
466 return -ENOMEM;
467 kctl->private_value = pin_idx;
468 kctl->id.device = device;
469
470 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
471 if (err < 0)
472 return err;
473
474 get_pin(spec, pin_idx)->eld_ctl = kctl;
475 return 0;
476 }
477
478 #ifdef BE_PARANOID
479 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
480 int *packet_index, int *byte_index)
481 {
482 int val;
483
484 val = snd_hda_codec_read(codec, pin_nid, 0,
485 AC_VERB_GET_HDMI_DIP_INDEX, 0);
486
487 *packet_index = val >> 5;
488 *byte_index = val & 0x1f;
489 }
490 #endif
491
492 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
493 int packet_index, int byte_index)
494 {
495 int val;
496
497 val = (packet_index << 5) | (byte_index & 0x1f);
498
499 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
500 }
501
502 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
503 unsigned char val)
504 {
505 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
506 }
507
508 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
509 {
510 struct hdmi_spec *spec = codec->spec;
511 int pin_out;
512
513 /* Unmute */
514 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
515 snd_hda_codec_write(codec, pin_nid, 0,
516 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
517
518 if (spec->dyn_pin_out)
519 /* Disable pin out until stream is active */
520 pin_out = 0;
521 else
522 /* Enable pin out: some machines with GM965 gets broken output
523 * when the pin is disabled or changed while using with HDMI
524 */
525 pin_out = PIN_OUT;
526
527 snd_hda_codec_write(codec, pin_nid, 0,
528 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
529 }
530
531 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
532 {
533 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
534 AC_VERB_GET_CVT_CHAN_COUNT, 0);
535 }
536
537 static void hdmi_set_channel_count(struct hda_codec *codec,
538 hda_nid_t cvt_nid, int chs)
539 {
540 if (chs != hdmi_get_channel_count(codec, cvt_nid))
541 snd_hda_codec_write(codec, cvt_nid, 0,
542 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
543 }
544
545 /*
546 * ELD proc files
547 */
548
549 #ifdef CONFIG_PROC_FS
550 static void print_eld_info(struct snd_info_entry *entry,
551 struct snd_info_buffer *buffer)
552 {
553 struct hdmi_spec_per_pin *per_pin = entry->private_data;
554
555 mutex_lock(&per_pin->lock);
556 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
557 mutex_unlock(&per_pin->lock);
558 }
559
560 static void write_eld_info(struct snd_info_entry *entry,
561 struct snd_info_buffer *buffer)
562 {
563 struct hdmi_spec_per_pin *per_pin = entry->private_data;
564
565 mutex_lock(&per_pin->lock);
566 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
567 mutex_unlock(&per_pin->lock);
568 }
569
570 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
571 {
572 char name[32];
573 struct hda_codec *codec = per_pin->codec;
574 struct snd_info_entry *entry;
575 int err;
576
577 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
578 err = snd_card_proc_new(codec->bus->card, name, &entry);
579 if (err < 0)
580 return err;
581
582 snd_info_set_text_ops(entry, per_pin, print_eld_info);
583 entry->c.text.write = write_eld_info;
584 entry->mode |= S_IWUSR;
585 per_pin->proc_entry = entry;
586
587 return 0;
588 }
589
590 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
591 {
592 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
593 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
594 per_pin->proc_entry = NULL;
595 }
596 }
597 #else
598 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
599 int index)
600 {
601 return 0;
602 }
603 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
604 {
605 }
606 #endif
607
608 /*
609 * Channel mapping routines
610 */
611
612 /*
613 * Compute derived values in channel_allocations[].
614 */
615 static void init_channel_allocations(void)
616 {
617 int i, j;
618 struct cea_channel_speaker_allocation *p;
619
620 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
621 p = channel_allocations + i;
622 p->channels = 0;
623 p->spk_mask = 0;
624 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
625 if (p->speakers[j]) {
626 p->channels++;
627 p->spk_mask |= p->speakers[j];
628 }
629 }
630 }
631
632 static int get_channel_allocation_order(int ca)
633 {
634 int i;
635
636 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
637 if (channel_allocations[i].ca_index == ca)
638 break;
639 }
640 return i;
641 }
642
643 /*
644 * The transformation takes two steps:
645 *
646 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
647 * spk_mask => (channel_allocations[]) => ai->CA
648 *
649 * TODO: it could select the wrong CA from multiple candidates.
650 */
651 static int hdmi_channel_allocation(struct hda_codec *codec,
652 struct hdmi_eld *eld, int channels)
653 {
654 int i;
655 int ca = 0;
656 int spk_mask = 0;
657 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
658
659 /*
660 * CA defaults to 0 for basic stereo audio
661 */
662 if (channels <= 2)
663 return 0;
664
665 /*
666 * expand ELD's speaker allocation mask
667 *
668 * ELD tells the speaker mask in a compact(paired) form,
669 * expand ELD's notions to match the ones used by Audio InfoFrame.
670 */
671 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
672 if (eld->info.spk_alloc & (1 << i))
673 spk_mask |= eld_speaker_allocation_bits[i];
674 }
675
676 /* search for the first working match in the CA table */
677 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
678 if (channels == channel_allocations[i].channels &&
679 (spk_mask & channel_allocations[i].spk_mask) ==
680 channel_allocations[i].spk_mask) {
681 ca = channel_allocations[i].ca_index;
682 break;
683 }
684 }
685
686 if (!ca) {
687 /* if there was no match, select the regular ALSA channel
688 * allocation with the matching number of channels */
689 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
690 if (channels == channel_allocations[i].channels) {
691 ca = channel_allocations[i].ca_index;
692 break;
693 }
694 }
695 }
696
697 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
698 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
699 ca, channels, buf);
700
701 return ca;
702 }
703
704 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
705 hda_nid_t pin_nid)
706 {
707 #ifdef CONFIG_SND_DEBUG_VERBOSE
708 struct hdmi_spec *spec = codec->spec;
709 int i;
710 int channel;
711
712 for (i = 0; i < 8; i++) {
713 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
714 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
715 channel, i);
716 }
717 #endif
718 }
719
720 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
721 hda_nid_t pin_nid,
722 bool non_pcm,
723 int ca)
724 {
725 struct hdmi_spec *spec = codec->spec;
726 struct cea_channel_speaker_allocation *ch_alloc;
727 int i;
728 int err;
729 int order;
730 int non_pcm_mapping[8];
731
732 order = get_channel_allocation_order(ca);
733 ch_alloc = &channel_allocations[order];
734
735 if (hdmi_channel_mapping[ca][1] == 0) {
736 int hdmi_slot = 0;
737 /* fill actual channel mappings in ALSA channel (i) order */
738 for (i = 0; i < ch_alloc->channels; i++) {
739 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
740 hdmi_slot++; /* skip zero slots */
741
742 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
743 }
744 /* fill the rest of the slots with ALSA channel 0xf */
745 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
746 if (!ch_alloc->speakers[7 - hdmi_slot])
747 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
748 }
749
750 if (non_pcm) {
751 for (i = 0; i < ch_alloc->channels; i++)
752 non_pcm_mapping[i] = (i << 4) | i;
753 for (; i < 8; i++)
754 non_pcm_mapping[i] = (0xf << 4) | i;
755 }
756
757 for (i = 0; i < 8; i++) {
758 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
759 int hdmi_slot = slotsetup & 0x0f;
760 int channel = (slotsetup & 0xf0) >> 4;
761 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
762 if (err) {
763 codec_dbg(codec, "HDMI: channel mapping failed\n");
764 break;
765 }
766 }
767 }
768
769 struct channel_map_table {
770 unsigned char map; /* ALSA API channel map position */
771 int spk_mask; /* speaker position bit mask */
772 };
773
774 static struct channel_map_table map_tables[] = {
775 { SNDRV_CHMAP_FL, FL },
776 { SNDRV_CHMAP_FR, FR },
777 { SNDRV_CHMAP_RL, RL },
778 { SNDRV_CHMAP_RR, RR },
779 { SNDRV_CHMAP_LFE, LFE },
780 { SNDRV_CHMAP_FC, FC },
781 { SNDRV_CHMAP_RLC, RLC },
782 { SNDRV_CHMAP_RRC, RRC },
783 { SNDRV_CHMAP_RC, RC },
784 { SNDRV_CHMAP_FLC, FLC },
785 { SNDRV_CHMAP_FRC, FRC },
786 { SNDRV_CHMAP_TFL, FLH },
787 { SNDRV_CHMAP_TFR, FRH },
788 { SNDRV_CHMAP_FLW, FLW },
789 { SNDRV_CHMAP_FRW, FRW },
790 { SNDRV_CHMAP_TC, TC },
791 { SNDRV_CHMAP_TFC, FCH },
792 {} /* terminator */
793 };
794
795 /* from ALSA API channel position to speaker bit mask */
796 static int to_spk_mask(unsigned char c)
797 {
798 struct channel_map_table *t = map_tables;
799 for (; t->map; t++) {
800 if (t->map == c)
801 return t->spk_mask;
802 }
803 return 0;
804 }
805
806 /* from ALSA API channel position to CEA slot */
807 static int to_cea_slot(int ordered_ca, unsigned char pos)
808 {
809 int mask = to_spk_mask(pos);
810 int i;
811
812 if (mask) {
813 for (i = 0; i < 8; i++) {
814 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
815 return i;
816 }
817 }
818
819 return -1;
820 }
821
822 /* from speaker bit mask to ALSA API channel position */
823 static int spk_to_chmap(int spk)
824 {
825 struct channel_map_table *t = map_tables;
826 for (; t->map; t++) {
827 if (t->spk_mask == spk)
828 return t->map;
829 }
830 return 0;
831 }
832
833 /* from CEA slot to ALSA API channel position */
834 static int from_cea_slot(int ordered_ca, unsigned char slot)
835 {
836 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
837
838 return spk_to_chmap(mask);
839 }
840
841 /* get the CA index corresponding to the given ALSA API channel map */
842 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
843 {
844 int i, spks = 0, spk_mask = 0;
845
846 for (i = 0; i < chs; i++) {
847 int mask = to_spk_mask(map[i]);
848 if (mask) {
849 spk_mask |= mask;
850 spks++;
851 }
852 }
853
854 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
855 if ((chs == channel_allocations[i].channels ||
856 spks == channel_allocations[i].channels) &&
857 (spk_mask & channel_allocations[i].spk_mask) ==
858 channel_allocations[i].spk_mask)
859 return channel_allocations[i].ca_index;
860 }
861 return -1;
862 }
863
864 /* set up the channel slots for the given ALSA API channel map */
865 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
866 hda_nid_t pin_nid,
867 int chs, unsigned char *map,
868 int ca)
869 {
870 struct hdmi_spec *spec = codec->spec;
871 int ordered_ca = get_channel_allocation_order(ca);
872 int alsa_pos, hdmi_slot;
873 int assignments[8] = {[0 ... 7] = 0xf};
874
875 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
876
877 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
878
879 if (hdmi_slot < 0)
880 continue; /* unassigned channel */
881
882 assignments[hdmi_slot] = alsa_pos;
883 }
884
885 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
886 int err;
887
888 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
889 assignments[hdmi_slot]);
890 if (err)
891 return -EINVAL;
892 }
893 return 0;
894 }
895
896 /* store ALSA API channel map from the current default map */
897 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
898 {
899 int i;
900 int ordered_ca = get_channel_allocation_order(ca);
901 for (i = 0; i < 8; i++) {
902 if (i < channel_allocations[ordered_ca].channels)
903 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
904 else
905 map[i] = 0;
906 }
907 }
908
909 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
910 hda_nid_t pin_nid, bool non_pcm, int ca,
911 int channels, unsigned char *map,
912 bool chmap_set)
913 {
914 if (!non_pcm && chmap_set) {
915 hdmi_manual_setup_channel_mapping(codec, pin_nid,
916 channels, map, ca);
917 } else {
918 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
919 hdmi_setup_fake_chmap(map, ca);
920 }
921
922 hdmi_debug_channel_mapping(codec, pin_nid);
923 }
924
925 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
926 int asp_slot, int channel)
927 {
928 return snd_hda_codec_write(codec, pin_nid, 0,
929 AC_VERB_SET_HDMI_CHAN_SLOT,
930 (channel << 4) | asp_slot);
931 }
932
933 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
934 int asp_slot)
935 {
936 return (snd_hda_codec_read(codec, pin_nid, 0,
937 AC_VERB_GET_HDMI_CHAN_SLOT,
938 asp_slot) & 0xf0) >> 4;
939 }
940
941 /*
942 * Audio InfoFrame routines
943 */
944
945 /*
946 * Enable Audio InfoFrame Transmission
947 */
948 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
949 hda_nid_t pin_nid)
950 {
951 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
952 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
953 AC_DIPXMIT_BEST);
954 }
955
956 /*
957 * Disable Audio InfoFrame Transmission
958 */
959 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
960 hda_nid_t pin_nid)
961 {
962 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
963 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
964 AC_DIPXMIT_DISABLE);
965 }
966
967 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
968 {
969 #ifdef CONFIG_SND_DEBUG_VERBOSE
970 int i;
971 int size;
972
973 size = snd_hdmi_get_eld_size(codec, pin_nid);
974 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
975
976 for (i = 0; i < 8; i++) {
977 size = snd_hda_codec_read(codec, pin_nid, 0,
978 AC_VERB_GET_HDMI_DIP_SIZE, i);
979 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
980 }
981 #endif
982 }
983
984 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
985 {
986 #ifdef BE_PARANOID
987 int i, j;
988 int size;
989 int pi, bi;
990 for (i = 0; i < 8; i++) {
991 size = snd_hda_codec_read(codec, pin_nid, 0,
992 AC_VERB_GET_HDMI_DIP_SIZE, i);
993 if (size == 0)
994 continue;
995
996 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
997 for (j = 1; j < 1000; j++) {
998 hdmi_write_dip_byte(codec, pin_nid, 0x0);
999 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1000 if (pi != i)
1001 codec_dbg(codec, "dip index %d: %d != %d\n",
1002 bi, pi, i);
1003 if (bi == 0) /* byte index wrapped around */
1004 break;
1005 }
1006 codec_dbg(codec,
1007 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1008 i, size, j);
1009 }
1010 #endif
1011 }
1012
1013 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1014 {
1015 u8 *bytes = (u8 *)hdmi_ai;
1016 u8 sum = 0;
1017 int i;
1018
1019 hdmi_ai->checksum = 0;
1020
1021 for (i = 0; i < sizeof(*hdmi_ai); i++)
1022 sum += bytes[i];
1023
1024 hdmi_ai->checksum = -sum;
1025 }
1026
1027 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1028 hda_nid_t pin_nid,
1029 u8 *dip, int size)
1030 {
1031 int i;
1032
1033 hdmi_debug_dip_size(codec, pin_nid);
1034 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1035
1036 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1037 for (i = 0; i < size; i++)
1038 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1039 }
1040
1041 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1042 u8 *dip, int size)
1043 {
1044 u8 val;
1045 int i;
1046
1047 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1048 != AC_DIPXMIT_BEST)
1049 return false;
1050
1051 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1052 for (i = 0; i < size; i++) {
1053 val = snd_hda_codec_read(codec, pin_nid, 0,
1054 AC_VERB_GET_HDMI_DIP_DATA, 0);
1055 if (val != dip[i])
1056 return false;
1057 }
1058
1059 return true;
1060 }
1061
1062 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1063 hda_nid_t pin_nid,
1064 int ca, int active_channels,
1065 int conn_type)
1066 {
1067 union audio_infoframe ai;
1068
1069 memset(&ai, 0, sizeof(ai));
1070 if (conn_type == 0) { /* HDMI */
1071 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1072
1073 hdmi_ai->type = 0x84;
1074 hdmi_ai->ver = 0x01;
1075 hdmi_ai->len = 0x0a;
1076 hdmi_ai->CC02_CT47 = active_channels - 1;
1077 hdmi_ai->CA = ca;
1078 hdmi_checksum_audio_infoframe(hdmi_ai);
1079 } else if (conn_type == 1) { /* DisplayPort */
1080 struct dp_audio_infoframe *dp_ai = &ai.dp;
1081
1082 dp_ai->type = 0x84;
1083 dp_ai->len = 0x1b;
1084 dp_ai->ver = 0x11 << 2;
1085 dp_ai->CC02_CT47 = active_channels - 1;
1086 dp_ai->CA = ca;
1087 } else {
1088 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1089 pin_nid);
1090 return;
1091 }
1092
1093 /*
1094 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1095 * sizeof(*dp_ai) to avoid partial match/update problems when
1096 * the user switches between HDMI/DP monitors.
1097 */
1098 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1099 sizeof(ai))) {
1100 codec_dbg(codec,
1101 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1102 pin_nid,
1103 active_channels, ca);
1104 hdmi_stop_infoframe_trans(codec, pin_nid);
1105 hdmi_fill_audio_infoframe(codec, pin_nid,
1106 ai.bytes, sizeof(ai));
1107 hdmi_start_infoframe_trans(codec, pin_nid);
1108 }
1109 }
1110
1111 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1112 struct hdmi_spec_per_pin *per_pin,
1113 bool non_pcm)
1114 {
1115 struct hdmi_spec *spec = codec->spec;
1116 hda_nid_t pin_nid = per_pin->pin_nid;
1117 int channels = per_pin->channels;
1118 int active_channels;
1119 struct hdmi_eld *eld;
1120 int ca, ordered_ca;
1121
1122 if (!channels)
1123 return;
1124
1125 if (is_haswell_plus(codec))
1126 snd_hda_codec_write(codec, pin_nid, 0,
1127 AC_VERB_SET_AMP_GAIN_MUTE,
1128 AMP_OUT_UNMUTE);
1129
1130 eld = &per_pin->sink_eld;
1131
1132 if (!non_pcm && per_pin->chmap_set)
1133 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1134 else
1135 ca = hdmi_channel_allocation(codec, eld, channels);
1136 if (ca < 0)
1137 ca = 0;
1138
1139 ordered_ca = get_channel_allocation_order(ca);
1140 active_channels = channel_allocations[ordered_ca].channels;
1141
1142 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1143
1144 /*
1145 * always configure channel mapping, it may have been changed by the
1146 * user in the meantime
1147 */
1148 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1149 channels, per_pin->chmap,
1150 per_pin->chmap_set);
1151
1152 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1153 eld->info.conn_type);
1154
1155 per_pin->non_pcm = non_pcm;
1156 }
1157
1158 /*
1159 * Unsolicited events
1160 */
1161
1162 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1163
1164 static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
1165 {
1166 struct hdmi_spec *spec = codec->spec;
1167 int pin_idx = pin_nid_to_pin_index(codec, jack->nid);
1168 if (pin_idx < 0)
1169 return;
1170
1171 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1172 snd_hda_jack_report_sync(codec);
1173 }
1174
1175 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1176 {
1177 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1178 struct hda_jack_tbl *jack;
1179 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1180
1181 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1182 if (!jack)
1183 return;
1184 jack->jack_dirty = 1;
1185
1186 codec_dbg(codec,
1187 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1188 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1189 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1190
1191 jack_callback(codec, jack);
1192 }
1193
1194 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1195 {
1196 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1197 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1198 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1199 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1200
1201 codec_info(codec,
1202 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1203 codec->addr,
1204 tag,
1205 subtag,
1206 cp_state,
1207 cp_ready);
1208
1209 /* TODO */
1210 if (cp_state)
1211 ;
1212 if (cp_ready)
1213 ;
1214 }
1215
1216
1217 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1218 {
1219 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1220 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1221
1222 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1223 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1224 return;
1225 }
1226
1227 if (subtag == 0)
1228 hdmi_intrinsic_event(codec, res);
1229 else
1230 hdmi_non_intrinsic_event(codec, res);
1231 }
1232
1233 static void haswell_verify_D0(struct hda_codec *codec,
1234 hda_nid_t cvt_nid, hda_nid_t nid)
1235 {
1236 int pwr;
1237
1238 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1239 * thus pins could only choose converter 0 for use. Make sure the
1240 * converters are in correct power state */
1241 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1242 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1243
1244 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1245 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1246 AC_PWRST_D0);
1247 msleep(40);
1248 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1249 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1250 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1251 }
1252 }
1253
1254 /*
1255 * Callbacks
1256 */
1257
1258 /* HBR should be Non-PCM, 8 channels */
1259 #define is_hbr_format(format) \
1260 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1261
1262 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1263 bool hbr)
1264 {
1265 int pinctl, new_pinctl;
1266
1267 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1268 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1269 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1270
1271 if (pinctl < 0)
1272 return hbr ? -EINVAL : 0;
1273
1274 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1275 if (hbr)
1276 new_pinctl |= AC_PINCTL_EPT_HBR;
1277 else
1278 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1279
1280 codec_dbg(codec,
1281 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1282 pin_nid,
1283 pinctl == new_pinctl ? "" : "new-",
1284 new_pinctl);
1285
1286 if (pinctl != new_pinctl)
1287 snd_hda_codec_write(codec, pin_nid, 0,
1288 AC_VERB_SET_PIN_WIDGET_CONTROL,
1289 new_pinctl);
1290 } else if (hbr)
1291 return -EINVAL;
1292
1293 return 0;
1294 }
1295
1296 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1297 hda_nid_t pin_nid, u32 stream_tag, int format)
1298 {
1299 struct hdmi_spec *spec = codec->spec;
1300 int err;
1301
1302 if (is_haswell_plus(codec))
1303 haswell_verify_D0(codec, cvt_nid, pin_nid);
1304
1305 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1306
1307 if (err) {
1308 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1309 return err;
1310 }
1311
1312 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1313 return 0;
1314 }
1315
1316 static int hdmi_choose_cvt(struct hda_codec *codec,
1317 int pin_idx, int *cvt_id, int *mux_id)
1318 {
1319 struct hdmi_spec *spec = codec->spec;
1320 struct hdmi_spec_per_pin *per_pin;
1321 struct hdmi_spec_per_cvt *per_cvt = NULL;
1322 int cvt_idx, mux_idx = 0;
1323
1324 per_pin = get_pin(spec, pin_idx);
1325
1326 /* Dynamically assign converter to stream */
1327 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1328 per_cvt = get_cvt(spec, cvt_idx);
1329
1330 /* Must not already be assigned */
1331 if (per_cvt->assigned)
1332 continue;
1333 /* Must be in pin's mux's list of converters */
1334 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1335 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1336 break;
1337 /* Not in mux list */
1338 if (mux_idx == per_pin->num_mux_nids)
1339 continue;
1340 break;
1341 }
1342
1343 /* No free converters */
1344 if (cvt_idx == spec->num_cvts)
1345 return -ENODEV;
1346
1347 per_pin->mux_idx = mux_idx;
1348
1349 if (cvt_id)
1350 *cvt_id = cvt_idx;
1351 if (mux_id)
1352 *mux_id = mux_idx;
1353
1354 return 0;
1355 }
1356
1357 /* Assure the pin select the right convetor */
1358 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1359 struct hdmi_spec_per_pin *per_pin)
1360 {
1361 hda_nid_t pin_nid = per_pin->pin_nid;
1362 int mux_idx, curr;
1363
1364 mux_idx = per_pin->mux_idx;
1365 curr = snd_hda_codec_read(codec, pin_nid, 0,
1366 AC_VERB_GET_CONNECT_SEL, 0);
1367 if (curr != mux_idx)
1368 snd_hda_codec_write_cache(codec, pin_nid, 0,
1369 AC_VERB_SET_CONNECT_SEL,
1370 mux_idx);
1371 }
1372
1373 /* Intel HDMI workaround to fix audio routing issue:
1374 * For some Intel display codecs, pins share the same connection list.
1375 * So a conveter can be selected by multiple pins and playback on any of these
1376 * pins will generate sound on the external display, because audio flows from
1377 * the same converter to the display pipeline. Also muting one pin may make
1378 * other pins have no sound output.
1379 * So this function assures that an assigned converter for a pin is not selected
1380 * by any other pins.
1381 */
1382 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1383 hda_nid_t pin_nid, int mux_idx)
1384 {
1385 struct hdmi_spec *spec = codec->spec;
1386 hda_nid_t nid, end_nid;
1387 int cvt_idx, curr;
1388 struct hdmi_spec_per_cvt *per_cvt;
1389
1390 /* configure all pins, including "no physical connection" ones */
1391 end_nid = codec->start_nid + codec->num_nodes;
1392 for (nid = codec->start_nid; nid < end_nid; nid++) {
1393 unsigned int wid_caps = get_wcaps(codec, nid);
1394 unsigned int wid_type = get_wcaps_type(wid_caps);
1395
1396 if (wid_type != AC_WID_PIN)
1397 continue;
1398
1399 if (nid == pin_nid)
1400 continue;
1401
1402 curr = snd_hda_codec_read(codec, nid, 0,
1403 AC_VERB_GET_CONNECT_SEL, 0);
1404 if (curr != mux_idx)
1405 continue;
1406
1407 /* choose an unassigned converter. The conveters in the
1408 * connection list are in the same order as in the codec.
1409 */
1410 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1411 per_cvt = get_cvt(spec, cvt_idx);
1412 if (!per_cvt->assigned) {
1413 codec_dbg(codec,
1414 "choose cvt %d for pin nid %d\n",
1415 cvt_idx, nid);
1416 snd_hda_codec_write_cache(codec, nid, 0,
1417 AC_VERB_SET_CONNECT_SEL,
1418 cvt_idx);
1419 break;
1420 }
1421 }
1422 }
1423 }
1424
1425 /*
1426 * HDA PCM callbacks
1427 */
1428 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1429 struct hda_codec *codec,
1430 struct snd_pcm_substream *substream)
1431 {
1432 struct hdmi_spec *spec = codec->spec;
1433 struct snd_pcm_runtime *runtime = substream->runtime;
1434 int pin_idx, cvt_idx, mux_idx = 0;
1435 struct hdmi_spec_per_pin *per_pin;
1436 struct hdmi_eld *eld;
1437 struct hdmi_spec_per_cvt *per_cvt = NULL;
1438 int err;
1439
1440 /* Validate hinfo */
1441 pin_idx = hinfo_to_pin_index(codec, hinfo);
1442 if (snd_BUG_ON(pin_idx < 0))
1443 return -EINVAL;
1444 per_pin = get_pin(spec, pin_idx);
1445 eld = &per_pin->sink_eld;
1446
1447 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1448 if (err < 0)
1449 return err;
1450
1451 per_cvt = get_cvt(spec, cvt_idx);
1452 /* Claim converter */
1453 per_cvt->assigned = 1;
1454 per_pin->cvt_nid = per_cvt->cvt_nid;
1455 hinfo->nid = per_cvt->cvt_nid;
1456
1457 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1458 AC_VERB_SET_CONNECT_SEL,
1459 mux_idx);
1460
1461 /* configure unused pins to choose other converters */
1462 if (is_haswell_plus(codec) || is_valleyview(codec))
1463 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1464
1465 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1466
1467 /* Initially set the converter's capabilities */
1468 hinfo->channels_min = per_cvt->channels_min;
1469 hinfo->channels_max = per_cvt->channels_max;
1470 hinfo->rates = per_cvt->rates;
1471 hinfo->formats = per_cvt->formats;
1472 hinfo->maxbps = per_cvt->maxbps;
1473
1474 /* Restrict capabilities by ELD if this isn't disabled */
1475 if (!static_hdmi_pcm && eld->eld_valid) {
1476 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1477 if (hinfo->channels_min > hinfo->channels_max ||
1478 !hinfo->rates || !hinfo->formats) {
1479 per_cvt->assigned = 0;
1480 hinfo->nid = 0;
1481 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1482 return -ENODEV;
1483 }
1484 }
1485
1486 /* Store the updated parameters */
1487 runtime->hw.channels_min = hinfo->channels_min;
1488 runtime->hw.channels_max = hinfo->channels_max;
1489 runtime->hw.formats = hinfo->formats;
1490 runtime->hw.rates = hinfo->rates;
1491
1492 snd_pcm_hw_constraint_step(substream->runtime, 0,
1493 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1494 return 0;
1495 }
1496
1497 /*
1498 * HDA/HDMI auto parsing
1499 */
1500 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1501 {
1502 struct hdmi_spec *spec = codec->spec;
1503 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1504 hda_nid_t pin_nid = per_pin->pin_nid;
1505
1506 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1507 codec_warn(codec,
1508 "HDMI: pin %d wcaps %#x does not support connection list\n",
1509 pin_nid, get_wcaps(codec, pin_nid));
1510 return -EINVAL;
1511 }
1512
1513 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1514 per_pin->mux_nids,
1515 HDA_MAX_CONNECTIONS);
1516
1517 return 0;
1518 }
1519
1520 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1521 {
1522 struct hda_jack_tbl *jack;
1523 struct hda_codec *codec = per_pin->codec;
1524 struct hdmi_spec *spec = codec->spec;
1525 struct hdmi_eld *eld = &spec->temp_eld;
1526 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1527 hda_nid_t pin_nid = per_pin->pin_nid;
1528 /*
1529 * Always execute a GetPinSense verb here, even when called from
1530 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1531 * response's PD bit is not the real PD value, but indicates that
1532 * the real PD value changed. An older version of the HD-audio
1533 * specification worked this way. Hence, we just ignore the data in
1534 * the unsolicited response to avoid custom WARs.
1535 */
1536 int present;
1537 bool update_eld = false;
1538 bool eld_changed = false;
1539 bool ret;
1540
1541 snd_hda_power_up(codec);
1542 present = snd_hda_pin_sense(codec, pin_nid);
1543
1544 mutex_lock(&per_pin->lock);
1545 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1546 if (pin_eld->monitor_present)
1547 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1548 else
1549 eld->eld_valid = false;
1550
1551 codec_dbg(codec,
1552 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1553 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1554
1555 if (eld->eld_valid) {
1556 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1557 &eld->eld_size) < 0)
1558 eld->eld_valid = false;
1559 else {
1560 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1561 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1562 eld->eld_size) < 0)
1563 eld->eld_valid = false;
1564 }
1565
1566 if (eld->eld_valid) {
1567 snd_hdmi_show_eld(codec, &eld->info);
1568 update_eld = true;
1569 }
1570 else if (repoll) {
1571 queue_delayed_work(codec->bus->workq,
1572 &per_pin->work,
1573 msecs_to_jiffies(300));
1574 goto unlock;
1575 }
1576 }
1577
1578 if (pin_eld->eld_valid && !eld->eld_valid) {
1579 update_eld = true;
1580 eld_changed = true;
1581 }
1582 if (update_eld) {
1583 bool old_eld_valid = pin_eld->eld_valid;
1584 pin_eld->eld_valid = eld->eld_valid;
1585 eld_changed = pin_eld->eld_size != eld->eld_size ||
1586 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1587 eld->eld_size) != 0;
1588 if (eld_changed)
1589 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1590 eld->eld_size);
1591 pin_eld->eld_size = eld->eld_size;
1592 pin_eld->info = eld->info;
1593
1594 /*
1595 * Re-setup pin and infoframe. This is needed e.g. when
1596 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1597 * - transcoder can change during stream playback on Haswell
1598 * and this can make HW reset converter selection on a pin.
1599 */
1600 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1601 if (is_haswell_plus(codec) || is_valleyview(codec)) {
1602 intel_verify_pin_cvt_connect(codec, per_pin);
1603 intel_not_share_assigned_cvt(codec, pin_nid,
1604 per_pin->mux_idx);
1605 }
1606
1607 hdmi_setup_audio_infoframe(codec, per_pin,
1608 per_pin->non_pcm);
1609 }
1610 }
1611
1612 if (eld_changed)
1613 snd_ctl_notify(codec->bus->card,
1614 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1615 &per_pin->eld_ctl->id);
1616 unlock:
1617 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1618
1619 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1620 if (jack)
1621 jack->block_report = !ret;
1622
1623 mutex_unlock(&per_pin->lock);
1624 snd_hda_power_down(codec);
1625 return ret;
1626 }
1627
1628 static void hdmi_repoll_eld(struct work_struct *work)
1629 {
1630 struct hdmi_spec_per_pin *per_pin =
1631 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1632
1633 if (per_pin->repoll_count++ > 6)
1634 per_pin->repoll_count = 0;
1635
1636 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1637 snd_hda_jack_report_sync(per_pin->codec);
1638 }
1639
1640 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1641 hda_nid_t nid);
1642
1643 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1644 {
1645 struct hdmi_spec *spec = codec->spec;
1646 unsigned int caps, config;
1647 int pin_idx;
1648 struct hdmi_spec_per_pin *per_pin;
1649 int err;
1650
1651 caps = snd_hda_query_pin_caps(codec, pin_nid);
1652 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1653 return 0;
1654
1655 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1656 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1657 return 0;
1658
1659 if (is_haswell_plus(codec))
1660 intel_haswell_fixup_connect_list(codec, pin_nid);
1661
1662 pin_idx = spec->num_pins;
1663 per_pin = snd_array_new(&spec->pins);
1664 if (!per_pin)
1665 return -ENOMEM;
1666
1667 per_pin->pin_nid = pin_nid;
1668 per_pin->non_pcm = false;
1669
1670 err = hdmi_read_pin_conn(codec, pin_idx);
1671 if (err < 0)
1672 return err;
1673
1674 spec->num_pins++;
1675
1676 return 0;
1677 }
1678
1679 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1680 {
1681 struct hdmi_spec *spec = codec->spec;
1682 struct hdmi_spec_per_cvt *per_cvt;
1683 unsigned int chans;
1684 int err;
1685
1686 chans = get_wcaps(codec, cvt_nid);
1687 chans = get_wcaps_channels(chans);
1688
1689 per_cvt = snd_array_new(&spec->cvts);
1690 if (!per_cvt)
1691 return -ENOMEM;
1692
1693 per_cvt->cvt_nid = cvt_nid;
1694 per_cvt->channels_min = 2;
1695 if (chans <= 16) {
1696 per_cvt->channels_max = chans;
1697 if (chans > spec->channels_max)
1698 spec->channels_max = chans;
1699 }
1700
1701 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1702 &per_cvt->rates,
1703 &per_cvt->formats,
1704 &per_cvt->maxbps);
1705 if (err < 0)
1706 return err;
1707
1708 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1709 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1710 spec->num_cvts++;
1711
1712 return 0;
1713 }
1714
1715 static int hdmi_parse_codec(struct hda_codec *codec)
1716 {
1717 hda_nid_t nid;
1718 int i, nodes;
1719
1720 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1721 if (!nid || nodes < 0) {
1722 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1723 return -EINVAL;
1724 }
1725
1726 for (i = 0; i < nodes; i++, nid++) {
1727 unsigned int caps;
1728 unsigned int type;
1729
1730 caps = get_wcaps(codec, nid);
1731 type = get_wcaps_type(caps);
1732
1733 if (!(caps & AC_WCAP_DIGITAL))
1734 continue;
1735
1736 switch (type) {
1737 case AC_WID_AUD_OUT:
1738 hdmi_add_cvt(codec, nid);
1739 break;
1740 case AC_WID_PIN:
1741 hdmi_add_pin(codec, nid);
1742 break;
1743 }
1744 }
1745
1746 return 0;
1747 }
1748
1749 /*
1750 */
1751 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1752 {
1753 struct hda_spdif_out *spdif;
1754 bool non_pcm;
1755
1756 mutex_lock(&codec->spdif_mutex);
1757 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1758 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1759 mutex_unlock(&codec->spdif_mutex);
1760 return non_pcm;
1761 }
1762
1763
1764 /*
1765 * HDMI callbacks
1766 */
1767
1768 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1769 struct hda_codec *codec,
1770 unsigned int stream_tag,
1771 unsigned int format,
1772 struct snd_pcm_substream *substream)
1773 {
1774 hda_nid_t cvt_nid = hinfo->nid;
1775 struct hdmi_spec *spec = codec->spec;
1776 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1777 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1778 hda_nid_t pin_nid = per_pin->pin_nid;
1779 bool non_pcm;
1780 int pinctl;
1781
1782 if (is_haswell_plus(codec) || is_valleyview(codec)) {
1783 /* Verify pin:cvt selections to avoid silent audio after S3.
1784 * After S3, the audio driver restores pin:cvt selections
1785 * but this can happen before gfx is ready and such selection
1786 * is overlooked by HW. Thus multiple pins can share a same
1787 * default convertor and mute control will affect each other,
1788 * which can cause a resumed audio playback become silent
1789 * after S3.
1790 */
1791 intel_verify_pin_cvt_connect(codec, per_pin);
1792 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1793 }
1794
1795 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1796 mutex_lock(&per_pin->lock);
1797 per_pin->channels = substream->runtime->channels;
1798 per_pin->setup = true;
1799
1800 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1801 mutex_unlock(&per_pin->lock);
1802
1803 if (spec->dyn_pin_out) {
1804 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1805 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1806 snd_hda_codec_write(codec, pin_nid, 0,
1807 AC_VERB_SET_PIN_WIDGET_CONTROL,
1808 pinctl | PIN_OUT);
1809 }
1810
1811 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1812 }
1813
1814 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1815 struct hda_codec *codec,
1816 struct snd_pcm_substream *substream)
1817 {
1818 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1819 return 0;
1820 }
1821
1822 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1823 struct hda_codec *codec,
1824 struct snd_pcm_substream *substream)
1825 {
1826 struct hdmi_spec *spec = codec->spec;
1827 int cvt_idx, pin_idx;
1828 struct hdmi_spec_per_cvt *per_cvt;
1829 struct hdmi_spec_per_pin *per_pin;
1830 int pinctl;
1831
1832 if (hinfo->nid) {
1833 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1834 if (snd_BUG_ON(cvt_idx < 0))
1835 return -EINVAL;
1836 per_cvt = get_cvt(spec, cvt_idx);
1837
1838 snd_BUG_ON(!per_cvt->assigned);
1839 per_cvt->assigned = 0;
1840 hinfo->nid = 0;
1841
1842 pin_idx = hinfo_to_pin_index(codec, hinfo);
1843 if (snd_BUG_ON(pin_idx < 0))
1844 return -EINVAL;
1845 per_pin = get_pin(spec, pin_idx);
1846
1847 if (spec->dyn_pin_out) {
1848 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1849 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1850 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1851 AC_VERB_SET_PIN_WIDGET_CONTROL,
1852 pinctl & ~PIN_OUT);
1853 }
1854
1855 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1856
1857 mutex_lock(&per_pin->lock);
1858 per_pin->chmap_set = false;
1859 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1860
1861 per_pin->setup = false;
1862 per_pin->channels = 0;
1863 mutex_unlock(&per_pin->lock);
1864 }
1865
1866 return 0;
1867 }
1868
1869 static const struct hda_pcm_ops generic_ops = {
1870 .open = hdmi_pcm_open,
1871 .close = hdmi_pcm_close,
1872 .prepare = generic_hdmi_playback_pcm_prepare,
1873 .cleanup = generic_hdmi_playback_pcm_cleanup,
1874 };
1875
1876 /*
1877 * ALSA API channel-map control callbacks
1878 */
1879 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1880 struct snd_ctl_elem_info *uinfo)
1881 {
1882 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1883 struct hda_codec *codec = info->private_data;
1884 struct hdmi_spec *spec = codec->spec;
1885 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1886 uinfo->count = spec->channels_max;
1887 uinfo->value.integer.min = 0;
1888 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1889 return 0;
1890 }
1891
1892 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1893 int channels)
1894 {
1895 /* If the speaker allocation matches the channel count, it is OK.*/
1896 if (cap->channels != channels)
1897 return -1;
1898
1899 /* all channels are remappable freely */
1900 return SNDRV_CTL_TLVT_CHMAP_VAR;
1901 }
1902
1903 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1904 unsigned int *chmap, int channels)
1905 {
1906 int count = 0;
1907 int c;
1908
1909 for (c = 7; c >= 0; c--) {
1910 int spk = cap->speakers[c];
1911 if (!spk)
1912 continue;
1913
1914 chmap[count++] = spk_to_chmap(spk);
1915 }
1916
1917 WARN_ON(count != channels);
1918 }
1919
1920 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1921 unsigned int size, unsigned int __user *tlv)
1922 {
1923 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1924 struct hda_codec *codec = info->private_data;
1925 struct hdmi_spec *spec = codec->spec;
1926 unsigned int __user *dst;
1927 int chs, count = 0;
1928
1929 if (size < 8)
1930 return -ENOMEM;
1931 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1932 return -EFAULT;
1933 size -= 8;
1934 dst = tlv + 2;
1935 for (chs = 2; chs <= spec->channels_max; chs++) {
1936 int i;
1937 struct cea_channel_speaker_allocation *cap;
1938 cap = channel_allocations;
1939 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1940 int chs_bytes = chs * 4;
1941 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1942 unsigned int tlv_chmap[8];
1943
1944 if (type < 0)
1945 continue;
1946 if (size < 8)
1947 return -ENOMEM;
1948 if (put_user(type, dst) ||
1949 put_user(chs_bytes, dst + 1))
1950 return -EFAULT;
1951 dst += 2;
1952 size -= 8;
1953 count += 8;
1954 if (size < chs_bytes)
1955 return -ENOMEM;
1956 size -= chs_bytes;
1957 count += chs_bytes;
1958 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1959 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1960 return -EFAULT;
1961 dst += chs;
1962 }
1963 }
1964 if (put_user(count, tlv + 1))
1965 return -EFAULT;
1966 return 0;
1967 }
1968
1969 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1970 struct snd_ctl_elem_value *ucontrol)
1971 {
1972 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1973 struct hda_codec *codec = info->private_data;
1974 struct hdmi_spec *spec = codec->spec;
1975 int pin_idx = kcontrol->private_value;
1976 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1977 int i;
1978
1979 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1980 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1981 return 0;
1982 }
1983
1984 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1985 struct snd_ctl_elem_value *ucontrol)
1986 {
1987 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1988 struct hda_codec *codec = info->private_data;
1989 struct hdmi_spec *spec = codec->spec;
1990 int pin_idx = kcontrol->private_value;
1991 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1992 unsigned int ctl_idx;
1993 struct snd_pcm_substream *substream;
1994 unsigned char chmap[8];
1995 int i, err, ca, prepared = 0;
1996
1997 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1998 substream = snd_pcm_chmap_substream(info, ctl_idx);
1999 if (!substream || !substream->runtime)
2000 return 0; /* just for avoiding error from alsactl restore */
2001 switch (substream->runtime->status->state) {
2002 case SNDRV_PCM_STATE_OPEN:
2003 case SNDRV_PCM_STATE_SETUP:
2004 break;
2005 case SNDRV_PCM_STATE_PREPARED:
2006 prepared = 1;
2007 break;
2008 default:
2009 return -EBUSY;
2010 }
2011 memset(chmap, 0, sizeof(chmap));
2012 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2013 chmap[i] = ucontrol->value.integer.value[i];
2014 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2015 return 0;
2016 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2017 if (ca < 0)
2018 return -EINVAL;
2019 if (spec->ops.chmap_validate) {
2020 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2021 if (err)
2022 return err;
2023 }
2024 mutex_lock(&per_pin->lock);
2025 per_pin->chmap_set = true;
2026 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2027 if (prepared)
2028 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2029 mutex_unlock(&per_pin->lock);
2030
2031 return 0;
2032 }
2033
2034 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2035 {
2036 struct hdmi_spec *spec = codec->spec;
2037 int pin_idx;
2038
2039 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2040 struct hda_pcm *info;
2041 struct hda_pcm_stream *pstr;
2042 struct hdmi_spec_per_pin *per_pin;
2043
2044 per_pin = get_pin(spec, pin_idx);
2045 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2046 info = snd_array_new(&spec->pcm_rec);
2047 if (!info)
2048 return -ENOMEM;
2049 info->name = per_pin->pcm_name;
2050 info->pcm_type = HDA_PCM_TYPE_HDMI;
2051 info->own_chmap = true;
2052
2053 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2054 pstr->substreams = 1;
2055 pstr->ops = generic_ops;
2056 /* other pstr fields are set in open */
2057 }
2058
2059 codec->num_pcms = spec->num_pins;
2060 codec->pcm_info = spec->pcm_rec.list;
2061
2062 return 0;
2063 }
2064
2065 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2066 {
2067 char hdmi_str[32] = "HDMI/DP";
2068 struct hdmi_spec *spec = codec->spec;
2069 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2070 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2071
2072 if (pcmdev > 0)
2073 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2074 if (!is_jack_detectable(codec, per_pin->pin_nid))
2075 strncat(hdmi_str, " Phantom",
2076 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2077
2078 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
2079 }
2080
2081 static int generic_hdmi_build_controls(struct hda_codec *codec)
2082 {
2083 struct hdmi_spec *spec = codec->spec;
2084 int err;
2085 int pin_idx;
2086
2087 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2088 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2089
2090 err = generic_hdmi_build_jack(codec, pin_idx);
2091 if (err < 0)
2092 return err;
2093
2094 err = snd_hda_create_dig_out_ctls(codec,
2095 per_pin->pin_nid,
2096 per_pin->mux_nids[0],
2097 HDA_PCM_TYPE_HDMI);
2098 if (err < 0)
2099 return err;
2100 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2101
2102 /* add control for ELD Bytes */
2103 err = hdmi_create_eld_ctl(codec, pin_idx,
2104 get_pcm_rec(spec, pin_idx)->device);
2105
2106 if (err < 0)
2107 return err;
2108
2109 hdmi_present_sense(per_pin, 0);
2110 }
2111
2112 /* add channel maps */
2113 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2114 struct snd_pcm_chmap *chmap;
2115 struct snd_kcontrol *kctl;
2116 int i;
2117
2118 if (!codec->pcm_info[pin_idx].pcm)
2119 break;
2120 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2121 SNDRV_PCM_STREAM_PLAYBACK,
2122 NULL, 0, pin_idx, &chmap);
2123 if (err < 0)
2124 return err;
2125 /* override handlers */
2126 chmap->private_data = codec;
2127 kctl = chmap->kctl;
2128 for (i = 0; i < kctl->count; i++)
2129 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2130 kctl->info = hdmi_chmap_ctl_info;
2131 kctl->get = hdmi_chmap_ctl_get;
2132 kctl->put = hdmi_chmap_ctl_put;
2133 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2134 }
2135
2136 return 0;
2137 }
2138
2139 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2140 {
2141 struct hdmi_spec *spec = codec->spec;
2142 int pin_idx;
2143
2144 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2145 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2146
2147 per_pin->codec = codec;
2148 mutex_init(&per_pin->lock);
2149 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2150 eld_proc_new(per_pin, pin_idx);
2151 }
2152 return 0;
2153 }
2154
2155 static int generic_hdmi_init(struct hda_codec *codec)
2156 {
2157 struct hdmi_spec *spec = codec->spec;
2158 int pin_idx;
2159
2160 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2161 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2162 hda_nid_t pin_nid = per_pin->pin_nid;
2163
2164 hdmi_init_pin(codec, pin_nid);
2165 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2166 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2167 }
2168 return 0;
2169 }
2170
2171 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2172 {
2173 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2174 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2175 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2176 }
2177
2178 static void hdmi_array_free(struct hdmi_spec *spec)
2179 {
2180 snd_array_free(&spec->pins);
2181 snd_array_free(&spec->cvts);
2182 snd_array_free(&spec->pcm_rec);
2183 }
2184
2185 static void generic_hdmi_free(struct hda_codec *codec)
2186 {
2187 struct hdmi_spec *spec = codec->spec;
2188 int pin_idx;
2189
2190 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2191 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2192
2193 cancel_delayed_work(&per_pin->work);
2194 eld_proc_free(per_pin);
2195 }
2196
2197 flush_workqueue(codec->bus->workq);
2198 hdmi_array_free(spec);
2199 kfree(spec);
2200 }
2201
2202 #ifdef CONFIG_PM
2203 static int generic_hdmi_resume(struct hda_codec *codec)
2204 {
2205 struct hdmi_spec *spec = codec->spec;
2206 int pin_idx;
2207
2208 codec->patch_ops.init(codec);
2209 snd_hda_codec_resume_amp(codec);
2210 snd_hda_codec_resume_cache(codec);
2211
2212 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2213 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2214 hdmi_present_sense(per_pin, 1);
2215 }
2216 return 0;
2217 }
2218 #endif
2219
2220 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2221 .init = generic_hdmi_init,
2222 .free = generic_hdmi_free,
2223 .build_pcms = generic_hdmi_build_pcms,
2224 .build_controls = generic_hdmi_build_controls,
2225 .unsol_event = hdmi_unsol_event,
2226 #ifdef CONFIG_PM
2227 .resume = generic_hdmi_resume,
2228 #endif
2229 };
2230
2231 static const struct hdmi_ops generic_standard_hdmi_ops = {
2232 .pin_get_eld = snd_hdmi_get_eld,
2233 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2234 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2235 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2236 .pin_hbr_setup = hdmi_pin_hbr_setup,
2237 .setup_stream = hdmi_setup_stream,
2238 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2239 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2240 };
2241
2242
2243 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2244 hda_nid_t nid)
2245 {
2246 struct hdmi_spec *spec = codec->spec;
2247 hda_nid_t conns[4];
2248 int nconns;
2249
2250 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2251 if (nconns == spec->num_cvts &&
2252 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2253 return;
2254
2255 /* override pins connection list */
2256 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2257 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2258 }
2259
2260 #define INTEL_VENDOR_NID 0x08
2261 #define INTEL_GET_VENDOR_VERB 0xf81
2262 #define INTEL_SET_VENDOR_VERB 0x781
2263 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2264 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2265
2266 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2267 bool update_tree)
2268 {
2269 unsigned int vendor_param;
2270
2271 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2272 INTEL_GET_VENDOR_VERB, 0);
2273 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2274 return;
2275
2276 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2277 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2278 INTEL_SET_VENDOR_VERB, vendor_param);
2279 if (vendor_param == -1)
2280 return;
2281
2282 if (update_tree)
2283 snd_hda_codec_update_widgets(codec);
2284 }
2285
2286 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2287 {
2288 unsigned int vendor_param;
2289
2290 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2291 INTEL_GET_VENDOR_VERB, 0);
2292 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2293 return;
2294
2295 /* enable DP1.2 mode */
2296 vendor_param |= INTEL_EN_DP12;
2297 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2298 INTEL_SET_VENDOR_VERB, vendor_param);
2299 }
2300
2301 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2302 * Otherwise you may get severe h/w communication errors.
2303 */
2304 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2305 unsigned int power_state)
2306 {
2307 if (power_state == AC_PWRST_D0) {
2308 intel_haswell_enable_all_pins(codec, false);
2309 intel_haswell_fixup_enable_dp12(codec);
2310 }
2311
2312 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2313 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2314 }
2315
2316 static int patch_generic_hdmi(struct hda_codec *codec)
2317 {
2318 struct hdmi_spec *spec;
2319
2320 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2321 if (spec == NULL)
2322 return -ENOMEM;
2323
2324 spec->ops = generic_standard_hdmi_ops;
2325 codec->spec = spec;
2326 hdmi_array_init(spec, 4);
2327
2328 if (is_haswell_plus(codec)) {
2329 intel_haswell_enable_all_pins(codec, true);
2330 intel_haswell_fixup_enable_dp12(codec);
2331 }
2332
2333 if (is_haswell_plus(codec) || is_valleyview(codec))
2334 codec->depop_delay = 0;
2335
2336 if (hdmi_parse_codec(codec) < 0) {
2337 codec->spec = NULL;
2338 kfree(spec);
2339 return -EINVAL;
2340 }
2341 codec->patch_ops = generic_hdmi_patch_ops;
2342 if (is_haswell_plus(codec)) {
2343 codec->patch_ops.set_power_state = haswell_set_power_state;
2344 codec->dp_mst = true;
2345 }
2346
2347 generic_hdmi_init_per_pins(codec);
2348
2349 init_channel_allocations();
2350
2351 return 0;
2352 }
2353
2354 /*
2355 * Shared non-generic implementations
2356 */
2357
2358 static int simple_playback_build_pcms(struct hda_codec *codec)
2359 {
2360 struct hdmi_spec *spec = codec->spec;
2361 struct hda_pcm *info;
2362 unsigned int chans;
2363 struct hda_pcm_stream *pstr;
2364 struct hdmi_spec_per_cvt *per_cvt;
2365
2366 per_cvt = get_cvt(spec, 0);
2367 chans = get_wcaps(codec, per_cvt->cvt_nid);
2368 chans = get_wcaps_channels(chans);
2369
2370 info = snd_array_new(&spec->pcm_rec);
2371 if (!info)
2372 return -ENOMEM;
2373 info->name = get_pin(spec, 0)->pcm_name;
2374 sprintf(info->name, "HDMI 0");
2375 info->pcm_type = HDA_PCM_TYPE_HDMI;
2376 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2377 *pstr = spec->pcm_playback;
2378 pstr->nid = per_cvt->cvt_nid;
2379 if (pstr->channels_max <= 2 && chans && chans <= 16)
2380 pstr->channels_max = chans;
2381
2382 codec->num_pcms = 1;
2383 codec->pcm_info = info;
2384
2385 return 0;
2386 }
2387
2388 /* unsolicited event for jack sensing */
2389 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2390 unsigned int res)
2391 {
2392 snd_hda_jack_set_dirty_all(codec);
2393 snd_hda_jack_report_sync(codec);
2394 }
2395
2396 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2397 * as long as spec->pins[] is set correctly
2398 */
2399 #define simple_hdmi_build_jack generic_hdmi_build_jack
2400
2401 static int simple_playback_build_controls(struct hda_codec *codec)
2402 {
2403 struct hdmi_spec *spec = codec->spec;
2404 struct hdmi_spec_per_cvt *per_cvt;
2405 int err;
2406
2407 per_cvt = get_cvt(spec, 0);
2408 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2409 per_cvt->cvt_nid,
2410 HDA_PCM_TYPE_HDMI);
2411 if (err < 0)
2412 return err;
2413 return simple_hdmi_build_jack(codec, 0);
2414 }
2415
2416 static int simple_playback_init(struct hda_codec *codec)
2417 {
2418 struct hdmi_spec *spec = codec->spec;
2419 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2420 hda_nid_t pin = per_pin->pin_nid;
2421
2422 snd_hda_codec_write(codec, pin, 0,
2423 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2424 /* some codecs require to unmute the pin */
2425 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2426 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2427 AMP_OUT_UNMUTE);
2428 snd_hda_jack_detect_enable(codec, pin, pin);
2429 return 0;
2430 }
2431
2432 static void simple_playback_free(struct hda_codec *codec)
2433 {
2434 struct hdmi_spec *spec = codec->spec;
2435
2436 hdmi_array_free(spec);
2437 kfree(spec);
2438 }
2439
2440 /*
2441 * Nvidia specific implementations
2442 */
2443
2444 #define Nv_VERB_SET_Channel_Allocation 0xF79
2445 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2446 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2447 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2448
2449 #define nvhdmi_master_con_nid_7x 0x04
2450 #define nvhdmi_master_pin_nid_7x 0x05
2451
2452 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2453 /*front, rear, clfe, rear_surr */
2454 0x6, 0x8, 0xa, 0xc,
2455 };
2456
2457 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2458 /* set audio protect on */
2459 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2460 /* enable digital output on pin widget */
2461 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2462 {} /* terminator */
2463 };
2464
2465 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2466 /* set audio protect on */
2467 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2468 /* enable digital output on pin widget */
2469 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2470 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2471 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2472 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2473 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2474 {} /* terminator */
2475 };
2476
2477 #ifdef LIMITED_RATE_FMT_SUPPORT
2478 /* support only the safe format and rate */
2479 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2480 #define SUPPORTED_MAXBPS 16
2481 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2482 #else
2483 /* support all rates and formats */
2484 #define SUPPORTED_RATES \
2485 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2486 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2487 SNDRV_PCM_RATE_192000)
2488 #define SUPPORTED_MAXBPS 24
2489 #define SUPPORTED_FORMATS \
2490 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2491 #endif
2492
2493 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2494 {
2495 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2496 return 0;
2497 }
2498
2499 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2500 {
2501 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2502 return 0;
2503 }
2504
2505 static unsigned int channels_2_6_8[] = {
2506 2, 6, 8
2507 };
2508
2509 static unsigned int channels_2_8[] = {
2510 2, 8
2511 };
2512
2513 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2514 .count = ARRAY_SIZE(channels_2_6_8),
2515 .list = channels_2_6_8,
2516 .mask = 0,
2517 };
2518
2519 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2520 .count = ARRAY_SIZE(channels_2_8),
2521 .list = channels_2_8,
2522 .mask = 0,
2523 };
2524
2525 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2526 struct hda_codec *codec,
2527 struct snd_pcm_substream *substream)
2528 {
2529 struct hdmi_spec *spec = codec->spec;
2530 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2531
2532 switch (codec->preset->id) {
2533 case 0x10de0002:
2534 case 0x10de0003:
2535 case 0x10de0005:
2536 case 0x10de0006:
2537 hw_constraints_channels = &hw_constraints_2_8_channels;
2538 break;
2539 case 0x10de0007:
2540 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2541 break;
2542 default:
2543 break;
2544 }
2545
2546 if (hw_constraints_channels != NULL) {
2547 snd_pcm_hw_constraint_list(substream->runtime, 0,
2548 SNDRV_PCM_HW_PARAM_CHANNELS,
2549 hw_constraints_channels);
2550 } else {
2551 snd_pcm_hw_constraint_step(substream->runtime, 0,
2552 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2553 }
2554
2555 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2556 }
2557
2558 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2559 struct hda_codec *codec,
2560 struct snd_pcm_substream *substream)
2561 {
2562 struct hdmi_spec *spec = codec->spec;
2563 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2564 }
2565
2566 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2567 struct hda_codec *codec,
2568 unsigned int stream_tag,
2569 unsigned int format,
2570 struct snd_pcm_substream *substream)
2571 {
2572 struct hdmi_spec *spec = codec->spec;
2573 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2574 stream_tag, format, substream);
2575 }
2576
2577 static const struct hda_pcm_stream simple_pcm_playback = {
2578 .substreams = 1,
2579 .channels_min = 2,
2580 .channels_max = 2,
2581 .ops = {
2582 .open = simple_playback_pcm_open,
2583 .close = simple_playback_pcm_close,
2584 .prepare = simple_playback_pcm_prepare
2585 },
2586 };
2587
2588 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2589 .build_controls = simple_playback_build_controls,
2590 .build_pcms = simple_playback_build_pcms,
2591 .init = simple_playback_init,
2592 .free = simple_playback_free,
2593 .unsol_event = simple_hdmi_unsol_event,
2594 };
2595
2596 static int patch_simple_hdmi(struct hda_codec *codec,
2597 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2598 {
2599 struct hdmi_spec *spec;
2600 struct hdmi_spec_per_cvt *per_cvt;
2601 struct hdmi_spec_per_pin *per_pin;
2602
2603 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2604 if (!spec)
2605 return -ENOMEM;
2606
2607 codec->spec = spec;
2608 hdmi_array_init(spec, 1);
2609
2610 spec->multiout.num_dacs = 0; /* no analog */
2611 spec->multiout.max_channels = 2;
2612 spec->multiout.dig_out_nid = cvt_nid;
2613 spec->num_cvts = 1;
2614 spec->num_pins = 1;
2615 per_pin = snd_array_new(&spec->pins);
2616 per_cvt = snd_array_new(&spec->cvts);
2617 if (!per_pin || !per_cvt) {
2618 simple_playback_free(codec);
2619 return -ENOMEM;
2620 }
2621 per_cvt->cvt_nid = cvt_nid;
2622 per_pin->pin_nid = pin_nid;
2623 spec->pcm_playback = simple_pcm_playback;
2624
2625 codec->patch_ops = simple_hdmi_patch_ops;
2626
2627 return 0;
2628 }
2629
2630 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2631 int channels)
2632 {
2633 unsigned int chanmask;
2634 int chan = channels ? (channels - 1) : 1;
2635
2636 switch (channels) {
2637 default:
2638 case 0:
2639 case 2:
2640 chanmask = 0x00;
2641 break;
2642 case 4:
2643 chanmask = 0x08;
2644 break;
2645 case 6:
2646 chanmask = 0x0b;
2647 break;
2648 case 8:
2649 chanmask = 0x13;
2650 break;
2651 }
2652
2653 /* Set the audio infoframe channel allocation and checksum fields. The
2654 * channel count is computed implicitly by the hardware. */
2655 snd_hda_codec_write(codec, 0x1, 0,
2656 Nv_VERB_SET_Channel_Allocation, chanmask);
2657
2658 snd_hda_codec_write(codec, 0x1, 0,
2659 Nv_VERB_SET_Info_Frame_Checksum,
2660 (0x71 - chan - chanmask));
2661 }
2662
2663 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2664 struct hda_codec *codec,
2665 struct snd_pcm_substream *substream)
2666 {
2667 struct hdmi_spec *spec = codec->spec;
2668 int i;
2669
2670 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2671 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2672 for (i = 0; i < 4; i++) {
2673 /* set the stream id */
2674 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2675 AC_VERB_SET_CHANNEL_STREAMID, 0);
2676 /* set the stream format */
2677 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2678 AC_VERB_SET_STREAM_FORMAT, 0);
2679 }
2680
2681 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2682 * streams are disabled. */
2683 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2684
2685 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2686 }
2687
2688 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2689 struct hda_codec *codec,
2690 unsigned int stream_tag,
2691 unsigned int format,
2692 struct snd_pcm_substream *substream)
2693 {
2694 int chs;
2695 unsigned int dataDCC2, channel_id;
2696 int i;
2697 struct hdmi_spec *spec = codec->spec;
2698 struct hda_spdif_out *spdif;
2699 struct hdmi_spec_per_cvt *per_cvt;
2700
2701 mutex_lock(&codec->spdif_mutex);
2702 per_cvt = get_cvt(spec, 0);
2703 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2704
2705 chs = substream->runtime->channels;
2706
2707 dataDCC2 = 0x2;
2708
2709 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2710 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2711 snd_hda_codec_write(codec,
2712 nvhdmi_master_con_nid_7x,
2713 0,
2714 AC_VERB_SET_DIGI_CONVERT_1,
2715 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2716
2717 /* set the stream id */
2718 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2719 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2720
2721 /* set the stream format */
2722 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2723 AC_VERB_SET_STREAM_FORMAT, format);
2724
2725 /* turn on again (if needed) */
2726 /* enable and set the channel status audio/data flag */
2727 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2728 snd_hda_codec_write(codec,
2729 nvhdmi_master_con_nid_7x,
2730 0,
2731 AC_VERB_SET_DIGI_CONVERT_1,
2732 spdif->ctls & 0xff);
2733 snd_hda_codec_write(codec,
2734 nvhdmi_master_con_nid_7x,
2735 0,
2736 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2737 }
2738
2739 for (i = 0; i < 4; i++) {
2740 if (chs == 2)
2741 channel_id = 0;
2742 else
2743 channel_id = i * 2;
2744
2745 /* turn off SPDIF once;
2746 *otherwise the IEC958 bits won't be updated
2747 */
2748 if (codec->spdif_status_reset &&
2749 (spdif->ctls & AC_DIG1_ENABLE))
2750 snd_hda_codec_write(codec,
2751 nvhdmi_con_nids_7x[i],
2752 0,
2753 AC_VERB_SET_DIGI_CONVERT_1,
2754 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2755 /* set the stream id */
2756 snd_hda_codec_write(codec,
2757 nvhdmi_con_nids_7x[i],
2758 0,
2759 AC_VERB_SET_CHANNEL_STREAMID,
2760 (stream_tag << 4) | channel_id);
2761 /* set the stream format */
2762 snd_hda_codec_write(codec,
2763 nvhdmi_con_nids_7x[i],
2764 0,
2765 AC_VERB_SET_STREAM_FORMAT,
2766 format);
2767 /* turn on again (if needed) */
2768 /* enable and set the channel status audio/data flag */
2769 if (codec->spdif_status_reset &&
2770 (spdif->ctls & AC_DIG1_ENABLE)) {
2771 snd_hda_codec_write(codec,
2772 nvhdmi_con_nids_7x[i],
2773 0,
2774 AC_VERB_SET_DIGI_CONVERT_1,
2775 spdif->ctls & 0xff);
2776 snd_hda_codec_write(codec,
2777 nvhdmi_con_nids_7x[i],
2778 0,
2779 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2780 }
2781 }
2782
2783 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2784
2785 mutex_unlock(&codec->spdif_mutex);
2786 return 0;
2787 }
2788
2789 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2790 .substreams = 1,
2791 .channels_min = 2,
2792 .channels_max = 8,
2793 .nid = nvhdmi_master_con_nid_7x,
2794 .rates = SUPPORTED_RATES,
2795 .maxbps = SUPPORTED_MAXBPS,
2796 .formats = SUPPORTED_FORMATS,
2797 .ops = {
2798 .open = simple_playback_pcm_open,
2799 .close = nvhdmi_8ch_7x_pcm_close,
2800 .prepare = nvhdmi_8ch_7x_pcm_prepare
2801 },
2802 };
2803
2804 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2805 {
2806 struct hdmi_spec *spec;
2807 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2808 nvhdmi_master_pin_nid_7x);
2809 if (err < 0)
2810 return err;
2811
2812 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2813 /* override the PCM rates, etc, as the codec doesn't give full list */
2814 spec = codec->spec;
2815 spec->pcm_playback.rates = SUPPORTED_RATES;
2816 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2817 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2818 return 0;
2819 }
2820
2821 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2822 {
2823 struct hdmi_spec *spec = codec->spec;
2824 int err = simple_playback_build_pcms(codec);
2825 if (!err) {
2826 struct hda_pcm *info = get_pcm_rec(spec, 0);
2827 info->own_chmap = true;
2828 }
2829 return err;
2830 }
2831
2832 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2833 {
2834 struct hdmi_spec *spec = codec->spec;
2835 struct hda_pcm *info;
2836 struct snd_pcm_chmap *chmap;
2837 int err;
2838
2839 err = simple_playback_build_controls(codec);
2840 if (err < 0)
2841 return err;
2842
2843 /* add channel maps */
2844 info = get_pcm_rec(spec, 0);
2845 err = snd_pcm_add_chmap_ctls(info->pcm,
2846 SNDRV_PCM_STREAM_PLAYBACK,
2847 snd_pcm_alt_chmaps, 8, 0, &chmap);
2848 if (err < 0)
2849 return err;
2850 switch (codec->preset->id) {
2851 case 0x10de0002:
2852 case 0x10de0003:
2853 case 0x10de0005:
2854 case 0x10de0006:
2855 chmap->channel_mask = (1U << 2) | (1U << 8);
2856 break;
2857 case 0x10de0007:
2858 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2859 }
2860 return 0;
2861 }
2862
2863 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2864 {
2865 struct hdmi_spec *spec;
2866 int err = patch_nvhdmi_2ch(codec);
2867 if (err < 0)
2868 return err;
2869 spec = codec->spec;
2870 spec->multiout.max_channels = 8;
2871 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2872 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2873 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2874 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2875
2876 /* Initialize the audio infoframe channel mask and checksum to something
2877 * valid */
2878 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2879
2880 return 0;
2881 }
2882
2883 /*
2884 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2885 * - 0x10de0015
2886 * - 0x10de0040
2887 */
2888 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2889 int channels)
2890 {
2891 if (cap->ca_index == 0x00 && channels == 2)
2892 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2893
2894 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2895 }
2896
2897 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2898 {
2899 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2900 return -EINVAL;
2901
2902 return 0;
2903 }
2904
2905 static int patch_nvhdmi(struct hda_codec *codec)
2906 {
2907 struct hdmi_spec *spec;
2908 int err;
2909
2910 err = patch_generic_hdmi(codec);
2911 if (err)
2912 return err;
2913
2914 spec = codec->spec;
2915 spec->dyn_pin_out = true;
2916
2917 spec->ops.chmap_cea_alloc_validate_get_type =
2918 nvhdmi_chmap_cea_alloc_validate_get_type;
2919 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2920
2921 return 0;
2922 }
2923
2924 /*
2925 * ATI/AMD-specific implementations
2926 */
2927
2928 #define is_amdhdmi_rev3_or_later(codec) \
2929 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2930 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2931
2932 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2933 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2934 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
2935 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
2936 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
2937 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
2938 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2939 #define ATI_VERB_SET_HBR_CONTROL 0x77c
2940 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
2941 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
2942 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
2943 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
2944 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2945 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2946 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2947 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2948 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2949 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2950 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2951 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
2952 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2953 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2954 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2955 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2956 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2957
2958 /* AMD specific HDA cvt verbs */
2959 #define ATI_VERB_SET_RAMP_RATE 0x770
2960 #define ATI_VERB_GET_RAMP_RATE 0xf70
2961
2962 #define ATI_OUT_ENABLE 0x1
2963
2964 #define ATI_MULTICHANNEL_MODE_PAIRED 0
2965 #define ATI_MULTICHANNEL_MODE_SINGLE 1
2966
2967 #define ATI_HBR_CAPABLE 0x01
2968 #define ATI_HBR_ENABLE 0x10
2969
2970 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2971 unsigned char *buf, int *eld_size)
2972 {
2973 /* call hda_eld.c ATI/AMD-specific function */
2974 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2975 is_amdhdmi_rev3_or_later(codec));
2976 }
2977
2978 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2979 int active_channels, int conn_type)
2980 {
2981 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2982 }
2983
2984 static int atihdmi_paired_swap_fc_lfe(int pos)
2985 {
2986 /*
2987 * ATI/AMD have automatic FC/LFE swap built-in
2988 * when in pairwise mapping mode.
2989 */
2990
2991 switch (pos) {
2992 /* see channel_allocations[].speakers[] */
2993 case 2: return 3;
2994 case 3: return 2;
2995 default: break;
2996 }
2997
2998 return pos;
2999 }
3000
3001 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3002 {
3003 struct cea_channel_speaker_allocation *cap;
3004 int i, j;
3005
3006 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3007
3008 cap = &channel_allocations[get_channel_allocation_order(ca)];
3009 for (i = 0; i < chs; ++i) {
3010 int mask = to_spk_mask(map[i]);
3011 bool ok = false;
3012 bool companion_ok = false;
3013
3014 if (!mask)
3015 continue;
3016
3017 for (j = 0 + i % 2; j < 8; j += 2) {
3018 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3019 if (cap->speakers[chan_idx] == mask) {
3020 /* channel is in a supported position */
3021 ok = true;
3022
3023 if (i % 2 == 0 && i + 1 < chs) {
3024 /* even channel, check the odd companion */
3025 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3026 int comp_mask_req = to_spk_mask(map[i+1]);
3027 int comp_mask_act = cap->speakers[comp_chan_idx];
3028
3029 if (comp_mask_req == comp_mask_act)
3030 companion_ok = true;
3031 else
3032 return -EINVAL;
3033 }
3034 break;
3035 }
3036 }
3037
3038 if (!ok)
3039 return -EINVAL;
3040
3041 if (companion_ok)
3042 i++; /* companion channel already checked */
3043 }
3044
3045 return 0;
3046 }
3047
3048 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3049 int hdmi_slot, int stream_channel)
3050 {
3051 int verb;
3052 int ati_channel_setup = 0;
3053
3054 if (hdmi_slot > 7)
3055 return -EINVAL;
3056
3057 if (!has_amd_full_remap_support(codec)) {
3058 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3059
3060 /* In case this is an odd slot but without stream channel, do not
3061 * disable the slot since the corresponding even slot could have a
3062 * channel. In case neither have a channel, the slot pair will be
3063 * disabled when this function is called for the even slot. */
3064 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3065 return 0;
3066
3067 hdmi_slot -= hdmi_slot % 2;
3068
3069 if (stream_channel != 0xf)
3070 stream_channel -= stream_channel % 2;
3071 }
3072
3073 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3074
3075 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3076
3077 if (stream_channel != 0xf)
3078 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3079
3080 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3081 }
3082
3083 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3084 int asp_slot)
3085 {
3086 bool was_odd = false;
3087 int ati_asp_slot = asp_slot;
3088 int verb;
3089 int ati_channel_setup;
3090
3091 if (asp_slot > 7)
3092 return -EINVAL;
3093
3094 if (!has_amd_full_remap_support(codec)) {
3095 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3096 if (ati_asp_slot % 2 != 0) {
3097 ati_asp_slot -= 1;
3098 was_odd = true;
3099 }
3100 }
3101
3102 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3103
3104 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3105
3106 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3107 return 0xf;
3108
3109 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3110 }
3111
3112 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3113 int channels)
3114 {
3115 int c;
3116
3117 /*
3118 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3119 * we need to take that into account (a single channel may take 2
3120 * channel slots if we need to carry a silent channel next to it).
3121 * On Rev3+ AMD codecs this function is not used.
3122 */
3123 int chanpairs = 0;
3124
3125 /* We only produce even-numbered channel count TLVs */
3126 if ((channels % 2) != 0)
3127 return -1;
3128
3129 for (c = 0; c < 7; c += 2) {
3130 if (cap->speakers[c] || cap->speakers[c+1])
3131 chanpairs++;
3132 }
3133
3134 if (chanpairs * 2 != channels)
3135 return -1;
3136
3137 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3138 }
3139
3140 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3141 unsigned int *chmap, int channels)
3142 {
3143 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3144 int count = 0;
3145 int c;
3146
3147 for (c = 7; c >= 0; c--) {
3148 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3149 int spk = cap->speakers[chan];
3150 if (!spk) {
3151 /* add N/A channel if the companion channel is occupied */
3152 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3153 chmap[count++] = SNDRV_CHMAP_NA;
3154
3155 continue;
3156 }
3157
3158 chmap[count++] = spk_to_chmap(spk);
3159 }
3160
3161 WARN_ON(count != channels);
3162 }
3163
3164 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3165 bool hbr)
3166 {
3167 int hbr_ctl, hbr_ctl_new;
3168
3169 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3170 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3171 if (hbr)
3172 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3173 else
3174 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3175
3176 codec_dbg(codec,
3177 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3178 pin_nid,
3179 hbr_ctl == hbr_ctl_new ? "" : "new-",
3180 hbr_ctl_new);
3181
3182 if (hbr_ctl != hbr_ctl_new)
3183 snd_hda_codec_write(codec, pin_nid, 0,
3184 ATI_VERB_SET_HBR_CONTROL,
3185 hbr_ctl_new);
3186
3187 } else if (hbr)
3188 return -EINVAL;
3189
3190 return 0;
3191 }
3192
3193 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3194 hda_nid_t pin_nid, u32 stream_tag, int format)
3195 {
3196
3197 if (is_amdhdmi_rev3_or_later(codec)) {
3198 int ramp_rate = 180; /* default as per AMD spec */
3199 /* disable ramp-up/down for non-pcm as per AMD spec */
3200 if (format & AC_FMT_TYPE_NON_PCM)
3201 ramp_rate = 0;
3202
3203 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3204 }
3205
3206 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3207 }
3208
3209
3210 static int atihdmi_init(struct hda_codec *codec)
3211 {
3212 struct hdmi_spec *spec = codec->spec;
3213 int pin_idx, err;
3214
3215 err = generic_hdmi_init(codec);
3216
3217 if (err)
3218 return err;
3219
3220 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3221 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3222
3223 /* make sure downmix information in infoframe is zero */
3224 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3225
3226 /* enable channel-wise remap mode if supported */
3227 if (has_amd_full_remap_support(codec))
3228 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3229 ATI_VERB_SET_MULTICHANNEL_MODE,
3230 ATI_MULTICHANNEL_MODE_SINGLE);
3231 }
3232
3233 return 0;
3234 }
3235
3236 static int patch_atihdmi(struct hda_codec *codec)
3237 {
3238 struct hdmi_spec *spec;
3239 struct hdmi_spec_per_cvt *per_cvt;
3240 int err, cvt_idx;
3241
3242 err = patch_generic_hdmi(codec);
3243
3244 if (err)
3245 return err;
3246
3247 codec->patch_ops.init = atihdmi_init;
3248
3249 spec = codec->spec;
3250
3251 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3252 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3253 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3254 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3255 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3256 spec->ops.setup_stream = atihdmi_setup_stream;
3257
3258 if (!has_amd_full_remap_support(codec)) {
3259 /* override to ATI/AMD-specific versions with pairwise mapping */
3260 spec->ops.chmap_cea_alloc_validate_get_type =
3261 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3262 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3263 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3264 }
3265
3266 /* ATI/AMD converters do not advertise all of their capabilities */
3267 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3268 per_cvt = get_cvt(spec, cvt_idx);
3269 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3270 per_cvt->rates |= SUPPORTED_RATES;
3271 per_cvt->formats |= SUPPORTED_FORMATS;
3272 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3273 }
3274
3275 spec->channels_max = max(spec->channels_max, 8u);
3276
3277 return 0;
3278 }
3279
3280 /* VIA HDMI Implementation */
3281 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3282 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3283
3284 static int patch_via_hdmi(struct hda_codec *codec)
3285 {
3286 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3287 }
3288
3289 /*
3290 * called from hda_codec.c for generic HDMI support
3291 */
3292 int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3293 {
3294 return patch_generic_hdmi(codec);
3295 }
3296 EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
3297
3298 /*
3299 * patch entries
3300 */
3301 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3302 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3303 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3304 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
3305 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
3306 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3307 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3308 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3309 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3310 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3311 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3312 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3313 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
3314 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3315 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3316 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3317 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3318 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3319 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3320 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3321 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3322 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3323 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3324 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3325 /* 17 is known to be absent */
3326 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3327 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3328 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3329 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3330 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3331 { .id = 0x10de0028, .name = "Tegra12x HDMI", .patch = patch_nvhdmi },
3332 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3333 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3334 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3335 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3336 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3337 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3338 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3339 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3340 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi },
3341 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3342 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3343 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3344 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3345 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3346 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3347 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3348 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3349 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3350 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3351 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3352 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3353 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3354 { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3355 { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
3356 { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
3357 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3358 { .id = 0x80862883, .name = "Braswell HDMI", .patch = patch_generic_hdmi },
3359 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3360 {} /* terminator */
3361 };
3362
3363 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3364 MODULE_ALIAS("snd-hda-codec-id:10027919");
3365 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3366 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3367 MODULE_ALIAS("snd-hda-codec-id:10951390");
3368 MODULE_ALIAS("snd-hda-codec-id:10951392");
3369 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3370 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3371 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3372 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3373 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3374 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3375 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3376 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3377 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3378 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3379 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3380 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3381 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3382 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3383 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3384 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3385 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3386 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3387 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3388 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3389 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3390 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3391 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3392 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3393 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3394 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3395 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3396 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3397 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3398 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3399 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3400 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3401 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3402 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3403 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3404 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3405 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3406 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3407 MODULE_ALIAS("snd-hda-codec-id:80860054");
3408 MODULE_ALIAS("snd-hda-codec-id:80862801");
3409 MODULE_ALIAS("snd-hda-codec-id:80862802");
3410 MODULE_ALIAS("snd-hda-codec-id:80862803");
3411 MODULE_ALIAS("snd-hda-codec-id:80862804");
3412 MODULE_ALIAS("snd-hda-codec-id:80862805");
3413 MODULE_ALIAS("snd-hda-codec-id:80862806");
3414 MODULE_ALIAS("snd-hda-codec-id:80862807");
3415 MODULE_ALIAS("snd-hda-codec-id:80862808");
3416 MODULE_ALIAS("snd-hda-codec-id:80862880");
3417 MODULE_ALIAS("snd-hda-codec-id:80862882");
3418 MODULE_ALIAS("snd-hda-codec-id:80862883");
3419 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3420
3421 MODULE_LICENSE("GPL");
3422 MODULE_DESCRIPTION("HDMI HD-audio codec");
3423 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3424 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3425 MODULE_ALIAS("snd-hda-codec-atihdmi");
3426
3427 static struct hda_codec_preset_list intel_list = {
3428 .preset = snd_hda_preset_hdmi,
3429 .owner = THIS_MODULE,
3430 };
3431
3432 static int __init patch_hdmi_init(void)
3433 {
3434 return snd_hda_add_codec_preset(&intel_list);
3435 }
3436
3437 static void __exit patch_hdmi_exit(void)
3438 {
3439 snd_hda_delete_codec_preset(&intel_list);
3440 }
3441
3442 module_init(patch_hdmi_init)
3443 module_exit(patch_hdmi_exit)
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